Semiconductor Device

Abstract

To provide a novel semiconductor device that can write and read multilevel data.SOLUTION: A memory cell includes a bit line, a power supply line, first and second nodes, first to fourth transistors, and first and second capacitors. One of two divided multilevel data is written to the first node through the first transistor. The other of the divided multilevel data is written to the second node through the second transistor. A gate of the third transistor is connected to the first node, and a gate of the fourth transistor is connected to the second node. The third and fourth transistors control a conduction state between the bit line and the power supply line. The first and second transistors preferably include an oxide semiconductor in a semiconductor layer.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to an article, a method, or a manufacturing method. The present invention also relates to a composition of matter. One embodiment relates to a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, and a driving method thereof. In particular, one embodiment of the present invention relates to a semiconductor device, a display device, or a light-emitting device including an oxide semiconductor. Regarding the device.

[0002] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. The display device, the electro-optical device, the semiconductor circuit, and the electronic device are generally devices having semiconductor devices. There may be cases where this occurs. [Background technology]

[0003] Transistors using silicon (Si) as the semiconductor layer and transistors using oxide semiconductors (Oxide Se) The device is made by combining a transistor that uses an OS (semiconductor) as a semiconductor layer. Semiconductor devices that enable data retention have been attracting attention (see Patent Document 1).

[0004] In recent years, with the increase in the amount of data handled, there is a demand for semiconductor devices with large storage capacities. In the semiconductor device described in the above-mentioned Patent Document 1, multi-value data is recorded. The present specification discloses a configuration for storing data in a memory and reading out the data. Unless otherwise specified, multi-valued data refers to j-bit (j is a natural number greater than or equal to 2) data. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2012-256400 A Summary of the Invention [Problem to be solved by the invention]

[0006] For example, the semiconductor device described in Patent Document 1 uses one transistor to store multi-value data. However, as the number of bits of multi-value data increases, The difference between the potential and the potential becomes smaller, making it difficult to judge the potential when reading data, resulting in erroneous reading. There is a possibility that a wrong value may be read.

[0007] One embodiment of the present invention is a semiconductor device capable of writing and reading multilevel data. To provide a semiconductor device capable of writing and reading multi-value data. Another object of the present invention is to provide a method for driving a novel semiconductor device. One object of the present invention is to provide an apparatus.

[0008] In addition, the description of a plurality of problems does not preclude the existence of each problem. The embodiments do not necessarily solve all of these problems. Problems other than those listed may be solved by the present specification. These problems will become apparent from the description of the present invention, drawings, claims, etc. This could be a form of challenge for the Ming. [Means for solving the problem]

[0009] One embodiment of the present invention is a semiconductor memory device including a bit line, a power supply line, first and second word lines, and first to fourth A semiconductor device having a transistor, first and second capacitance elements, and first and second retention nodes. The first holding node is provided with first data through a first transistor. The second data is applied to the second holding node via the second transistor. The gate of the third transistor is electrically connected to the first retention node. One of the source and drain of the third transistor is electrically connected to the bit line. The other of the source and drain of the first transistor is connected to one of the source and drain of a fourth transistor. The other of the source and the drain of the fourth transistor is electrically connected to the power supply line. The gate of the fourth transistor is electrically connected to the second retention node. The first terminal of the first capacitance element is electrically connected to the first retention node. The second terminal of the capacitive element is electrically connected to the first word line. The second terminal of the second capacitance element is electrically connected to a second holding node. The first and second data are either binary or multi-valued data. The first and second transistors each include an oxide semiconductor in a semiconductor layer.

[0010] In the above embodiment, the third and fourth transistors are p-channel transistors.

[0011] In the above embodiment, the third and fourth transistors are n-channel transistors.

[0012] One embodiment of the present invention is a semiconductor device according to any one of the above embodiments, a display device, a microphone, and a speaker. The electronic device has a car, an operation key, or a housing.

[0013] In this specification, a transistor is defined as a transistor having a gate (gate terminal or gate electrode) and a drain. It is an element that has at least three terminals, including an in, a source, and a drain ( Drain terminal, drain region or drain electrode) and source (source terminal, source region or A channel region is formed between the drain and the channel region and the source. It is capable of passing electric current through it.

[0014] Here, the source and drain vary depending on the structure or operating conditions of the transistor. Therefore, it is difficult to determine which is the source and which is the drain. The part that functions as a source and the part that functions as a drain are not called a source or a drain. One of the source and the drain is referred to as a first electrode, and the other of the source and the drain is referred to as a second electrode. It may be indicated.

[0015] The ordinal numbers "first," "second," and "third" used in this specification are intended to avoid confusion of elements. It should be noted that these are added for the purpose of convenience and are not intended to be limiting in number.

[0016] In this specification, "A and B are connected" does not mean that A and B are directly connected. In addition to the above, it also includes those that are electrically connected. Here, A and B are electrically connected. Being connected means that there is an object between A and B that has some electrical effect. A communication line is a line that enables the transmission of electrical signals between A and B.

[0017] For example, the source (or first terminal, etc.) of the transistor may be connected via Z1 (or not) , X, and the drain (or second terminal, etc.) of the transistor is electrically connected to It may be electrically connected to Y through (or without) the source (or The first terminal, for example, is directly connected to a part of Z1, and another part of Z1 is directly connected to X. The drain (or second terminal, etc.) of the transistor is directly connected to a portion of Z2. When another part of Z2 is directly connected to Y, it can be expressed as follows: It is possible to do this.

[0018] For example, "X and Y and the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor The terminals of the transistor (or the first terminal, etc.) are electrically connected to each other, and X, the source of the transistor (or the first terminal, etc.) 1 terminal, etc.), the drain (or second terminal, etc.) of the transistor, and Y. "The source (or the third) of the transistor is connected to the The drain (or second terminal, etc.) of the transistor is electrically connected to X. The transistor source (or first terminal, etc.) is electrically connected to Y, and the transistor source (or first terminal, etc.) is electrically connected to X. The drain (or second terminal, etc.) of the transistor, Y, is electrically connected in this order. " Alternatively, "X is the source (or first terminal, etc.) of a transistor. The transistor is electrically connected to Y via a drain (or a second terminal, etc.) and a transistor is electrically connected to X via a drain (or a second terminal, etc.). The source (or first terminal, etc.) of a resistor, the drain (or second terminal, etc.) of a transistor ), Y is provided in this connection order. By using a simple expression method and specifying the order of connections in the circuit configuration, Distinguish between the source (or first terminal, etc.) and the drain (or second terminal, etc.) of a transistor. The technical scope can be determined by the above expressions. Here, X, Y, Z1, and Z2 are the object (e.g., the device , elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0019] In this specification, the terms "above" and "below" that indicate the positional relationship between components are used. The above is used for convenience in describing the drawings. The meaning of the term varies depending on the direction in which the configuration is depicted. It is not limited to this and can be rephrased appropriately depending on the situation.

[0020] In this specification, unless otherwise specified, the off-state current refers to the current flowing when a transistor is in an off state. The off state refers to the drain current when the transistor is in the off state unless otherwise specified. In a transistor, the potential difference between the gate and source (V GS ) is lower than the threshold voltage (Vth) state, for p-channel transistor, V GS is higher than Vth. For example, The off-state current of an n-channel transistor is V GS When Vth is lower than the drain The off-state current of a transistor is V GS It may depend on The off-state current of the transistor is 10 -21 A or less means that the off-state current of the transistor is 10 -21 V below A GS Sometimes it is said that there exists a value of

[0021] The off-state current of a transistor is determined by the potential difference between the drain and source (V DS ) In this specification, unless otherwise specified, the off-state current is V DS The absolute value of is 0 .1V, 0.8V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 1 It may represent the off-state current at 2 V, 16 V, or 20 V. V is used to measure the reliability required for semiconductor devices that contain transistors. DS , or V used in a semiconductor device or the like that includes the transistor DS The off-state current at It may represent. Effect of the Invention

[0022] According to one aspect of the present invention, a semiconductor device capable of writing and reading multi-level data is provided. To provide a semiconductor device capable of writing and reading multi-level data. In addition, according to one aspect of the present invention, a novel semiconductor device can be provided. It is possible to provide a conductor device.

[0023] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have all of these effects. Effects other than these may be included in the description, This is self-evident from the description in the drawings, claims, etc. It is possible to extract other effects from any of the descriptions. [Brief description of the drawings]

[0024] [Figure 1] FIG. 2 is a circuit diagram showing an example of a memory cell. [Diagram 2] 4 is a timing chart showing an example of the operation of a memory cell. [Diagram 3] 4 is a timing chart showing an example of the operation of a memory cell. [Figure 4] FIG. 2 is a circuit diagram showing an example of a memory cell. [Diagram 5] 4 is a timing chart showing an example of the operation of a memory cell. [Figure 6] 4 is a timing chart showing an example of the operation of a memory cell. [Figure 7] FIG. 1 is a circuit block diagram illustrating an example of a semiconductor device. [Figure 8] FIG. 1 is a circuit block diagram illustrating an example of a semiconductor device. [Figure 9] FIG. 4 is a circuit block diagram showing an example of a row selection driver. [Figure 10] FIG. 4 is a circuit block diagram showing an example of a column selection driver. [Figure 11] FIG. 2 is a circuit block diagram showing an example of an A / D converter. [Figure 12] FIG. 1 is a cross-sectional view showing an example of a semiconductor device. [Figure 13] 1A and 1B are a top view and a cross-sectional view illustrating an example of a transistor. [Figure 14] 1A and 1B are a cross-sectional view and a band diagram illustrating an example of a transistor. [Figure 15] High-resolution TEM image and local Fourier transform image of a cross section of an oxide semiconductor. [Figure 16] 1A and 1B are diagrams showing a nanobeam electron diffraction pattern of an oxide semiconductor film and an example of a transmission electron diffraction measurement apparatus. [Figure 17] FIG. 4 is a diagram showing changes in a crystalline portion due to electron irradiation. [Figure 18] An example of structural analysis using transmission electron diffraction measurements, and a high-resolution TEM image in a plan view. [Figure 19] 1A and 1B are diagrams illustrating examples of electronic devices. [Figure 20] FIG. 1 shows an example of an RF tag. [Figure 21] FIG. 2 is a circuit diagram showing an example of a memory cell. [Figure 22] FIG. 2 is a circuit diagram showing an example of a memory cell. [Figure 23] FIG. 2 is a circuit diagram showing an example of a memory cell. [Figure 24] FIG. 1 is a circuit block diagram illustrating an example of a semiconductor device. [Diagram 25] FIG. 1 is a circuit block diagram illustrating an example of a semiconductor device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] Hereinafter, an embodiment will be described with reference to the drawings. However, the embodiment may be different from the embodiment. The present invention can be implemented in any manner without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that various modifications may be made to the embodiments and details of the present invention. The present invention should not be construed as being limited to the description of the following embodiments.

[0026] In addition, in the drawings, the size, layer thickness, or area may be exaggerated for clarity. Therefore, the scale is not necessarily limited to that shown in the drawings. The above is a formula, and is not limited to the shapes or values ​​shown in the drawings. For example, Variations in signals, voltages, or currents due to timing differences, or variations in signals, voltages, Alternatively, it is possible to include current variation. In the drawings, the same reference numerals are used to designate the same parts or parts having similar functions. and the repeated explanation will be omitted.

[0027] (Embodiment 1) In this embodiment, a circuit configuration and a memory cell included in a semiconductor device according to one embodiment of the present invention will be described. The operation of the same will be described with reference to FIGS.

[0028] <<Example of memory cell configuration>> FIG. 1 is a circuit diagram of a memory cell 100 according to one embodiment of the present invention.

[0029] In the memory cell 100 shown in FIG. A transistor 103, a capacitor 104, a transistor 105, a capacitor 106, and a The memory cell 100 also has a bit line BL , power line SL, word line WLC1, word line WLOS1, word line WLC2 and word line Electrically connected to WLOS2.

[0030] The gate of the transistor 101 is electrically connected to the word line WLOS1. One of the source and drain of 101 is electrically connected to a bit line BL, The other of the source and drain of the transistor 101 is electrically connected to a node FN1. The second gate of the first gate electrode 101 is electrically connected to a wiring line through which a signal BG1 is applied.

[0031] The gate of the transistor 102 is electrically connected to the node FN1. One of the source and drain of the transistor 10 is electrically connected to the bit line BL. The other of the source and drain of transistor 2 is connected to one of the source and drain of transistor 103. are electrically connected.

[0032] The gate of the transistor 103 is electrically connected to the node FN2. The other of the source and drain is electrically connected to a power supply line SL.

[0033] One terminal of the capacitance element 104 is electrically connected to the word line WLC1. The other terminal is electrically connected to a node FN1.

[0034] The gate of the transistor 105 is electrically connected to the word line WLOS2. One of the source and drain of 105 is electrically connected to the bit line BL. The other of the source and drain of the transistor 105 is electrically connected to a node FN2. The second gate of the gate electrode 105 is electrically connected to a wiring to which a signal BG2 is applied.

[0035] One terminal of the capacitance element 106 is electrically connected to the word line WLC2. The other terminal of the transistor FN2 is electrically connected to a node FN2.

[0036] The node FN1 has a function of holding binary or multi-valued data. FN1 is M bit (2 M It has the function of storing data (value, M is a natural number greater than or equal to 1). Specifically, if the data is 2 bits, it can be expressed as 4 values ​​(2 2 ) data for four voltage levels It is a signal having either one of them.

[0037] Similarly, the node FN2 has a function of holding binary or multi-valued data. , node FN2 has N bits (2 N The function to hold data (value, N is a natural number greater than or equal to 1) Yes.

[0038] The M-bit data and the N-bit data are applied to bit lines. The data of the bit is provided from the bit line to the node FN1 through the transistor 101. The N-bit data is also transferred from the bit line to the node F via the transistor 105. Given to N2.

[0039] In this specification, the potential of the node FN1 or the node FN2 varies in response to the voltage of the bit line BL. The voltage of the bit line BL is set to the same value as the voltage of the bit line BL. The potential of the memory cell 10 corresponds to the potential of the node FN1 or the node FN2. It reads data from.

[0040] A write signal is applied to the word lines WLOS1 and WLOS2.

[0041] The write signal is a transistor for applying the potential of the bit line BL to the node FN1 or FN2. This is a signal that puts the transistor 101 or the transistor 105 into a conductive state.

[0042] A read signal is applied to the word lines WLC1 and WLC2.

[0043] A read signal is applied to one of the capacitive elements 104 to selectively read data from the memory cells. The signal is supplied to one terminal of the capacitance element 106 or one terminal of the capacitance element 106 .

[0044] The transistors 101 and 105 are assumed to be n-channel transistors. In addition, the transistors 102 and 103 are assumed to be p-channel transistors. This shall be the case.

[0045] The transistors 101 and 105 are switched between a conductive state and a non-conductive state to transmit and receive data. It functions as a switch to control writing. It also maintains a non-conducting state. The memory cell has a function of holding a potential based on the written data.

[0046] In addition, in the transistors 101 and 105, when in a non-conducting state, current flows between the source and drain. It is preferable to use a transistor having a low off-state current. A low channel current is defined as a current that is 10 V between the source and drain at room temperature. The normalized off-state current per 1 μm of width is 10 × 10 -21 This means that it is A or lower. As a transistor with such a low off-state current, a transistor having an oxide semiconductor in a semiconductor layer One example is the NGIS.

[0047] In the configuration of the memory cell 100 shown in FIG. 1, the non-conductive state is maintained, so that the written data is Therefore, the potential is maintained based on the capacitance of the nodes FN1 and FN2. Transistors with low off-state current are often used as switches to suppress fluctuations in the potential of Particularly preferred.

[0048] The transistors 102 and 103 are connected to the bit line BL according to the potentials of the nodes FN1 and FN2. It has the function of passing a current between the power supply line SL.

[0049] The transistors 102 and 103 are transistors with small variations in threshold voltage. Here, the transistor having a small variation in threshold voltage is preferably a transistor having a small variation in threshold voltage. When transistors are manufactured using the same process, the allowable difference in threshold voltage is within 100 mV. Specifically, the channel is made of single crystal silicon. Examples of such transistors include:

[0050] The second gates of the transistors 101 and 105 are or a function of controlling the threshold voltage of the transistors 101 and 105, However, in some cases it may be omitted.

[0051] <<Timing Chart>> Next, an example of the operation of the memory cell 100 will be explained with reference to the timing charts of FIGS. Reveal.

[0052] The timing charts shown in FIGS. 2 and 3 are for the bit line BL and the power supply line S of the memory cell 100. L, word line WLOS1, word line WLC1, node FN1, word line WLOS2, 2 shows the potential changes of the node WLC2 and the node FN2. FIG. 3 shows a timing chart for writing data to the memory cell 100 shown in FIG. 4 shows a timing chart for reading out the stored data.

[0053] In FIG. 2 and FIG. 3, the power supply line SL and the word lines WLOS1 and WLOS2 are connected to a high power supply potential. and potential V H1 is given, and potential V GND The potential V GND The potential V H1 H level potential, potential V GN D is sometimes called the L level potential. V GND potential lower than -V L1 The potential -V L1 is a negative potential ( -V L1 <0V).

[0054] 2 and 3, the word lines WLC1 and WLC2 are connected to a high power supply potential V H2 but is given as the low power supply potential, V GND The potential V GND Ground The potential V H2 H level potential, potential V GND L level potential Furthermore, the word lines WLC1 and WLC2 are connected to a potential V GND Lower voltage than Place-V L2 The potential -V L2 is a negative potential (-V L2 <0V) It is preferable that

[0055] Write Operation The write operation of the memory cell 100 will be described with reference to the timing chart of FIG. cormorant.

[0056] FIG. 2 is composed of four periods p0 to p3. Period p0 is the initial period, period p1 is the normal period, and period p1 is the period for writing data to node FN1, period p2 is the period for writing data to node FN2, The period p3 represents the period during which the written data is retained. Times T0 to T8 are added to explain the timing of the operations.

[0057] First, during the period p0, the bit line BL is V GND The power supply line SL is initialized to V GND The word line WLOS1 is given a potential of L level, and the word line WLC1 is given a potential of H level. A potential of the L level is applied to the word line WLOS1, a potential of the L level is applied to the word line WLC 2 is given a high level potential.

[0058] Next, at time T0, the potential of the word line WLOS1 changes from L level to H level, The potential of the word line WLC1 changes from H level to L level. At this time, the transistor 101 is turned on, the connection between the bit line BL and the node FN1 is made conductive, and the node F N1 is the potential V GND is initialized to .

[0059] Next, at time T1, a potential V1 is applied to the bit line BL, and the bit line BL is electrically connected to the The potential V1 is also written to a node FN1 located at the node FN2.

[0060] In the timing charts of Figures 2 and 3, the hatched areas indicate The potential of the chip pattern is given in a given range, i.e., multi-value data is given. For example, when writing 4 bits of data to node FN1, , potential V1 is 2 4 =16 potential values ​​can be obtained.

[0061] Next, at time T2, the potential of the word line WLOS1 is set to the L level, and the transistor 101 After turning off, at time T3, the potential of the bit line BL is set to V GND Initialize to At this time, the node FN1 is in an electrically floating state and holds the potential V1.

[0062] Next, at time T4, the potential of the word line WLC1 is set to the H level, and the node The potential of the FN1 terminal is V1+V H2 By keeping the potential of the node FN1 high, The p-channel transistor 102 is kept off, and a line is formed between the bit line BL and the power supply line SL. At the same time, the potential of the word line WLOS2 is set to the L level. The potential of the word line WLC1 is changed from the high level to the low level. At this time, the transistor 105 is turned on and the node FN2 is initialized.

[0063] In order to transmit the potential of the word line WLC1 to the node FN1 through the capacitor 104, The capacitance of the capacitor 104 is sufficiently larger than the gate capacitance of the transistor 101, and It is preferable that the capacitance of the capacitor 104 is sufficiently larger than the gate capacitance of the transistor 102. In this embodiment, for the sake of simplicity, the potential applied to the word line WLC1 is It is transmitted directly to the node FN1 (for example, when the word line WLC1 is applied with a potential V H2 If you give The potential of node FN1 changes from potential V1 to potential V1+V H2 However, the capacity Capacitance of element 104, gate capacitance of transistor 101, and gate capacitance of transistor 102 Depending on the magnitude relationship, the potential applied to the word line WLC1 may be directly transmitted to the node FN1. This may not be possible.

[0064] Next, at time T5, the bit line BL is supplied with the potential V2, and the node FN2 is supplied with the potential V2. Note that multi-value data is given to the potential V2. For example, When writing 4-bit data, the potential V2 is 2 4 = 16 potential values ​​are possible Cut.

[0065] Next, at time T6, the potential of the word line WLOS2 is changed from H level to L level. At time T7, the transistor 105 is turned off, and the potential of the bit line BL is set to V GND Initialize to At this time, the node FN2 is electrically floating and therefore holds the potential V2.

[0066] Next, at time T8, the potential of the word line WLC2 is changed from the L level to the H level. This causes the potential of node FN2 to be V2+V H2 The potential of node FN2 is kept high. As a result, the p-channel transistor 103 remains off, and the power supply line BL is Prevents leakage current from flowing to SL.

[0067] In order to transmit the potential of the word line WLC2 to the node FN2 through the capacitor 106, The capacitance of the capacitor 106 is sufficiently larger than the gate capacitance of the transistor 105, and It is preferable that the capacitance of the capacitor 106 is sufficiently larger than the gate capacitance of the transistor 103. In this embodiment, for the sake of simplicity, the potential applied to the word line WLC2 is It is transmitted directly to the node FN2 (for example, the word line WLC2 is supplied with a potential V H2 If you give The potential of node FN2 changes from potential V2 to potential V2+V H2 However, the capacity Capacitance of element 106, gate capacitance of transistor 105, and gate capacitance of transistor 103 Depending on the magnitude relationship, the potential applied to the word line WLC2 may be transmitted directly to the node FN2. This may not be possible.

[0068] In a period p3 after time T8, the data written to the nodes FN1 and FN2 is Each is retained.

[0069] As described above, by the write operation explained in the timing chart of FIG. 2, the nodes FN1 and FN2 Multi-value data can be written to the

[0070] During the period p1, the potential V H1 is connected to potential V1. It is preferable that the potential is higher than the potential obtained by adding the threshold voltage of the transistor 101. For example, If the potential V1 is 3 V, and the threshold voltage of the transistor 101 is 1 V, then the potential V H 1 is preferably 4V (3V+1V) or more. This is because When writing a potential of 3V to FN1, if the potential of the word line WLOS1 is less than 4V, Before the potential on board FN1 reaches 3V, the potential between the gate and source of transistor 101 Difference (V GS ) becomes equal to or lower than the threshold voltage, the transistor 101 is turned off, and the node FN1 This is because a potential of 3V cannot be written.

[0071] Similarly, during the period p2, the potential V H1 is at potential V2 It is preferable that the potential be higher than the potential plus the threshold voltage of the transistor 105 .

[0072] In this specification, V GS is the voltage between the gate and source with respect to the source. For example, if a potential of 1 V is applied to the source and 3 V to the gate, then V G S is 2V. For example, if a potential of 3V is applied to the source and 1V to the gate, V GS is -2V.

[0073] Read Operation The data written in the memory cell 100 is read according to the timing chart of FIG. The operation will now be described.

[0074] FIG. 3 is composed of four periods p3 to p6. Period p3 is a derivation from period p3 in FIG. The period p1 is the period during which the data of node FN1 is continuously held, the period p2 is the period during which the data of node FN2 is read, and the period p3 is the period during which the data of node FN3 is read. Period p5 is the period during which data from node FN2 is read, and period p6 is the period during which the data is held. In addition, times T9 to T13 shown in FIG. 3 are used to explain the operation timing. This is attached.

[0075] First, at time T9, the bit line BL is at a potential V BL is charged (precharged).

[0076] Next, at time T10, the bit line BL is set to an electrically floating state. The line BL is in a state where the potential fluctuates due to charging or discharging of electric charges. This state is called the bit line This is achieved by turning off the switch that applies potential to the BL.

[0077] At time T10, the potential of the word line WLC1 drops from H level to L level. Due to the coupling, the potential of node FN1 is also V1+V H2 The potential at node F drops to the potential V1. When the potential of N1 decreases, the V GS The absolute value of is large At the same time, the potential of the word line WLC2 becomes H level. potential -V L2 Due to capacitive coupling, the potential of node FN2 also drops to potential V2+V H 2 to potential V2-V L2 When the potential of the node FN2 decreases, a p-channel V of transistor 103 GS The absolute value of becomes large, and the transistor 103 turns on. When both transistors 102 and 103 are turned on, the bit line BL and the power supply The line SL is conductive, current flows, the bit line BL is discharged, and the bit line BL The potential of decreases.

[0078] When the potential of the bit line BL decreases due to discharge, the V GS and the absolute value of V of transistor 103 GS The absolute values ​​of both decrease. V GS When the voltage of the transistor reaches the threshold voltage, the discharge is completed and the bit The potential of the line BL converges to a constant potential. During the period p4, the potential of the node FN2 is higher than that of the node FN1. Since a lower potential is applied to the transistor 103 than to the transistor 102, Rimo, V GSIn other words, the absolute value of the transistor 103 is larger than that of the transistor 102. The channel resistance is lower and the on-current is larger than that of the bit line BL. and the V of transistor 102 GS reaches its threshold voltage first, and transistor 102 will be turned off first.

[0079] When the transistor 102 is turned off, the bit line BL converges to a constant potential (potential V1'). This potential V1' is approximately equal to the potential of the node FN1, and is set to the threshold voltage of the transistor 102. That is, the potential V1' of the bit line BL is the higher potential of the node FN1. By using this difference in potential to judge the data, The multi-level data written in the code FN1 can be read out.

[0080] At time T10, the potential of the word line WLOS2 is changed from the L level to −V L1 Change it to As a result, the potential change of the bit line BL or the node FN2 causes the transistor 1 This prevents the 05 from turning on.

[0081] Next, at time T11, the potential of the bit line BL is again set to the potential V BL Restore it to Precha At the same time, the potentials of all the word lines and the nodes FN1 and FN2 are maintained for a period p 3, turning off transistors 102 and 103.

[0082] Next, at time T12, the bit line BL is set to an electrically floating state. This is achieved by turning off the switch that applies potential to line BL.

[0083] At time T12, the potential of the word line WLC1 changes from the H level to the potential −V L2 Change to At this time, the potential of the word line WLC2 changes from H level to L level. The potential of node FN1 is V1+V H2 to potential V1-V L2 and node F The potential of N2 is V2+V H2 to potential V2. As a result, the transistor 10 2, 103 are turned on, the bit line BL and the power supply line SL are in a conductive state, and the bit line B L discharges the charge, and the potential of the bit line BL drops.

[0084] In the period p5, a lower potential is applied to the node FN1 than to the node FN2. Transistor 102 has a higher V GS The absolute value of is large. The transistor 102 has a lower channel resistance than the transistor 103, and the on-state current Therefore, when the bit line BL starts to discharge, the V GS It is better to The threshold voltage is reached first, and transistor 103 turns off first.

[0085] When the transistor 103 is turned off, the bit line BL converges to a constant potential (potential V2'). The potential V2' is approximately equal to the potential of the node FN2, and is set to the threshold voltage of the transistor 103. That is, the potential V2' of the bit line BL is the higher potential of the node FN2. By using this difference in potential to judge the data, The multi-level data written in the code FN2 can be read out.

[0086] At time T12, the potential of the word line WLOS1 is changed from the L level to −V L1Change it to As a result, the potential change of the bit line BL or the node FN2 causes the transistor 1 This prevents the 05 from turning on.

[0087] Next, at time T13, the bit line BL is set to V GND All word lines, no The potentials of the electrodes FN1 and FN2 are returned to the state in period p3, and the transistors 102 and 103 are turned off. This holds the potentials of the nodes FN1 and FN2.

[0088] As described above, by the read operation explained in the timing chart of FIG. 3, the nodes FN1 and FN2 It is possible to read multi-level data written in the memory.

[0089] For example, 8-bit data, that is, 256 (=2 8 ) potential is written to one node. In this case, if the width of the potential of one value is 0.17V, the data is retained. The range of potentials applied to the nodes is 0.17V x 256 = 43.52V. To store 8 bits of data in one node, a power supply potential of approximately 45V is applied to the memory cell. However, this power supply potential is not practical because it can destroy transistors. It is not a reasonable value.

[0090] On the other hand, when 8-bit data is written to the memory cell 100 shown in this embodiment, The bit data is divided into two, 4-bit data and 4-bit data, and one is FN1 and the other can be stored in node FN2. 4 )value If the potential width of one value is 0.17V, then one node will bear the potential of The potential difference between the two nodes is 0.17V x 16 = 2.72V. This is a realistic value for driving a memory cell.

[0091] As described above, by using the memory cell 100 according to one embodiment of the present invention, 8-bit data can be stored. It is possible to provide a semiconductor device that stores information.

[0092] In addition, the number of bits of data that the memory cell 100 can store is not limited to 8 bits, and various For example, node FN1 can store M bits (2 M value) data, and store N bits (2 N If you save the value, Cell 100 is M+N bits (2 M+N This makes it possible to store data (values).

[0093] The memory cell 100 in FIG. 1 includes a transistor 101, A common signal BG may be applied to the second gate of 105 .

[0094] The memory cell 100 of FIG. 1 may be configured as shown in the circuit diagram of FIG. The circuit diagram shown in FIG. 1 has two bit lines BL1 and BL2, and a transistor 1 The fact that transistor 01 and transistor 105 are connected to a common word line WLOS is the same as the circuit in FIG. In addition, the second gate and the second gate of the transistor 101 shown in FIG. A common signal may be applied to the second gate of the first gate 105 in the same manner as in FIG. In some cases, these second gates may be omitted.

[0095] The memory cell 100 of FIG. 1 may be configured as shown in the circuit diagram of FIG. The circuit diagram shown in FIG. 1 includes a transistor 107, a capacitor 108, a transistor 109, and a node F 1 in that it has word lines N3, WLOS3, and WLC3. In addition, the second gate of the transistor 101 and the second gate of the transistor 105 shown in FIG. The second gate of the transistor 105 and the second gate of the transistor 107 are connected to a common Alternatively, these second gates may be omitted in some cases.

[0096] Note that the configurations, methods, and the like described in this embodiment may be used in conjunction with the configurations, methods, and the like described in other embodiments. They can be used in any suitable combination.

[0097] (Embodiment 2) In this embodiment, a circuit configuration and a memory cell included in a semiconductor device according to one embodiment of the present invention will be described. The operation thereof will be described with reference to FIGS.

[0098] Example of memory cell configuration FIG. 4 is a circuit diagram of a memory cell 110 according to one embodiment of the present invention.

[0099] In the memory cell 110 shown in FIG. 4, a transistor 101, a transistor 112, and a transistor A transistor 113, a capacitor 104, a transistor 105, a capacitor 106, and a The memory cell 110 has a bit line BL , power line SL, word line WLC1, word line WLOS1, word line WLC2 and word line Electrically connected to WLOS2.

[0100] The memory cell 110 is the same as the memory cell 100 shown in the first embodiment except for the transistors 102 and 10 3 is replaced with n-channel transistors 112 and 113. Hereinafter, transistors 101, 112, 113, and 105 are n-channel transistors. I will give an explanation as a star.

[0101] The transistors 112 and 113 are connected to the bit line BL according to the potentials of the nodes FN1 and FN2. It has the function of passing a current between the power supply line SL.

[0102] The transistors 112 and 113 are transistors with small variations in threshold voltage. Here, the transistor having a small variation in threshold voltage is preferably a transistor having a small variation in threshold voltage. When transistors are manufactured using the same process, the allowable difference in threshold voltage is within 100 mV. Specifically, the channel is made of single crystal silicon. Examples of such transistors include:

[0103] For details regarding the other components of memory cell 110, please refer to the description of memory cell 100. That's good.

[0104] <Timing Chart> Next, an example of the operation of the memory cell 110 will be explained with reference to the timing charts of FIGS. Reveal.

[0105] The timing charts shown in FIGS. 5 and 6 are for the bit line BL and the power supply line S of the memory cell 110. L, word line WLOS1, word line WLC1, node FN1, word line WLOS2, 5 shows the potential changes of the node WLC2 and the node FN2. 6 shows a timing chart for writing data to the memory cell 110 in FIG. 4 shows a timing chart for reading out the stored data.

[0106] 5 and 6, the power supply line SL is connected to a potential V H0 Given the low power Potential as potential V GND The potential V GND is also at ground potential GND. Also, the potential V H0 H level potential, potential V GND is sometimes called the L level potential .

[0107] 5 and 6, the word lines WLOS1 and WLOS2 are set to a high power supply potential. The potential V H1 is given, and potential V GND The potential V G ND The potential V H1 H level potential, potential V GND is also called the L level potential. is the potential V GND potential lower than -V L1 The potential -V L1 is negative potential (-V L1 <0V).

[0108] 5 and 6, a high power supply potential is applied to the word lines WLC1 and WLC2. Place V H2 is given, and potential V GND The potential V GND The potential V H2 H level potential, potential V GND L In addition, the word lines WLC1 and WLC2 are applied with a potential V GND potential lower than -V L2The potential -V L2 is a negative potential (- V L2 <0V).

[0109] Write Operation An example of a write operation of the memory cell 110 will be described with reference to the timing chart of FIG. Make a statement.

[0110] FIG. 5 is composed of four periods p0 to p3. Period p0 is the initial period, period p1 is the normal period, and period p1 is the period for writing data to node FN1, period p2 is the period for writing data to node FN2, The period p3 represents the period during which the written data is retained. Times T0 to T8 are added to explain the timing of the operations.

[0111] First, during the period p0, the bit line BL and the power supply line SL are at a potential V GND It is initialized to The potential of the power line WLOS1 is -V L1 is applied to the word line WLC1, and a potential of -V L2 Given The word line WLOS2 is then at a potential of -V L1 is applied to the word line WLC2, and a potential of −V L2 but Given.

[0112] Next, at time T0, a high-level potential is applied to the word line WLOS1, and the word line W An L level potential is applied to LC1. At this time, the transistor 101 is turned on, and The bit line BL and the node FN1 are in a conductive state, and the node FN1 is at the potential V GND is initialized to do.

[0113] Next, at time T1, a potential V1 is applied to the bit line BL, and the bit line BL is electrically connected to the A potential V1 is written to a node FN1 located at

[0114] In the timing charts of Figures 5 and 6, the hatched areas indicate The potential of the chip pattern is given in a given range, i.e., multi-value data is given. For example, when 4 bits of data are written to node FN1, In this case, the potential V1 is 2 4 =16 potential values ​​can be obtained.

[0115] At time T1, in order to keep the transistor 112 off, the power supply line SL is At this time, the potential V H0 is a bit It is preferable that the potential V is higher than the potential V1 applied to the line BL and the node FN1. H0 but By satisfying the above conditions, the V GS can be kept at 0V.

[0116] Next, at time T2, a low-level potential is applied to the word line WLOS1, and the transistor The controller 101 turns off.

[0117] Next, at time T3, the bit line BL and the power supply line SL are at a potential V GND is initialized to . At this time, the node FN1 is in an electrically floating state and holds the potential V1.

[0118] Next, at time T4, a high-level potential is applied to the word line WLOS2, and the word line W At this time, the transistor 105 is turned on, and the The bit line BL and node FN2 are in a conductive state, and node FN2 is at the potential V GND is initialized to do.

[0119] At time T4, the word line WLC1 is set to a potential of −V L2 Given that node FN1 has Potential V1-V L2 When the potential of the node FN1 is kept low, an n-channel The transistor 112 remains off, preventing leakage current flowing between the bit line BL and the power supply line SL. At this time, in order to prevent the transistor 101 from being turned on, the potential - V L1 is applied to word line WLOS1.

[0120] Note that the potential of the word line WLC1 is transmitted to the node FN1 through the capacitor 104. The capacitance of the capacitor 104 is sufficiently larger than the gate capacitance of the transistor 101, and It is preferable that the capacitance of the capacitor 104 is sufficiently larger than the gate capacitance of the transistor 112. In this embodiment, for the sake of simplicity, the potential applied to the word line WLC1 is The potential of the word line WLC1 is directly transmitted to the node FN1 (for example, the potential of the word line WLC1 is V GND From Place-V L2 When the potential of the node FN1 changes from the potential V1 to the potential V1-V L2 Change to The capacitance of the capacitor 104, the gate capacitance of the transistor 101, and the Depending on the magnitude relationship with the gate capacitance of the transistor 112, There are cases where the potential is not transmitted directly to the node FN1.

[0121] Next, at time T5, the bit line BL is supplied with the potential V2, and the node FN2 is supplied with the potential V2. The potential V2 can have multiple values. For example, 4-bit data When is written to node FN2, the potential V2 is 2 4= 16 potential values ​​are possible can.

[0122] At time T5, in order to keep the transistor 113 off, the power supply line SL is At this time, the potential V H0 Is, bit It is preferable that the potential V is higher than the potential V2 applied to the line BL and the node FN1. H0 By satisfying the above condition, the V GS is kept at 0V.

[0123] Next, at time T6, a low-level potential is applied to the word line WLOS2, and the transistor The controller 105 is turned off.

[0124] Next, at time T7, the bit line BL and the power supply line SL are at a potential V GND is initialized to . At this time, the node FN2 is in an electrically floating state and therefore holds the potential V2.

[0125] Next, at time T8, the word line WLC2 is set to a potential of −V L2 is given, and at node FN2, Potential V2-V L2 When the potential of the node FN2 is kept low, an n-channel The transistor 113 remains off, preventing leakage current flowing between the bit line BL and the power supply line SL. The current is cut off. Also, the word line WLOS2 is set to a potential of -V L1 Given that transistor 1 This prevents the 05 from turning on.

[0126] Note that the potential of the word line WLC2 is transmitted to the node FN2 through the capacitor 106. The capacitance of the capacitor 106 is sufficiently larger than the gate capacitance of the transistor 105, and It is preferable that the capacitance of the capacitor 106 is sufficiently larger than the gate capacitance of the transistor 113. In this embodiment, for the sake of simplicity, the potential applied to the word line WLC2 is The potential of the word line WLC2 is transmitted to the node FN2 as it is (for example, the potential of the word line WLC2 is V GND From Place-V L2 When the potential of the node FN2 changes from the potential V2 to the potential V2-V L2 Change to However, the capacitance of the capacitor 106, the gate capacitance of the transistor 105, Depending on the magnitude relationship with the gate capacitance of the transistor 113, In some cases, the potential thus obtained may not be transmitted directly to the node FN2.

[0127] In a period p3 after the time T8, the data written to the nodes FN1 and FN2 are The data is stored respectively.

[0128] As described above, by the write operation explained in the timing chart of FIG. Multi-value data can be written to FN2.

[0129] During the period p1, the potential V H1 is connected to potential V1. It is preferable that the potential be higher than the potential obtained by adding the threshold voltage of the transistor 101 .

[0130] Similarly, during the period p2, the potential V H1 is at potential V2 It is preferable that the potential be higher than the potential plus the threshold voltage of the transistor 105 .

[0131] Read Operation The data written in the memory cell 110 is read according to the timing chart of FIG. The operation will now be described.

[0132] FIG. 6 is composed of four periods p3 to p6. Period p3 is a derivation from period p3 in FIG. The period p1 is the period during which the data of node FN1 is continuously held, the period p2 is the period during which the data of node FN2 is read, and the period p3 is the period during which the data of node FN3 is read. Period p5 is the period during which data from node FN2 is read, and period p6 is the period during which the data is held. In addition, times T9 to T15 shown in FIG. 6 are used to explain the operation timing. This is attached.

[0133] First, at time T9, a low-level potential is applied to the word line WLOS1. A low-level potential is applied to LC1, and the potential of node FN1 becomes the potential V1- V L2 When the potential of the node FN1 is raised to the potential V1, V of the transistor 112 GS becomes large and transistor 112 turns on.

[0134] At time T9, the word line WLOS2 is given an L-level potential, and the word line WLC 2 is given a high-level potential, and the potential of node FN2 becomes the potential V2-V L 2 to potential V2+V H2 When the potential of the node FN2 is raised, V of the 113-channel transistor GS becomes large and transistor 113 turns on. do.

[0135] Next, at time T10, the bit line BL is electrically floating. The line BL is in a state where the potential fluctuates due to charging or discharging of electric charges. This state is called the bit line This can be achieved by turning off the switch that applies potential to the BL.

[0136] At time T10, a high-level potential is applied to the power supply line SL. When a potential is applied to the bit line BL, a potential difference occurs between the bit line BL and the power supply line SL. A current flows from the bit line BL to the bit line BL. The bit line BL is charged, and the potential of the bit line BL rises. do.

[0137] When the potential of the bit line BL rises due to charging, the V GS And, Transi Sta 113 V GS The V of either transistor drops. GS But, When the voltage of the transistor becomes equal to its threshold voltage, the charging is completed and the potential of the bit line BL becomes equal to In the period p4, a higher potential is applied to the node FN2 than to the node FN1. Therefore, transistor 113 has a higher V GS is large That is, the transistor 113 has a lower channel resistance than the transistor 112. The on-state current is large. Therefore, when the bit line BL starts to charge, the V GS reaches its threshold voltage first, and transistor 112 turns off first.

[0138] When the transistor 112 is turned off, the bit line BL converges to a constant potential (potential V1'). This potential V1' is approximately equal to the potential of the node FN1, and is set to the threshold voltage of the transistor 112. That is, the potential V1' of the bit line BL is the higher potential of the node FN1. This difference in potential is used to determine the data, and the node FN Multi-value data written to 1 can be read out.

[0139] Next, at time T11, the bit line BL and the power supply line SL are set to a potential V GND is initialized to .

[0140] Next, at time T12, a high-level potential is applied to the word line WLC1, and Therefore, the potential of the node FN1 changes from potential V1 to potential V1+V H2 At the same time, Then, the word line WLC2 is given a low-level potential, and the potential of the node FN2 becomes a potential V2+V H2 The transistors 112 and 113 are both turned on. do.

[0141] Next, at time T13, the bit line BL is brought into an electrically floating state.

[0142] At the same time, at time T13, a high-level potential is applied to the power supply line SL. When the potential becomes H level, a potential difference occurs between the bit line BL and the power supply line SL. A current flows from the bit line BL to the bit line BL. The bit line BL is charged, and the potential of the bit line BL rises. do.

[0143] When the potential of the bit line BL rises due to charging, the V GS And, Transi Sta 113 V GS The V of either transistor drops. GS But, When the voltage of the transistor becomes equal to its threshold voltage, the charging is completed and the potential of the bit line BL becomes equal to In the period p5, a higher potential is applied to the node FN1 than to the node FN2. transistor 112 has a higher V GS It is big. That is, the transistor 112 has a lower channel resistance than the transistor 113, and The current is large. Therefore, when the bit line BL starts to charge, the V GS reaches its threshold voltage first, and transistor 113 turns off first.

[0144] When the transistor 113 is turned off, the bit line BL converges to a constant potential (potential V2'). This potential V2' is approximately equal to the potential of the node FN2, and is set to the threshold voltage of the transistor 113. That is, the potential V2' of the bit line BL is the higher potential of the node FN2. By using this difference in potential to judge the data, The multi-level data written in the code FN2 can be read out.

[0145] Next, at time T14, the bit line BL and the power supply line SL are set to the potential V GND is initialized to .

[0146] Next, at time T15, the same potential as that in the period p3 is applied to all the wirings and nodes in FIG. The potentials of the nodes FN1 and FN2 are held.

[0147] As described above, by the read operation explained in the timing chart of FIG. 6, the nodes FN1 and FN2 It is possible to read multi-level data written in the memory.

[0148] For example, 8-bit data, that is, 256 (=2 8 ) potential is written to one node. In this case, if the width of the potential of one value is 0.17V, the data is retained. The range of potentials applied to the nodes is 0.17V x 256 = 43.52V. To store 8 bits of data in one node, a power supply potential of approximately 45V is applied to the memory cell. However, this power supply potential is not practical because it can destroy transistors. It is not a reasonable value.

[0149] On the other hand, when 8-bit data is written to the memory cell 110 shown in this embodiment, The bit data is divided into two, 4-bit data and 4-bit data, and one is FN1 and the other can be stored in node FN2. 4 )value If the potential width of one value is 0.17V, then one node will bear the potential of The potential difference between the two nodes is 0.17V x 16 = 2.72V. This is a realistic value for driving a memory cell.

[0150] As described above, by using the memory cell 110 according to one embodiment of the present invention, 8-bit data can be stored. It is possible to provide a semiconductor device that can store data. The number of data bits is not limited to 8 bits, and data of various bit numbers can be stored. For example, node FN1 has M bits (2 M value) data, and the node FN 2 to N bits (2 N When M+N bits (2 values) are stored in the memory cell 110, M+N This makes it possible to store data (values).

[0151] The memory cell 110 in FIG. 4 includes a transistor 101, A common signal BG may be applied to the second gate of 105 .

[0152] The memory cell 110 of FIG. 4 may be configured as shown in the circuit diagram of FIG. The circuit diagram shown in FIG. 1 has two bit lines BL1 and BL2, and a transistor 1 The fact that transistor 01 and transistor 105 are connected to a common word line WLOS is the circuit of FIG. In addition, the second gate and the second gate of the transistor 101 shown in FIG. A common signal may be applied to the second gate of the first gate 105 in the same manner as in FIG. In some cases, these second gates may be omitted.

[0153] The memory cell 110 of FIG. 4 may be configured as shown in the circuit diagram of FIG. The circuit diagram shown in FIG. 1 includes a transistor 107, a capacitor 108, a transistor 114, and a node F 4 in that it has word lines N3, WLOS3, and WLC3. In addition, the second gate of the transistor 101 and the second gate of the transistor 105 shown in FIG. The second gate of the transistor 105 and the second gate of the transistor 107 are connected to a common Alternatively, these second gates may be omitted in some cases.

[0154] Note that one embodiment of the present invention has been described in this embodiment. An embodiment of the present invention will be described below. However, the embodiment of the present invention is not limited to these. For example, although an example in which the present invention is applied to a memory cell has been described, One aspect of the invention is not limited to this. In some cases or depending on the situation, the present invention An aspect of the present invention does not have to be applied to memory cells. For example, an aspect of the present invention may be applied to memory cells that have another function. The present invention may be applied to a circuit having

[0155] Note that the configurations, methods, and the like described in this embodiment may be used in conjunction with the configurations, methods, and the like described in other embodiments. They can be used in any suitable combination.

[0156] (Embodiment 3) In this embodiment, a semiconductor device capable of performing the driving method described in the first embodiment is An example will be described with reference to the drawings.

[0157] <Configuration Example of Semiconductor Device> FIG. 7 shows a configuration example of a semiconductor device having the memory cell 100 described in the first embodiment. FIG.

[0158] The semiconductor device 500 shown in FIG. 7 is a memory device including a plurality of the memory cells 100 described with reference to FIG. A recell array 501, a row selection driver 502, a column selection driver 503, and an A / D converter The semiconductor device 500 has m rows (m is a natural number of 2 or more) and n columns (n The memory cells 100 are arranged in a matrix of 100 x 100 (wherein n is a natural number of 2 or more). In this case, the word line WLO is connected to the memory cell 100 in the (m-1)th row. S1[m-1], word line WLC1[m-1], word line WLOS2[m-1], word A line WLC2[m-1] is shown as a word line connected to the memory cell 100 in the mth row. Word line WLOS1[m], word line WLC1[m], word line WLOS2[m], The bit line BLC2[m] is connected to the memory cell 100 in the (n-1)th column. L[n-1] denotes the bit line BL[n] connected to the memory cell 100 in the nth column, (n -1) A power supply line SL connected to the memory cell 100 in the th column and the memory cell 100 in the nth column This shows that.

[0159] The memory cell array 501 shown in FIG. 7 includes the memory cells 100 described with reference to FIG. The components of the memory cell 100 are the same as those shown in FIG. 4 is used, so the explanation will be omitted.

[0160] In the memory cell array 501 shown in FIG. 7, adjacent memory cells share a power supply line SL. By adopting this configuration, the area that was previously occupied by the power supply line SL is reduced. Therefore, in a semiconductor device employing this configuration, The storage capacity can be improved.

[0161] The row select driver 502 selects the transistors 101 and 102 in each row of memory cells 100. 100 in each row. The circuit has a function of selectively changing the potentials of the nodes FN1 and FN2. By including the driver 502, the semiconductor device 500 can write data to the memory cell 100. The data can be read and written selectively on a row-by-row basis.

[0162] The column select driver 503 selects the nodes FN1 and FN 2, a function to initialize the potential of the bit line BL, and Specifically, the bit line B L, a potential corresponding to multi-value data and a potential V GND In a circuit that provides a current through a switch, By providing the column selection driver 503, the semiconductor device 500 can Data can be written and read by selecting each column.

[0163] The A / D converter 504 converts the potential of the bit line BL, which is an analog value, into a digital value. Specifically, a flash-type A / D converter is used. By including the A / D converter 504, the semiconductor device 500 The potential of the bit line BL corresponding to the data read from the memory cell 100 is output to the outside. It is possible.

[0164] Although the A / D converter 504 will be described as a flash type A / D converter, A successive approximation type, multi-slope type, or delta-sigma type A / D converter may also be used.

[0165] FIG. 8 shows a configuration in which the memory cell 100 in FIG. 7 is replaced with the memory cell 110 described in the second embodiment. For details, please refer to the description in FIG.

[0166] The semiconductor device 500 shown in FIGS. 7 and 8 may be configured as shown in the block diagram of FIG. The block diagram shown in FIG. 24 shows that the second gates of the transistors connected to the same word line are The transistor connected to the word line WLOS1[m-1] is The second gate of the transistor is connected to a wiring to which a signal BG1[m-1] is applied. The second gate of the transistor connected to the word line WLOS2[m-1] receives the signal BG2 [m-1] is connected to the wiring to which the word line WLOS1[m] is connected. The second gate of the transistor is connected to a wiring to which a signal BG1[m] is applied. The second gate of the transistor connected to the word line WLOS2[m] receives the signal BG2[m ] is connected to the wiring that receives the signal BG1[m-1] and the signal BG2[m-1]. The signals BG1[m] and BG2[m] may be the same signal or different signals. m] may be a common signal or may be different signals.

[0167] The semiconductor device 500 shown in FIGS. 7 and 8 may be configured as shown in the block diagram of FIG. In the block diagram shown in FIG. 25, all the second gates included in the memory cell array 501 are A common signal BG is applied to the common wiring.

[0168] Example of row selection driver configuration FIG. 9 is a block diagram showing an example of the configuration of the row selection driver 502 described with reference to FIGS. .

[0169] The row selection driver 502 shown in FIG. 9 includes a decoder 517 and a read / write control circuit. The read / write control circuit 518 controls the word lines WLOS1, WLC1, and W It is connected to LOS2 and WLC2 and provided for each row.

[0170] The decoder 517 has a function of outputting a signal for selecting a row to which a word line is provided. Specifically, an address signal Address is input, and the address signal A A circuit that selects a read / write control circuit 518 for any row according to the address. By providing a decoder 517, the row selection driver 502 can select an arbitrary row and Data can be written or read.

[0171] The read / write control circuit 518 controls the row having the word line selected by the decoder 517. , a function of outputting a write word signal and a function of selectively outputting a read word signal. Specifically, the read / write control circuit 518 is a circuit that includes a write control signal. Write_CONT and a read control signal Read_CONT are input. Therefore, it is a circuit that selectively outputs a write signal or a read signal. By providing a control circuit 518, the row selection driver 502 controls the row selection signal selected by the decoder 517. Either the write word signal or the read word signal on a row can be selected for output.

[0172] Example of column selection driver configuration FIG. 10 is a block diagram showing an example of the configuration of the column selection driver 503 described with reference to FIGS. do.

[0173] The column selection driver 503 shown in FIG. The circuit includes a converter 523, a switch circuit 524, and a transistor 526. The switch circuit 524 and the transistor are provided for each column. The resistor 526 is connected to the bit line BL.

[0174] The decoder 521 selects a column to which the bit line BL is provided and distributes the input data. Specifically, the address signal Address and the data Data is input, and the latch of one of the columns is selected according to the address signal Address. The decoder 521 is a circuit that outputs data to the circuit 522. The selection driver 503 can select any column to write data to.

[0175] The data Data input to the decoder 521 is k-bit digital data. A k-bit digital data is a signal represented by binary data of '1' or '0' for each bit. Specifically, for 2-bit digital data, the codes are '00', '01', and '1 The data is represented by '0' and '11'.

[0176] The latch circuit 522 is a circuit that has a function of temporarily storing input data. Specifically, when a latch signal W_LAT is input, the stored data Data is A flip-flop circuit outputs to the D / A converter 523 according to the latch signal W_LAT. By providing the latch circuit 522, the column selection driver 503 can Data can be written.

[0177] The D / A converter 523 converts the input digital data (Data) into an analog data (Data). Data V data Specifically, the D / A converter 523 is a circuit that has the function of converting If the number of bits of the data Data is 3 bits, then the potentials V0 to V7 are set to eight levels. The D / A converter 524 converts the digital signal into one of the three digital values ​​and outputs it to the switch circuit 524. 23, the column selection driver 503 selects data to be written to the memory cell 110 as follows: The potential can correspond to multi-value data.

[0178] The data V output from the D / A converter 523 data are expressed in different voltage values. In the case of 2-bit data, it is 0.5V, 1.0V, 1.5V, and 2.0V. The data is expressed as one of four voltage values.

[0179] The switch circuit 524 receives the input data V data to the bit line BL, and The circuit has the function of electrically floating the analog input and bit lines BL. The switch control signal Write_SW is used to control the Data V data The voltage is applied to the bit line BL and then the analog switch is turned off. By providing the switch circuit 524, the column selection driver 503 is Data V data After applying the voltage to the bit line BL, the bit line BL is set in an electrically floating state. The state can be maintained.

[0180] The transistor 526 is supplied with an initializing potential V GND to the bit line BL, The circuit has a function of electrically floating the bit line BL and the The potential V GND is applied to the bit line BL, and then A switch that makes the bit line BL electrically floating. The column selection driver 503 is connected to a potential V GND After applying to the bit line BL, It can be held electrically floating.

[0181] <Example of A / D converter configuration> FIG. 11 is a block diagram showing an example of the configuration of the A / D converter 504 described with reference to FIG.

[0182] The A / D converter 504 shown in FIG. The aforementioned circuits and transistors are connected to the column The buffer 534 for each column outputs data Dout.

[0183] The comparator 531 compares the potential of the bit line BL with the reference voltages Vref0 to Vref6. The potential of the bit line BL is compared to the high potential, and the potential of the bit line BL is determined to be one of the potentials corresponding to the multi-value data. Specifically, the circuit is provided with a plurality of comparators 531, Each comparator 531 receives the potential of the bit line BL and different reference voltages Vref0 to Vref6 is applied, and it is determined whether the potential of the bit line BL is between any of the potentials. By providing the comparator 531, the A / D converter 504 It is possible to determine whether the potential of BL corresponds to any one of the multi-value data.

[0184] As an example, the reference voltages Vref0 to Vref6 shown in FIG. This is the potential given when the data is one bit, i.e., eight values.

[0185] The encoder 532 judges the potential of the bit line BL output from the comparator 531. It is a circuit that has the function of generating a multi-bit digital signal based on a signal. , and encoding is performed based on the H level or L level signals output from the multiple comparators 531. The A / D converter 532 is a circuit that generates a digital signal. The converter 504 converts the data read from the memory cell 110 into digital value data. It is possible.

[0186] The latch circuit 533 is a circuit having a function of temporarily storing input digital value data. Specifically, a latch signal LAT is input, and the stored data is latched by the latch signal LAT. The latch circuit 53 is a flip-flop circuit that outputs to the buffer 534 according to the LAT. 3, the A / D converter 504 can output data at any timing. The latch circuit 533 can be omitted.

[0187] The buffer 534 amplifies the data output from the latch circuit 533 and outputs the output signal Dout Specifically, it is a circuit with an even number of inverter circuits. By providing the buffer 534, the A / D converter 504 converts the digital signal into It is possible to reduce noise in the signal. Note that the buffer 534 may be omitted.

[0188] As described above, the configurations, methods, etc. described in this embodiment may be used in conjunction with the configurations, methods, etc. described in other embodiments. They can be used in any suitable combination.

[0189] (Embodiment 4) In this embodiment, a semiconductor device capable of realizing the circuits of the memory cell 100 and the memory cell 110 is An example of the device will be described with reference to FIG.

[0190] <Configuration Example of Semiconductor Device> The semiconductor device shown in FIG. 12 includes a substrate 2000, a transistor 101, and a transistor 12. 2, a transistor 123, a transistor 105, a capacitance element 104, and a capacitance element 10 6, an insulating film 2001, an insulating film 2002, an insulating film 2003, an insulating film 2004, The insulating film 2005, the insulating film 2006, the insulating film 2007, the insulating film 2008, and the plug 21 01, plug 2102, plug 2103, plug 2104, plug 2105, A plug 2106, a plug 2107, a plug 2108, a wiring 2301, and a wiring 230 2, a wiring 2501, a wiring 2502, a conductive film 2701, and a conductive film 2702. is.

[0191] In the following description, when memory cell 100 is implemented as shown in FIG. is replaced with transistor 102, and transistor 123 is replaced with transistor 103. Similarly, when implementing memory cell 110 in FIG. Transistor 122 is replaced with transistor 112, and transistor 123 is replaced with transistor 11 Just replace it with 3.

[0192] The transistors 122 and 123 each include a gate electrode 2205, a gate insulating film 2204, and a sidewall an insulating layer 2206; an impurity region 2203 functioning as a source region or a drain region; As an LDD (Lightly Doped Drain) region or extension region It has a functioning impurity region 2202 and a channel forming region 2201 .

[0193] The capacitor 104 includes a first electrode 2401, a second electrode 2402, an insulating film 2403, and has.

[0194] The capacitor 106 includes a first electrode 2601, a second electrode 2602, an insulating film 2603, and has.

[0195] The conductive film 2701 is the same conductive film as the source electrode or the drain electrode of the transistor 101. The conductive film formed through the process of processing the semiconductor layer of the transistor 101 is The semiconductor layer is formed through a process of processing the dielectric layer.

[0196] The conductive film 2702 is the same conductive film as the source electrode or the drain electrode of the transistor 105. The conductive film formed through the process of processing the conductive film and the semiconductor layer of the transistor 105 are The semiconductor layer is formed through a process of processing the dielectric layer.

[0197] In FIG. 12, when multiple plugs exist in the same layer, only one representative plug is marked. Similarly, if there are multiple wirings in the same layer, In this case, a code is given to only one representative, and the others are used in combination. When multiple conductive films are present, a symbol is given to only one representative film, and the others are also used. .

[0198] FIG. 12 shows a bit line BL, a power supply line SL, a word line WLOS1, and a word line WLOS 2, the word line WLC1, and the word line WLC2 are connected to the terminals shown in FIG. is.

[0199] The semiconductor device shown in FIG. 12 includes transistors 122 and 123 provided on a substrate 2000. A capacitor 104 is provided on the transistors 122 and 123. A transistor 101 is provided, a transistor 105 is provided on the transistor 101, and a transistor A capacitance element 106 is provided on the transistor 105. The vertical relationship of these elements is as follows: For example, a capacitor 106 is provided over the transistor 101. A transistor 105 may be provided on 106 .

[0200] The substrate 2000 may be a single crystal semiconductor substrate made of silicon or silicon carbide, or a polycrystalline semiconductor substrate. semiconductor substrates, compound semiconductor substrates made of silicon germanium, and SOI (Silicon on Insulator) A semiconductor substrate may be used. The transistor thus formed can easily operate at high speed. When a silicon substrate is used, an impurity element that gives n-type is added to a part of the substrate 2000 to form an n-type A p-type transistor is formed in the region where the n-type well is formed. Impurity elements that give n-type conductivity include phosphorus (P) and arsenic (As). As an impurity element for imparting p-type conductivity, boron (B) or the like can be used. can.

[0201] The substrate 2000 may be an insulating substrate or a metal substrate on which a semiconductor film is provided. The substrates include stainless steel substrates, substrates with stainless steel foil, Examples of insulating substrates include tungsten substrates and substrates with tungsten foil. For example, glass substrates, quartz substrates, plastic substrates, flexible substrates, lamination films, Examples of the substrate include a glass substrate, a paper substrate containing a fibrous material, and a base film. For glass, barium borosilicate glass, aluminoborosilicate glass, or soda lime glass Examples of flexible substrates include polyethylene terephthalate (PET), poly Plastics such as ethylene naphthalate (PEN) and polyethersulfone (PES) The adhesive film can be made of a flexible synthetic resin such as acrylic. Examples include polypropylene, polyester, polyvinyl fluoride, or polyvinyl chloride. Examples of the base film include polyester, polyamide, polyimide, and a Examples include amide, epoxy, inorganic vapor deposition film, and paper.

[0202] Note that a semiconductor element is formed using a certain substrate, and then the semiconductor element is transferred to another substrate. Examples of the substrate onto which the semiconductor element is transferred include the above-mentioned substrates, as well as paper substrates, Polyimide film substrate, stone substrate, wood substrate, Fabric substrates (natural fibers (silk, cotton, linen), synthetic fibers (nylon, polyurethane, polyester) or recycled fibers (including acetate, cupra, rayon, recycled polyester, etc.) , leather substrate, or rubber substrate. By using these substrates, Formation of transistors, formation of transistors with low power consumption, manufacturing of durable devices, heat resistance It is possible to provide the device with improved durability, weight reduction, or thinness.

[0203] The transistors 122 and 123 preferably use a first semiconductor material for the channel. In addition, the transistors 101 and 105 preferably use a second semiconductor material for the channel. It is preferable that the first semiconductor material and the second semiconductor material have different forbidden band widths. For example, the first semiconductor material may be a semiconductor material other than an oxide semiconductor (silicon (strained silicon) (including gallium), germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum (e.g., tritium gallium arsenide, indium phosphide, gallium nitride, organic semiconductors, etc.), and the second The semiconductor material can be an oxide semiconductor. Single crystal silicon or the like can be used as the semiconductor material. The transistors used in this study can easily operate at high speed. The off-state current is small.

[0204] The transistors 101 and 105 will be described in detail in the fourth embodiment.

[0205] The transistors 122 and 123 may be transistors having silicide (salicide), A transistor without the sidewall insulating layer 2206 may be used. In the case of the structure having the above structure, the resistance of the source region and the drain region can be further reduced, and the semiconductor device In addition, since it can operate at a low voltage, the power consumption of the semiconductor device can be reduced. It is possible.

[0206] The transistors 122 and 123 are n-channel transistors or p-channel transistors. Either a transistor or a transistor having a proper function may be used depending on the circuit. The impurity concentration of the impurity region 2203 is higher than that of the impurity region 2202. 205 and the sidewall insulating layer 2206 are used as a mask to form the impurity region 2203 and the impurity Region 2202 may be formed in a self-aligned manner.

[0207] When a silicon-based semiconductor material is used for the transistors 122 and 123, the insulating film 2001 and The insulating film 2002 preferably contains hydrogen. By providing the insulating film on the semiconductor film, the hydrogen in the insulating film is oxidized by heat treatment. The ring bonds are terminated to improve the reliability of the transistors 122 and 123. can.

[0208] The insulating films 2001 and 2002 may be made of, for example, silicon oxide, silicon oxynitride, or silicon nitride. Silicon nitride, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide The insulating layer 10 may be formed of a single layer or a multilayer structure.

[0209] When an oxide semiconductor is used for the transistors 101 and 105, the insulating films 2001 and 2002 are formed on the insulating film 2001. Hydrogen in the 002 layer is one of the factors that generate carriers in the oxide semiconductor. This may cause a decrease in the reliability of the transistors 101 and 105. Between the transistors 101 and 105 and the transistors 122 and 123, there is provided a function for preventing hydrogen diffusion. It is particularly effective to provide the insulating films 2003 and 2006 having the insulating properties. In 2006, hydrogen was trapped in the lower layer to form transistor 122 and transistor In addition to improving the reliability of 123, the diffusion of hydrogen from the lower layer to the upper layer is suppressed. This also improves the reliability of the transistors 101 and 105.

[0210] The insulating films 2003 and 2006 may be, for example, aluminum oxide, aluminum oxynitride, Gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide zirconia, hafnium oxide nitride, yttria stabilized zirconia (YSZ), etc. can be used. In particular, aluminum oxide films have high resistance to both impurities such as hydrogen and moisture, and oxygen. This is preferable because it has a high blocking effect that prevents the substance from passing through the membrane.

[0211] The insulating films 2004 and 2007, like the insulating films 2003 and 2006, are resistant to the diffusion of water and hydrogen. It is preferable to use a material that is not easily permeable to oxygen. By covering the oxide semiconductor film with an insulating film that is difficult for oxygen to permeate, It is possible to suppress the release of oxygen beyond the insulating film.

[0212] In addition, the insulating films 2004 and 2007, which are difficult for water and hydrogen to permeate, prevent the oxide semiconductor from being exposed to the outside. This makes it possible to suppress the intrusion of water and hydrogen, which are impurities for the transistors 101 and 10 Fluctuations in the electrical characteristics of 5 are suppressed, making it possible to realize a highly reliable transistor.

[0213] The insulating film 2005 has a function of protecting the transistor 101, and the insulating film 2008 has a function of protecting the transistor 101. The insulating films 2005 and 2008 are made of silicon oxide, Silicon oxynitride, silicon oxynitride, silicon nitride, aluminum oxide, aluminum oxynitride nium, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, An insulating film containing one or more of lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide is used. The insulating films 2005 and 2008 may be laminated with the above materials. In some cases, the insulating films 2005 and 2008 may not be provided.

[0214] The wiring 2301 functions as a second gate electrode of the transistor 101. A constant potential may be supplied to the first gate electrode of the transistor 101. The wiring 2302 may be supplied with the same potential or the same signal as that of the transistor 105. The wiring 2302 has a function as a second gate electrode. A constant potential is supplied to the wiring 2302. Alternatively, the same potential or signal as that of the first gate electrode of the transistor 105 may be supplied. In addition, the wirings 2301 and 2302 may be omitted in some cases.

[0215] The plugs 2101 to 2108 are made of copper (Cu), tungsten (W), molybdenum (Mo), etc. , Gold (Au), Aluminum (Al), Manganese (Mn), Titanium (Ti), Tantalum ( Ta), Nickel (Ni), Chromium (Cr), Lead (Pb), Tin (Sn), Iron (Fe), Co A single substance or alloy made of low-resistance material such as Cobalt (Co), or a material that mainly contains these It is preferable to use a single layer or a multilayer of a conductive film containing a compound. It is preferable to use a high melting point material such as tungsten or molybdenum, which has a high melting point. It is preferable to form the insulating layer from a low-resistance conductive material such as aluminum or copper. When gold is used, manganese oxide is formed at the interface with the oxygen-containing insulator, and the manganese oxide is converted to Cu. This is preferable because it has the function of suppressing the diffusion of

[0216] Wirings 2301, 2302, 2501, and 2502, a first electrode 2401 of the capacitor 104, The second electrode 2402 of the capacitor 104, the first electrode 2601 of the capacitor 106, and the The second electrode 2602 of the electrode 106 is made of copper (Cu), tungsten (W), molybdenum (Mo ), gold (Au), aluminum (Al), manganese (Mn), titanium (Ti), tantalum (Ta), Nickel (Ni), Chromium (Cr), Lead (Pb), Tin (Sn), Iron (Fe), Cobalt (Co) low resistance material, its alloy, or its main component It is preferable to use a single layer or a multilayer of a conductive film containing a compound having a high heat resistance and electrical conductivity. It is preferable to use a high melting point material such as tungsten or molybdenum. It is preferable to form the insulating layer from a low-resistance conductive material such as aluminum or copper. When an alloy is used, manganese oxide is formed at the interface with the insulator containing oxygen, and the manganese oxide becomes C This is preferable since it has the function of suppressing the diffusion of u.

[0217] The insulating film 2403 of the capacitor 104 and the insulating film 2603 of the capacitor 106 have a high dielectric constant. It is preferable to use an insulating film. For example, the insulating film may be made of aluminum oxide, manium oxide, or the like. Magnesium, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, oxide Gallium, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, acid The insulating film may contain one or more of neodymium oxide, hafnium oxide, and tantalum oxide. The insulating film 2403 and the insulating film 2603 may each be a stack of the above materials. Lanthanum (La), nitrogen, zirconium (Zr), etc. are added to these insulating films as impurities. It may also include.

[0218] In FIG. 12, the regions without symbols and hatching patterns are insulators. These regions are composed of aluminum oxide, aluminum oxynitride, and Aluminum, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride silicon, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, oxide Contains one or more selected from lanthanum, neodymium oxide, hafnium oxide, tantalum oxide, etc. Insulators can be used. In addition, polyimide resin, polyamide resin, By using organic resins such as acrylic resin, siloxane resin, epoxy resin, and phenolic resin, It is also possible.

[0219] The transistors 122 and 123 are not limited to planar transistors, but may be of various types. For example, FIN type, TRI-GAT type, The transistors may be of E (tri-gate) type or the like.

[0220] By configuring the memory cell 110 shown in FIG. 4 as shown in FIG. 12, In addition, the memory cell 110 can store multi-value data. Therefore, by using the configuration shown in Figure 12, it is possible to store a high density amount of information in a small area. A semiconductor device can be provided.

[0221] As described above, the configurations, methods, etc. described in this embodiment may be used in conjunction with the configurations, methods, etc. described in other embodiments. They can be used in any suitable combination.

[0222] (Embodiment 5) <Configuration Example of Oxide Semiconductor Transistor> In this embodiment, a channel A transistor using an oxide semiconductor layer (hereinafter referred to as OS) An example of a transistor will be described with reference to FIGS.

[0223] 13A to 13C are top views and cross-sectional views of an OS transistor. 3(A) is a top view, and the cross section taken along the dashed line A1-A2 shown in FIG. 13(A) is the cross section shown in FIG. B), and the cross section taken along the dashed line B1-B2 in FIG. 13(A) corresponds to FIG. 13(C). In addition, in Fig. 13(A) to Fig. 13(C), some elements are enlarged for clarity. The direction of the dashed dotted line A1-A2 is the channel length direction. The direction of the dashed dotted line B1-B2 may be referred to as the channel width direction.

[0224] Note that the channel length is, for example, the length of a semiconductor (or transistor) in a top view of a transistor. The area where the gate electrode overlaps with the semiconductor (the part through which current flows when the transistor is on), The source (source region or source electrode) and drain in the region where the channel is formed This refers to the distance between the drain region or drain electrode of a transistor. In a transistor, the channel length does not necessarily have the same value in all regions. The channel length of a transistor may not be determined to a single value. The channel length is a value, maximum, minimum or any value in the region where the channel is formed. is the average value.

[0225] The channel width is the width at which current can flow through a semiconductor (or transistor) when it is on. In the region where the gate electrode overlaps with the gate electrode, or in the region where the channel is formed, The length of the part where the source and drain face each other. In a transconductance analysis, the channel width does not necessarily have the same value in all regions. The channel width of a transistor may not be determined to a single value. The channel width is a value, a maximum value, a minimum value or a width in the region where the channel is formed. is the average value.

[0226] Depending on the structure of the transistor, the channel in the region where the channel is actually formed may vary. The effective channel width (hereinafter referred to as the effective channel width) shown in the top view of the transistor The channel width (hereinafter referred to as the apparent channel width) may be different. For example, In a transistor having a three-dimensional structure, the effective channel width is The effect of the channel width becomes larger than the apparent channel width shown in For example, in a transistor with a fine, three-dimensional structure, The percentage of the channel region that is formed on the side of the semiconductor, compared to the percentage of the channel region that is formed In that case, the apparent channel width shown in the top view may be larger. In this case, the effective channel width where the channel is actually formed is larger than the width of the channel formed by the MOSFET.

[0227] By the way, in a transistor having a three-dimensional structure, the effective channel width is For example, it may be difficult to estimate the effective channel width from the design value. In order to obtain this, it is necessary to assume that the shape of the semiconductor is known. Unless k is precisely known, it is difficult to accurately measure the effective channel width.

[0228] Therefore, in this specification, in a top view of a transistor, a semiconductor and a gate electrode are overlapped. The apparent channel length is the length of the area where the source and drain face each other. The width of the channel is called the "surrounded channel width (SCW)". In this specification, when it is simply referred to as the channel width, may refer to enclosed channel width or apparent channel width. In this document, when the term "channel width" is used, it may refer to the effective channel width. Channel length, channel width, effective channel width, apparent channel width, enclosure channel The channel width, etc., can be determined by acquiring cross-sectional TEM images and analyzing those images. A value can be determined.

[0229] In addition, the field effect mobility of the transistor and the current value per channel width are calculated. In some cases, the effective channel width is calculated using the enclosed channel width. The value may differ from that calculated using the channel width.

[0230] The OS transistor includes an insulating film 652 on an insulating film 651 and a first oxide film 653 on the insulating film 652. A stack of a first oxide semiconductor 661 and a second oxide semiconductor 662 is formed in this order. A source electrode 671 and a drain electrode 672 electrically connected to each other, a part of the stack, a third oxide semiconductor 663 covering a part of the electrode 671 and a part of the drain electrode 672; A part of the laminate, a part of the source electrode 671, a part of the drain electrode 672, a third oxide semiconductor The gate insulating film 653 and the gate electrode 673 overlapping a part of the body 663, and the source electrode 67 1, the drain electrode 672, and the insulating film 654 on the gate electrode 673; The insulating film 655 is disposed over the first oxide semiconductor 661 and the second oxide semiconductor 662. The oxide semiconductor 662 and the third oxide semiconductor 663 are collectively referred to as an oxide semiconductor 660.

[0231] At least a part (or a part) of the source electrode 671 (and / or the drain electrode 672) The second oxide semiconductor 662 (and / or the first oxide semiconductor 661) At least a portion (or all) of the surface, side, top, and / or bottom surface of any semiconductor layer It is provided in.

[0232] Alternatively, at least a portion ( or all of the second oxide semiconductor 662 (and / or the first oxide semiconductor 661) At least a part (or all) of the surface, side, upper surface, and / or lower surface of the semiconductor layer ) or the source electrode 671 (and / or the drain electrode 672). At least a part (or the whole) of the second oxide semiconductor 662 (and / or the first The semiconductor layer is in contact with at least a portion (or all) of a semiconductor layer such as an oxide semiconductor 661.

[0233] Alternatively, at least a portion ( or all of the second oxide semiconductor 662 (and / or the first oxide semiconductor 661) At least a part (or all) of the surface, side, upper surface, and / or lower surface of the semiconductor layer ) is electrically connected to the source electrode 671 (and / or the drain electrode At least a part (or all) of the second oxide semiconductor 662 (and / or is electrically connected to a part (or the whole) of the semiconductor layer such as the first oxide semiconductor 661. It is being done.

[0234] Alternatively, at least a portion ( or all of the second oxide semiconductor 662 (and / or the first oxide semiconductor 661) At least a part (or all) of the surface, side, upper surface, and / or lower surface of the semiconductor layer ) is disposed adjacent to the source electrode 671 (and / or the drain electrode At least a part (or all) of the second oxide semiconductor 662 (and / or is disposed adjacent to a part (or the whole) of a semiconductor layer such as a first oxide semiconductor 661. It is being done.

[0235] Alternatively, at least a portion ( or all of the second oxide semiconductor 662 (and / or the first oxide semiconductor 661) At least a part (or all) of the surface, side, upper surface, and / or lower surface of the semiconductor layer ) is disposed on the side of the source electrode 671 (and / or the drain electrode 6 At least a part (or all) of the second oxide semiconductor 662 (and / or The first oxide semiconductor 661 is disposed on the side of a part (or the whole) of a semiconductor layer. .

[0236] Alternatively, at least a portion ( or all of the second oxide semiconductor 662 (and / or the first oxide semiconductor 661) At least a part (or all) of the surface, side, upper surface, and / or lower surface of the semiconductor layer ) is disposed diagonally above the source electrode 671 (and / or the drain electrode 672). At least a part (or all) of the second oxide semiconductor 662 (and / or is disposed obliquely above a part (or the whole) of a semiconductor layer such as a first oxide semiconductor 661. It is being done.

[0237] Alternatively, at least a portion ( or all of the second oxide semiconductor 662 (and / or the first oxide semiconductor 661) At least a part (or all) of the surface, side, upper surface, and / or lower surface of the semiconductor layer ) is disposed on the upper side of the source electrode 671 (and / or the drain electrode 6 At least a part (or all) of the second oxide semiconductor 662 (and / or The first oxide semiconductor 661 is disposed on a part (or the whole) of a semiconductor layer. .

[0238] The functions of the "source" and "drain" of a transistor are different for transistors of different polarities. This may be reversed when using a current source or when the direction of the current changes during circuit operation. For this reason, in this specification, the terms "source" and "drain" are used interchangeably. It is possible to use it in a variety of ways.

[0239] The transistor according to one embodiment of the present invention preferably has a channel length of 10 nm or more and 1000 nm or less. Preferably, the channel length is 20 nm or more and 500 nm or less, more preferably, the channel length is 30 nm or less. It is a top-gate structure of less than 300 nm.

[0240] The components included in the semiconductor device of this embodiment will be described in detail below.

[0241] <Insulating film undercoat> The insulating film 651 and the insulating film 652 serve to prevent the diffusion of impurities from below the insulating film 651. In addition, the oxide semiconductor 660 can supply oxygen to the oxide semiconductor 660. The insulating films 651 and 652 are preferably insulating films containing oxygen. It is more preferable that the insulating film contains more oxygen than the composition. Converted to oxygen atoms using mal desorption spectroscopy (MDS) analysis The amount of oxygen released is 1.0×10 19 atoms / cm 3 The membrane is as above. The surface temperature of the membrane during the above TDS analysis is 100°C to 700°C, or 10 The temperature range is preferably 0° C. or more and 500° C. or less. Also, as shown in FIG. When the device is formed, the insulating film 651 and the insulating film 652 have flat surfaces. For example, chemical mechanical polishing (CMP) is used. It is preferable to carry out a planarization treatment.

[0242] The insulating film 651 and the insulating film 652 are made of aluminum oxide, magnesium oxide, or silicon oxide. , silicon oxide nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide oxides such as tungsten oxide, lanthanum oxide, neodymium oxide, hafnium oxide and tantalum oxide Insulating film, silicon nitride, silicon oxynitride, aluminum nitride, aluminum oxynitride, etc. The insulating film may be formed using any of a nitride insulating film and a mixture of these materials.

[0243] <Oxide Semiconductor> The oxide semiconductor 660 is typically an In-Ga oxide, an In-Zn oxide, or an In-Mn oxide. Zn oxide (M is Ti, Ga, Y, Zr, La, Ce, Nd, Sn or Hf) In particular, it is preferable to use In-M-Zn oxide as the oxide semiconductor 660.

[0244] However, the oxide semiconductor 660 is not limited to an oxide containing indium. 660 is, for example, Zn oxide, Zn-Sn oxide, Ga oxide, Ga-Sn oxide. That's okay.

[0245] In the case where the oxide semiconductor 660 is an In-M-Zn oxide prepared by a sputtering method, In The atomic ratio of the metal elements in the target used to form the -M-Zn oxide film is In≧M It is preferable that Zn≧M is satisfied. The atomic ratio of the metal elements in such a target is , In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=3 The atomic ratio of the oxide semiconductor 660 to be formed is preferably within the range of 0.1 to 1.0. The atomic ratio of the metal elements contained in the sputtering target is plus or minus Including a 40% variance.

[0246] Next, the first oxide semiconductor 661, the second oxide semiconductor 662, and the third oxide semiconductor The function and effect of the oxide semiconductor 660 formed by stacking the oxide semiconductor 663 are shown in FIG. The energy band structure shown in FIG. 14(B) is used for the explanation. FIG. 14(B) is an enlarged view of a channel portion of the OS transistor shown in FIG. A) shows the energy band structure of the portion indicated by the dashed line C1-C2. FIG. 14(B) shows the energy band structure of the channel formation region of an OS transistor. do.

[0247] In Figure 14(B), Ec652, Ec661, Ec662, Ec663, and Ec653 are The insulating film 652, the first oxide semiconductor 661, the second oxide semiconductor 662, and the third oxide semiconductor 663 are formed on the insulating film 652, the first oxide semiconductor 661, the second oxide semiconductor 662, and the third oxide semiconductor 663, respectively. The energy at the bottom of the conduction band of the oxide semiconductor 663 and the gate insulating film 653 is shown.

[0248] Here, the difference between the vacuum level and the conduction band minimum energy (also called "electron affinity") is The energy difference between the vacant level and the top of the valence band (also called the ionization potential) The energy gap is calculated by subtracting the energy gap from the spectroscopic ellipsometer ( It can be measured using HORIBA JOBIN YVON UT-300. The energy difference between the unoccupied level and the top of the valence band was determined by ultraviolet photoelectron spectroscopy (UPS). iolet Photoelectron Spectroscopy) equipment (ULVA) C It can be measured using a PHI VersaProbe.

[0249] The sputtering target used had an atomic ratio of In:Ga:Zn=1:3:2. The energy gap of the synthesized In-Ga-Zn oxide is about 3.5 eV, and the electron affinity is about 4 The atomic ratio of In:Ga:Zn is 1:3:4. The energy gap of the In-Ga-Zn oxide formed using the get is about 3.4 eV. The electron affinity is about 4.5 eV. The atomic ratio of In:Ga:Zn is 1:3:6. Energy gap of In-Ga-Zn oxide formed using a sputtering target The electron affinity is about 4.5 eV. The atomic ratio of In:Ga:Zn In-Ga-Zn oxide was formed using a sputtering target with a ratio of 1:6:2. The energy gap is about 3.9 eV and the electron affinity is about 4.3 eV. In-Ga formed using a sputtering target with In:Ga:Zn=1:6:8 The energy gap of -Zn oxide is about 3.5 eV and the electron affinity is about 4.4 eV. In addition, a sputtering target with an atomic ratio of In:Ga:Zn=1:6:10 was used. The energy gap of the formed In-Ga-Zn oxide is about 3.5 eV, and the electron affinity is about The atomic ratio of In:Ga:Zn is 1:1:1. The energy gap of the In-Ga-Zn oxide formed using a target was approximately 3.2 eV. The electron affinity is about 4.7 eV. The atomic ratio of In:Ga:Zn is 3:1:2. Energy gap of In-Ga-Zn oxide formed using a sputtering target The electron affinity is about 5.0 eV and the electron pump is about 2.8 eV.

[0250] Since the insulating film 652 and the gate insulating film 653 are insulators, Ec653 and Ec652 are Closer to the vacuum level (lower electron affinity) than C661, Ec662, and Ec663 .

[0251] Also, Ec661 is closer to the vacuum level than Ec662. More than 0.05 eV, more than 0.07 eV, more than 0.1 eV, or more than 0.15 eV higher than C662 V or more and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less at the vacuum level Close proximity is preferable.

[0252] Also, Ec663 is closer to the vacuum level than Ec662. More than 0.05 eV, more than 0.07 eV, more than 0.1 eV, or more than 0.15 eV higher than C662 V or more and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less at the vacuum level Close proximity is preferable.

[0253] In addition, the vicinity of the interface between the first oxide semiconductor 661 and the second oxide semiconductor 662 and the A mixed region is formed in the vicinity of the interface between the second oxide semiconductor 662 and the third oxide semiconductor 663. Therefore, the energy of the conduction band edge changes continuously. , there are few or no levels.

[0254] Therefore, in the stacked structure having the above energy band structure, the electrons are Therefore, the electrons move mainly through the first oxide semiconductor 661 and the insulating film 662. 652 or the interface between the third oxide semiconductor 663 and the gate insulating film 653. Even if a level exists, it has little effect on the transfer of electrons. The interface between the oxide semiconductor 661 and the second oxide semiconductor 662 and the third oxide semiconductor 663 Since there is no or almost no state at the interface between the second oxide semiconductor 662 and the second oxide semiconductor 663, Therefore, the stacked structure of the oxide semiconductor is effective in preventing the movement of electrons in the oxide semiconductor layer. Such an OS transistor can achieve high field-effect mobility.

[0255] As shown in FIG. 6, the interface between the first oxide semiconductor 661 and the insulating film 652 and the third oxide semiconductor 663 are In the vicinity of the interface between the oxide semiconductor 663 and the gate insulating film 653, Although a trap level Et600 may be formed, the first oxide semiconductor 661 and the third The oxide semiconductor 663 is provided, and thus the second oxide semiconductor 662 and the trap states can be kept away.

[0256] In particular, the OS transistor described in this embodiment has a second oxide layer in the channel width direction. The top and side surfaces of the second oxide semiconductor 662 are in contact with the third oxide semiconductor 663. The bottom surface of the oxide semiconductor 662 is in contact with the first oxide semiconductor 661 (see FIG. 13C). In this manner, the second oxide semiconductor 662 is a first oxide semiconductor 661 and a third oxide semiconductor 662. By covering the semiconductor 663, the influence of the trap level can be further reduced. can.

[0257] However, if the energy difference between Ec661 or Ec663 and Ec662 is small, Electrons in the second oxide semiconductor 662 may exceed the energy difference and reach the trap level. When electrons are captured in the trap level, a negative fixed charge is generated at the interface of the insulating film. , the threshold voltage of the transistor shifts in the positive direction.

[0258] Therefore, the energy difference between Ec661, Ec663 and Ec662 is 0 If the capacitance is set to 0.1 eV or more, preferably 0.15 eV or more, the change in the threshold voltage of the transistor is This is preferable because the electric characteristics of the transistor can be improved by reducing the electric field. .

[0259] The band gaps of the first oxide semiconductor 661 and the third oxide semiconductor 663 are , preferably wider than the band gap of the second oxide semiconductor 662.

[0260] The first oxide semiconductor 661 and the third oxide semiconductor 663 may include, for example, Al, Ti, Ga, Ge, Y, Zr, Sn, La, Ce or Hf is added to the second oxide semiconductor 662. A material containing a high atomic ratio can be used. Specifically, the atomic ratio is 1.5 times or more. The above elements are strongly bonded to oxygen, and preferably two or more times, and more preferably three or more times. Therefore, the oxide semiconductor has a function of suppressing oxygen vacancies from being generated. The first oxide semiconductor 661 and the third oxide semiconductor 663 are It can be said that oxygen deficiency is less likely to occur than in 2.

[0261] When the third oxide semiconductor 663 contains In, the In diffuses into the gate insulating film 653. Therefore, the third oxide semiconductor 663 is preferably made of In. It is preferable to use a material that does not contain gallium oxide, for example.

[0262] Note that the first oxide semiconductor 661, the second oxide semiconductor 662, and the third oxide semiconductor 66 3 is at least indium, zinc and M (Al, Ti, Ga, Ge, Y, Zr, Sn When the first oxide is an In-M-Zn oxide containing a metal such as In, La, Ce or Hf, The compound semiconductor 661 is In:M:Zn=x1:y1:z1 [atomic ratio], and the second oxide semiconductor 662 is In:M:Zn=x2:y2:z2 [atomic ratio], and the third oxide semiconductor 663 is If the atomic ratio is In:M:Zn=x3:y3:z3, then y1 / x1 and y3 / x3 is preferably greater than y2 / x2. y1 / x1 and y3 / x3 are The ratio is set to 1.5 times or more, preferably 2 times or more, and more preferably 3 times or more. In the second oxide semiconductor 662, when y2 is equal to or larger than x2, the electrical characteristics of the transistor are improved. However, if y2 is three times or more larger than x2, the transistor Since the field effect mobility is reduced, y2 is preferably less than three times x2.

[0263] The first oxide semiconductor 661 and the third oxide semiconductor 663 are made of I except for Zn and O. The atomic ratio of n and M is preferably less than 50 atomic % for In and less than 50 atomic % for M. mic% or more, more preferably In is less than 25 atomic % and M is 75 atomic % or more. % or more. In addition, the second oxide semiconductor 662 contains In and M other than Zn and O. The atomic ratio of In is preferably 25 atomic % or more and M is less than 75 atomic %. More preferably, In is 34 atomic % or more and M is less than 66 atomic %. do.

[0264] The thickness of the first oxide semiconductor 661 and the third oxide semiconductor 663 is 3 nm or more and 100 nm or less. The thickness of the second oxide semiconductor 662 is preferably 3 nm to 50 nm. The thickness of the film is 3 nm or more and 200 nm or less, preferably 3 nm or more and 100 nm or less, and more preferably The second oxide semiconductor 662 has a thickness of preferably 3 nm to 50 nm. It is preferable that the thickness of the second insulating film 662 be thicker than that of the first insulating film 662 and the third oxide semiconductor 663 .

[0265] In order to provide a transistor with an oxide semiconductor channel with stable electrical characteristics, The present invention relates to a method for reducing the impurity concentration in an oxide semiconductor to make the oxide semiconductor intrinsic or substantially intrinsic. Here, the term "substantially intrinsic" means that the carrier density of the oxide semiconductor is 1× 10 17 / cm 3 Preferably less than 1 × 10 15 / cm 3 Less than More preferably, 1×10 13 / cm 3 It means that it is less than.

[0266] In addition, in an oxide semiconductor, hydrogen, nitrogen, carbon, silicon, and metal elements other than the main component For example, hydrogen and nitrogen contribute to the formation of donor levels, increasing the carrier density. In addition, silicon contributes to the formation of impurity levels in an oxide semiconductor. The impurity levels can become traps and degrade the electrical characteristics of the transistor. Therefore, the first oxide semiconductor 661, the second oxide semiconductor 662, and the third oxide semiconductor It is preferable to reduce the impurity concentration in the layers of conductor 663 and at their respective interfaces.

[0267] In order to make the oxide semiconductor intrinsic or substantially intrinsic, secondary electron spectroscopy (SIMS) is used. In the case of Ion Mass Spectrometry (IMMS), for example, At a certain depth or in a certain region of the oxide semiconductor, the silicon concentration is set to 1×1 0 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than, more Preferably 1 x 10 18 atoms / cm 3 The hydrogen concentration is, for example, At a certain depth in the oxide semiconductor or in a certain region in the oxide semiconductor, 20 atoms / cm 3 Less than or equal to 5×10 19 atoms / cm 3 The following is better Preferably 1×10 19 atoms / cm 3 Less than 5×10, more preferably 18 atom s / cm 3 The nitrogen concentration at a certain depth in the oxide semiconductor is, for example, Or, in a region of an oxide semiconductor, 19 atoms / cm 3 Less than, preferred Or 5×10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5×10, more preferably 17 atoms / cm 3 The following applies.

[0268] In addition, when the oxide semiconductor contains crystals, if silicon or carbon is contained at a high concentration, the oxide semiconductor In order to prevent the crystallinity of the oxide semiconductor from being reduced, For example, at a certain depth in the oxide semiconductor or in a certain region in the oxide semiconductor, Silicon concentration 1×10 19 atoms / cm 3 Less than 5 x 10 18 atom s / cm 3 less than 1×10 18 atoms / cm 3 The portion that is less than In addition, for example, at a certain depth of the oxide semiconductor or In a given area of ​​the body, the carbon concentration is increased to 1×10 19 atoms / cm 3 Less than 5, preferably ×10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 It is sufficient that the part is less than

[0269] In addition, a transistor using the highly purified oxide semiconductor for a channel formation region as described above can be fabricated. The off-state current of the transistor is extremely small. For example, when the voltage between the source and drain is set to 0.1 V or 5 V, , or about 10 V, the off-state current normalized by the channel width of the transistor is It is possible to reduce the flux density from several yA / μm to several zA / μm.

[0270] In the OS transistor described in this embodiment, the oxide semiconductor 660 is electrically connected in the channel width direction. Since the gate electrode 673 is formed so as to surround the oxide semiconductor 660, In addition to the gate electric field applied vertically, a gate electric field is also applied from the side (Fig. 13(C)). In other words, the gate electric field is applied to the entire oxide semiconductor. As a result, a current flows through the entire second oxide semiconductor 662 which serves as a channel. The switching current can be increased.

[0271] <Gate electrode> The gate electrode 673 is made of chromium (Cr), copper (Cu), aluminum (Al), or gold (Au). , Silver (Ag), Zinc (Zn), Molybdenum (Mo), Tantalum (Ta), Titanium (Ti) , Tungsten (W), Manganese (Mn), Nickel (Ni), Iron (Fe), Cobalt ( Metal elements selected from the group consisting of Co, ruthenium (Ru), and alloys containing the above-mentioned metal elements. Alternatively, the metal elements may be combined to form an alloy. The gate electrode 673 may have a single-layer structure or a laminated structure of two or more layers. A single-layer structure of an aluminum film containing titanium, a two-layer structure of an aluminum film with a titanium film laminated on it, Two-layer structure with a titanium film laminated on a titanium nitride film, and a tungsten film laminated on a titanium nitride film A two-layer structure in which a tungsten film is laminated on a tantalum nitride film or a tungsten nitride film. Two-layer structure: titanium film, aluminum film laminated on top of the titanium film, and titanium on top of that. The three-layer structure of the Cu-Mn alloy film, the single-layer structure of the Cu-Mn alloy film, and the Cu film on the Cu-Mn alloy film A two-layer structure in which a Cu film is laminated on a Cu-Mn alloy film, and a Cu-Mn alloy film is further laminated on top of that. In particular, Cu-Mn alloy films have low electrical resistance and are resistant to oxidation. This is preferred because it can form manganese oxide at the interface with the insulating film containing silicon and prevent Cu diffusion. I wish.

[0272] The gate electrode 673 is made of indium tin oxide or indium containing tungsten oxide. Oxide, indium zinc oxide with tungsten oxide, indium oxide with titanium oxide Indium tin oxide, indium zinc oxide, silicon oxide, etc. A light-transmitting conductive material such as doped indium tin oxide can also be used. Alternatively, the conductive material having light-transmitting properties and the metal element may be laminated together.

[0273] <Gate insulating film> The gate insulating film 653 may be formed of aluminum oxide, magnesium oxide, silicon oxide, or nitride oxide. Silicon oxide, silicon nitride, silicon oxide, gallium oxide, germanium oxide, Yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide and An insulating film containing one or more types of tantalum oxide can be used. The gate insulating film 653 may be a laminate of the above materials. , zirconium (Zr), etc. may be contained as impurities.

[0274] Next, an example of a laminated structure of the gate insulating film 653 will be described. The gate insulating film 653 is For example, it contains oxygen, nitrogen, silicon, hafnium, etc. Specifically, hafnium oxide and preferably includes silicon oxide or silicon oxynitride.

[0275] Hafnium oxide has a higher dielectric constant than silicon oxide and silicon oxynitride. Since the physical thickness can be made larger than the equivalent oxide thickness, the equivalent oxide thickness can be made 10 nm or less. Even if the thickness is reduced to 5 nm or less, the leakage current due to the tunnel current can be reduced. That is, a transistor with low off-state current can be realized.

[0276] <Source and Drain Electrodes> The source electrode 671 and the drain electrode 672 are made of the same material as the gate electrode 673. In particular, the Cu-Mn alloy film has low electrical resistance and is a good This is preferable because it can form manganese oxide at the interface with the copper, thereby preventing the diffusion of copper.

[0277] <Protective insulating film> The insulating film 654 is a blocking material for oxygen, hydrogen, water, alkali metals, alkaline earth metals, etc. The insulating film 654 prevents oxygen from the oxide semiconductor 660 from entering the outside. and the intrusion of hydrogen, water, and the like into the oxide semiconductor 660 from the outside. The insulating film 654 can be, for example, a nitride insulating film. Examples include silicon nitride, silicon nitride oxide, aluminum nitride, and aluminum nitride oxide. In addition, blocking effects of oxygen, hydrogen, water, alkali metals, alkaline earth metals, etc. Instead of a nitride insulating film, which has a blocking effect against oxygen, hydrogen, water, etc., an oxide insulating film is used. An oxide insulating film having a blocking effect against oxygen, hydrogen, water, etc. may be provided. Examples include aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, Yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, etc. do.

[0278] The aluminum oxide membrane is permeable to both impurities such as hydrogen and moisture, and oxygen. Therefore, aluminum oxide is preferable for use as the insulating film 654 because it has a high blocking effect. The aluminum film improves the electrical characteristics of the transistor during and after the transistor manufacturing process. Preventing impurities such as hydrogen and moisture, which are factors that cause fluctuations in the oxide semiconductor 660, from entering the oxide semiconductor 660; Preventing the release of oxygen from the oxide semiconductor, which is the main component material of the semiconductor 660, and insulating film 6 It is suitable for use as a protective film having the effect of preventing unnecessary release of oxygen from 52. In addition, oxygen contained in the aluminum oxide film can be diffused into the oxide semiconductor. .

[0279] Crystal structure of oxide semiconductor Next, the crystal structure of an oxide semiconductor that can be used for an OS transistor will be described.

[0280] In this specification, "parallel" means that the angle between two straight lines is between -10° and 10°. Therefore, it includes the case where the angle is between -5° and 5°. "Straight" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. This also includes cases where the angle is between 85° and 95°.

[0281] In addition, in this specification, when the crystal is a trigonal or rhombohedral crystal, it is represented as a hexagonal crystal system. .

[0282] Oxide semiconductor films are roughly classified into non-single-crystal oxide semiconductor films and single-crystal oxide semiconductor films. The single-crystal oxide semiconductor film is called CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor). Talline Oxide Semiconductor film, polycrystalline oxide semiconductor film The oxide semiconductor film includes a microcrystalline oxide semiconductor film, an amorphous oxide semiconductor film, and the like.

[0283] First, we will explain the CAAC-OS film.

[0284] The CAAC-OS film is one of oxide semiconductor films having a plurality of crystal parts aligned along the c-axis.

[0285] Transmission Electron Microscope (TEM) A bright-field image and a combined diffraction pattern of the CAAC-OS film were obtained by using a microscope. Also called a high-resolution TEM image. By observing the TEM image, multiple crystals can be confirmed. On the other hand, the high-resolution TEM image also clearly shows the boundaries between crystals, i.e., grain boundaries. Therefore, the CAAC-OS film is It can be said that the decrease in electron mobility caused by the grain boundaries is unlikely to occur.

[0286] When a high-resolution TEM image of the cross section of the CAAC-OS film was observed from a direction roughly parallel to the sample surface, It can be seen that the metal atoms are arranged in layers in the crystal part. Each layer of metal atoms is The CAAC-OS film is formed on the surface (also called the surface on which the film is formed) or on the upper surface. The CAAC-OS film has a shape similar to that of the crystalline silicon film, and is aligned parallel to the surface on which the CAAC-OS film is formed or the upper surface.

[0287] On the other hand, a high-resolution TEM image of the plane of the CAAC-OS film was observed from a direction roughly perpendicular to the sample surface. They then confirmed that the metal atoms in the crystals were arranged in triangular or hexagonal shapes. However, there is no regularity in the arrangement of metal atoms between different crystal parts.

[0288] Figure 15(a) shows a high-resolution TEM image of the cross section of the CAAC-OS film. ) is a high-resolution TEM image of the cross section of Fig. 15(a) enlarged for easier understanding. The atomic arrangement is highlighted for ease of understanding.

[0289] FIG. 15(c) shows the area surrounded by a circle (diameter approximately 4n m) are local Fourier transform images. From Fig. 15(c), it is clear that the c-axis orientation is In addition, the orientation of the c-axis is different between the AO and O-A' sections, so different gradients are observed. In addition, the c-axis angles between the A and A are 14.3° and 16.6°. 26.4°, and so on. Similarly, O-A' Between these, the c-axis angle changes gradually and continuously from -18.3° to -17.6° to -15.9°. It is clear that the

[0290] When electron diffraction was performed on the CAAC-OS film, spots (bright spots) indicating orientation were observed. For example, a potential difference of 1 nm to 30 nm is measured on the top surface of the CAAC-OS film. When electron diffraction using a sagittal beam (also called nanobeam electron diffraction) is performed, spots are observed. (See FIG. 16(A)).

[0291] The high-resolution TEM images of the cross section and the plan view show that the crystalline part of the CAAC-OS film It can be seen that the film has an orientation.

[0292] Most of the crystals in the CAAC-OS film are cubes with sides less than 100 nm. Therefore, the crystal part in the CAAC-OS film has a side length of 10n This also includes cases where the size fits within a cube of less than 100 mm, 5 nm, or 3 nm. In addition, multiple crystals in the CAAC-OS film are connected to form a single large crystal region. For example, in a high-resolution TEM image of a plane, 2 End , 5 μm 2 More than or equal to 1000μm 2 In some cases, crystal regions having more than this amount may be observed.

[0293] X-ray diffraction (XRD) was performed on the CAAC-OS film. For example, a CAAC-OS film with InGaZnO4 crystals was In the out-of-plane analysis, a peak was observed at a diffraction angle (2θ) of approximately 31°. This peak is attributed to the (009) plane of the InGaZnO4 crystal. This indicates that the crystals in the CAAC-OS film have a c-axis orientation, and the c-axis is generally aligned on the surface on which the film is formed or on the upper surface. It can be seen that it is oriented in a substantially vertical direction.

[0294] On the other hand, in-plane X-ray irradiation is performed on the CAAC-OS film in a direction perpendicular to the c-axis. In the analysis by the ane method, a peak may appear at 2θ around 56°. This peak is This is attributed to the (110) plane of the InGaZnO4 crystal. In the case of a semiconductor film, 2θ is fixed at around 56°, and the normal vector of the sample surface is set as the axis (φ axis). When the sample is rotated and analyzed (φ scan), the crystal plane equivalent to the (110) plane is In contrast, in the case of the CAAC-OS film, the 2θ is set to 5 Even when the φ is fixed at around 6° and scanned, no clear peak appears.

[0295] From the above, it is considered that the a-axis and b-axis orientations are inconsistent between different crystal regions in the CAAC-OS film. The crystal is regular, but has a c-axis orientation, and the c-axis is parallel to the normal vector of the surface on which the crystal is formed or the upper surface. Therefore, it is clear that the orientation of the nuclei is consistent with that confirmed by the high-resolution TEM observation of the cross section mentioned above. Each layer of metal atoms arranged in layers is parallel to the ab plane of the crystal.

[0296] The crystalline portion is formed when the CAAC-OS film is formed or when a crystallization process such as a heat treatment is performed. As described above, the c-axis of the crystal is aligned along the surface on which the CAAC-OS film is formed or along the surface on which the CAAC-OS film is formed. The orientation of the CAAC-OS film is parallel to the normal vector of the top surface. When the shape of the CAAC-OS film is changed by etching, the c-axis of the crystal is aligned with the surface on which the CAAC-OS film is formed. Or it may not be parallel to the normal vector of the upper surface.

[0297] Furthermore, the distribution of c-axis oriented crystal parts in the CAAC-OS film does not need to be uniform. For example, the crystals in the CAAC-OS film grow from the top surface of the CAAC-OS film. When the crystal is formed by the above method, the region near the top surface has more c-axis oriented crystals than the region near the surface on which the crystal is formed. In addition, the CAAC-OS film containing impurities may have a high ratio of impurities. The doped region changes and regions with different proportions of c-axis oriented crystals are formed. This sometimes happens.

[0298] In addition, the out-of-plane method of CAAC-OS film with InGaZnO4 crystals In the analysis by , in addition to the peak at 2θ near 31°, a peak also appeared at 2θ near 36°. The peak at 2θ of around 36° may be due to the c-axis orientation in some parts of the CAAC-OS film. The CAAC-OS film contains crystals that do not have a 2θ of around 31°. It is preferred that the spectrum exhibits a peak and does not exhibit a peak at 2θ of around 36°.

[0299] The CAAC-OS film is an oxide semiconductor film with a low concentration of impurities. The impurities include hydrogen, carbon, and The elements are other than the main components of the oxide semiconductor film, such as silicon and transition metal elements. The elements that bond to oxygen more strongly than the metal elements that form the oxide semiconductor film, such as arsenic, are oxidized. By removing oxygen from the oxide semiconductor film, the atomic arrangement of the oxide semiconductor film is disrupted, reducing its crystallinity. In addition, heavy metals such as iron and nickel, argon, and carbon dioxide have an atomic radius of Since the molecular radius is large, when the cation is contained in the oxide semiconductor film, the The impurities in the oxide semiconductor film may cause the atomic arrangement to be disturbed, which may result in a decrease in crystallinity. Objects can act as carrier traps or carrier generation sources.

[0300] The CAAC-OS film is an oxide semiconductor film having a low density of defect states. Oxygen vacancies in the semiconductor film can become carrier traps or trap hydrogen, It can be a carrier source.

[0301] A material with a low impurity concentration and a low defect level density (few oxygen vacancies) is called a high-purity intrinsic or The term "substantially high-purity intrinsic" refers to a highly-purified intrinsic oxide semiconductor film. Since the carrier generation source is small, the carrier density can be reduced. A transistor using an oxide semiconductor film has electrical characteristics in which the threshold voltage is negative ( Also called marion.) It is rare for it to become high purity genuine or substantially high purity genuine. The oxide semiconductor film has few carrier traps. A transistor using such a material has small fluctuation in electrical characteristics and is highly reliable. Note that it takes a long time for charges trapped in the carrier traps in the oxide semiconductor film to be released. The charge is long and can behave like a fixed charge. In addition, a transistor using an oxide semiconductor film having a high density of defect states has unstable electrical characteristics. There are cases.

[0302] In addition, the electrical characteristics of transistors using CAAC-OS films were improved by irradiation with visible light or ultraviolet light. The fluctuation is small.

[0303] Next, a microcrystalline oxide semiconductor film will be described.

[0304] The microcrystalline oxide semiconductor film has a region where crystals can be confirmed in a high-resolution TEM image. The microcrystalline oxide semiconductor film has a crystal structure including a region where a crystal part is not clearly observed and a region where a crystal part is not clearly observed. The crystal part contained in the crystal has a size of 1 nm to 100 nm or 1 nm to 10 nm. In particular, the fineness is often between 1 nm and 10 nm, or between 1 nm and 3 nm. The oxide semiconductor film having nanocrystals (nc) is called nc -OS(nanocrystalline oxide semiconductor) In the nc-OS film, for example, the grain boundaries are clearly identified in high-resolution TEM images. It may not be possible to recognize

[0305] The nc-OS film is a microscopic region (e.g., a region of 1 nm to 10 nm, especially a region of 1 nm or more). The atomic arrangement has periodicity in the region of 3 nm or less. There is no regularity in the crystal orientation between the crystal parts. Therefore, no orientation is observed throughout the film. Therefore, depending on the analysis method, the nc-OS film may be indistinguishable from an amorphous oxide semiconductor film. For example, an XRD apparatus that uses X-rays with a diameter larger than that of the crystal part for an nc-OS film may be used. When the structure was analyzed using the out-of-plane method, the crystal plane was not shown. In addition, the probe diameter ( For example, electron diffraction (also called selected area electron diffraction) is performed using an electron beam of 50 nm or more. On the other hand, for the nc-OS film, Nanobeam electron diffraction using an electron beam with a probe diameter close to or smaller than the size of the crystal part In addition, nanobeam electron diffraction was performed on the nc-OS film. In some cases, a bright area with a circular shape (ring shape) may be observed. When nanobeam electron diffraction was performed on the -OS film, multiple spots were observed within the ring-shaped region. (See FIG. 16(B)).

[0306] The nc-OS film is an oxide semiconductor film that has higher order than an amorphous oxide semiconductor film. Therefore, the nc-OS film has a lower density of defect states than the amorphous oxide semiconductor film. In the nc-OS film, there is no regularity in the crystal orientation between different crystal parts. The S film has a higher density of defect states than the CAAC-OS film.

[0307] Next, the amorphous oxide semiconductor film will be described.

[0308] The amorphous oxide semiconductor film is an oxide semiconductor film in which the atomic arrangement in the film is irregular and does not have a crystal part. An example is an oxide semiconductor film that has an amorphous state, such as quartz.

[0309] In the amorphous oxide semiconductor film, no crystalline parts can be confirmed in a high-resolution TEM image.

[0310] When the structure of the amorphous oxide semiconductor film is analyzed using an XRD device, out-of-p In the lane analysis, no peaks indicating crystal planes were detected. When electron diffraction is performed on a conductive film, a halo pattern is observed. When nanobeam electron diffraction is performed on a conductive film, no spots are observed, and a halo pattern is observed. Observed.

[0311] Note that the oxide semiconductor film has a structure that exhibits physical properties between the nc-OS film and the amorphous oxide semiconductor film. An oxide semiconductor film having such a structure may have a structure such as the following. Amorphous-like Ox The resulting film is called an ide semiconductor membrane.

[0312] The amorphous-like OS membrane appears as voids in high-resolution TEM images. In addition, crystals may be clearly observed in high-resolution TEM images. There are areas where crystals can be seen and areas where crystals cannot be seen. The phos-like OS film is formed by irradiating a small amount of electrons, which is the same level as observed by TEM. Crystallization may occur and the growth of crystals may be observed. On the other hand, if the nc-OS film is of good quality, However, crystallization due to minute amounts of electron irradiation, such as that observed by TEM, is hardly observed.

[0313] The size of the crystals in the amorphous-like OS film and the nc-OS film was calculated. Measurements can be performed using high-resolution TEM images. For example, the crystal of InGaZnO4 It has a layered structure, with two Ga-Zn-O layers between In-O layers. InGaZnO4 The unit cell of this crystal has three In-O layers and six Ga-Zn-O layers, for a total of nine layers. The layers are stacked in the c-axis direction. Therefore, the spacing between adjacent layers is is approximately the same as the lattice spacing (also called the d value) of the (009) plane, and crystal structure analysis has revealed that The value is expected to be 0.29 nm. Therefore, we focus on the lattice fringes in the high-resolution TEM image. In the area where the lattice spacing is 0.28 nm or more and 0.30 nm or less, The lattice fringes of the InGaZnO4 crystal were considered to correspond to the ab plane. The maximum length of the region to be covered was determined for the amorphous-like OS membrane and the nc-OS membrane. The size of the crystal part of the film is used. Note that the size of the crystal part is selected to be 0.8 nm or more. evaluate.

[0314] Figure 17 shows the high-resolution TEM images of the amorphous-like OS film and the nc This is an example of investigating the change in the average size of crystal parts (20 to 40 parts) in an -OS film. As shown in Figure 17, the amorphous-like OS film crystallizes according to the cumulative dose of electron irradiation. Specifically, in the early stages of TEM observation, the area becomes larger. The crystals, which were about 2 nm in size, were irradiated with a cumulative dose of 4.2 × 10 8 e - / nm 2 In On the other hand, the good quality nc-OS film The cumulative electron dose from the start of electron irradiation was 4.2×10 8 e - / nm 2 Range up to It can be seen that there is no change in the size of the crystal part regardless of the cumulative electron irradiation dose.

[0315] In addition, the crystallinity of the amorphous-like OS film and the nc-OS film shown in FIG. The change in the size of the part is linearly approximated, and the cumulative electron dose is 0e - / nm 2 Extrapolating to It can be seen that the average size of the amorphous crystals is positive. The crystals of the ke-OS and nc-OS films existed before TEM observation. You can understand.

[0316] The oxide semiconductor film may be, for example, an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, or a CA The AC-OS film may be a laminate film having two or more kinds of films.

[0317] When an oxide semiconductor film has multiple structures, the structure can be analyzed by using nanobeam electron diffraction. may be possible.

[0318] FIG. 16C shows the electron gun chamber 10, the optical system 12 below the electron gun chamber 10, and the optical system 12 below the optical system 12. A sample chamber 14, an optical system 16 below the sample chamber 14, an observation chamber 20 below the optical system 16, and an observation chamber A transmission electron microscope having a camera 18 mounted on the observation chamber 20 and a film chamber 22 below the observation chamber 20. The diffraction measurement device is shown. The camera 18 is installed facing the inside of the observation room 20. The housing 22 may not be provided.

[0319] FIG. 16(D) shows the internal structure of the transmission electron diffraction measurement apparatus shown in FIG. 16(C). Inside the transmission electron diffraction measurement device, electrons emitted from an electron gun installed in the electron gun chamber 10 The light is irradiated onto a substance 28 placed in a sample chamber 14 via an optical system 12. The electrons are incident on a fluorescent screen 32 installed inside the observation chamber 20 via the optical system 16. On the plate 32, a pattern appears according to the intensity of the incident electrons, which is called a transmission electron diffraction pattern. can be measured.

[0320] The camera 18 is set facing the fluorescent screen 32 and captures the pattern appearing on the fluorescent screen 32. A straight line passing through the center of the lens of the camera 18 and the center of the fluorescent screen 32 The angle between the upper surface of the fluorescent screen 32 and the light source 31 is, for example, 15° to 80°, or 30° to 70°. The smaller the angle, the more difficult it is to capture with the camera 18. However, if the angle is known in advance, the resulting transmission electron diffraction pattern will be significantly distorted. If a camera is used, it is possible to correct distortions in the obtained transmission electron diffraction pattern. In some cases, it may be acceptable to place the camera 18 in the film chamber 22. The fluorescent screen 3 may be installed in the electron chamber 22 so as to face the direction of incidence of the electrons 24. It is possible to capture a transmission electron diffraction pattern with little distortion from the back surface of 2.

[0321] A holder for fixing a substance 28, which is a sample, is installed in the sample chamber 14. The holder is structured to be transparent to electrons passing through the material 28. The holder may have a function of moving the holder 28 along the X-axis, Y-axis, Z-axis, etc. For example, 1 nm or more and 10 nm or less, 5 nm or more and 50 nm or less, 10 nm or more and 100 nm or less The range is 50 nm to 500 nm, 100 nm to 1 μm, etc. These ranges can be set optimally depending on the structure of the substance 28. good.

[0322] Next, the transmission electron diffraction pattern of the material is measured using the above-mentioned transmission electron diffraction measurement device. The method will be explained.

[0323] For example, as shown in FIG. 16(D), the irradiation position of the nanobeam electron 24 on the material is By changing (scanning) the material, it is possible to observe how the structure of the material changes. In this case, if the substance 28 is a CAAC-OS film, the circuit shown in FIG. If the material 28 is an nc-OS film, a fold pattern is observed. A diffraction pattern similar to the one shown in the figure is observed.

[0324] By the way, even if material 28 is a CAAC-OS film, it may be partially composed of an nc-OS film, etc. The same diffraction pattern may be observed. Therefore, the quality of the CAAC-OS film can be judged by The ratio of the area where the diffraction pattern of the CAAC-OS film is observed in a certain range (CAAC For example, a good quality CAAC-OS film can be expressed as In this case, the CAAC ratio is 50% or more, preferably 80% or more, and more preferably 90% or more. The diffraction pattern of the CAAC-OS film is different from that of the CAAC-OS film. The proportion of observed areas is denoted as the non-CAAC rate.

[0325] As an example, the film is deposited immediately after (denoted as-sputtered), or in an oxygen-containing atmosphere. The top surface of each sample with CAAC-OS film after the 450 °C heat treatment was scanned. Transmission electron diffraction patterns were obtained while scanning at a speed of 5 nm / s for 60 s. The diffraction pattern was observed while scanning, and the observed diffraction pattern was recorded as a still image every 0.5 seconds. The CAAC conversion rate was derived by converting the electron beam. The nano-beam electron beam was used. The same measurements were performed on six samples. The carbonization rate was calculated using the average value of six samples.

[0326] The CAAC ratio in each sample is shown in Fig. 18(A). The AC ratio was 75.7% (non-CAAC ratio was 24.3%). The CAAC content of the treated CAAC-OS film was 85.3% (non-CAAC content was 14.7%). It can be seen that the CAAC conversion rate is higher after the 450°C heat treatment than immediately after the film formation. In other words, the non-CAAC ratio is low due to heat treatment at high temperatures (e.g., 400°C or higher). In addition, in the case of heat treatment at temperatures below 500°C, It can be seen that a CAAC-OS membrane with a high CAAC content can be obtained.

[0327] Here, most of the diffraction patterns different from those of the CAAC-OS film are similar to those of the nc-OS film. In addition, the amorphous oxide semiconductor film was not observed in the measurement area. Therefore, it is possible that the heat treatment produces a region with a structure similar to that of the nc-OS film. It is suggested that the CAAC domain is rearranged due to the influence of the structure of the neighboring domain.

[0328] 18(B) and 18(C) show the CAAC-O immediately after deposition and after heat treatment at 450° C. 18(B) and 18(C) are high-resolution TEM images of the S film. It is clear from these results that the CAAC-OS film after the heat treatment at 450° C. has a more uniform film quality. That is, it was found that the quality of the CAAC-OS film was improved by heat treatment at a high temperature. Light.

[0329] By using such a measurement method, it is possible to analyze the structure of oxide semiconductor films having multiple structures. This may be the case.

[0330] As described above, the configurations, methods, etc. described in this embodiment may be used in conjunction with the configurations, methods, etc. described in other embodiments. They can be used in any suitable combination.

[0331] (Embodiment 6) A semiconductor device according to one aspect of the present invention includes a display device, a personal computer, and a recording medium. Image playback devices with advanced functions (typically DVD: Digital Versatile Disc (Devices having a display capable of playing back recording media such as 3D models and displaying the images) In addition, an electronic device in which the semiconductor device according to one embodiment of the present invention can be used Mobile phones, handheld game consoles, portable data terminals, e-book terminals, video cameras , cameras such as digital still cameras, goggle-type displays (head-mounted displays) Ray), navigation systems, audio playback devices (car audio, digital audio players, copiers, fax machines, printers, printer-combiners, automated teller machines Examples of such electronic devices include ATMs and vending machines. vinegar.

[0332] FIG. 19A shows a portable game machine, which includes a housing 901, a housing 902, a display unit 903, and a display unit 904. 904, microphone 905, speaker 906, operation key 907, stylus 908 The portable game machine shown in FIG. 19A has two display units 903 and a display However, the number of display units that the portable game machine has is not limited to this. .

[0333] FIG. 19B shows a portable data terminal, which includes a first housing 911, a second housing 912, and a first display unit 9 13, a second display unit 914, a connection unit 915, an operation key 916, etc. The first display unit 911 is provided in the first housing 911, and the second display unit 914 is provided in the second housing 912. The first housing 911 and the second housing 912 are connected by a connection part 915. The angle between the first housing 911 and the second housing 912 can be changed by the connection part 915. The image on the first display unit 913 is transmitted between the first housing 911 and the second housing 912 at the connection unit 915. 12. Also, the first display unit 913 and At least one of the first display unit 912 and the second display unit 914 is a display device having a function as a position input device. The function of the position input device may be realized by using a touch panel on the display device. Alternatively, the function as a position input device can be added by providing a It can also be added by providing a photoelectric conversion element, also called a photo sensor, in the pixel part of the display device. can be done.

[0334] FIG. 19C shows a notebook personal computer, which includes a housing 921, a display unit 922, and a keyboard. The display device 922 includes a keyboard 923, a pointing device 924, and the like.

[0335] FIG. 19(D) shows an electric refrigerator-freezer, which includes a housing 931, a refrigerator door 932, and a freezer door 93. Holds 3rd place.

[0336] FIG. 19E shows a video camera, which includes a first housing 941, a second housing 942, a display unit 943, The operation key 944, the lens 945, the connection part 946, etc. 945 is provided in the first housing 941, and the display unit 943 is provided in the second housing 942. The first housing 941 and the second housing 942 are connected by a connection portion 946. The angle between the first housing 941 and the second housing 942 can be changed by the connection part 946. The image on the display unit 943 is transmitted between the first housing 941 and the second housing 94 at the connection unit 946. 2.

[0337] FIG. 19(F) shows a standard automobile, which includes a body 951, wheels 952, a dashboard 953, and a rear window. It has 954 etc.

[0338] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. .

[0339] (Embodiment 7) In this embodiment, a usage example of an RF tag according to one embodiment of the present invention will be described with reference to FIG. RF tags are used in a wide range of applications, including banknotes, coins, securities, and anonymous documents. Bonds, certificates (driver's licenses, resident cards, etc., see Figure 20 (A)), recording media (DVDs and videos) (See Fig. 20(B)), packaging containers (wrapping paper, bottles, etc., See Fig. 20(C) ), vehicles (bicycles, etc., see Figure 20 (D)), personal belongings (bags, glasses, etc.), food, plants Objects, animals, the human body, clothing, daily necessities, medicines and medical products including drugs, or electronic devices (liquids LCD display devices, EL display devices, television devices, or mobile phones) or other items It can be used on tags attached to goods (see Figure 20(E) and Figure 20(F)). Cut.

[0340] The RF tag 4000 according to one embodiment of the present invention can be attached to or embedded in a surface of an object. For example, in a book, the sensor is embedded in the paper, and in a package made of organic resin, the sensor is embedded in the paper. For example, the RF tag is embedded in the organic resin and fixed to each article. The 4000 is small, thin, and lightweight, and even after it is attached to an object, it does not change the design of the object. In addition, the security of banknotes, coins, securities, bearer bonds, or certificates is not lost. By providing an RF tag 4000 according to one aspect of the present invention to a product or the like, an authentication function can be provided. This authentication function can be used to prevent counterfeiting. The present invention can be applied to various items, such as items of clothing, recording media, personal belongings, food, clothing, household goods, and electronic devices. By attaching RF tags related to the above, the efficiency of systems such as inspection systems can be improved. In addition, even in the case of vehicles, the RF tag according to one embodiment of the present invention can be attached. This can improve security against theft and the like.

[0341] As described above, the RF tag according to one aspect of the present invention is used for each of the applications described in this embodiment. This reduces the power required for operations, including writing and reading information, thereby extending the maximum communication distance. It is also possible to store information for an extremely long period of time even if the power is cut off. Since the data can be retained for a long time, it can be used for applications where the frequency of writing and reading is low. Cut.

[0342] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. . [Explanation of symbols]

[0343] BG1 signal BG2 signal BL bit line BL1 bit line BL2 bit line FN1 node FN2 Node FN3 Node p0 Period p1 Period p2 Period p3 Period p4 Period p5 Period p6 period T0 time T1 time T2 time T3 time T4 time T5 time T6 time T7 time T8 time T9 time T10 time T11 time T12 time T13 time T14 time T15 time WLC1 Word Line WLC2 Word Line WLC3 Word Line WLOS1 Word Line WLOS2 Word Line WLOS3 Word Line 10 Electron Gun Room 12 Optical system 14 Sample Room 16 Optical system 18 Camera 20 Observation Room 22 Film Room 24 electronic 28 Substance 32 Fluorescent Screen 100 memory cells 101 Transistor 102 Transistor 103 Transistor 104 Capacitive element 105 Transistor 106 Capacitive element 107 Transistor 108 Capacitive element 109 Transistor 110 Memory Cells 112 Transistor 113 Transistor 114 Transistor 122 Transistor 123 Transistor 500 Semiconductor device 501 Memory Cell Array 502 Row Selection Driver 503 Column Select Driver 504 A / D Converter 517 Decoder 518 Control Circuit 521 Decoder 522 Latch Circuit 523 D / A Converter 524 Switch Circuit 526 Transistor 531 Comparator 532 Encoder 533 Latch Circuit 534 Buffer 651 Insulating film 652 Insulating film 653 Gate insulating film 654 Insulating film 655 Insulating film 660 Oxide Semiconductors 661 Oxide Semiconductors 662 Oxide Semiconductors 663 Oxide Semiconductors 671 Source Electrode 672 Drain electrode 673 Gate electrode 901 Case 902 Case 903 Display section 904 Display section 905 Microphone 906 Speaker 907 Operation Key 908 Stylus 911 Case 912 Case 913 Display section 914 Display section 915 Connection 916 Operation Key 921 Case 922 Display section 923 Keyboard 924 Pointing Device 931 Case 932 Refrigerator door 933 Freezer door 941 Case 942 Case 943 Display section 944 Operation Key 945 Lens 946 Connection 951 Body 952 wheels 953 Dashboard 954 Light 2000 boards 2001 Insulating film 2002 Insulating film 2003 Insulating film 2004 Insulating film 2005 Insulating film 2006 Insulating film 2007 Insulating film 2008 Insulating film 2101 Plug 2102 Plug 2103 Plug 2104 Plug 2105 Plug 2106 Plug 2107 Plug 2108 Plug 2201 Channel formation region 2202 Impurity region 2203 Impurity region 2204 Gate insulating film 2205 Gate electrode 2206 Sidewall insulation layer 2301 Wiring 2302 Wiring 2401 Electrode 2402 Electrode 2403 Insulating film 2501 Wiring 2502 Wiring 2601 Electrode 2602 Electrode 2603 Insulating film 2701 Conductive film 2702 Conductive film 4000 RF tags

Claims

1. a semiconductor film having a channel formation region of a first transistor and a channel formation region of a second transistor; a first conductive film having a region in contact with an upper surface of the semiconductor film; a second conductive film having a region located above the semiconductor film and functioning as one electrode of a capacitor; a first insulating film having a region located above the second conductive film and including nitrogen and silicon; a third conductive film having a region overlapping with the second conductive film with the first insulating film interposed therebetween and functioning as the other electrode of the capacitor; a second insulating film having a region located above the third conductive film; an oxide semiconductor film having a region located above the second insulating film and including a channel formation region of a third transistor; a third insulating film having a region located above the oxide semiconductor film; a fourth conductive film having a region located above the third insulating film and functioning as a gate electrode of the second transistor; a fourth insulating film having a region located above the fourth conductive film; a fifth insulating film having a region located above the fourth insulating film; a fifth conductive film having a region located above the fifth insulating film; the semiconductor film comprises silicon; the oxide semiconductor film contains In, Ga, and Zn; the fourth insulating film is a stack of a first layer having oxygen and silicon and a second layer having nitrogen and silicon, one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor; one of a source and a drain of the third transistor is electrically connected to a gate of the first transistor and one electrode of the capacitance element; the other of the source and the drain of the third transistor is electrically connected to the other of the source and the drain of the first transistor; the fifth conductive film is electrically connected to the other of the source and the drain of the second transistor via the first conductive film.

2. In claim 1, The fifth conductive film functions as a power supply line.

3. In claim 1 or 2, A sixth conductive film is provided, the sixth conductive film has a region overlapping with the fourth conductive film with the oxide semiconductor film therebetween and functions as a second gate electrode of the third transistor.

Images