Semiconductor Device

Abstract

To provide a transistor structure and a manufacturing method of the same which achieve a normally-off switching element; and provide a constitution and a manufacturing method of the same which achieve high-speed response and high-speed drive of a semiconductor device; and provide a semiconductor device having high reliability while improving ON characteristics of a transistor.SOLUTION: In a transistor where a semiconductor layer, a source electrode layer or a drain electrode layer, a gate insulation film and a gate electrode layer are sequentially laminated, an oxide semiconductor layer which contains at least four elements such as indium, gallium, zinc and oxygen and when composition ratios of the four elements are represented by atomic percentages, a ratio of indium is equal to or larger than twice the ratio of each of gallium and zinc is used as the semiconductor layer.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Generally speaking, electro-optical devices, semiconductor circuits, and electronic devices are all semiconductor devices. [Background technology]

[0003] A transistor (thin film transistor) is made using a semiconductor thin film formed on a substrate with an insulating surface. The technology of constructing thin-film transistors (also called TFTs) is attracting attention. It is widely used in electronic devices such as ICs and image display devices. Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors. As another material, oxide semiconductors are attracting attention.

[0004] For example, indium (In), gallium (Ga), and nickel are used as active layers of transistors. A transistor using an amorphous oxide containing lead (Zn) has been disclosed (see Patent Document 1). ). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2006-165528 A Summary of the Invention [Problem to be solved by the invention]

[0006] The threshold voltage of a transistor that uses an oxide semiconductor in the channel formation region is plotted. This transistor structure realizes a so-called normally-off switching element. One of the objectives of the present invention is to provide a structure and a method for manufacturing the same.

[0007] In order to realize a semiconductor device with higher performance, the on-characteristics of a transistor (e.g., A configuration that improves the current and field effect mobility to realize high-speed response and high-speed operation of semiconductor devices. It is another object of the present invention to provide a method for manufacturing the same.

[0008] Furthermore, the threshold voltage is unlikely to fluctuate even when used for a long period of time, making the semiconductor device highly reliable. One of our goals is to provide the following:

[0009] The object of the present invention is to solve at least one of the above problems. [Means for solving the problem]

[0010] A semiconductor layer, a source electrode layer or a drain electrode layer, a gate insulating film, and a gate electrode layer are stacked in this order. In the layered transistor, the semiconductor layer is made of indium, gallium, zinc, and oxide. When the composition ratio of the four elements is expressed in atomic percentage, The oxide semiconductor layer has a ratio of gallium or more that is twice as large as the ratio of gallium and the ratio of zinc.

[0011] One embodiment of the configuration of the present invention disclosed in this specification is a channel formation region provided on an oxide insulating layer. a gate insulating film on the oxide semiconductor layer; and an oxide semiconductor layer on the gate insulating film. a gate electrode layer overlapping the oxide semiconductor layer, When the composition ratio of the four elements is expressed in atomic percentage, The semiconductor device has an indium content of at least twice the gallium content and the zinc content. .

[0012] One embodiment of the configuration of the present invention disclosed in this specification is a channel formation region provided on an oxide insulating layer. an oxide semiconductor layer including a source electrode layer and a drain electrode layer over the oxide semiconductor layer; A gate insulating film is formed on the source electrode layer and the drain electrode layer, and an oxide semiconductor layer is formed on the gate insulating film. and a gate electrode layer overlapping the gate electrode layer. The oxide semiconductor layer is made of indium, gallium, zinc, and oxygen. The composition ratio of the four elements is expressed in atomic percentage. The proportion of gallium is at least twice as high as the proportion of zinc.

[0013] One embodiment of the present invention disclosed in this specification is a semiconductor device having a semiconductor substrate and a semiconductor device disposed on an oxide insulating layer with a space therebetween. A pair of first oxide semiconductor layers, an oxide insulating layer, and a first oxide semiconductor layer A second oxide semiconductor layer including a channel formation region, an oxide insulating layer, and a second oxide A gate insulating film is formed on the oxide semiconductor layer, and a gate insulating film overlapping the second oxide semiconductor layer is formed on the gate insulating film. and a second oxide semiconductor layer formed of four elements selected from indium, gallium, zinc, and oxygen. The composition ratio of the four elements is expressed as atomic percentage, and the ratio of indium is is more than twice the proportion of gallium and the proportion of zinc.

[0014] The oxide semiconductor layer or the second oxide semiconductor layer is a non-single crystal semiconductor having a c-axis oriented crystal structure. The crystal region may include

[0015] The oxide semiconductor layer or the second oxide semiconductor layer is a non-single-crystal semiconductor and is It can be produced using an oxide target with a lithium:zinc composition ratio of 3:1:2.

[0016] In the oxide semiconductor layer or the second oxide semiconductor layer, a region that does not overlap with the gate electrode layer is A dopant may be included.

[0017] In addition, in the oxide semiconductor layer or the second oxide semiconductor layer, The region not overlapping with the electrode layer has a higher thickness than the region overlapping with the source electrode layer or the drain electrode layer. It may be configured to have a low oxygen concentration.

[0018] Further, a dopant is introduced into the oxide semiconductor layer in a self-aligned manner by using the gate electrode layer as a mask; In the oxide semiconductor layer, the resistance between the two regions is lower than that of the channel formation region. A low-resistance region containing a dopant may be formed. The dopant increases the electrical conductivity of the oxide semiconductor layer. The dopant is an impurity that changes the material. There are two methods for introducing dopants: ion implantation and ion doping. The plasma immersion ion implantation method and the like can be used. .

[0019] The oxide semiconductor layer includes a channel formation region and a low-resistance region in the channel length direction. As a result, the transistor has high on-characteristics (e.g., on-current and field-effect mobility), High-speed operation and high-speed response are possible.

[0020] Further, a heat treatment for releasing hydrogen or moisture into the oxide semiconductor layer (dehydration or dehydrogenation treatment) may be performed. In addition, when a crystalline oxide semiconductor layer is used as the oxide semiconductor layer, A heat treatment for crystallization may be carried out.

[0021] In addition, oxygen, which is a main component material of an oxide semiconductor, can be removed by the dehydration or dehydrogenation treatment. In the oxide semiconductor film, oxygen is released and the amount of the oxide semiconductor film is reduced. In the area where the oxygen is removed, oxygen vacancies exist, and these oxygen vacancies cause fluctuations in the electrical characteristics of the transistor. Therefore, donor levels are generated.

[0022] Therefore, oxygen is preferably supplied to the oxide semiconductor layer that has been subjected to dehydration or dehydrogenation treatment. By supplying oxygen to the oxide semiconductor layer, oxygen vacancies in the film can be filled. Cut.

[0023] For example, an oxide insulating film containing a large amount (excessive amount) of oxygen, which serves as an oxygen supply source, may be used as an oxide semiconductor layer. By providing the oxide insulating film in contact with the oxide semiconductor layer, oxygen can be supplied from the oxide insulating film to the oxide semiconductor layer. In the above structure, the oxide semiconductor is subjected to a heat treatment as a dehydration or dehydrogenation treatment. The oxide insulating film is oxidized by performing a heat treatment while the oxide insulating film and the oxide layer are in contact with each other at least partially. Oxygen may be supplied to the semiconductor layer.

[0024] In addition, oxygen (at least oxygen radiative) may be added to the oxide semiconductor layer that has been subjected to the dehydration or dehydrogenation treatment. Oxygen may be supplied to the film by introducing oxygen into the film. The oxygen introduction method includes ion implantation, ion doping, plasma immersion, etc. For example, ion implantation, plasma treatment, etc. can be used.

[0025] Further, the oxide semiconductor layer provided in the transistor is preferably a crystalline oxide semiconductor. The film includes a region in which the oxygen content is excessive with respect to the stoichiometric composition ratio in the state. In this case, the oxygen content is preferably set to a level exceeding the stoichiometric composition ratio of the oxide semiconductor. Alternatively, the oxygen content is set to a level that exceeds the amount of oxygen in the case of a single crystal. Oxygen may also be present in the conductor's interstitial spaces.

[0026] Hydrogen or moisture is removed from the oxide semiconductor, and the semiconductor is highly purified to minimize the amount of impurities contained therein. By supplying oxygen to compensate for oxygen vacancies, an I-type (intrinsic) oxide semiconductor or an I-type By doing so, it is possible to obtain an oxide semiconductor that is as close to an intrinsic oxide semiconductor as possible. To bring the Fermi level (Ef) of a semiconductor to the same level as the intrinsic Fermi level (Ei) Therefore, by using the oxide semiconductor layer in a transistor, the oxide semiconductor layer can be effectively prevented from being generated due to oxygen vacancies. Reduces the variation in threshold voltage Vth of transistors and the threshold voltage shift ΔVth It is possible.

[0027] One embodiment of the present invention includes a transistor or a circuit including a transistor. The present invention relates to a semiconductor device, for example, a transistor in which a channel formation region is formed using an oxide semiconductor. The present invention relates to a semiconductor device having a circuit including a transistor. , LSI, CPU, power devices mounted on power circuits, memory, thyristors, converters, semiconductor integrated circuits including image sensors, and liquid crystal display panels. The present invention relates to electronic equipment that incorporates, as a component, a light-emitting display device having a magneto-optical device or a light-emitting element. Effect of the Invention

[0028] The threshold voltage of a transistor that uses an oxide semiconductor in the channel formation region is plotted. This transistor structure realizes a so-called normally-off switching element. The present invention provides a structure and a method for making the same.

[0029] In order to realize a semiconductor device with higher performance, the on-characteristics of a transistor (e.g., A configuration that improves the current and field effect mobility to realize high-speed response and high-speed operation of semiconductor devices. A method for producing the same can also be provided.

[0030] In addition, the threshold voltage is unlikely to shift even after long-term use, resulting in highly reliable semiconductor devices. Locations can be provided. [Brief description of the drawings]

[0031] [Figure 1] 1A to 1C illustrate one embodiment of a semiconductor device and a manufacturing method thereof; [Diagram 2] 1A to 1C illustrate one embodiment of a semiconductor device. [Diagram 3] 1A to 1C illustrate one embodiment of a semiconductor device. [Figure 4] 1A to 1C illustrate one embodiment of a semiconductor device and a manufacturing method thereof; [Diagram 5] 1A to 1C are a cross-sectional view, a plan view, and a circuit diagram illustrating one embodiment of a semiconductor device. [Figure 6] 1A and 1B are a circuit diagram and a perspective view illustrating one embodiment of a semiconductor device. [Figure 7] 1A and 1B are a cross-sectional view and a plan view illustrating one embodiment of a semiconductor device. [Figure 8] FIG. 1 is a circuit diagram illustrating one embodiment of a semiconductor device. [Figure 9] FIG. 1 is a block diagram illustrating one embodiment of a semiconductor device. [Figure 10] FIG. 1 is a block diagram illustrating one embodiment of a semiconductor device. [Figure 11] FIG. 1 is a block diagram illustrating one embodiment of a semiconductor device. [Figure 12] 1 is an energy band diagram of an oxide semiconductor; [Figure 13] 13A and 13B show XRD measurement results of an oxide semiconductor film. [Figure 14] FIG. 13 shows an evaluation of the electrical characteristics of a transistor 1. [Figure 15]13A to 13C show electrical characteristics and reliability evaluations of a transistor 2. [Figure 16] TEM image of an oxide semiconductor film. [Figure 17] FIG. 1 is a diagram showing leakage current of a transistor. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0032] Hereinafter, embodiments of the invention disclosed in this specification will be described in detail with reference to the drawings. However, the invention disclosed in this specification is not limited to the following description, and the forms and details thereof may be changed in various ways. It will be easily understood by those skilled in the art that the invention disclosed in this specification can be modified in any manner. The present invention should not be construed as being limited to the description of the following embodiments. The ordinal numbers 2 are used for convenience and do not indicate the order of steps or stacking. In addition, the present specification does not indicate specific names as matters for identifying the invention. do not have.

[0033] (Embodiment 1) In this embodiment mode, one embodiment of a semiconductor device and a manufacturing method thereof will be described with reference to FIGS. In this embodiment, a transistor having an oxide semiconductor film will be described as an example of a semiconductor device. This indicates a transistor.

[0034] A transistor can have either a single-gate structure in which one channel formation region is formed or a structure in which two are formed. The gate structure may be a double gate structure in which three gates are formed, or a triple gate structure in which three gates are formed. The semiconductor device has two gate electrode layers disposed above and below a channel region with a gate insulating film interposed therebetween. A dual gate type may also be used.

[0035] The transistor 440a shown in FIGS. 1A to 1E is a plate having a top gate structure. This is an example of a N-type transistor.

[0036] The transistor 440a is formed on a substrate 400 having an insulating surface on which an oxide insulating layer 436 is provided. An oxide semiconductor layer 4 including a channel formation region 409 and low-resistance regions 404a and 404b is formed on the oxide semiconductor layer 4 03, a source electrode layer 405a, a drain electrode layer 405b, a gate insulating film 402, a gate electrode The transistor 440a includes an electrode layer 401. An insulating film 407 is formed over the transistor 440a.

[0037] FIG. 1 shows a structure in which a source electrode layer 405a and a drain electrode layer 405b are formed over an oxide semiconductor layer 403. Although the gate electrode layer 405b does not overlap with the gate electrode layer 401, the transistor shown in FIG. As shown in FIG. 440b, the source electrode layer 405a, the drain electrode layer 405b and the gate electrode It may have a structure in which it partially overlaps with layer 401 .

[0038] The oxide semiconductor layer 403 contains at least four elements, that is, indium, gallium, zinc, and oxygen. When the composition ratio of the four elements is expressed in atomic percentage, the ratio of indium is 1 / 1000 that of gallium. The ratio of the metal and zinc in the oxide semiconductor layer is twice or more (also referred to as an IGZO layer).

[0039] The oxide semiconductor layer 403 is an oxide semiconductor layer having a composition ratio of indium:gallium:zinc of 3:1:2. The film can be fabricated by a sputtering method using a target.

[0040] The oxide semiconductor is non-single crystal and may be amorphous or polycrystalline. The structure may include a portion having crystallinity in the matrix, or may be non-amorphous.

[0041] Since it is relatively easy to obtain a flat surface for an amorphous oxide semiconductor, This can reduce interface scattering when fabricating a transistor, and can be achieved relatively easily and with relatively high quality. Therefore, high mobility can be obtained.

[0042] In addition, in a crystalline oxide semiconductor, defects in the bulk can be further reduced, and the surface By improving the flatness of the oxide semiconductor, it is possible to obtain a mobility equal to or higher than that of an oxide semiconductor in an amorphous state. In order to improve the flatness of the surface, it is preferable to form an oxide semiconductor on a flat surface. Specifically, the average surface roughness (Ra) is 1 nm or less, preferably 0.3 nm or less, and more preferably It is preferable to form the surface on a thickness of 0.1 nm or less.

[0043] In addition, Ra is the arithmetic mean roughness defined in JIS B0601 that can be applied to the surface. This is a three-dimensional extension of the method, which is based on the averaging of the absolute value of the deviation from the reference surface to the specified surface. This can be expressed as a "value" and is defined by the following formula:

[0044]

number

[0045] In the above, S0 is the measurement surface (coordinates (x1, y1) (x1, y2) (x2, y1 )(x2,y2) is the rectangular area bounded by the four points, and Z0 is It refers to the average height of the measurement surface. Ra is measured by an atomic force microscope (AFM). It can be evaluated using a microscope.

[0046] As the oxide semiconductor layer 403, an oxide semiconductor layer that contains crystals and has crystallinity (a crystalline oxide The crystalline state of the crystalline oxide semiconductor layer is such that the crystal axis The directions may be in a random state or may have a certain orientation.

[0047] For example, the crystalline oxide semiconductor layer may be formed of an oxide semiconductor material having crystals with a c-axis approximately perpendicular to the surface. A nitride semiconductor layer can be used.

[0048] The oxide semiconductor layer including crystals having a c-axis approximately perpendicular to the surface does not have a single crystal structure, It is not an amorphous structure, but a crystal with c-axis orientation (C Axis Aligned Crystal (CAAC)-containing oxide semiconductor (CAAC-OS) layer. .

[0049] CAAC-OS is a type of nanostructure that has a c-axis orientation and is three-dimensionally aligned in the direction perpendicular to the ab plane, surface, or interface. It has a square or hexagonal atomic arrangement, and the metal atoms are arranged in layers in the direction perpendicular to the c-axis. Or metal atoms and oxygen atoms are arranged in layers, and the ab plane (or surface or interface) In CA, the a-axis or b-axis is rotated around the c-axis. A thin film containing AC is a thin film crystallized along the c axis, but not necessarily along the ab plane. Not arranged.

[0050] In a broad sense, CAAC is a non-single crystal that has a triangular shape when viewed perpendicular to the ab plane. The atomic arrangement is a regular triangle or a regular hexagon, and the c-axis direction is perpendicular to the When viewed from a certain direction, the phase includes a phase in which metal atoms are arranged in layers or metal atoms and oxygen atoms are arranged in layers.

[0051] A thin film containing CAAC is not a single crystal, but is not composed solely of amorphous matter. In addition, the thin film containing CAAC contains crystallized parts (crystalline parts), but one crystalline part and another In some cases, the boundaries of the crystalline portions cannot be clearly distinguished.

[0052] A part of the oxygen constituting the CAAC may be replaced by nitrogen. The c-axis of each crystalline part is aligned in a certain direction (e.g., the substrate surface on which the CAAC is formed or the C The AAC may be aligned in a direction perpendicular to the surface, film surface, interface, etc. of the AAC. Alternatively, the CAAC may be aligned in a direction perpendicular to the film surface, interface, etc. of the AAC. The normal to the ab plane of each crystal part that constitutes the thin film is in a certain direction (for example, the substrate surface, the surface , perpendicular to the film surface, interface, etc.

[0053] By using the crystalline oxide semiconductor layer, the electric field of the transistor can be reduced by irradiation with visible light or ultraviolet light. Thus, the change in electrical characteristics can be further suppressed, resulting in a highly reliable semiconductor device.

[0054] There are three methods for obtaining a crystalline oxide semiconductor layer having a c-axis orientation. The oxide semiconductor layer is formed at a film formation temperature of 200° C. to 500° C., and the oxide semiconductor layer is formed on the surface of the oxide semiconductor layer. The second method is to form a thin film and then heat it at 200°C or higher for 70°C. The third method is to align the c-axis approximately perpendicular to the surface by heat treatment at 0°C or less. After the first layer is thinly formed, it is heated at 200℃ to 700℃ to form the second layer. This method involves forming a film and orienting the c-axis approximately perpendicular to the surface.

[0055] The thickness of the oxide semiconductor layer 403 is 1 nm to 30 nm (preferably 5 nm to 10 nm). m or less) and sputtering method, MBE (Molecular Beam Epita xy) method, CVD method, pulsed laser deposition method, ALD (Atomic Layer Dep The oxide semiconductor layer 403 can be formed by a spatulation method or the like. Film deposition is performed on multiple substrate surfaces set approximately perpendicular to the target surface. Alternatively, the film may be formed using a sputtering apparatus which performs the above steps.

[0056] The CAAC-OS film can be formed, for example, by sputtering a polycrystalline oxide semiconductor target. The sputtering target is used to form a film by sputtering. Upon impact, the crystalline regions in the sputtering target cleave from the ab plane, forming a -b: The particles peel off as plate-like or pellet-like sputtered particles with surfaces parallel to the surface. In this case, the plate-like sputtered particles may be crystalline and may be crystalline. By reaching the plate, a CAAC-OS film can be formed.

[0057] In addition, the following conditions are preferably applied to form the CAAC-OS film.

[0058] By reducing the amount of impurities mixed in during film formation, it is possible to prevent the crystal state from being destroyed by impurities. For example, the concentration of impurities (hydrogen, water, carbon dioxide, nitrogen, etc.) present in the film formation chamber is In addition, the impurity concentration in the deposition gas may be reduced. A deposition gas having a temperature of -80°C or lower, preferably -100°C or lower, is used.

[0059] In addition, by increasing the substrate heating temperature during film formation, the migration of sputtered particles after they reach the substrate is reduced. Specifically, the substrate heating temperature is set to 100° C. or higher and 740° C. or lower, preferably The deposition temperature is set to 200°C or higher and 500°C or lower. When a plate-shaped sputtered particle reaches a substrate, migration occurs on the substrate, The flat surface of the sputtered particle adheres to the substrate.

[0060] In addition, by increasing the oxygen ratio in the deposition gas and optimizing the power, plasma damage during deposition is reduced. The oxygen ratio in the deposition gas is preferably 30% by volume or more, and more preferably 100% by volume or more. The product is %.

[0061] As an example of a sputtering target, an In-Ga-Zn-O compound target is The details are shown below.

[0062] InO X powder, GaO Y Powder and ZnO Z The powders are mixed in a specified molar ratio and pressurized. Then, it is heated at a temperature between 1000℃ and 1500℃ to produce polycrystalline In-G The target is a-Zn-O compound. X, Y, and Z are any positive numbers. The specified mole ratio is, for example, InO X powder, GaO Y Powder and ZnO Z The powder, 2:2:1, 8:4:3, 3:1:1, 1:1:1, 4:2:3 or 3:1:2 mo The powder types and their mixing ratios depend on the sputtering process to be produced. The thickness may be appropriately changed depending on the target.

[0063] An example of a manufacturing method using a transistor 440a is shown in FIGS.

[0064] First, an oxide insulating layer 436 is formed over a substrate 400 having an insulating surface.

[0065] There is no significant limitation on the substrate that can be used for the substrate 400 having an insulating surface. In either case, it is necessary to have heat resistance sufficient to withstand subsequent heat treatment. Glass substrates such as borosilicate glass and aluminoborosilicate glass, ceramic substrates, A quartz substrate, a sapphire substrate, etc. can be used. In addition, a silicon substrate, a silicon carbide substrate, etc. can be used. Any single crystal semiconductor substrate, polycrystalline semiconductor substrate, compound semiconductor substrate such as silicon germanium A semiconductor device having a semiconductor element on a substrate such as a silicon-on-insulator (SOI) substrate can also be used. may be used as the substrate 400.

[0066] A semiconductor device may be manufactured using a flexible substrate as the substrate 400. In order to manufacture such a semiconductor device, a transistor including an oxide semiconductor layer 403 is formed on a flexible substrate. Alternatively, the transistor 440a including the oxide semiconductor layer 403 may be formed on another substrate. Alternatively, the resistor 440a may be fabricated and then peeled off and transferred to a flexible substrate. In order to peel and transfer the transistor 4 including the oxide semiconductor film from the substrate to a flexible substrate, A release layer may be provided between 40a and the film.

[0067] The oxide insulating layer 436 is formed by depositing an oxide insulating film by a plasma CVD method, a sputtering method, or the like. Silicon, silicon oxynitride, aluminum oxide, aluminum oxynitride, hafnium oxide , gallium oxide, or a mixture of these materials.

[0068] The oxide insulating layer 436 may be a single layer or a stacked layer. For example, Alternatively, the In-Hf-Zn oxide film and the oxide semiconductor layer 403 may be laminated in this order on the substrate 4. 00, silicon oxide film, In-Zr-Zn with atomic ratio of In:Zr:Zn=1:1:1 A silicon oxide film and an oxide semiconductor layer 403 may be laminated in this order. In-Gd-Zn oxide film with an atomic ratio of In:Gd:Zn=1:1:1, oxide The semiconductor layers 403 may be stacked in order.

[0069] In this embodiment, the oxide insulating layer 436 is formed using a silicon oxide film by a sputtering method. Use a Con membrane.

[0070] A nitride insulating film may be provided between the oxide insulating layer 436 and the substrate 400. The nitride insulating film is formed by depositing silicon nitride, nitride, etc., by plasma CVD or sputtering. Silicon oxide, aluminum nitride, aluminum oxide nitride, or a mixture of these materials is used. It can be formed by:

[0071] Next, the oxide semiconductor layer 403 is formed over the oxide insulating layer 436.

[0072] The oxide insulating layer 436 is in contact with the oxide semiconductor layer 403 and therefore has a small amount of oxide in the film (bulk). In both cases, it is preferable that the amount of oxygen present exceeds the stoichiometric composition ratio. For example, in the case of oxide insulation, When a silicon oxide film is used as the layer 436, SiO 2+α (where α>0) By using such an oxide insulating layer 436, oxygen can be supplied to the oxide semiconductor layer 403. Oxygen can be supplied to the oxide semiconductor layer 403, and the characteristics can be improved. By doing so, oxygen vacancies in the film can be compensated for.

[0073] For example, the oxide insulating layer 436 containing a large amount (excessive amount) of oxygen, which serves as an oxygen source, is formed on an oxide semiconductor. By providing the oxide insulating layer 436 in contact with the oxide semiconductor layer 403, The oxide semiconductor layer 403 and the oxide insulating layer 436 can be supplied with oxygen. By performing heat treatment in a state where the oxide semiconductor layer 403 is at least partially in contact with the oxide semiconductor layer 403, oxygen is introduced into the oxide semiconductor layer 403. Supply may be provided.

[0074] In the step of forming the oxide semiconductor layer 403, hydrogen or water is added to the oxide semiconductor layer 403. In order to prevent the inclusion of the oxide semiconductor layer 403, a sputtering process was performed as a pretreatment for the formation of the oxide semiconductor layer 403. The substrate on which the oxide insulating layer 436 is formed is preheated in a preheating chamber of the deposition apparatus, and the substrate and It is preferable to desorb and exhaust impurities such as hydrogen and moisture adsorbed in the oxide insulating layer 436. The exhaust means provided in the preheating chamber is preferably a cryopump.

[0075] A planarization treatment is performed on a region of the oxide insulating layer 436 that is to be in contact with the oxide semiconductor layer 403. The planarization process may be, but is not limited to, a polishing process (e.g., chemical polishing). Chemical Mechanical Polishing (CMP) A method for removing the impurities, a dry etching process, or a plasma process can be used.

[0076] The plasma treatment may be, for example, a reverse sputtering treatment in which argon gas is introduced to generate plasma. Reverse sputtering is a process in which RF is applied to the substrate side in an argon atmosphere. This method involves applying voltage using a power supply to generate plasma in the vicinity of the substrate to modify the surface. Instead of the argon atmosphere, nitrogen, helium, oxygen, etc. may be used. When the cleaning is performed, powdery substances (particles, dust, etc.) attached to the surface of the oxide insulating layer 436 are removed. (also called) can be removed.

[0077] As the planarization process, the polishing process, the dry etching process, and the plasma process may be performed multiple times. In addition, when performing the steps in combination, the order of the steps is not particularly limited. The thickness is not limited to a specific value and may be appropriately set depending on the unevenness of the surface of the oxide insulating layer 436.

[0078] Note that the oxide semiconductor layer 403 is formed under conditions in which a large amount of oxygen is contained (for example, The film is formed by sputtering in a 100% oxygen atmosphere. (preferably, the oxide semiconductor has a stoichiometric composition ratio in a crystalline state, and Preferably, the membrane is a membrane containing regions in which the amount of

[0079] Note that in this embodiment, the oxide semiconductor layer 403 is formed by a sputtering method. The target composition is In:Ga:Zn=3:1:2 [atomic percentage]. Using this oxide target, an In-Ga-Zn oxide film (IGZO film) is formed.

[0080] The relative density (filling rate) of the metal oxide target is preferably 90% or more and 100% or less. The relative density is 95% or more and 99.9% or less. Use a metal oxide target with high relative density. As a result, the formed oxide semiconductor film can be a dense film.

[0081] The oxide semiconductor layer 403 is formed using a sputtering gas of hydrogen, water, a hydroxyl group, or an arsenic compound. It is preferable to use a high-purity gas from which impurities such as hydrides have been removed.

[0082] The substrate is held in a film-forming chamber that is kept in a reduced pressure state. Then, the remaining moisture in the film-forming chamber is removed. A sputtering gas from which hydrogen and moisture have been removed is introduced, and the substrate 40 is sputtered using the above target. In order to remove moisture remaining in the deposition chamber, an oxide semiconductor layer 403 is formed on the oxide semiconductor layer 403. type vacuum pumps, such as cryopumps, ion pumps, titanium sublimation pumps It is preferable to use a turbo molecular pump with a cold trap as the exhaust means. The deposition chamber evacuated using a cryopump may be, for example, Hydrogen atoms, water (H2O) and other compounds that contain hydrogen atoms (preferably compounds that contain carbon atoms) Since gases such as impurities and impurities are exhausted from the deposition chamber, the impurities contained in the oxide semiconductor layer 403 formed in the deposition chamber are The concentration of substances can be reduced.

[0083] In addition, the oxide insulating layer 436 and the oxide semiconductor layer 403 are successively formed without exposure to the air. It is preferable that the oxide insulating layer 436 and the oxide semiconductor layer 403 be connected without exposure to air. When the oxide insulating layer 436 is formed in succession, impurities such as hydrogen and moisture are adsorbed to the surface of the oxide insulating layer 436. It can be prevented.

[0084] The oxide semiconductor layer 403 is formed by forming an oxide semiconductor film into an island shape by a photolithography process. The insulating film can be formed by processing into an oxide semiconductor layer.

[0085] In addition, a resist mask for forming the island-shaped oxide semiconductor layer 403 was formed by an ink-jet method. If the resist mask is formed by the inkjet method, a photomask is not used. This reduces the manufacturing cost.

[0086] Note that the etching of the oxide semiconductor film may be dry etching or wet etching. For example, an etchant used for wet etching of an oxide semiconductor film may be used. The cleaning solution can be a mixture of phosphoric acid, acetic acid, and nitric acid. O07N (manufactured by Kanto Chemical Co., Ltd.) may also be used.

[0087] In addition, excess hydrogen (including water and a hydroxyl group) is removed (dehydrated or The temperature for the heat treatment is 300° C. or higher and 700° C. or lower. The temperature should be below ℃ or below the distortion point of the substrate. Heat treatment should be performed under reduced pressure or in a nitrogen atmosphere. For example, the substrate can be introduced into an electric furnace, which is one type of heat treatment device, and an oxide semiconductor The layer 403 is subjected to a heat treatment at 450° C. for 1 hour in a nitrogen atmosphere.

[0088] The heat treatment device is not limited to an electric furnace, and may be a heat treatment device using heat conduction or heat from a heating element such as a resistance heating element. A device that heats the workpiece by radiation may be used. For example, a GRTA (Gas Reactor Transformer) apid Thermal Anneal) equipment, LRTA (Lamp Rapid T RTA (Rapid Thermal Anneal) equipment, etc. al) equipment can be used. The LRTA equipment can be a halogen lamp, a metal halide lamp, lamp, xenon arc lamp, carbon arc lamp, high pressure sodium lamp, high pressure mercury lamp This is a device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp or other light source. The GRTA device is a device that uses high-temperature gas to perform heat treatment. Inert gases such as argon or nitrogen that do not react with the workpiece during heat treatment An active gas is used.

[0089] For example, the substrate is placed in an inert gas heated to a high temperature of 650°C to 700°C as a heat treatment. After heating for several minutes, GRTA may be performed in which the substrate is taken out of the inert gas.

[0090] In the heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the nitrogen or hydrogen introduced into the heat treatment device is not included. The purity of rare gases such as sodium, neon, and argon is preferably 6N (99.9999%) or higher. is 7N (99.99999%) or more (i.e. impurity concentration is 1 ppm or less, preferably 0.1 It is preferable to set the concentration to less than ppm.

[0091] After the oxide semiconductor layer 403 is heated by the heat treatment, high-purity oxygen gas, high-purity 100°C nitrous oxide gas or ultra dry air (CRDS (Cavity Ring Down Laser Dispersion) When measured using a dew point meter using the optical method, the moisture content is 20 ppm (-55°C in dew point equivalent). (air having a concentration of 1 ppm or less, preferably 10 ppb or less) may be introduced. It is preferable that the oxygen gas or nitrous oxide gas does not contain water, hydrogen, etc. Alternatively, the purity of the oxygen gas or nitrous oxide gas introduced into the heat treatment device is preferably 6N or more. or 7N or more (i.e., impurity concentration in oxygen gas or nitrous oxide gas is 1 ppm or less, Preferably, the concentration is 0.1 ppm or less. The action of dehydration or dehydrogenation reduces the amount of impurities present in the process. By supplying oxygen, which is the main component of oxide semiconductors, The semiconductor layer 403 can be highly purified and made electrically I-type (intrinsic).

[0092] Note that the heat treatment for dehydration or dehydrogenation is performed on the oxide semiconductor layer 403 before processing the oxide semiconductor layer 403. If the step is performed after the formation of the compound semiconductor film and before the formation of the insulating film 407, the step of fabricating the transistor 440a may be performed. For example, after the formation of a film-like oxide semiconductor film, This can be performed after the island-shaped oxide semiconductor layer 403 is formed.

[0093] The heat treatment for dehydration or dehydrogenation may be carried out multiple times or may be carried out in combination with other heat treatments. You can sleep.

[0094] The heat treatment for dehydration or dehydrogenation is performed to process the oxide semiconductor layer 403 into an island shape. If the oxide insulating layer 436 is covered with the oxide semiconductor film, the oxide insulating layer 4 This is preferable because it can prevent the oxygen contained in 36 from being released by the heat treatment. stomach.

[0095] In addition, oxygen (at least oxygen radiative) may be added to the oxide semiconductor layer that has been subjected to the dehydration or dehydrogenation treatment. Oxygen may be supplied to the film by introducing oxygen into the film. stomach.

[0096] Oxygen is introduced into the oxide semiconductor layer 403 that has been subjected to dehydration or dehydrogenation treatment. By supplying the oxide semiconductor layer 403, the oxide semiconductor layer 403 is highly purified and electrically made to be i-type (intrinsic). The oxide semiconductor layer 403 that has been highly purified and made electrically i-type (intrinsic) can be used. The transistor thus formed has suppressed fluctuations in electrical characteristics and is electrically stable.

[0097] The oxygen introduction method includes ion implantation, ion doping, plasma immersion An implantation method, a plasma treatment, or the like can be used.

[0098] In the step of introducing oxygen into the oxide semiconductor layer 403, oxygen is introduced into the oxide semiconductor layer 403. It may be introduced directly or may be oxidized through other films such as the gate insulating film 402 and the insulating film 407. The oxygen may be introduced into the semiconductor layer 403. When oxygen is introduced through another film, ion implantation is used. implantation method, ion doping method, plasma immersion ion implantation method, etc. However, when oxygen is directly introduced into the exposed oxide semiconductor layer 403, a plasma Processing such as masking can also be used.

[0099] Oxygen may be introduced into the oxide semiconductor layer 403 after dehydration or dehydrogenation treatment. The oxide semiconductor layer 40 that has been subjected to the dehydration or dehydrogenation treatment may be formed by the following method. Oxygen may be introduced into 3 multiple times.

[0100] Next, a source electrode layer and a drain electrode layer (the same layer as this A conductive film that will become a wiring (including the wiring) is formed. The conductive film is resistant to subsequent heat treatment. As a conductive film used for the source electrode layer and the drain electrode layer, for example, A metal film containing an element selected from the group consisting of I, Cr, Cu, Ta, Ti, Mo, and W, or the above-mentioned Metal nitride films containing elements (titanium nitride film, molybdenum nitride film, tungsten nitride film) ) or the like can be used. In addition, either the upper or lower side of a metal film such as Al or Cu can be used. Both are covered with a high melting point metal film such as Ti, Mo, W, etc. or a metal nitride film of these metals (titanium nitride film, A layered structure of a molybdenum nitride film, a tungsten nitride film, etc. may also be used. The conductive film used for the electrode layer and the drain electrode layer may be formed of a conductive metal oxide. Good. Conductive metal oxides include indium oxide (In2O3) and tin oxide (SnO2 ), zinc oxide (ZnO), indium oxide tin oxide (In2O3-SnO2), indium oxide In2O3-ZnO or these metal oxide materials with silicon oxide It is possible to use one containing

[0101] A resist mask is formed on the conductive film by a photolithography process, and selective etching is performed. After forming the source electrode layer 405a and the drain electrode layer 405b by this, a resist mask Remove.

[0102] Next, the oxide semiconductor layer 403, the source electrode layer 405a, and the drain electrode layer 405b were A covering gate insulating film 402 is formed (see FIG. 1C).

[0103] In order to improve coverage of the gate insulating film 402, the oxide semiconductor layer 403 and the source The above-described planarization treatment may also be performed on surfaces of the electrode layer 405a and the drain electrode layer 405b. In particular, when a thin insulating film is used as the gate insulating film 402, the oxide semiconductor layer 403, It is preferable that the surfaces of the source electrode layer 405a and the drain electrode layer 405b have good flatness. I wish.

[0104] The thickness of the gate insulating film 402 is set to 1 nm or more and 20 nm or less. Methods such as a CVD method, a pulsed laser deposition method, and an ALD method can be used as appropriate. The insulating film 402 is formed by depositing a plurality of substrate surfaces approximately perpendicular to the sputtering target surface. The film may be formed using a sputtering device that performs film formation in a set state.

[0105] The material of the gate insulating film 402 is a silicon oxide film, a gallium oxide film, an aluminum oxide film, or the like. a silicon nitride film, a silicon oxynitride film, an aluminum oxynitride film, or a nitride oxide film. The gate insulating film 402 can be formed by using a silicon film. It is preferable that the gate insulating film 402 contains oxygen in the portion in contact with the gate insulating film 402. It is preferable that oxygen is present in the bulk in an amount exceeding the stoichiometric ratio. For example, when a silicon oxide film is used as the gate insulating film 402, SiO 2+α (where α>0). In this embodiment, the gate insulating film 402 is made of SiO 2+ α (where α>0) is used. This silicon oxide film is used as the gate insulator. By using the oxide semiconductor film 402, oxygen can be supplied to the oxide semiconductor layer 403, and the characteristics can be improved. Furthermore, the gate insulating film 402 can improve the surface roughness of the transistor to be manufactured. It is preferable to form the gate insulating film 402 in consideration of the noise and the step coverage of the gate insulating film 402 .

[0106] The material of the gate insulating film 402 is hafnium oxide, yttrium oxide, hafnium Silicate (HfSi x O y (x>0, y>0)), nitrogen-doped hafnium silicate HfSiO x N y (x>0, y>0)), hafnium aluminate (HfAl x O y (x>0, y>0)), and the use of high-k materials such as lanthanum oxide for the gate In addition, the gate insulating film 402 may have a single layer structure or a stacked structure. It may also be a structure.

[0107] Then, the gate electrode layer 401 is formed by plasma CVD or sputtering. The gate electrode layer 401 is formed on an insulating film 402 (see FIG. 1B). Titanium, Tantalum, Tungsten, Aluminum, Copper, Chromium, Neodymium, Scandium The insulating layer 11 can be formed using a metal material such as aluminum or an alloy material containing this as a main component. Also, a polycrystalline silicon film doped with an impurity element such as phosphorus is used as the gate electrode layer 401. A semiconductor film such as a nickel silicide film may be used. The electrode layer 401 may have a single-layer structure or a stacked structure.

[0108] The material of the gate electrode layer 401 is indium tin oxide or indium oxide containing tungsten oxide. Indium oxide, indium zinc oxide with tungsten oxide, indium zinc oxide with titanium oxide Indium oxide, indium tin oxide with titanium oxide, indium zinc oxide, silicon oxide A conductive material such as indium tin oxide doped with the above-mentioned conductive material can also be used. It is also possible to use a laminated structure of an electrically conductive material and the above-mentioned metal material.

[0109] In addition, a layer of the gate electrode layer 401 in contact with the gate insulating film 402 is made of a metal oxide containing nitrogen. In-Ga-Zn-O films containing nitrogen and In-Sn-O films containing nitrogen , In-Ga-O film containing nitrogen, In-Zn-O film containing nitrogen, Sn- O film, nitrogen-containing In-O film, and metal nitride film (InN, SnN, etc.) can be used. These films have a valence of 5 eV (electron volts), preferably 5.5 eV (electron volts) or more. When used as a gate electrode layer, the threshold voltage of the electrical characteristics of a transistor is increased. In this way, the voltage can be made positive, and a so-called normally-off switching element can be realized.

[0110] Next, the gate electrode layer 401, the source electrode layer 405a, and the drain electrode layer 405b are formed on a mask. A dopant 421 is introduced into the oxide semiconductor layer 403 as a gate insulating film, and the low resistance regions 404a and 40 Form 4b.

[0111] The thicknesses of the source electrode layer 405a and the drain electrode layer 405b and the amount of the dopant 421 introduced Depending on the conditions, the oxide semiconductor under the source electrode layer 405a and the drain electrode layer 405b Layer 403 may or may not also be doped with dopant 421. Even if the source electrode layer 405a or the drain electrode layer 405b is exposed to the low resistance region, the concentration is low. In some cases, the resistance may be higher than that of the surrounding area.

[0112] The transistor 440c shown in FIG. 2B includes a source electrode layer 405a, a drain electrode layer 40 As 5b, a thin tungsten film, for example, 10 nm thick, is formed. When the thicknesses of the electrode layer 405a and the drain electrode layer 405b are small, a low resistance region is formed. When a dopant is introduced into the oxide semiconductor layer 403, The oxide semiconductor layer 405b passes through the source electrode layer 405a and the drain electrode layer 405b. Dopants can also be introduced into the semiconductor layer 403. Thus, the transistor 440c is The regions of the oxide semiconductor layer 403 below the source electrode layer 405a and the drain electrode layer 405b also have low resistance. Regions 404a and 404b are formed.

[0113] The dopant 421 is an impurity that changes the electrical conductivity of the oxide semiconductor layer 403. The 421st group of elements includes group 15 elements (typically phosphorus (P), arsenic (As), and antimony). Sb), Boron (B), Aluminum (Al), Nitrogen (N), Argon (Ar) , Helium (He), Neon (Ne), Indium (In), Fluorine (F), Chlorine (Cl ), titanium (Ti), and zinc (Zn) may be used. can.

[0114] The dopant 421 is implanted into other films (e.g., the insulating film 407, the source electrode layer 405, a) and the drain electrode layer 405b) into the oxide semiconductor layer 403. The method of introducing the dopant 421 includes ion implantation, ion doping, and proton implantation. The plasma ion implantation method can be used. It is preferable to use a single ion of the dopant 421 or an ion of a fluoride or chloride. It is nice.

[0115] The dopant 421 introduction process is performed by controlling the injection conditions such as the acceleration voltage and the dose amount, and the membrane through which the dopant 421 passes. In this embodiment, boron is used as the dopant 421. Boron ions are implanted by ion implantation using boron. The amount of deviation is 1×10 13 ions / cm 2 5×10 or more 16 ions / cm 2 Let's say the following: stomach.

[0116] The concentration of dopant 421 in the low resistance region is 5×10 18 / cm 3 More than 1×10 22 / cm 3 It is preferable that:

[0117] The dopant 421 may be introduced while the substrate 400 is being heated.

[0118] Note that the treatment of introducing the dopant 421 into the oxide semiconductor layer 403 may be performed multiple times. A plurality of dopants may be used.

[0119] After the dopant 421 is introduced, a heat treatment may be performed. The temperature is 300°C to 700°C, preferably 300°C to 450°C, for 1 hour in an oxygen atmosphere. It is preferable to carry out the heating under nitrogen atmosphere, reduced pressure, or air (ultra-dry air). Processing may be carried out.

[0120] When the oxide semiconductor layer 403 is a crystalline oxide semiconductor film, the dopant 421 is introduced. In this case, a heat treatment is performed after the introduction of the dopant 421. By this, the crystallinity of the oxide semiconductor layer 403 can be restored.

[0121] Therefore, in the oxide semiconductor layer 403, the low-resistance regions 40 An oxide semiconductor layer 403 including the layers 404a and 404b is formed.

[0122] Through the above steps, a transistor 440a of this embodiment is manufactured (see FIG. 1C). The composition ratio of at least four elements, indium, gallium, zinc, and oxygen, is When expressed in atomic percentage, the proportion of indium is more than twice the proportion of gallium and the proportion of zinc. By using the oxide semiconductor layer 403 using the IGZO film, a transistor To give 440a high on-characteristics (field effect mobility), low off-current, and high reliability This becomes possible.

[0123] Next, the oxide semiconductor layer 403, the source electrode layer 405a, the drain electrode layer 405b, An insulating film 407 is formed over the gate insulating film 402 and the gate electrode layer 401 (see FIG. 1(D)).

[0124] The insulating film 407 is formed by a plasma CVD method, a sputtering method, a vapor deposition method, or the like. The insulating film 407 is typically a silicon oxide film, a silicon oxynitride film, or a silicon oxide nitride film. For example, an inorganic insulating film such as an aluminum oxide film or a gallium oxide film can be used.

[0125] The insulating film 407 may be an aluminum oxide film, a hafnium oxide film, or a magnesium oxide film. film, zirconium oxide film, lanthanum oxide film, barium oxide film), or metal nitride film (e.g. For example, an aluminum nitride film can also be used.

[0126] The insulating film 407 may be a single layer or a multilayer, for example, a silicon oxide film and an aluminum oxide film. A laminate of the above can be used.

[0127] The insulating film 407 is formed by mixing impurities such as water and hydrogen into the insulating film 407 by a method such as sputtering. In addition, the insulating film 407 is preferably formed by using an appropriate method. When the insulating film in contact with the conductor layer 403 contains excess oxygen, the oxide semiconductor layer 403 This is preferable because it serves as a source of oxygen.

[0128] In this embodiment, a silicon oxide film having a thickness of 100 nm is formed as the insulating film 407 by sputtering. The silicon oxide film is formed by sputtering. Typically, under an argon atmosphere, oxygen atmosphere, or a mixture of rare gas and oxygen atmosphere. This can be done.

[0129] In order to remove residual moisture in the deposition chamber of the insulating film 407, similarly to the deposition of the oxide semiconductor film, It is preferable to use an adsorption type vacuum pump (such as a cryopump). The concentration of impurities contained in the insulating film 407 formed in the film formation chamber evacuated by using a vacuum pump can be reduced. In addition, as an exhaust means for removing residual moisture in the film forming chamber of the insulating film 407, a turbo A molecular pump plus a cold trap may also be used.

[0130] The insulating film 407 is formed using a sputtering gas of hydrogen, water, a hydroxyl group, or hydrogen. It is preferable to use a high-purity gas from which impurities such as oxides have been removed.

[0131] An aluminum oxide film that can be used as the insulating film 407 provided over the oxide semiconductor layer 403 The aluminum film has a blocking effect that does not allow impurities such as hydrogen and moisture, as well as oxygen, to pass through the film. The blocking effect is high.

[0132] Therefore, the aluminum oxide film is free from hydrogen, which is a variable factor during and after the manufacturing process. Impurities such as moisture may be mixed into the oxide semiconductor layer 403, and the main components of the oxide semiconductor may be The oxide semiconductor layer 403 functions as a protective film for preventing oxygen, which is a material, from being released from the oxide semiconductor layer 403 .

[0133] In addition, a planarizing insulating film may be formed to reduce surface irregularities caused by the transistors. The smoothing insulating film is made of organic materials such as polyimide, acrylic, and benzocyclobutene resins. In addition to the above organic materials, low-dielectric constant materials (low-k materials) can be used. In addition, by stacking a plurality of insulating films made of these materials, A planarizing insulating film may be formed.

[0134] In addition, the source electrode layer 405a and the drain electrode layer 405b are formed on the gate insulating film 402 and the insulating film 407. An opening is formed reaching the source electrode layer 405a and the drain electrode layer 405b in the opening. Wiring layers 465a and 465b are formed to electrically connect the wiring layers 465a and 465b (see FIG. 1(E)). 5a, 465b can be used to connect with other transistors to configure various circuits. do.

[0135] In addition, as in a transistor 440d shown in FIG. The wiring layers 465a and 465b are directly formed on the oxide semiconductor layer 403 without providing the gate electrode layer 405b. It may be provided so as to be in contact with the surface of the substrate.

[0136] The wiring layer 465a and the wiring layer 465b are connected to the gate electrode layer 401 and the source electrode layers 405a and 405 For example, the wiring layer 465a and the wiring The layer 465b may be a laminate of a tantalum nitride film and a copper film, or a tantalum nitride film and a tungsten film. and the like can be used.

[0137] The oxide semiconductor layer 403 which is highly purified and in which oxygen vacancies are filled is free of impurities such as hydrogen and water. The hydrogen concentration in the oxide semiconductor layer 403 is 5×10 19 / cm 3 below , preferably 5 x 10 18 / cm 3 Note that the hydrogen concentration in the oxide semiconductor layer 403 is as follows. Secondary ion mass spectrometry (SIMS) This is measured by optic ectrometry.

[0138] The oxide film produced by the present embodiment is highly purified and contains an excess of oxygen to compensate for the oxygen deficiency. The transistor 440a using the organic semiconductor layer 403 has a current value in an off state (off current value) at room temperature per 1 μm of channel width, is 1×10 -21 A) or less, preferably to a level of 50zA / μm or less. can.

[0139] As described above, the threshold of the electrical characteristics of a transistor in which an oxide semiconductor is used for a channel formation region can be obtained. This allows a low voltage to be made positive, realizing what is called a normally-off switching element. A transistor structure and a method for fabricating the same may be provided.

[0140] In order to realize a semiconductor device with higher performance, the on-characteristics of a transistor (e.g., A configuration that improves the current and field effect mobility to realize high-speed response and high-speed operation of semiconductor devices. A method for producing the same can also be provided.

[0141] Furthermore, the threshold voltage is unlikely to fluctuate even when used for a long period of time, making the semiconductor device highly reliable. can be provided.

[0142] (Embodiment 2) In this embodiment mode, another embodiment of a semiconductor device and a manufacturing method of the semiconductor device will be described with reference to FIGS. The following description will be given using the following examples. The same parts as those in the above embodiment or parts and steps having similar functions are The above-mentioned embodiment can be carried out in the same manner, and the repeated explanation will be omitted. Detailed explanation will be omitted.

[0143] The transistor 450 shown in FIGS. 3A to 3C is a top-gate transistor. This is an example. Fig. 3(A) is a plan view, and Fig. 3(A) is a cross section taken along the dashed line XY in Fig. 3(A). corresponds to Fig. 3(B), and the cross section cut by the dashed line VW in Fig. 3(A) corresponds to Fig. 3(C). Correct.

[0144] As shown in FIG. 3B, which is a cross-sectional view in the channel length direction, the transistor 450 has an oxide A first oxide semiconductor layer is formed on a substrate 400 having an insulating surface on which an insulating layer 436 is provided. the oxide semiconductor layers 408a and 408b, the channel formation region 409, the low-resistance region 414a, The oxide semiconductor layer 403, which is the second oxide semiconductor layer including the oxide semiconductor layer 414b, the source electrode layer 405 a, a drain electrode layer 405b, a gate insulating film 402, and a gate electrode layer 401. The oxide semiconductor layers 408a and 408b are formed on the oxide insulating layer 436 with a gap therebetween. The oxide semiconductor layer 403 includes the oxide semiconductor layers 408a and 408b and the oxide insulating layer 436. It is formed in contact.

[0145] FIG. 3C is a cross-sectional view in the channel width direction, in which the oxide semiconductor layer 403 is bent at an angle of 20 degrees to the edge. It has a 50 degree taper. If the end is vertical, oxygen will escape easily and oxygen defects will occur. However, by having a taper at the end, oxygen defects are suppressed, and the leakage of the transistor 450 is reduced. It reduces the generation of current (parasitic channel).

[0146] Oxide semiconductor layers 408a and 408b are provided under an oxide semiconductor layer 403 having a thickness of 3 to 5 nm. This can reduce the contact resistance with the source electrode layers 405a and 405b. do.

[0147] The low resistance regions 414a and 414b are formed by etchant-coating the oxide semiconductor layer 40 using the gate electrode layer 401 as a mask. The low resistance region can be formed by introducing a dopant into 3. It can also be formed by diffusing dopants and metal elements. By forming a low resistance region, the contact resistance with the wiring layer can be further reduced. do.

[0148] Further, a sidewall insulating layer having a sidewall structure may be provided on the side surface of the gate electrode layer 401. The transistor 450 is provided with thin sidewall insulating layers 412a and 412b on the side surfaces of the gate electrode layer 401. The sidewall insulating layers 412a and 412b are insulating layers covering the gate electrode layer 401. After forming the vein, this is then subjected to RIE (Reactive ion etching). The insulating film is processed by anisotropic etching using the ion etching method, and the gate electrode layer is Sidewall insulating layers 412a and 412b having a sidewall structure are formed in a self-aligned manner on the sidewalls of 401. Here, the insulating film is not particularly limited, but for example, TEOS (Tetra ethyl-Ortho-Silicate) or silane, etc., and oxygen or suboxide Silicon oxide, which has good step coverage and is formed by reacting with nitrogen or the like, can be used. The coating is made by thermal CVD, plasma CVD, atmospheric CVD, bias ECRCVD, and sputtering. It can be formed by low temperature oxidation (LTO). Silicon oxide formed by a thermal oxidation method may be used.

[0149] By providing the sidewall insulating layers 412a and 412b, the gate electrode layer 401 and the low resistance region 404 a, 404b can be prevented from shorting.

[0150] When a dopant is introduced into the entire oxide semiconductor layers 408a and 408b to form low-resistance regions, The oxide insulating layer 436 is electrically connected to other conductive layers under the oxide semiconductor layers 408a and 408b. The continuation can be done.

[0151] The oxide semiconductor layer 403 is formed by forming a semiconductor layer including at least four elements of indium, gallium, zinc, and oxygen. When the composition ratio of the four elements is expressed in atomic percentage, the ratio of indium is 1 / 100 the ratio of gallium. The IGZO film has a high field effect mobility, with a ratio of Zn and ZnO more than twice that of Zn. By thinning to 5 nm, the normal transistor This can prevent over-turning on.

[0152] The oxide semiconductor layers 408a and 408b may be formed of indium oxide, tin oxide, zinc oxide, or tin oxide. In-Zn oxides, Sn-Zn oxides, and Al-Zn oxides, which are oxides of elemental metals , Zn-Mg oxide, Sn-Mg oxide, In-Mg oxide, In-Ga oxide , In-Ga-Zn oxide (also written as IGZO), which is an oxide of a ternary metal, In -Al-Zn oxide, In-Sn-Zn oxide, Sn-Ga-Zn oxide, Al- Ga-Zn oxide, Sn-Al-Zn oxide, In-Hf-Zn oxide, In-L a-Zn oxide, In-Ce-Zn oxide, In-Pr-Zn oxide, In-Nd -Zn oxide, In-Sm-Zn oxide, In-Eu-Zn oxide, In-Gd- Zn-based oxide, In-Tb-Zn-based oxide, In-Dy-Zn-based oxide, In-Ho-Z n-type oxides, In-Er-Zn-type oxides, In-Tm-Zn-type oxides, In-Yb-Zn In-Sn-Ga-Z oxides, In-Lu-Zn ​​oxides, and oxides of quaternary metals, such as In-Sn-Ga-Z n-based oxides, In-Hf-Ga-Zn-based oxides, In-Al-Ga-Zn-based oxides, In -Sn-Al-Zn oxide, In-Sn-Hf-Zn oxide, In-Hf-Al-Z An n-based oxide can be used.

[0153] The oxide semiconductor layers 408a and 408b may be formed using a material such as indium oxide, tin oxide, or zinc oxide. Alternatively, an oxide semiconductor layer having high conductivity may be used.

[0154] In this embodiment, the oxide semiconductor layers 408a and 408b are formed using an indium:gallium: An oxide semiconductor layer is used that is produced using an oxide target with a zinc composition ratio of 1:1:1.

[0155] The oxide semiconductor layers 408a and 408b may have a thickness of 20 to 50 nm.

[0156] An example of a method for manufacturing the transistor 450 is shown in FIGS.

[0157] First, an oxide insulating layer 436 is formed over a substrate 400 having an insulating surface, and the oxide insulating layer 43 An oxide semiconductor film 444 is formed over the oxide semiconductor film 6 (see FIG. 4A). The conductor film 444 is formed by using an oxide target having a composition ratio of indium, gallium, and zinc of 1:1:1. The film is formed by sputtering using a film.

[0158] Next, the oxide semiconductor film 444 is processed into an island shape by a photolithography process. The oxide semiconductor layers 408a and 408b are formed so as to have the above structure. The oxide semiconductor layer 403 is formed in contact with the oxide insulating layer 436 and the oxide insulating layer 408a and 408b (FIG. 4 The oxide semiconductor layer 403 has a composition ratio of indium:gallium:zinc of 3:1. The oxide semiconductor layer 40 is formed by a sputtering method using an oxide target of 2. The end of the nozzle 3 is preferably tapered, and in this embodiment, it has a 30 degree taper. The shape shall be as follows.

[0159] Next, a gate insulating film 402, a gate electrode layer 401, and a gate electrode 402 are formed on the oxide semiconductor layer 403. Sidewall insulating layers 412a and 412b are formed to cover the side surfaces of the pole layer 401 (see FIG. 4(C)). The gate insulating film 402 is formed on the oxide semiconductor layer 403, and the insulating film is used as a gate electrode. The insulating layer 401 and the sidewall insulating layers 412a and 412b are used as a mask to etch the insulating layer 401. Note that part of the oxide semiconductor layer 403 is exposed.

[0160] Next, the oxide semiconductor layer 403, the source electrode layer 405a, the drain electrode layer 405b, A metal oxide semiconductor layer is formed on the gate insulating film 402 and the gate electrode layer 401. A film 417 containing the element is formed (see FIG. 1C).

[0161] Examples of the film 417 containing a metal element include a metal film, a metal oxide film, and a metal nitride film. .

[0162] The metal elements in the film containing metal elements include aluminum (Al), titanium (Ti), molybdenum (Mo), and tin (Ti). Butan (Mo), Tungsten (W), Hafnium (Hf), Tantalum (Ta), Lanthanum La, barium (Ba), magnesium (Mg), zirconium (Zr), and nickel One or more selected from the group consisting of nickel (Ni) and zinc (Ni) can be used. As the film, a metal film containing one or more selected from any of the above metal elements, a metal oxide film, or a metal nitride film (e.g., titanium nitride film, molybdenum nitride film, tungsten nitride film) In addition, dopants such as phosphorus (P) and boron (B) can be added to the film containing metal elements. In this embodiment, the film 417 containing a metal element has a conductive property. .

[0163] The film 417 containing a metal element is formed by a plasma CVD method, a sputtering method, a deposition method, or the like. The thickness of the film 417 containing the metal element is set to 5 nm or more and 30 nm or less. Good.

[0164] In this embodiment, an aluminum film having a thickness of 10 nm is used as the film 417 containing a metal element. It is formed by a tarring method.

[0165] Next, the gate insulating film 402, the gate electrode layer 401, and the sidewall insulating layers 412a and 412b are The dopant 4 is introduced into the oxide semiconductor layer 403 through the film 417 containing a metal element as a mask. 21 is selectively introduced to form a low resistance region (see FIG. 4(D)).

[0166] The dopant 421 is an impurity that changes the electrical conductivity of the oxide semiconductor layer 403. The 421st group of elements includes group 15 elements (typically phosphorus (P), arsenic (As), and antimony). Sb), Boron (B), Aluminum (Al), Nitrogen (N), Argon (Ar) , Helium (He), Neon (Ne), Indium (In), Fluorine (F), Chlorine (Cl ), titanium (Ti), and zinc (Zn) may be used. can.

[0167] The dopant may be contained in the film 417 containing a metal element.

[0168] The dopant 421 is implanted through the film 417 containing a metal element to be introduced into the oxide semiconductor The dopant 421 is introduced into the layer 403. The method of introducing the dopant 421 includes ion implantation, ion doping, etc. The plasma immersion ion implantation method, etc. can be used. In this case, the dopant 421 may be a single ion or a hydride, fluoride, or chloride. It is preferable to use the ion:

[0169] The dopant 421 introduction process is performed by adjusting the injection conditions such as the acceleration voltage and the dose amount, and the amount of gold to be passed through. The thickness of the metal-containing film 417 can be appropriately set and controlled. For example, boron can be used to When implanting boron ions using the ion implantation method, the acceleration voltage is 15 kV and the dose is 1×10 15 ions / cm 2 The dose is set to 1×10 13 ions / cm 2 More than 5× 10 16 ions / cm 2 The following would suffice.

[0170] The concentration of dopant 421 in the low resistance region is 5×10 18 / cm 3 More than 1×10 22 / cm 3 It is preferable that:

[0171] The dopant may be introduced while the substrate 400 is being heated.

[0172] Note that the treatment of introducing the dopant 421 into the oxide semiconductor layer 403 may be performed multiple times. A plurality of dopants may be used.

[0173] After the dopant 421 is introduced, a heat treatment may be performed. The temperature is 300°C to 700°C, preferably 300°C to 450°C, for 1 hour in an oxygen atmosphere. It is preferable to carry out the heating under nitrogen atmosphere, reduced pressure, or air (ultra-dry air). Processing may be carried out.

[0174] Next, heat treatment is performed while the metal-element-containing film 417 and the oxide semiconductor layer 403 are partly in contact with each other. The heat treatment is preferably carried out in an oxygen atmosphere. The heat treatment is preferably carried out in a nitrogen atmosphere under reduced pressure. The heating temperature is 100° C. or higher and 700° C. or lower, preferably 200° C. or lower. The temperature should be from 0°C to 400°C.

[0175] For example, the substrate is introduced into an electric furnace, which is one of the heat treatment devices, and the film 417 containing a metal element and The oxide semiconductor layer 403 is subjected to heat treatment at 200° C. in an oxygen atmosphere for one hour.

[0176] The heat treatment device is not limited to an electric furnace, and may be a heat treatment device using heat conduction or heat from a heating element such as a resistance heating element. A device that heats the workpiece by radiation may be used. For example, a GRTA (Gas Reactor Transformer) apid Thermal Anneal) equipment, LRTA (Lamp Rapid T RTA (Rapid Thermal Anneal) equipment, etc. al) equipment can be used. The LRTA equipment can be a halogen lamp, a metal halide lamp, lamp, xenon arc lamp, carbon arc lamp, high pressure sodium lamp, high pressure mercury lamp This is a device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp or other light source. The GRTA device is a device that uses high-temperature gas to perform heat treatment. Inert gases such as argon or nitrogen that do not react with the workpiece during heat treatment An active gas is used.

[0177] For example, the substrate is placed in an inert gas heated to a high temperature of 650°C to 700°C as a heat treatment. After heating for several minutes, GRTA may be performed in which the substrate is taken out of the inert gas.

[0178] Heat treatment is carried out in a vacuum of nitrogen, oxygen, or ultra-dry air (water content of 20 ppm or less, preferably 1 ppm). m or less, preferably 10 ppb or less air), or rare gases (argon, helium, etc.) However, the above-mentioned nitrogen, oxygen, ultra-dry air, rare gas, or other atmosphere may be used. It is preferable that the gas does not contain nitrogen, oxygen, or hydrogen. The purity of the rare gas should be 6N (99.9999%) or more, preferably 7N (99.99999%). %) or more (i.e., the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less). preferable.

[0179] By the heat treatment, a metal element is introduced from the film 417 containing a metal element into the oxide semiconductor layer 403. As a result, low-resistance regions 414a and 414b are formed in the oxide semiconductor layer 403. , a low resistance region 414a containing a dopant and a metal element is disposed between the channel forming region 409. , 414b are formed.

[0180] In this embodiment, boron is used as the dopant and aluminum is used as the metal element. , the low resistance regions 414a, 414b contain boron and aluminum.

[0181] Next, the film 417 containing a metal element is removed by wet etching. The film 417 containing metal elements is removed by etching.

[0182] Through the above steps, the transistor 450 of this embodiment is manufactured. The oxide semiconductor layer 403 includes low-resistance regions 414a and 414b sandwiching the panel formation region 409. By having such a configuration, the transistor 450 has on-characteristics (e.g., on-current and field effect The high mobility enables high-speed operation and high-speed response.

[0183] The low resistance regions 414a and 414b can function as a source region or a drain region. By providing the low resistance regions 414a and 414b, The electric field applied to the channel forming region 409 formed between the first and second electrodes 14b can be reduced. In addition, the oxide semiconductor layer 403 and the source electrode layer 4 The drain electrode layer 405a and the drain electrode layer 405b are electrically connected to each other. The contact resistance between the layer 403 and the source electrode layer 405a and the drain electrode layer 405b is reduced. This can be done.

[0184] In addition, a planarizing insulating film may be formed to reduce surface irregularities caused by the transistors. The smoothing insulating film is made of organic materials such as polyimide, acrylic, and benzocyclobutene resins. In addition to the above organic materials, low-dielectric constant materials (low-k materials) can be used. In addition, by stacking a plurality of insulating films made of these materials, A planarizing insulating film may be formed.

[0185] In this embodiment, a planarization insulating film 415 is formed over the transistor 450. An opening is formed in the oxide insulating film 415 so as to reach the oxide semiconductor layer 403, and the oxide semiconductor layer 403 is 3, a source electrode layer 405a and a drain electrode layer 405b are formed (FIG. 4 (See (E)).

[0186] As described above, the threshold of the electrical characteristics of a transistor in which an oxide semiconductor is used for a channel formation region can be obtained. This allows a low voltage to be made positive, realizing what is called a normally-off switching element. A transistor structure and a method for fabricating the same may be provided.

[0187] In order to realize a semiconductor device with higher performance, the on-characteristics of a transistor (e.g., A configuration that improves the current and field effect mobility to realize high-speed response and high-speed operation of semiconductor devices. A method for producing the same can also be provided.

[0188] In addition, the threshold voltage is unlikely to shift even after long-term use, resulting in highly reliable semiconductor devices. Locations can be provided.

[0189] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0190] (Embodiment 3) In this embodiment, the transistor described in Embodiment 1 or 2 is used, and A semiconductor that can retain memory contents even when power is not supplied and has no limit on the number of times it can be written to. An example of a semiconductor device according to the present embodiment will be described with reference to the drawings. The transistor described in the first or second embodiment is used as the transistor 162. The transistor 162 can be any of the transistors described in Embodiment 1 and 2. The structure of the above can also be applied.

[0191] Since the off-state current of the transistor 162 is small, the use of the transistor 162 enables long-term recording. The contents of the memory can be retained, i.e., no refresh operation is required, or Therefore, it is possible to realize a semiconductor memory device in which the frequency of refresh operations is extremely low. Power consumption can be reduced sufficiently.

[0192] FIG. 5 shows an example of the configuration of a semiconductor device. FIG. 5(A) shows a cross-sectional view of the semiconductor device, and FIG. FIG. 5B is a plan view of the semiconductor device, and FIG. 5C is a circuit diagram of the semiconductor device. FIG. 5A corresponds to the cross sections taken along lines C1-C2 and D1-D2 in FIG. 5B.

[0193] The semiconductor device shown in FIG. 5(A) and FIG. 5(B) has a transistor using a first semiconductor material in the lower part. 160 and a transistor 162 made of a second semiconductor material on top. The transistor 162 has the same structure as that described in Embodiment 1 or 2. It can be said that it is completed.

[0194] Here, the first semiconductor material and the second semiconductor material may be materials having different forbidden band widths. For example, the first semiconductor material may be a semiconductor material other than an oxide semiconductor (such as silicon). The second semiconductor material can be an oxide semiconductor. The transistors used in this study can easily operate at high speed. The characteristics of the charge storage capacitor enable it to retain electric charge for a long period of time.

[0195] It should be noted that the above transistors are all n-channel transistors. However, it goes without saying that a p-channel transistor can be used. The technical essence of the present invention is to use an oxide semiconductor as the transistor 162 to store data. Since the semiconductor device is used in a semiconductor device, the semiconductor device is The specific configuration of the is not necessarily limited to that shown here.

[0196] The transistor 160 in FIG. 5A includes a semiconductor material (e.g., silicon). A channel forming region 116 is provided on a substrate 185, and a pair of electrodes are provided so as to sandwich the channel forming region 116. an impurity region 120 provided in the semiconductor substrate 10 and a metal compound region 124 in contact with the impurity region 120; A gate insulating layer 108 is provided on the channel forming region 116. In the figure, the source electrode and There are cases where a transistor does not have a drain electrode, but for convenience, such a case is also referred to as a transistor. In this case, the source region is sometimes called the The source and drain regions are sometimes referred to as the source and drain electrodes. In the specification, the term "source electrode" may include a source region.

[0197] An element isolation insulating layer 106 is provided on the substrate 185 so as to surround the transistor 160. An insulating layer 130 is provided to cover the transistor 160. To achieve this, the transistor 160 is provided with a sidewall insulating layer as shown in FIG. On the other hand, when the characteristics of the transistor 160 are important, In this case, a sidewall insulating layer is provided on the side surface of the gate electrode 110, and the regions with different impurity concentrations are formed. The impurity region 120 may include a region.

[0198] A transistor 162 illustrated in FIG. 5A is a transistor in which an oxide semiconductor is used for a channel formation region. Here, the oxide semiconductor layer 144 included in the transistor 162 is a high-purity By using a highly purified oxide semiconductor, In this way, the transistor 162 having excellent off-state characteristics can be obtained.

[0199] An insulating layer 150 is provided over the transistor 162 as a single layer or a stacked layer. A conductive layer is formed in a region overlapping the electrode layer 142a of the transistor 162 via the edge layer 150. The electrode layer 142a, the insulating layer 150, and the conductive layer 148b are provided. In other words, the electrode layer 142a of the transistor 162 is The conductive layer 148b functions as one electrode of the capacitor 164, and the conductive layer 148c functions as the other electrode of the capacitor 164. When a capacitance is not required, the capacitor 164 is not provided. The capacitor 164 may be provided above the transistor 162. Good too.

[0200] An insulating layer 152 is provided over the transistor 162 and the capacitor 164. On the insulating layer 152, a transistor 162 and wiring for connecting other transistors are provided. Although not shown in FIG. 5A, the wiring 156 is provided on the insulating layer 150, An electric current is applied via an electrode formed in an opening formed in the insulating layer 152 and the gate insulating film 146. The electrode is electrically connected to the electrode layer 142b of at least the transistor 162. The insulating film 144 is preferably provided so as to overlap with part of the oxide semiconductor layer 144 .

[0201] In FIG. 5A and FIG. 5B, the transistor 160 and the transistor 162 are The source region of the transistor 160 is provided so as to overlap at least a portion of the It is preferable that the drain region is provided so as to partially overlap the oxide semiconductor layer 144. In addition, the transistor 162 and the capacitor 164 are at least For example, the conductive layer 143b of the capacitor 164 is At least a portion of the gate electrode 128 of the transistor 160 is overlapped therewith. By adopting such a planar layout, the area occupied by the semiconductor device can be reduced. This allows for high integration.

[0202] The electrode layer 142b and the wiring 156 are electrically connected to each other. The contact may be performed by direct contact, or an electrode may be provided on the insulating layer between the electrodes and the contact may be performed through the electrode. In addition, the number of electrodes interposed may be multiple.

[0203] Next, an example of a circuit configuration corresponding to FIG. 5(A) and FIG. 5(B) is shown in FIG. 5(C).

[0204] In FIG. 5C, the first wiring (1st Line) and the source voltage of the transistor 160 The electrodes are electrically connected to the second wiring (2nd Line) and the drain of the transistor 160. The third line and the drain electrode are electrically connected. The fourth transistor 162 is electrically connected to one of the source electrode and the drain electrode. The wiring (4th Line) and the gate electrode of the transistor 162 are electrically connected. The gate electrode of the transistor 160 and the source voltage of the transistor 162 are One of the electrode or drain electrode of the fifth electrode is electrically connected to the other electrode of the capacitor 164. The wiring (5th Line) and the other electrode of the capacitor element 164 are electrically connected. .

[0205] In the semiconductor device shown in FIG. 5C, the potential of the gate electrode of the transistor 160 can be held. By taking advantage of this feature, it is possible to write, retain, and read information as follows.

[0206] The writing and holding of data will be described. First, the potential of the fourth wiring is set to The transistor 162 is turned on by applying a potential to the transistor 162. The potential of the third wiring is applied to the gate electrode of the transistor 160 and the capacitor 164. That is, a predetermined charge is applied to the gate electrode of the transistor 160 (write Here, the charges that give two different potential levels (hereafter, low-level charges, H Then, the voltage of the fourth wire is The transistor 162 is turned off by setting the potential at which the transistor 162 is turned off. By this, the charge applied to the gate electrode of the transistor 160 is held (retained). Hold).

[0207] Since the off-state current of the transistor 162 is extremely small, the gate electrode of the transistor 160 The charge is retained for a long period of time.

[0208] Next, the reading of information will be explained. A state in which a predetermined potential (constant potential) is applied to the first wiring When an appropriate potential (read potential) is applied to the fifth wiring, the gate of the transistor 160 Depending on the amount of charge held in the electrode, the second wire takes on a different potential. If the transistor 160 is an n-channel type, a high level voltage is applied to the gate electrode of the transistor 160. Apparent threshold V when a load is applied th_His the gate of transistor 160 Apparent threshold voltage V when a low-level charge is applied to the electrode th_L Lower Here, the apparent threshold voltage is the voltage at which transistor 160 is turned on. This refers to the potential of the fifth wiring required to achieve this. Therefore, the potential of the fifth wiring V th_H and V th_L By setting the potential V0 between the gate of the transistor 160 and the For example, in writing, the high level voltage When a load is applied, the potential of the fifth wire is V0 (>V th_H ) Then, Tiger When a low level charge is applied, the first transistor 160 is in the "on state." The potential of the wire 5 is V0( <V th_L ) transistor 160 is in the "off state" Therefore, the stored information can be read out by checking the potential of the second wiring. It is possible.

[0209] When memory cells are arranged in an array, only the information in a desired memory cell can be read. If the information is not read out, the state of the gate electrode is Regardless of the potential at which transistor 160 is in the “off state,” i.e., V th_H Yo Alternatively, the transistor may be turned on regardless of the state of the gate electrode. The potential at which the transistor 160 is in the "on state," that is, V th_L A larger potential Just give it to the fifth wire.

[0210] In the semiconductor device described in this embodiment, an off-state current is low when an oxide semiconductor is used for a channel formation region. By using extremely small transistors, memory contents can be retained for an extremely long period of time. In other words, the refresh operation is unnecessary or the refresh operation is possible. This allows the frequency of operation to be reduced significantly, resulting in a significant reduction in power consumption. In addition, when there is no power supply (however, it is preferable that the potential is fixed), However, it is possible to retain the stored contents for a long period of time.

[0211] In addition, the semiconductor device described in this embodiment does not require a high voltage for writing data. There is no problem with degradation of the capacitance. For example, unlike conventional non-volatile memory, the floating gate Since there is no need to inject electrons into the floating gate or extract electrons from the floating gate, The problem of deterioration of the gate insulating layer does not occur at all. The device does not have the limit on the number of times it can be rewritten, which is a problem with conventional non-volatile memory, and is reliable. Furthermore, the on and off states of transistors allow the Since writing is performed, high speed operation can be easily achieved.

[0212] In addition, the transistor 162 contains four elements, namely, indium, gallium, zinc, and oxygen, at low concentrations. When the composition ratio of the four elements is expressed in atomic percentage, the ratio of indium is 1:1, and the ratio of gallium is 1:1. The oxide semiconductor layer has a ratio of Zn and a ratio of Zn that are more than twice as high as those of the oxide semiconductor layer. By adopting such a transistor, Furthermore, the semiconductor device of the present embodiment can be used for a long period of time. In addition, since the transistors used are less susceptible to threshold voltage shift, This can improve the reliability of the device.

[0213] As described above, the configurations, methods, etc. described in this embodiment may be used in conjunction with the configurations, methods, etc. described in other embodiments. They can be used in any suitable combination.

[0214] (Embodiment 4) In this embodiment, the transistor described in Embodiment 1 or 2 is used. It is possible to retain memory contents even when power is not supplied, and there is no limit to the number of times it can be written. Regarding a semiconductor device having a structure different from that shown in the third embodiment, the structure shown in FIG. 6 and FIG. 7 will be described. Note that the semiconductor device of this embodiment is implemented as the transistor 162. The transistor according to the first or second embodiment is used. As the transistor 162, the structure of either the transistor shown in the first embodiment or the transistor shown in the second embodiment can be applied. This can be done.

[0215] FIG. 6A shows an example of a circuit configuration of a semiconductor device, and FIG. 6B shows an example of the semiconductor device. First, the semiconductor device shown in FIG. 6(A) will be explained, followed by the semiconductor device shown in FIG. The semiconductor device shown in FIG.

[0216] In the semiconductor device shown in FIG. 6A, the bit line BL and the source electrode of the transistor 162 The word line WL and the gate electrode of the transistor 162 are electrically connected. The electrode is electrically connected to the source electrode or drain electrode of the transistor 162 and the capacitor element The first terminal of 254 is electrically connected to the first terminal of 254 .

[0217] The transistor 162 including an oxide semiconductor has an extremely low off-state current. For this reason, when the transistor 162 is turned off, the first The potential of the terminal (or the charge stored in the capacitance element 254) is kept constant for an extremely long period of time. It is possible to retain it.

[0218] Next, data is written and held in the semiconductor device (memory cell 250) shown in FIG. The case where the above is performed will be explained.

[0219] First, the potential of the word line WL is set to a potential at which the transistor 162 is turned on. This causes the potential of the bit line BL to change to the potential of the capacitor 254. The potential of the word line WL is then applied to the first terminal of the transistor 1 By setting the potential at which the transistor 62 is turned off, the transistor 162 is turned off. The potential of the first terminal of the quantum element 254 is held (held).

[0220] Since the off-state current of the transistor 162 is extremely small, the potential of the first terminal of the capacitor 254 (or the charge stored in the capacitive element) can be held for a long period of time.

[0221] Next, the reading of information will be described. When the transistor 162 is turned on, The bit line BL and the capacitance element 254 are electrically connected to each other. As a result, the potential of the bit line BL changes. The amount of change in the potential is determined by the potential of the first terminal of the capacitance element 254 (or the potential stored in the capacitance element 254). It takes on different values ​​depending on the charge.

[0222] For example, the potential of the first terminal of the capacitance element 254 is V, the capacitance of the capacitance element 254 is C, and the bit line The capacitance component of BL (hereinafter also referred to as bit line capacitance) is CB, If the potential of the bit line BL is VB0, the potential of the bit line BL after the charge is redistributed is (CB*VB0+C*V) / (CB+C). Therefore, the state of memory cell 250 is In this case, the potential of the first terminal of the capacitance element 254 is assumed to be in two states, V1 and V0 (V1>V0). Then, the potential of the bit line BL when the potential V1 is held is (=(CB*VB0+C*V1 ) / (CB+C)) is the potential of the bit line BL when the potential V0 is maintained (=(CB* VB0+C*V0) / (CB+C)).

[0223] Then, by comparing the potential of the bit line BL with a predetermined potential, information can be read out. do.

[0224] As described above, in the semiconductor device illustrated in FIG. 6A, the off-state current of the transistor 162 is extremely small. Due to its small size, the charge stored in the capacitance element 254 can be held for a long time. In other words, refresh operations are not required or the frequency of refresh operations can be reduced. Since it is possible to extremely reduce the power consumption, Even if there is no power supply, the memory contents can be retained for a long period of time. do.

[0225] Next, the semiconductor device shown in FIG. 6B will be described.

[0226] The semiconductor device shown in FIG. 6B has the memory cell 2 shown in FIG. 6A as a memory circuit in the upper portion. 50, and the memory cell arrays 251a and 251b are provided at the bottom. The peripheral circuits required to operate the array 251 (memory cell arrays 251a and 251b) The peripheral circuit 253 is electrically connected to the memory cell array 251. It is being done.

[0227] By configuring as shown in FIG. 6B, the peripheral circuit 253 is connected to the memory cell array 251 ( Since the memory cell arrays 251a and 251b can be provided directly under the It is possible to achieve miniaturization.

[0228] The transistors provided in the peripheral circuit 253 are made of a different semiconductor material from the transistor 162. It is more preferable to use silicon, germanium, silicon germanium, etc. Silicon carbide, gallium arsenide, or the like can be used, and a single crystal semiconductor can be used. In addition, organic semiconductor materials may be used. The transistor is capable of sufficiently high speed operation. It is possible to realize various circuits (logic circuits, driver circuits, etc.) that require operation in an optimal manner. do.

[0229] In the semiconductor device shown in FIG. 6B, two memory cell arrays 251 (memory cell In the above embodiment, the memory cell array 251a and the memory cell array 251b are stacked. The number of memory cells is not limited to this. A configuration in which three or more memory cells are stacked may also be used. good.

[0230] Next, a specific configuration of the memory cell 250 shown in FIG. 6A will be described with reference to FIG. conduct.

[0231] 7 shows an example of the configuration of a memory cell 250. FIG. 7A shows a plan view of the memory cell 250. 7(B) shows a cross-sectional view taken along line AB in FIG. 7(A).

[0232] The transistor 162 illustrated in FIGS. 7A and 7B is the transistor according to Embodiment 1 or 2. The configuration may be the same as that shown in FIG.

[0233] As shown in FIG. 7B, a transistor 162 is provided over the electrode 502 and the electrode 504. The electrode 502 is a wiring that functions as the bit line BL in FIG. The electrode 504 is provided in contact with the low resistance region of the transistor 162. ) serves as one electrode of the capacitor 254 in the low resistance region of the transistor 162. In the transistor 162, a region overlapping with the electrode 504 is provided The electrode 506 functions as the other electrode of the capacitor 254 .

[0234] As shown in FIG. 7A, the other electrode 506 of the capacitor 254 is connected to a capacitor line 508. The gate insulating film 146 is electrically connected to the oxide semiconductor layer 144. The port electrode 148 a is electrically connected to a word line 509 .

[0235] FIG. 7C is a cross-sectional view of a connection portion between the memory cell array 251 and a peripheral circuit. The peripheral circuitry includes, for example, an n-channel transistor 510 and a p-channel transistor The n-channel transistor 510 and the p-channel The semiconductor material used for the junction transistor 512 is a semiconductor material other than an oxide semiconductor ( It is preferable to use a material such as silicon. By using such a material, This allows the transistors to operate at high speed.

[0236] By adopting the planar layout shown in FIG. 7(A), the area occupied by the semiconductor device can be reduced. This allows for high integration.

[0237] As described above, the memory cells formed in multiple layers on the upper portion are transistors using oxide semiconductors. It is made of four elements: indium, gallium, zinc, and oxygen. When the composition ratio of the four elements is expressed in atomic percentage, the ratio of indium is gallium. The off-state current of a transistor using an oxide semiconductor having a ratio of Zn or more that is twice as high as that of a metal Since the current is small, it is possible to retain memory contents for a long period of time by using this. In other words, the frequency of refresh operations can be reduced significantly, resulting in reduced power consumption. In addition, the capacitance element 254 can reduce the current as shown in FIG. The electrode 504, the oxide semiconductor layer 144, the gate insulating film 146, and the electrode 506 are laminated. The oxide semiconductor layer having the above composition has a very high relative dielectric constant. Therefore, by using this as a dielectric film, a capacitance element 254 is not required. The area required can be reduced.

[0238] In this way, transistors using materials other than oxide semiconductors (in other words, transistors that operate at sufficiently high speed) The peripheral circuits are made of transistors that can be operated with a semiconductor oxide. In a broader sense, the off-state current of the transistor is sufficiently small. This makes it possible to realize a semiconductor device having unprecedented features. By forming the gate and the memory circuit in a stacked structure, the integration of the semiconductor device can be promoted.

[0239] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0240] (Embodiment 5) In this embodiment mode, the semiconductor device described in the above embodiment mode is applied to a mobile phone, a smartphone, An example of application to a portable device such as a child book will be described with reference to FIGS.

[0241] In mobile devices such as mobile phones, smartphones, and e-books, image data is temporarily stored. SRAM or DRAM is used in the following. SRAM or DRAM is used The reason is that flash memory has a slow response time and is not suitable for image processing. On the other hand, when SRAM or DRAM is used for temporary storage of image data, the following characteristics are observed: do.

[0242] In a normal SRAM, as shown in FIG. 8(A), one memory cell is made up of transistors 801 to 808. It is composed of six transistors, X decoder 807 and Y decoder 807. The transistor 803, the transistor 805, and the transistor 808 are driven by the 4 and transistor 806 form an inverter, enabling high-speed operation. The memory cell is composed of six transistors, so the cell area is large. When the minimum dimension of the design rule is F, the area of ​​the SRAM memory cell is usually 100 ~150F 2 For this reason, SRAM has the highest cost per bit among all types of memory. stomach.

[0243] In contrast, a DRAM memory cell has a transistor 811, a storage The signal is driven by an X decoder 813 and a Y decoder 814. Each cell is composed of one transistor and one capacitance, and has a small area. The memory cell area of ​​a RAM is usually 10F 2 However, DRAM is always refreshed. It requires a write operation and consumes power even if the data is not being rewritten.

[0244] However, the memory cell area of ​​the semiconductor device described in the above embodiment is 10F 2 Before and after and frequent refresh is not required. Therefore, the memory cell area is reduced, and Power consumption can be reduced.

[0245] A block diagram of the portable device is shown in FIG. 9. The portable device shown in FIG. 9 includes an RF circuit 901, an analog base station, and a a digital baseband circuit 902, a digital baseband circuit 903, a battery 904, and a power supply circuit 905, application processor 906, flash memory 910, display controller controller 911, memory circuit 912, display 913, touch sensor 919, voice The display 913 is a display unit 9 14, a source driver 915, and a gate driver 916. The application processor 906 includes a CPU 907, a DSP 908, and an interface 909 (I Generally, the memory circuit 912 is composed of an SRAM or a DRAM. By adopting the semiconductor device described in the previous embodiment for this portion, It has high speed writing and reading, long-term memory retention, and low power consumption. can be reduced.

[0246] FIG. 10 shows a display memory circuit 950 using the semiconductor device described in the previous embodiment. The memory circuit 950 shown in FIG. The memory controller 951 is also configured with a switch 954, a switch 955, and a memory controller 951. The memory circuit 950 includes a signal line for image data (input image data), a memory 952, and The data stored in the memory 953 (stored image data) is read and controlled by a disk. The play controller 956 and the display controller 956 display the signal. A display 957 is connected to the monitor.

[0247] First, certain image data is generated by an application processor (not shown). The input image data A is input to the memory 952 via the switch 954. The image data stored in the memory 952 (stored image data A) is then The image is sent to a display 957 via a switch 955 and a display controller 956. , will be displayed.

[0248] When there is no change in the input image data A, the stored image data A usually has a frequency of about 30 to 60 Hz. The display controller 956 reads the data from the memory 952 via the switch 955. It is revealed.

[0249] Next, for example, when the user rewrites the screen (i.e., input image data A If there is a change in the input image data, the application processor The input image data B is stored in the memory 953 via the switch 954. During this time, the stored image data A is periodically read out from the memory 952 via the switch 955. When the new image data (stored image data B) has been stored in the memory 953, From the next frame of the display 957, the stored image data B is read out, and the switch 95 5, and the stored image data is displayed on the display 957 via the display controller 956. Data B is sent and displayed. This readout is followed by the next new image data being stored in the memory. This continues until the data is stored in the memory 952.

[0250] In this way, the memory 952 and the memory 953 alternately write image data and receive image data. The display 957 is displayed by reading out the data from the memory 9 The memory 52 and the memory 953 are not limited to being separate memories, but may be one memory divided and used. The semiconductor device described in the above embodiment may be used as the memory 952 and the memory 953. By adopting this technology, it is possible to write and read information at high speed and retain data for a long period of time. This makes it possible to sufficiently reduce power consumption.

[0251] FIG. 11 shows a block diagram of an electronic book. FIG. 11 shows a battery 1001, a power supply circuit 1002, , microprocessor 1003, flash memory 1004, audio circuit 1005, keyboard A code 1006, a memory circuit 1007, a touch panel 1008, a display 1009, The display controller 1010 is configured as a display controller.

[0252] Here, the semiconductor device described in the previous embodiment is used for the memory circuit 1007 in FIG. The role of the memory circuit 1007 is to temporarily store the contents of the book. An example of a feature is when a user uses the highlight feature. When reading an e-book, you may want to mark a specific part. The highlighting function is called the highlight function, and it can be used to change the display color, underline, make text bold, etc. The aim is to differentiate the device from its surroundings by making it brighter or changing the font of the text. This is a function that memorizes and retains information at specified locations. If you want to store this information for a long period of time, It may be copied to the flash memory 1004. In this case, the same as in the previous embodiment is also possible. By adopting the semiconductor device described in the above embodiment, writing and reading of information can be improved. It is possible to store data quickly and for a long period of time, and the power consumption can be sufficiently reduced.

[0253] As described above, the portable device shown in this embodiment mode is equipped with the semiconductor device according to the above embodiment. This allows for high-speed readout, long-term memory retention, and low power consumption. Thus, a portable device with reduced noise is realized.

[0254] The structures, methods, and the like described in this embodiment may be combined as appropriate with the structures, methods, and the like described in other embodiments. They can be used in combination. EXAMPLES

[0255] In this embodiment, an oxide semiconductor film containing indium, gallium, and zinc (IGZO film) is used. The ionization potential of the oxide semiconductor film was measured, and the energy The Gee band diagram was calculated. In this specification, the value of the ionization potential is the band gap. The band gap is the sum of the energy gap and the electron affinity. The value obtained by measuring a single film of the material by spectroscopic ellipsometry is used. The composition of the film was analyzed.

[0256] First, the band gap results obtained by spectroscopic ellipsometry are shown.

[0257] The oxide semiconductor film to be used as the sample was deposited on a quartz substrate with a thickness of 100 nm by sputtering. The deposition conditions were a substrate temperature of 300°C and a target of An oxide target with an atomic ratio of In:Ga:Zn=3:1:2 was used.

[0258] The band gap is argon and oxygen (argon:oxygen=30sccm:15sccm) The sample was formed in a 450°C atmosphere and had a 2.83 eV value for the sample without heat treatment after film formation. The sample that was heat-treated (under a nitrogen atmosphere for 1 hour, then under an oxygen atmosphere for 1 hour) had an energy of 2.90 eV, The sample was heat-treated at 650℃ after deposition (1 hour in a nitrogen atmosphere, then 1 hour in an oxygen atmosphere). 2.94 eV, and the film was formed in an oxygen atmosphere (100% oxygen), without any heat treatment after film formation. The sample was 2.82 eV, and the film was heat-treated at 450°C after deposition (1 hour in a nitrogen atmosphere, then in an oxygen atmosphere). The sample that was heat-treated at 650°C after deposition (under nitrogen atmosphere for 1 hour) was 2.89 eV, The sample that was then placed in an oxygen atmosphere for 1 hour had a value of 2.94 eV, and the value was about 2.8 eV to 2.9 eV. It was V.

[0259] In addition, a single crystal silicon substrate was subjected to a thermal treatment under an oxygen atmosphere (100% oxygen) at a substrate temperature of 300°C. Sputtering method using an oxide target with an atomic ratio of n:Ga:Zn=3:1:2 The IGZO film obtained by forming a film with a thickness of 15 nm was sputtered from the surface side of the film. While performing ultraviolet photoelectron spectroscopy (UPS), The ionization potential was measured by Iontron Spectroscopy. The ionization potential represents the energy difference from the vacuum level to the valence band.

[0260] By subtracting the band gap measured by spectroscopic ellipsometry from the ionization potential value, The conduction band energy was calculated using the In:Ga:Zn=3:1:2 atomic ratio. The band structure of the IGZO film formed using an oxide target was created. The band gap of the O film was set to 2.8 eV. The results are shown in Figure 12.

[0261] Next, a single crystal silicon substrate was placed on the substrate in an oxygen atmosphere (100% oxygen) at a substrate temperature of 300°C. Sputtering method using an oxide target with an atomic ratio of n:Ga:Zn=3:1:2 The composition of the IGZO film obtained by forming a film with a thickness of 15 nm was measured by X-ray photoelectron spectroscopy (XPS: Determined by X-ray Photoelectron Spectroscopy (X-ray Photoelectron Spectroscopy) analysis was quantified and evaluated.

[0262] In the IGZO film, indium (In) is 23.7 atomic % and gallium (Ga) is 7.5 atomic%, zinc (Zn) 9 atomic%, oxygen (O) 59.7 atomic% omic%.

[0263] In addition, the film was formed using an oxide target with an atomic ratio of In:Ga:Zn=3:1:2. X-ray diffraction (XRD) measurements were performed on the IGZO film.

[0264] As a sample, a 100 nm thick IGZO film was formed on a quartz substrate by sputtering. The deposition conditions were as follows: substrate temperature was room temperature, 200°C, 300°C, or 400°C, and deposition atmosphere was The gas was argon and oxygen (argon:oxygen = 30sccm:15sccm), and the target An oxide target with an atomic ratio of In:Ga:Zn=3:1:2 was used as the target.

[0265] For each IGZO film, the XRD spectrum was measured using the out-of-plane method. The measurement results are shown in FIG. 13. In FIG. 13, the vertical axis is the X-ray diffraction intensity (arbitrary unit) The horizontal axis is the rotation angle 2θ (deg.). r An X-ray diffraction apparatus, D8 ADVANCE manufactured by AXS, was used.

[0266] As shown in Figure 13, the IGZO film formed at room temperature had no peaks indicating crystallinity in the XRD spectrum. No pits were observed, and it was confirmed that the film was an amorphous oxide semiconductor film. As shown in Figure 13, the IGZO films formed at 200°C and 400°C have the following characteristics in the XRD spectrum: A peak due to crystals was observed near 2θ=31°, which indicates that the film is a crystalline oxide semiconductor film. It was confirmed that...

[0267] Next, the edge of the IGZO film was cut out and examined using a high-resolution transmission electron microscope (Hitachi High-Technologies Corporation). The cross-section of the IGZO film was observed using a TEM (H9000-NAR) with an accelerating voltage of 300 kV. went.

[0268] As a sample, a 100 nm thick IGZO film was formed on a quartz substrate by sputtering. The deposition conditions were a substrate temperature of 300°C and a deposition atmosphere of argon and oxygen (argon:oxygen). The source gas was 30sccm:15sccm, and the target gas was In:Ga:Zn=3:1 An oxide target with an atomic ratio of 0.1:2 was used.

[0269] FIG. 16(A) shows the film without heat treatment after deposition, and FIG. 16(B) shows the film with heat treatment at 450°C (in nitrogen atmosphere) after deposition. In Fig. 16(C), the film was heat-treated at 650°C (in a nitrogen atmosphere for 1 hour, then in an oxygen atmosphere for 1 hour). The cross-sectional TEM images of the IGZO film were taken after heating in an air atmosphere for 1 hour and then heating in an oxygen atmosphere for 1 hour.

[0270] As shown in Fig. 16(A) to (C), a crystal having a c-axis approximately perpendicular to the surface (CAA C) was confirmed.

[0271] As described above, using an oxide target with an atomic ratio of In:Ga:Zn=3:1:2 It was confirmed that a non-single-crystalline IGZO film could be obtained. EXAMPLES

[0272] In this embodiment, an oxide target with an atomic ratio of In:Ga:Zn=3:1:2 was used. A transistor with the deposited IGZO film was fabricated and its electrical characteristics and reliability were evaluated. Ta.

[0273] As the transistor, a transistor 1 having the structure of a transistor 440a shown in FIG. A transistor 2 having the structure of a transistor 440b shown in FIG. 2(A) was fabricated. A method for fabricating a transistor 1 and a transistor 2 will be described.

[0274] A 300 nm thick silicon oxide film was deposited on a glass substrate as an insulating layer using the sputtering method. A film was formed (film formation conditions: oxygen atmosphere, pressure 0.4 Pa, power supply 1.5 kW, glass substrate The distance between the source and target was 60 mm, and the substrate temperature was 100°C.

[0275] After polishing the surface of the silicon oxide film, an oxide semiconductor film was formed by In:Ga:Zn=3:1:2. [Atomic ratio] oxide target was used for sputtering to produce IG with a thickness of 20 nm. The ZO film was formed under the following film forming conditions: argon and oxygen (argon:oxygen=30sccm:1 5sccm) atmosphere, pressure 0.4Pa, power supply 1.5kW, glass substrate and target The distance between the electrodes was 60 mm, and the substrate temperature was 200°C.

[0276] Next, heat treatment was performed at 450°C for 1 hour in a nitrogen atmosphere, and then for 1 hour in an oxygen atmosphere. The IGZO film was then deposited by ICP (Inductively Coupled Plasma: Etching by inductively coupled plasma (Etching conditions: Etching gas (BCl3:Cl2=60sccm:20sccm), power supply power 450W, bias voltage The powder was processed into islands using a power of 100 W and pressure of 1.9 Pa.

[0277] A tungsten film with a thickness of 50 nm was formed by sputtering (film formation conditions: under argon atmosphere, Pressure 0.8 Pa, power supply power 1 kW) and etched by ICP etching method ( Etching conditions: Etching gas (CF4:Cl2:O2=25sccm:25sccm : 10sccm), power supply power 500W, bias power 150W, pressure 1.0Pa) A source electrode layer and a drain electrode layer were formed.

[0278] Next, a silicon oxynitride film was formed to a thickness of 30 nm by CVD to form a gate insulating film.

[0279] A tantalum nitride film with a thickness of 15 nm was formed by sputtering (film formation conditions: argon and nitrogen ( Ar:N2=50sccm:10sccm) atmosphere, pressure 0.6Pa, power supply power 1kW ) and a tungsten film with a thickness of 135 nm (film formation conditions: under argon atmosphere, pressure 2.0 Pa A laminated film is formed using a power supply of 4 kW, and then etched using an etching method (first etching Conditions: Etching gas (Cl2:SF6:O2=33sccm:33sccm:10sc cm, power supply power 2000 W, bias power 50 W, pressure 0.67 Pa) (second etching Conditions: Etching gas (Cl2 = 100 sccm, power supply power 2000 W, bias power 5 A gate electrode layer was formed by applying a 100 W pulse and a pressure of 0.67 Pa.

[0280] Only the transistor 1 is masked by using the gate electrode layer, the source electrode layer, and the drain electrode layer. Phosphorus (P) ions were implanted into the IGZO film by the ion implantation method. The implantation conditions were an acceleration voltage of 40 kV and a dose of 1.0 × 10 15 ions / cm 2 It was decided.

[0281] An aluminum oxide film was deposited on the gate electrode layer by sputtering as an insulating film (film formation conditions: : Argon and oxygen (argon:oxygen=25sccm:25sccm) atmosphere, pressure 0 .4Pa, power supply power 2.5kW, distance between glass substrate and target 60mm, substrate A silicon oxynitride film was then deposited to a thickness of 300 nm by the CVD method.

[0282] Next, an opening is formed in the gate insulating film and the insulating film, reaching the IGZO film, and a sputtering A titanium film with a thickness of 50 nm was formed by the etching method (film formation conditions: argon (Ar = 20 sccm) atmosphere). Under atmospheric pressure, pressure 0.1 Pa, power supply power 12 kW), aluminum film with a thickness of 100 nm (film formation Conditions: Argon (Ar = 50 sccm) atmosphere, pressure 0.4 Pa, power supply power 1 kW), membrane A titanium film with a thickness of 50 nm (film formation conditions: Argon (Ar=20sccm) atmosphere, pressure 0. 1 Pa, power supply power 12 kW) laminated film was formed and etched (etching conditions: Gas (BCl3:Cl2=60sccm:20sccm), power supply power 450W, bias A wiring layer was formed at a power of 100 W and a pressure of 1.9 Pa.

[0283] Through the above steps, transistors 1 and 2 were manufactured. The channel length (L) is 3.2 μm and the channel width (W) is 10.1 μm. The conductive film is provided with a layer that does not overlap any of the source electrode layer, the drain electrode layer, and the gate electrode layer. The width of the thin region in the channel length direction (also called Loff) was set to 0.15 μm. In transistor 2, the channel length (L) is 2.9 μm and the channel width (W) is 10 0.1 μm, and the source electrode layer or the drain electrode layer is connected to the gate electrode layer on the oxide semiconductor film. The width of the overlapping region in the channel length direction (also called Lov) was set to 1.15 μm.

[0284] The electrical characteristics of the obtained transistors 1 and 2 and the Reliability evaluation was also performed. Gate voltage (Vg) - drain current (Id) characteristics and drain voltage (Vd) of 0.1V The field-effect mobility at the drain voltage (Vd) of transistor 1 is shown in Fig. 14. Gate voltage (Vg)-drain current (Id) characteristics at .1V and drain voltage (V d) The field-effect mobility at 0.1 V is shown in Figures 15(A) and (B).

[0285] As shown in FIGS. 14 and 15, the transistors 1 and 2 exhibit high on-state characteristics. The field effect mobility is 20 cm 2 / Vs, and 20 cm for transistor 2. 2 The field-effect mobility exceeded 1000 V / Vs.

[0286] One of the methods for checking the reliability of transistors is the bias-thermal stress test (hereinafter, This is called the GBT (Gate Bias Temperature) test. This test is a type of accelerated test that detects changes in transistor characteristics that occur over a long period of use. It can be evaluated in a short time. In particular, the threshold voltage of the transistor before and after the GBT test The amount of voltage change is an important indicator for investigating reliability. The smaller the change in threshold voltage, the higher the reliability.

[0287] The substrate on which the transistor is formed is kept at a constant temperature, and the source and drain of the transistor are The input and output are at the same potential, and the gate is given a potential different from that of the source and drain for a certain period of time. The plate temperature can be set appropriately depending on the purpose of the test. The potential applied to the gate is greater than the potential of the source and drain (the source and drain are at the same potential). In the -GBT test, the potential applied to the gate is equal to the potential of the source and drain (source The source and drain are at the same potential.

[0288] The test strength of the GBT test is determined by the substrate temperature, the electric field strength applied to the gate insulating layer, and the time when the electric field is applied. The electric field strength in the gate insulating layer can be determined by the distance between the gate and the source and drain. The potential difference between the drain and the gate electrode is determined by dividing the potential difference by the thickness of the gate insulating layer.

[0289] In this embodiment, a GBT test was performed on the transistor 1. First, a +GBT test was performed on the substrate temperature The temperature was set to 40° C., Vd was set to 3 V, and the Vg-Id characteristics of the transistor 1 were measured. The substrate temperature was set to 150° C., and Vd was set to 0.1 V. Next, the voltage applied to the gate insulating film was Apply 6 V to Vg so that the field strength is 2 MV / cm, and leave it in the air for 1 hour. Next, Vg was set to 0 V. Next, the substrate temperature was set to 40° C., Vd was set to 10 V, and the The Vg-Id measurement was carried out on the transistor 1. The +GBT test results are shown in FIG.

[0290] Similarly, the -GBT test begins with the substrate temperature set to 40°C, V(ds) set to 10V, and the transistor Next, the substrate temperature was set to 150°C and Vd was set to 0.1V. Next, Vg was adjusted so that the electric field strength applied to the gate insulating film was -2MV / cm. A voltage of -6 V was applied and the device was kept in the air for 1 hour. Next, Vg was set to 0 V. Then, the substrate temperature was set to 40°C, Vd was set to 10 V, and the Vg-Id measurement of the transistor 1 was performed. The results of the -GBT test are shown in Figure 15(B).

[0291] In addition, in Figures 15(A) and (B), the thick lines indicate the results before the GBT test, and the thin lines indicate the results after the test.

[0292] As shown in Fig. 15(A) and (B), in the +GBT test and the -GBT test of the transistor 1, The threshold voltage hardly changed due to the change in the temperature. It was confirmed that the threshold voltage did not vary much before and after the GBT test, and that the device was highly reliable. Ta.

[0293] In addition, the channel length (L) was set to 0.8 μm and the channel A transistor with a channel width (W) of 1000 μm and Loff of 0.3 μm was fabricated. The off-leak current (off-current) of the transistor was measured. The measurements were performed at 125℃ or 85℃. The measurement results are shown in FIG.

[0294] As shown in FIG. 17, when the transistor according to this embodiment is operated at 85° C. for 41.5 hours, The off-leak current was 0.5 zA / μm, which was an extremely low value.

[0295] From the above, the transistor of this embodiment has an extremely low off-state current and is a highly reliable transistor. It was shown to be a star.

Claims

1. A semiconductor device having a plurality of circuits arranged in a matrix, The circuit comprises: a first transistor having a first channel formation region including silicon; a second transistor having a second channel formation region including an oxide semiconductor; a gate electrode of the first transistor is electrically connected to one of a source electrode and a drain electrode of the second transistor, a first conductive layer provided above the first channel formation region and functioning as a gate electrode of the first transistor; a first insulating layer having a region in contact with a side surface of the first conductive layer; a second insulating layer above the first insulating layer; an oxide semiconductor layer above the second insulating layer; a second conductive layer provided above a channel formation region of the second transistor and functioning as a gate electrode of the second transistor; a third conductive layer electrically connected to the oxide semiconductor layer and functioning as one of a source electrode and a drain electrode of the second transistor; a third insulating layer above the second conductive layer and above the third conductive layer; a fourth conductive layer above the third insulating layer; and a fourth insulating layer over the fourth conductive layer; a fifth conductive layer above the fourth insulating layer; the oxide semiconductor layer has crystallinity, the fourth conductive layer has a region overlapping with the third conductive layer via the third insulating layer, the fourth conductive layer has a region overlapping with the first conductive layer via the third insulating layer and the third conductive layer; the fourth conductive layer overlaps both ends of the first conductive layer in a cross-sectional view of the second transistor in a channel length direction; a second channel formation region that does not overlap with the first channel formation region in a plan view;

2. A semiconductor device having a plurality of circuits arranged in a matrix, The circuit comprises: a first transistor having a first channel formation region including silicon; a second transistor having a second channel formation region including an oxide semiconductor; a gate electrode of the first transistor is electrically connected to one of a source electrode and a drain electrode of the second transistor, a first conductive layer provided above the first channel formation region and functioning as a gate electrode of the first transistor; a first insulating layer having a region in contact with a side surface of the first conductive layer; a second insulating layer above the first insulating layer; an oxide semiconductor layer above the second insulating layer; a second conductive layer provided above a channel formation region of the second transistor and functioning as a gate electrode of the second transistor; a third conductive layer electrically connected to the oxide semiconductor layer and functioning as one of a source electrode and a drain electrode of the second transistor; a third insulating layer above the second conductive layer and above the third conductive layer; a fourth conductive layer above the third insulating layer; and a fourth insulating layer over the fourth conductive layer; a fifth conductive layer above the fourth insulating layer; the oxide semiconductor layer has crystallinity, the fourth conductive layer has a region overlapping with the third conductive layer via the third insulating layer, the fourth conductive layer has a region overlapping with the first conductive layer via the third insulating layer and the third conductive layer; the fourth conductive layer overlaps both ends of the first conductive layer in a cross-sectional view of the second transistor in a channel length direction; the fifth conductive layer has an area overlapping with each of the first conductive layer and the second conductive layer; a second channel formation region that does not overlap with the first channel formation region in a plan view;

3. A semiconductor device having a plurality of circuits arranged in a matrix, The circuit comprises: a first transistor having a first channel formation region including silicon; a second transistor having a second channel formation region including an oxide semiconductor; a gate electrode of the first transistor is electrically connected to one of a source electrode and a drain electrode of the second transistor, a first conductive layer provided above the first channel formation region and functioning as a gate electrode of the first transistor; a first insulating layer having a region in contact with a side surface of the first conductive layer; a second insulating layer above the first insulating layer; an oxide semiconductor layer above the second insulating layer; a second conductive layer provided above a channel formation region of the second transistor and functioning as a gate electrode of the second transistor; a third conductive layer electrically connected to the oxide semiconductor layer and functioning as one of a source electrode and a drain electrode of the second transistor; a third insulating layer above the second conductive layer and above the third conductive layer; a fourth conductive layer above the third insulating layer; and a fourth insulating layer over the fourth conductive layer; a fifth conductive layer above the fourth insulating layer; the oxide semiconductor layer has crystallinity, the fourth conductive layer has a region overlapping with the third conductive layer via the third insulating layer, the fourth conductive layer has a region overlapping with the first conductive layer via the third insulating layer and the third conductive layer; the fourth conductive layer overlaps both ends of the first conductive layer in a cross-sectional view of the second transistor in a channel length direction; In a plan view, the oxide semiconductor layer does not overlap the first conductive layer.

4. A semiconductor device having a plurality of circuits arranged in a matrix, The circuit comprises: a first transistor having a first channel formation region including silicon; a second transistor having a second channel formation region including an oxide semiconductor; a gate electrode of the first transistor is electrically connected to one of a source electrode and a drain electrode of the second transistor, a first conductive layer provided above the first channel formation region and functioning as a gate electrode of the first transistor; a first insulating layer having a region in contact with a side surface of the first conductive layer; a second insulating layer above the first insulating layer; an oxide semiconductor layer above the second insulating layer; a second conductive layer provided above a channel formation region of the second transistor and functioning as a gate electrode of the second transistor; a third conductive layer electrically connected to the oxide semiconductor layer and functioning as one of a source electrode and a drain electrode of the second transistor; a third insulating layer above the second conductive layer and above the third conductive layer; a fourth conductive layer above the third insulating layer; and a fourth insulating layer over the fourth conductive layer; a fifth conductive layer above the fourth insulating layer; the oxide semiconductor layer has crystallinity, the fourth conductive layer has a region overlapping with the third conductive layer via the third insulating layer, the fourth conductive layer has a region overlapping with the first conductive layer via the third insulating layer and the third conductive layer; the fourth conductive layer overlaps both ends of the first conductive layer in a cross-sectional view of the second transistor in a channel length direction; the fifth conductive layer has an area overlapping with each of the first conductive layer and the second conductive layer; In a plan view, the oxide semiconductor layer does not overlap the first conductive layer.

5. In any one of claims 1 to 4, The oxide semiconductor layer contains In, Ga, and Zn.

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