Display device

Abstract

To provide a semiconductor device which has high reliability, and with which it is possible to realize a narrowed frame.SOLUTION: A drive circuit includes a first transistor having a first gate and a second gate electrically connected via a semiconductor film that is held therebetween, and a second transistor of which one of the source and the drain is electrically connected to one of the source and the drain of the first transistor. A pixel unit includes a third transistor, a liquid crystal element, and a capacitive element, and the liquid crystal element has a light-transmissive first conductive film electrically connected to one of the source and the drain of the third transistor, a second conductive film, a liquid crystal layer to which an electrical field generated between the first and the second conductive films is applied. The capacitive element includes a first conductive film, a light-transmissive third conductive film, and a nitride insulating film located between the first and the third conductive films, the nitride insulting film being located between the semiconductor film and the second gate of the first transistor.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. In particular, the present invention relates to a sequential circuit using transistors of the same conductivity type. The present invention relates to a semiconductor device, such as a semiconductor display device, using the sequential circuit. [Background technology]

[0002] Semiconductor display devices such as liquid crystal display devices and EL display devices used in portable electronic devices Therefore, there is a demand to narrow the area other than the pixel area (to narrow the frame). Or a system-on-panel in which all the components are fabricated on the same substrate as the pixel section meets the above requirements. In the case of a system-on-panel, the driver circuit is unipolar, just like the pixel section. It is desirable to use transistors with a larger number of transistors because this reduces the cost of manufacturing the panel. The following Patent Documents 1 and 2 disclose a semiconductor display device using a driving circuit. A technology that uses unipolar transistors to construct various circuits such as inverters and shift registers. The following has been disclosed: [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2001-325798 A [Patent Document 2] JP 2010-277652 A Summary of the Invention [Problem to be solved by the invention]

[0004] In a liquid crystal display device, which is one of the semiconductor devices, in the case of a transmission type, a region through which light passes By increasing the ratio of the number of pixels per pixel, or the aperture ratio, the light emitted from the backlight can be effectively However, the aperture ratio can be improved by using the If pixel layout is decided with priority given to the transistors and capacitance that make up the pixel, The size of semiconductor elements such as capacitors will also have to be reduced. When the driving frequency is increased, it becomes difficult to control the alignment of the liquid crystal molecules without lowering the driving frequency. The period during which the image can be displayed will be shortened, resulting in problems such as poor image quality. .

[0005] In addition, semiconductor display devices are required to have narrower frames. In the driver circuit of a semiconductor display device having a MOS transistor, a sequential circuit is used to output a signal having a pulse. In this case, the transistor may show degradation in electrical characteristics, such as a shift in threshold voltage. However, there is also a demand for semiconductor display devices to have high reliability.

[0006] In light of the above technical background, one aspect of the present invention provides a method for reducing power consumption while suppressing deterioration in image quality. Another object of the present invention is to provide a semiconductor device capable of reducing the One of the objects of the present invention is to provide a semiconductor device which is highly reliable and can have a narrow frame. [Means for solving the problem]

[0007] A semiconductor device according to one embodiment of the present invention has electrical conductivity and is transparent to visible light. a pixel electrode having a translucency to visible light; and A capacitance element having at least a nitride insulating film provided between the pixel electrodes is provided in the pixel. In the above configuration, the capacitive element is transparent to visible light. The aperture ratio of the pixels can be increased while maintaining the capacitance required to obtain high image quality, so the panel This makes it possible to reduce the loss of light within the filter, thereby reducing the power consumption of the semiconductor device. This can be done.

[0008] In addition, when the metal oxide film and the pixel electrode are used as a pair of electrodes in the capacitor element as described above, In this case, in order to increase the capacitance of the capacitance element, a resin film such as acrylic is interposed between the metal oxide film and the pixel electrode. However, if the resin film is not provided, it is preferable not to provide it between the side far from the gate electrode. The region near the surface of the semiconductor film (back channel region) and the element in which the transistor is formed The distance to the surface of the child substrate is shorter than when a resin film is provided. When moisture from the air adheres to the surface of a substrate, a positive fixed charge is generated near the surface. As a result, negative charges tend to be generated in the back channel region due to the fixed charges. Therefore, the period during which the potential of the gate electrode is low relative to the source electrode or drain electrode It has been empirically found that the longer the transistor, the more likely it is that the threshold voltage will shift in the negative direction. However, when there is no resin film, the difference in the threshold voltage is smaller than when there is a resin film. It was found that the shift toward the eggshell direction was particularly likely to be large.

[0009] In view of this, in one embodiment of the present invention, a transistor included in a sequential circuit, a buffer, or the like included in a driver circuit is Among the transistors, the ones whose threshold voltages tend to shift in the negative direction are the normal gate transistors. In addition to the gate electrode, the semiconductor film also has a gate electrode on the back channel region side. The gate electrode on the back channel region side is electrically connected to the normal gate electrode. It is assumed that there is.

[0010] By providing a gate electrode on the back channel region side, a negative potential is applied to the back channel region. This prevents the transistor threshold voltage from shifting in the negative direction. In addition, instead of applying a constant potential to the gate electrode on the back channel region side, The gate electrode is electrically connected to a normal gate electrode, and the pair of gate electrodes are provided with the same potential. By applying this, the channel formation region can be increased, and the drain current can be increased. Therefore, it is possible to reduce the size of the transistor while suppressing the decrease in on-state current. This makes it possible to keep the area of ​​the drive circuit small. Effect of the Invention

[0011] According to one embodiment of the present invention, a semiconductor device capable of suppressing deterioration in image quality and reducing power consumption Alternatively, according to one embodiment of the present invention, a highly reliable and narrow frame device can be provided. It is possible to provide a semiconductor device having such a structure. [Brief description of the drawings]

[0012] [Figure 1] FIG. 1 shows the configuration of a sequential circuit. [Diagram 2] FIG. 1 illustrates a structure of a transistor. [Diagram 3] Timing chart. [Figure 4] Top view of a pixel. [Diagram 5] FIG. [Figure 6] FIG. 1 is a diagram showing a configuration of a semiconductor display device. [Figure 7] FIG. 1 shows the configuration of a sequential circuit. [Figure 8] FIG. 2 is a diagram showing a configuration of a shift register. [Figure 9] FIG. 2 is a diagram showing the configuration of a buffer. [Figure 10] FIG. 2 is a diagram showing the configuration of a buffer. [Figure 11] 3A to 3C are diagrams illustrating a method for manufacturing an element substrate. [Figure 12] 3A to 3C are diagrams illustrating a method for manufacturing an element substrate. [Figure 13] 3A to 3C are diagrams illustrating a method for manufacturing an element substrate. [Figure 14] 3A to 3C are diagrams illustrating a method for manufacturing an element substrate. [Figure 15] FIG. [Figure 16] FIG. [Figure 17] 13A to 13C show electrical characteristics of a transistor. [Figure 18] Electronic devices illustration. [Figure 19] FIG. 1 illustrates a structure of a transistor. [Figure 20] FIG. 1 illustrates a structure of a transistor. [Figure 21] FIG. 1 illustrates a structure of a transistor. [Figure 22] A diagram showing the circuit symbol and the configuration of a transistor. [Figure 23] 1A and 1B are diagrams illustrating a cross-sectional structure of a transistor. [Figure 24] FIG. 1 illustrates a structure of a transistor. [Diagram 25] 1 is a cross-sectional view of a transistor at an edge portion of an oxide semiconductor film. [Figure 26] 4 shows the Vg-Id characteristics of a transistor according to an embodiment. [Figure 27] 4 shows the Vg-Id characteristics of a transistor according to an embodiment. [Figure 28] 4 shows the Vg-Id characteristics of a transistor according to an embodiment. [Figure 29] 13A to 13C are diagrams illustrating a structure of a transistor used in calculation and the calculated field-effect mobility and on-state current. [Diagram 30] FIG. 13 illustrates a model of a transistor used in calculation. [Diagram 31] FIG. 13 is a graph for explaining the channel length dependence of saturation mobility obtained by calculation. [Diagram 32]FIG. 13 is a graph for explaining the channel length dependence of on-current obtained by calculation. [Diagram 33] 13A to 13C are graphs showing calculated Vg-Id characteristics of a transistor and current distribution in an oxide semiconductor film. [Diagram 34] 13A and 13B are diagrams illustrating the Vg-Id characteristics of a transistor and current distribution in a silicon film obtained by calculation. [Diagram 35] 13A and 13B are diagrams illustrating the channel length dependence of electron traps used in the calculation and the saturation mobility obtained by the calculation. [Diagram 36] 1A to 1C are diagrams illustrating carrier flow in an off state and an on state of a transistor. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following description, and the embodiments and aspects of the present invention may be modified without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that various modifications may be made to the details. However, the present invention should not be construed as being limited to the description of the following embodiment.

[0014] The present invention can be applied to any device using transistors, such as integrated circuits, RF tags, and semiconductor display devices. The category includes all semiconductor devices. Control circuit, DSP (Digital Signal Processor), Microcomputer LSI (Large Scale Integrated Circuit) t), FPGA (Field Programmable Gate Array) and C Programmable logic circuits such as PLD (Complex PLD) The category includes semiconductor devices such as ammable logic devices. The display device includes a liquid crystal display device, a light-emitting device having a light-emitting element, typically an organic light-emitting element, in each pixel. Placement, electronic paper, DMD (Digital Micromirror Device) , PDP (Plasma Display Panel), FED (Field Emi The driving circuitry of LCDs includes circuit elements using semiconductor films, such as LCDs. Semiconductor display devices are included in this category.

[0015] In this specification, the term "semiconductor display device" refers to a display device in which display elements such as liquid crystal elements and light emitting elements are used for each screen. A panel formed as a base and a model in which ICs including a controller are mounted on the panel Furthermore, the semiconductor display device according to one embodiment of the present invention includes the above-mentioned In the process of manufacturing a semiconductor display device, an element corresponding to one form before the display element is completed The category includes a substrate, and the element substrate includes transistors and pixel electrodes used in the display element. Each of the plurality of pixels includes an electrode, such as a pole or a common electrode, and a capacitive element.

[0016] In addition, the semiconductor display device according to one embodiment of the present invention may include a display device that is pointed at by a finger or a stylus. A touch sensor is a position input device that can detect a position and generate a signal containing the position information. A chip panel may be included in the components.

[0017] In this specification, the term "connection" means electrical connection, and a current, a voltage, or a potential is Therefore, the connected state corresponds to a direct connection. It does not necessarily refer to the state in which a current, voltage or potential is available or is transmitted through circuit elements such as wires, resistors, diodes, and transistors. This also includes the state where the components are indirectly connected through a circuit diagram. Even when elements are connected to each other, in reality, for example, part of the wiring functions as an electrode. In some cases, a single conductive film may have the functions of multiple components. In the specification, the term "connection" refers to a state in which one conductive film has the functions of multiple components. If so, it will also be included in that category.

[0018] The source of a transistor is a source region that is a part of the semiconductor film that functions as an active layer. The source electrode of a transistor is a region connected to the semiconductor film. The drain is a part of the semiconductor film, or a drain region connected to the semiconductor film. The term "gate" refers to a gate electrode.

[0019] The source and drain of a transistor are determined by the conductivity type of the transistor and the terminals. The name is changed depending on the potential that is applied. Generally, n-channel transistors In a transistor, the terminal to which a low potential is applied is called the source, and the terminal to which a high potential is applied is called the drain. In addition, in a p-channel transistor, the terminal to which a low potential is applied is called the drain. The terminal to which the high potential is applied is called the input, and the terminal to which the high potential is applied is called the source. Explain the connection relationship of a transistor, assuming that the source and drain are fixed. In some cases, the names of the source and drain are interchangeable according to the above potential relationship. do.

[0020] <Example 1 of sequential circuit configuration> FIG. 1A illustrates an example of a configuration of a sequential circuit according to one embodiment of the present invention. The illustrated sequential circuit 10 includes a circuit 11, a transistor 12, and a transistor 13. The circuit 11 controls the gate and gate of the transistor 12 according to the potentials of the signals LIN and RIN. It has a function of controlling the potential of the gate of the transistor 13 .

[0021] The transistor 12 is connected to a wiring to which a signal Sig or a high-level potential VDD is applied, and The transistor 13 has a function of controlling an electrical connection with the output terminal OUT. Controls the electrical connection between the wiring to which the negative potential VSS is applied and the output terminal OUT. Specifically, one of the source and drain of the transistor 12 is connected to a signal Sig or connected to a wiring to which a high-level potential VDD is applied, One of the source and drain is connected to a wiring to which a low-level potential VSS is applied. The signal Sig has a data value, which is the ratio of the pulse width to the pulse period, such as a clock signal. A signal with a duty cycle of about 0.5 can be used. The other of the drain and the source of the transistor 13 is connected to an output terminal OU It is connected to T.

[0022] The circuit 11 controls the gate potential of the transistor 12 and the gate potential of the transistor 13. By controlling the transistor 12, the transistor 13 is selected to be conductive or non-conductive. The conductive or non-conductive state of transistor 12 is selected. When resistor 13 is in a non-conducting state, the line to which the signal Sig or the potential VDD is applied and the output The output terminal OUT is connected to the transistor 12. When the transistor 13 is in a conductive state, the wiring to which the potential VSS is applied is connected to the output terminal OUT. can be.

[0023] The output signal including the potential of the output terminal OUT of the sequential circuit 10 is connected to a plurality of pixels. When supplying the signal to a wiring called a bus line, for example a scanning line, the duty of the output signal is In this case, the transistor 12 outputs Since transistor 12 is continuously in a non-conducting state during periods other than the pulse of the signal, The period of time that transistor 13 is in the conductive state is significantly longer than the period of time that transistor 13 is in the non-conductive state. A signal Sig or a potential VD Since D is given, transistor 12 has a gate for either the source or the drain. The period during which the potential of the gate is in a low state is longer than that of the transistor 13, and the threshold voltage is negative. It can be seen that the shift is more likely to occur in the direction of the arrow.

[0024] Therefore, in one embodiment of the present invention, the transistor 12 is electrically connected and is a semiconductor The gate electrodes are electrically connected to each other. By providing a pair of gate electrodes in the transistor 12, a positive Even if fixed charges are generated, the fixed charges generate negative charges near the surface of the semiconductor film. This prevents the threshold voltage of the transistor 12 from shifting in the negative direction. This improves the reliability of the sequential circuit 10 and, in turn, the reliability of a semiconductor device using the sequential circuit 10. It is possible.

[0025] In addition, by electrically connecting a pair of gate electrodes, a single gate electrode is formed on only one of the pair of gate electrodes. Unlike the case where a constant potential is applied, the same potential is applied to a pair of gate electrodes, so As a result, the drain current of the transistor 12 can be increased. Therefore, the size of the transistor 12 can be reduced while suppressing the decrease in the on-state current. Therefore, the area of ​​the sequential circuit 10 and, in turn, the area of ​​the driving circuit using the sequential circuit 10 can be reduced. In particular, the transistor 12 provided on the output side of the sequential circuit 10 has a Since a larger current supply capacity is required than that of the transistors used in 2 has a pair of gate electrodes as described above, so that the other transistors in the sequential circuit 10 The area of ​​the sequential circuit or driver circuit is reduced compared to when the same configuration is applied to a single MOSFET. It can be said that the effect is significant.

[0026] In addition, by providing a pair of electrically connected gate electrodes, a depletion layer is unlikely to be formed in the semiconductor film. Therefore, the S value (subthreshold value) of the transistor 12 can be improved. do.

[0027] Next, FIG. 1B shows a more detailed configuration example of the sequential circuit 10 shown in FIG. 1A. The sequential circuit 10 shown in FIG. 1(B) is the same as the sequential circuit 10 shown in FIG. 1(A), and is connected to the circuit 11. 1B, the circuit 1 includes a transistor 12 and a transistor 13. 1 illustrates an example in which transistors 14 to 17 are included.

[0028] The transistor 14 is turned on or off according to the potential of the signal LIN. When the transistor 14 is in a conductive state, the wiring to which the potential VDD is applied and the The transistor 15 is turned on or off in response to the potential of a signal RIN. When the transistor 15 is in a conductive state, the potential VDD is applied. The wiring connected to the gate of the transistor 16 is electrically connected to the gate of the transistor 13. The transistor 16 is turned on or off depending on the potential of the signal RIN. When the potential VSS is applied to the gate of the transistor 12, the wiring to which the potential VSS is applied is electrically connected. The transistor 17 is turned on or off in accordance with the potential of the signal LIN. When the transistor 17 is in a conductive state, the wiring to which the potential VSS is applied and the transistor The gate of the transistor 13 is electrically connected to the transistor 12 .

[0029] Regarding an example of the operation of the sequential circuit 10 shown in FIG. An example will be described in which one of the inputs is connected to a wiring to which a signal Sig is applied. FIG. 3 illustrates a timing chart of the sequential circuit 10 shown in FIG. In FIG. 3, the transistors 12 to 17 are all n-channel transistors. 3 shows a timing chart of the gate of the transistor 12. It is shown as α.

[0030] As shown in FIG. 3, during a period T1, the potential of the signal Sig is at a low level, and the potential of the signal LIN is at a low level. The potential of the signal RIN is at a high level, and the potential of the signal RIN is at a low level. Transistor 14 and transistor 17 are in a conducting state, and transistor 15 and transistor 16 Therefore, the node α is turned off by a potential difference of VDD to the threshold voltage of the transistor 14. The gate of the transistor 13 is supplied with a potential VSS. Therefore, transistor 13 is non-conductive.

[0031] Next, as shown in FIG. 3, during a period T2, the potential of the signal Sig is at a high level, and the potential of the signal LIN The potential of the signal RIN is at a low level. Since the transistors 14 to 17 are turned off, the node α is floating. Therefore, the parasitic capacitance added to the node α is In the ideal state, the capacitance between the gate and the load is significantly smaller than the capacitance between the load and the gate. The change in the potential of the signal Sig that occurred during the period T2, that is, the low level of the signal Sig The potential of the node α rises by the potential difference between the low level potential and the high level potential. When the potential of α rises, the gate voltage of transistor 12 becomes sufficiently higher than its threshold voltage. Therefore, the high-level potential of the signal Sig is applied to the output terminal OUT.

[0032] The increase in the potential of the node α is determined by the parasitic capacitance added to the node α and the potential of the transistor 14. It changes depending on the capacitance ratio of the capacitance C formed between the source and gate. The smaller the parasitic capacitance added to node α is compared to capacitance C, the larger the rise in the potential of node α will be. In addition, the larger the parasitic capacitance added to node α is compared to capacitance C, the greater the increase in the potential of node α. The width is small, so that the gate voltage of transistor 12 is well above its threshold voltage. A potential difference between the source and gate of the transistor 14 is formed so that the potential of the node α rises to about 100 V. It is desirable to make the capacitance C formed larger than the parasitic capacitance added to the node α.

[0033] Next, as shown in FIG. 3, during a period T3, the potential of the signal Sig is at a low level, and the potential of the signal LIN The potential of the signal RIN is at a low level, and the potential of the signal RIN is at a high level. Transistors 14 and 17 are turned off, and transistors 15 and Therefore, the potential VSS is applied to the node α, and The transistor 12 is turned off. The gate of the transistor 13 is connected to the potential VDD Therefore, the transistor 13 is turned on. It is applied to the terminal OUT.

[0034] Next, as shown in FIG. 3, during a period T4, the potential of the signal Sig is at a high level, and the potential of the signal LIN The potential of the signal RIN is at a low level. Transistors 14 to 17 are turned off. maintains a non-conductive state, and transistor 13 maintains a conductive state. is applied to the output terminal OUT.

[0035] Due to the operation during the above-mentioned periods T1 to T4, the output terminal OUT of the sequential circuit 10 is An output signal having a pulse is output. An output signal including the pixel voltage is sent to a wiring called a bus line, which is connected to multiple pixels, such as a scanning line. When providing the input, transistors 14 to 17, like transistor 12, The period during which the gate potential is low relative to either the source or the drain is called the transistor. It can be seen that the threshold voltage is more likely to shift in the negative direction than that of transistor 13.

[0036] Therefore, in one embodiment of the present invention, at least one of the transistors 14 to 17 A pair of gate electrodes are electrically connected to each other and overlap each other with a semiconductor film sandwiched therebetween. In FIG. 1B, the transistors 14 to 17 may be electrically The figure illustrates an example in which a pair of electrically connected gate electrodes are provided. By providing the gate electrodes of the transistors 14 to 17, the transistors 1 4 to 17 can be prevented from shifting the threshold voltage in the negative direction. Therefore, the reliability of the sequential circuit 10 and, in turn, the reliability of the semiconductor device using the sequential circuit 10 can be improved. This can be done.

[0037] In addition, the size of the transistors 14 to 17 can be reduced while suppressing the decrease in the on-state current. Since the sequential circuit 10 and the driving circuit using the sequential circuit 10 can be suppressed, The product can be kept small.

[0038] In addition, by providing a pair of electrically connected gate electrodes, a depletion layer is unlikely to be formed in the semiconductor film. Therefore, the S value of the transistors 14 to 17 can be improved.

[0039] <Example of transistor configuration> Next, transistors 12, 14, 15, 16, 17, and 19 shown in FIG. A transistor 20 having a pair of electrically connected gate electrodes may be used. A specific configuration example is shown in FIG. 2. FIG. 2A shows a top view of a transistor 20. In FIG. 2A, in order to clarify the layout of the transistor 20, the gate insulating film In addition, the broken line A1-A in the top view shown in FIG. A cross-sectional view of the cross-section at 2 is shown in FIG. 2(B), and a cross-sectional view of the cross-section at dashed line A3-A4 is shown in FIG. 2(C). vinegar.

[0040] As shown in FIG. 2, the transistor 20 includes a gate electrode and a gate insulating film on a substrate 31 having an insulating surface. A conductive film 21 having a function as a gate insulating film and a conductive film 2 an insulating film 22 located on the first insulating film 21 and an oxide semiconductor film overlapping the conductive film 21 on the insulating film 22; 23, which is electrically connected to the oxide semiconductor film 23 and serves as a source electrode or a drain electrode. The conductive film 24 and the conductive film 25 have the above functions.

[0041] In addition, in FIG. 2, an insulating film 26 and a conductive film 25 are formed over the oxide semiconductor film 23, the conductive film 24, and the conductive film 25. The transistor 20 includes an insulating film 26 and an insulating film 27. The insulating film 27 may be included in the components. Although the film 26 and the insulating film 27 are illustrated, a single layer may be used instead of the insulating film 26 and the insulating film 27. An insulating film may be used, or a laminate of three or more insulating films may be used. .

[0042] In addition, a nitride insulating film 28 and an insulating film 29 are laminated in this order on the insulating film 26 and the insulating film 27. The insulating film 29 is not necessarily provided. However, the insulating film 2 9 functions as a dielectric film for a capacitance element of a pixel, which will be described later, together with a nitride insulating film 28. The nitride insulating film 28 has a higher dielectric constant and a lower internal stress than oxide insulating films such as silicon oxide. Therefore, the dielectric film of the capacitance element is not formed of the insulating film 29 but of the nitride. When only the nitride insulating film 28 is used, if the thickness of the nitride insulating film 28 is small, the capacitance value of the capacitance element becomes too large, and the speed at which image signals are written to pixels must be increased while still maintaining low power consumption. On the other hand, if the thickness of the nitride insulating film 28 is large, the internal stress becomes large. In the semiconductor element formed using the semiconductor film, the threshold voltage of the transistor is shifted due to the temperature rise. In addition, the internal stress of the nitride insulating film 28 may become too large. If this is the case, the nitride insulating film 28 becomes more likely to peel off from the substrate 31, which hinders improvement of the yield. Then, the insulating film 29 is formed using an insulating material such as silicon oxide having a lower relative dielectric constant than the nitride insulating film 28. By using the nitride insulating film 28 together with the dielectric film of the capacitance element of the pixel, The dielectric constant can be adjusted to a desired value without increasing the thickness of the nitride insulating film 28. do.

[0043] The insulating film 22, the insulating film 26, the insulating film 27, the nitride insulating film 28, and the insulating film 29 are formed in the opening 3. The opening 32 includes a region different from the oxide semiconductor film 23, the conductive film 24, and the conductive film 25. The conductive film 21 is disposed in a region overlapping the conductive film 21.

[0044] In addition, the transistor 20 has a conductive film 30 having a function as a gate electrode, and an insulating film 29. When the insulating film 29 is not provided, the conductive film is provided on the nitride insulating film 28. The conductive film 21 and the oxide semiconductor film 23 overlap with each other. The transistors 20 are electrically connected to each other and are made of an oxide semiconductor film, which is a semiconductor film. Thus, a pair of gate electrodes are formed, overlapping each other with the conductive film 30 sandwiched therebetween. The conductive film 30 is electrically connected to the conductive film 21 through the opening 32. It has translucency.

[0045] In FIG. 2C, after the openings are formed in the insulating film 26 and the insulating film 27, the nitride insulating film 28 and an insulating film 29 are formed, and then an insulating film 22 and a nitride film are formed so as to overlap the opening. The example shows a case where an opening 32 is formed in the insulating film 28 and the insulating film 29. In one embodiment of the present invention, the insulating film 22, the insulating film 26, the insulating film 27, the nitride insulating film 28, and An opening 32 may be formed in the insulating film 29 by etching or the like using a mask. However, in the case where the insulating film 29 is not provided in the pixel, The pixel electrode is provided on the nitride insulating film 28, and the pixel electrode is insulated from the insulating film 22. The conductive film located between the film 26 and the insulating film 27, the insulating film 26, the insulating film 27, and the nitride insulating film When the pixel is electrically connected to the opening formed in the insulating film 28 and the insulating film 29, The thickness of the insulating film to be removed by etching is different between the opening for the electrode and the opening 32. Therefore, the opening for the pixel electrode and the opening 32 are both formed with one mask. In this case, the conductive film between the insulating film 22 and the insulating film 26 and between the insulating film 27 and the insulating film 27 is used as a pixel electrode. The opening of the opening 3 is partially etched too much or not enough. 2, there is a risk of problems such as the conductive film 21 not being exposed. In order to obtain the structure shown in the cross-sectional view of FIG. 3C, an opening is formed in the insulating film 26 and the insulating film 27. After that, when forming the opening 32 in the insulating film 22, the nitride insulating film 28, and the insulating film 29, Even if the above opening and the opening 32 are both formed using the mask, the opening and the opening 32 are etched. The thickness of the insulating film removed by the etching is unlikely to vary. This makes it less susceptible to corrosion and increases yields.

[0046] In the transistor 20 illustrated in FIG. 2, the conductive film 24 and the oxide semiconductor film 23 are formed at the end portions of the oxide semiconductor film 23. and the end portion that does not overlap with the conductive film 25, in other words, the end portion where the conductive film 24 and the conductive film 25 are located. The conductive film 21 and the conductive film 30 have a configuration in which the end portion located in a region different from the region overlaps with each other. The end portion of the oxide semiconductor film 23 is etched by plasma to form the end portion. When exposed to the etching gas, chlorine radicals, fluorine radicals, etc. generated from the etching gas convert the oxide The metal element in the oxide semiconductor film is easily bonded to the metal element in the semiconductor film. Since the oxygen bonded to the metal element is easily released, oxygen vacancies are formed, resulting in n-type However, in the transistor 20 shown in FIG. The conductive film 21 and the conductive film 30 overlap with an end portion of the oxide semiconductor film 23 that does not overlap with the conductive film 25. Therefore, by controlling the potentials of the conductive film 21 and the conductive film 30, the electric field applied to the end portion Therefore, the conductive film 24 and the oxide semiconductor film 23 are electrically connected via the end of the oxide semiconductor film 23. The current flowing between the conductive films 21 and 30 is controlled by the potential applied to the conductive films 21 and 30. This can be done.

[0047] Specifically, a potential that makes the transistor 20 non-conductive is applied to the conductive film 21 and the conductive film 30. When the end portion is applied to the conductive film 24 and the conductive film 25, the off-current flowing between the conductive film 24 and the conductive film 25 through the end portion is reduced. Therefore, in order to obtain a large on-current in the transistor 20, The channel length is shortened, and as a result, the conductive film 24 and the conductive film 25 at the end of the oxide semiconductor film 23 are Even if the length between the first and second electrodes 25 is shortened, the off-current of the transistor 20 can be suppressed to a small value. Therefore, by shortening the channel length, the transistor 20 can be made to have a large It is possible to obtain a large on-current and to suppress the off-current to a small value when the device is in a non-conducting state. In order to obtain a large on-current, the channel length is preferably 0.5 μm or more and 4.5 μm or less. Preferably, the thickness is 1 μm or more and 4 μm or less, and more preferably, 1 μm or more and 3.5 μm or less. It is preferable that the thickness is 1 μm or less, and more preferably 1 μm or more and 2.5 μm or less. It is preferable that the thickness is 2 μm or less. Most preferred.

[0048] FIG. 25 illustrates an example of a cross-sectional view of the transistor 20 at an end portion of the oxide semiconductor film 23. In FIG. 25, the oxide is formed in the channel width direction corresponding to the dashed line A3-A4 in FIG. In the illustrated example, the end of the compound semiconductor film 23 is positioned so as to overlap the conductive film 21. In FIG. 25, the insulating film 26, the insulating film 27, the nitride insulating film 28, and the insulating film 29 are each formed as a single layer. The insulating film is shown as:

[0049] As shown in FIG. 25, the distance between the end of the oxide semiconductor film 23 and the end of the conductive film 30 is denoted by Tov. The distance between the conductive film 21 and the conductive film 30 is Tge. In one embodiment of the present invention, Tov is Tg The conductive film 24 and the conductive film 22 are separated from each other through the end of the oxide semiconductor film 23 by a distance of 1.0 times or more. This is preferable because it allows the current flowing between the time Tov and Tge to be controlled. A value of 5 times or less is preferable because it is possible to obtain the effect of controlling the current. The size of the transistor 20 can be made smaller.

[0050] Specifically, a potential that makes the transistor 20 conductive is applied to the conductive film 21 and the conductive film When the voltage Vcc is applied to the terminal 30, the current flowing between the conductive film 24 and the conductive film 25 via the terminal is increased. This current can be used to increase the field effect mobility and on-current of transistor 20. In addition, the end portion of the oxide semiconductor film 23 overlaps with the conductive film 21 and the conductive film 30. As a result, in the oxide semiconductor film 23, carriers are transported to the insulating film 22 and the insulating film 26 and the oxide Since the oxide semiconductor film 23 flows not only at the interface with the semiconductor film 23 but also over a wide area of ​​the oxide semiconductor film 23, The amount of carrier movement in the transistor 20 increases. As a result, As the on-current increases, the field effect mobility also increases. Typically, the field effect mobility is 1 0cm 2 / V·s or more, even 20 cm 2 / V·s or more. Note that the electric field effect The actual mobility is not an approximation of the mobility as a physical property value of the oxide semiconductor film, but This is the field effect mobility in the saturation region.

[0051] In addition, the transistor 20 shown in FIG. 2 has an etched portion for forming the conductive film 24 and the conductive film 25. During the etching, an insulating film (protective insulating film) for protecting the surface of the oxide semiconductor film 23 is formed. Unlike the structure (channel protection structure) in which the protective insulating film is provided, It has a channel etch structure.

[0052] In the case of a transistor having a channel protection structure, the purpose is to protect the surface of the oxide semiconductor film 23. In order to achieve this object, the ends of the conductive film 24 and the ends of the conductive film 25 are respectively disposed on the protective insulating film. Therefore, the conductive film 24 and the conductive film 25 are formed by etching. The alignment of the mask used to fabricate the transistor with the channel protection structure is This requires higher precision than a transistor with a channel etch structure. In the case of a transistor having a protective structure, the ends of the conductive film 24 and the ends of the conductive film 25 are more securely In order to position the conductive film 24 on the protective insulating film, the end of the conductive film 24 in the channel length direction and the conductive film 2 It is desirable to shorten the distance between the ends of 5 in order to prevent a decrease in yield. When the distance between the end of the conductive film 24 and the end of the conductive film 25 is shortened, the conductive film 24 and the conductive film 25 are Since the area where the conductive film 3 functions as a gate is overlapped with the nitride semiconductor film 23, the conductive film 3 From 0, the electric field that should be applied to the oxide semiconductor film 23 is reduced by the conductive film 24 and the conductive film 25. The channel length direction is defined as the direction extending from the conductive film 24 to the conductive film 25 at the shortest. This corresponds to the direction in which carriers move over a short distance.

[0053] On the other hand, in the case of the transistor 20 having a channel etch structure, the conductive film 24 and the conductive film 25 are etched. The mask used for forming the transistor by etching is aligned with the channel protection structure. Therefore, the transistor 20 having a channel etch structure is , the distance between the end of the conductive film 24 and the end of the conductive film 25 is longer than that of the transistor having the channel protection structure. Even if the time is increased, the decrease in yield is suppressed. Since the area where the oxide semiconductor film 23 overlaps with the conductive film 30 can be narrowed, The electric field that would otherwise be applied to the conductive film 23 is less likely to be blocked by the conductive films 24 and 25. Therefore, the transistor 20 with the channel etch structure is more efficient than the transistor 20 with the channel protection structure. It is easier to obtain a larger on-current than a transistor, and the oxide does not change even if the channel length is shortened. Therefore, the off-current flowing through the end portion of the compound semiconductor film 23 can be suppressed to a small value.

[0054] In addition, the protective insulating film is exposed to plasma during etching when the conductive film 24 and the conductive film 25 are formed. It is believed that oxygen is easily released due to the exposure to oxygen, and oxygen vacancies are easily formed. Therefore, the protective insulating film is formed on the oxide semiconductor film 23 in contact with the protective insulating film. It can be said that the ability to supply a sufficient amount of oxygen to reduce the oxygen vacancies in 3 is poor. On the other hand, in the transistor 20 having a channel etch structure, the conductive film 2 The portions that do not overlap with the conductive film 24 and the conductive film 25 are used as the edges when the conductive film 24 and the conductive film 25 are formed. However, after the conductive film 24 and the conductive film 25 are formed, The insulating film 26 and the insulating film 27 are capable of supplying a sufficient amount of oxygen to the oxide semiconductor film 23. By forming the oxide semiconductor film 23, oxygen vacancies in the oxide semiconductor film 23 can be reduced. The transistor 20 with the channel etch structure has a larger resistance than the transistor with the channel protection structure. , high reliability can be obtained.

[0055] In particular, in the transistor 20 having a channel etch structure, the oxide semiconductor film 23 is -OS(C Axis Aligned Crystalline Oxide Sem When an amorphous oxide semiconductor film is used, an amorphous oxide semiconductor film or a microcrystalline oxide semiconductor film is used. Compared with the case where a conductive film is used for the oxide semiconductor film 23, the conductive film 24 and the conductive film 25 are formed. By etching during the etching, the oxide semiconductor film 23 overlaps with the conductive film 24 and the conductive film 25. Therefore, the region where the CAA is not present in the oxide semiconductor film 23 is difficult to be removed by etching. The transistor 20 using the C-OS film has higher reliability. The amorphous oxide semiconductor film and the microcrystalline oxide semiconductor film will be described in detail later.

[0056] Note that the transistor including the oxide semiconductor film is an accumulation type transistor. The flow of carriers in an off state and an on state of a transistor including an oxide semiconductor film This will be explained using the schematic diagram shown in FIG. 36. Also, FIG. 36(A) and FIG. 36(B) are FIG. 36(A) is a cross-sectional view in the channel length direction, and FIG. 36(B) is a cross-sectional view in the channel width direction.

[0057] In FIG. 36, the transistor having an oxide semiconductor film includes a gate electrode GE_1 and a gate A gate insulating film GI_1 on the gate electrode GE_1, and an oxide semiconductor film on the gate insulating film GI_1 An OS, electrodes S and D on the oxide semiconductor film OS, and a The semiconductor device has a gate insulating film GI_2 and a gate electrode GE_2 on the gate insulating film GI_2. The semiconductor film OS is made up of a channel region i and a low-resistance region n in contact with electrodes S and D. + and The gate electrode GE_1 and the gate electrode GE_2 are connected as shown in FIG. is.

[0058] When the transistor is in an off state, as shown in FIG. When a negative voltage is applied to _2, electrons are expelled from the channel region i of the oxide semiconductor film OS. As a result, the off-current of the transistor is extremely small. It becomes smaller.

[0059] On the other hand, in the on-state, as shown in FIG. 36(B), the low-resistance region n + from Low resistance area n in contact with electrode D + Electrons accumulate along the As shown in FIG. 36(C), the gate electrodes GE_1 and GE_2 are formed at the same time. The side surface of the oxide semiconductor film OS faces the gate electrode GE_2. In the channel width direction, a gate electrode GE_1 and a gate electrode GE_2 are The oxide semiconductor film OS is surrounded by the insulating film GI_1 and the gate insulating film GI_2. As shown in FIG. 36(B), carriers in the oxide semiconductor film OS are transported to the gate insulating film GI_ 1. Not only at the interface between GI_2 and the oxide semiconductor film OS, but also in a wide range of the oxide semiconductor film OS This increases the amount of carrier movement in the transistor. As the on-current of a transistor increases, the field effect mobility increases. Field effect mobility is 10 cm 2 / V·s or more, even 20 cm 2 / V s or more. The field-effect mobility here is not an approximation of the mobility as a physical property value of the oxide semiconductor film. is the field effect mobility in the saturation region of the transistor. The length L of the loop is 0.5 μm or more and 6.5 μm or less, preferably 1 μm or more and less than 6 μm. Preferably, it is greater than 1 μm and less than 4 μm, more preferably greater than 1 μm and less than 3.5 μm. More preferably, the thickness is set to be greater than 1 μm and less than 2.5 μm, thereby increasing the field effect mobility. In addition, the channel length is small, 0.5 μm or more and 6.5 μm or less. Therefore, the channel width can be reduced as shown in FIG. Even if a region for connecting the gate electrodes GE_1 and GE_2 is provided, the transistor It is possible to reduce the area of ​​the transistor.

[0060] Next, a specific structure of a transistor 20 having a pair of electrically connected gate electrodes will be described. An example of the structure is shown in FIG. 19. FIG. 19A shows a top view of a transistor 20. In FIG. 9(A), the insulating film 26 and the insulating film 27 are omitted in order to clarify the layout of the transistor 20. Various insulating films such as a gate insulating film other than the film 27 are omitted. FIG. 19B shows a cross-sectional view taken along the dashed line A1-A2 of the top view shown in FIG. A cross-sectional view of the above is shown in FIG.

[0061] In the transistor 20 shown in FIG. 19, an insulating film 26 and an insulating film 27 are disposed around the transistor 20. 2 in that the transistor 20 shown in FIG. Specifically, in FIG. 19, the conductive film 24 and the conductive film 2 The insulating film 26 and the insulating film 27 are formed so as to cover at least the end portion that does not overlap with the insulating film 25. 6 and the insulating film 27 are partially removed. In this configuration, the conductive film 30 functioning as a gate is disposed at the end of the insulating film 26 and the insulating film 27. In this way, the oxide semiconductor film 23 can be located closer to the edge of the oxide semiconductor film 23. The end of the semiconductor film 23 is easily converted to n-type. By bringing the end closer, the electric field applied from the conductive film 30 to the end can be made stronger. Therefore, a current flows between the conductive film 24 and the conductive film 25 through the end of the oxide semiconductor film 23. can be more reliably controlled by the potential applied to the conductive film 30. Even if the channel length of the transistor 20 is shortened, the off-current of the transistor 20 is suppressed to be smaller. It is possible to obtain a larger on-current.

[0062] In the transistor 20 shown in FIG. 2 and FIG. 19, the conductive film The end of the insulating film 30 is provided at a position overlapping the oxide semiconductor film 23. The end of the conductive film 30 may be provided at a position overlapping the conductive film 30 .

[0063] In addition, the specific configuration of the transistor 20 having a pair of electrically connected gate electrodes An example is shown in FIG. 20. FIG. 20A shows a top view of a transistor 20. In (A), in order to clarify the layout of the transistor 20, each element such as a gate insulating film is not shown. In addition, in the top view shown in FIG. 20(A), the insulating film of the kind is omitted. A cross-sectional view taken along the dashed line A3-A4 is shown in FIG. 20(B), and a cross-sectional view taken along the dashed line A3-A4 is shown in FIG. 20(C). .

[0064] In the transistor 20 shown in FIG. 20, the conductive film 3 is disposed in a region where the oxide semiconductor film 23 is located. 0 does not overlap with the conductive film 24 and the conductive film 25. In other words, the oxide semiconductor In the region where the conductive film 23 is located, a region different from the region where the conductive film 24 and the conductive film 25 are located is provided. 2 in that a conductive film 30 is located in the region.

[0065] In addition, the specific configuration of the transistor 20 having a pair of electrically connected gate electrodes An example is shown in FIG. 21. FIG. 21A shows a top view of a transistor 20. In (A), in order to clarify the layout of the transistor 20, each element such as a gate insulating film is not shown. In addition, in the top view shown in FIG. 21(A), the insulating film of the kind is omitted. A cross-sectional view taken along the dashed line A3-A4 is shown in FIG. 21(B), and a cross-sectional view taken along the dashed line A3-A4 is shown in FIG. 21(C). .

[0066] In the transistor 20 illustrated in FIG. 21, the conductive film 3 is disposed in a region where the oxide semiconductor film 23 is located. 2. At the point where the conductive film 24 overlaps the conductive film 24 and does not overlap the conductive film 25, In other words, in the region where the oxide semiconductor film 23 is located, The conductive film 30 is located in a part of the region where the conductive film 24 is located, and the oxide semiconductor film 23 The conductive film 30 is located in a region different from the region where the conductive film 25 is located. In this respect, the structure of the transistor 20 shown in FIG.

[0067] In addition, the specific configuration of the transistor 20 having a pair of electrically connected gate electrodes An example is shown in FIG. 24. FIG. 24A shows a top view of a transistor 20. In (A), in order to clarify the layout of the transistor 20, each element such as a gate insulating film is not shown. In addition, the insulating film of the above-mentioned type is omitted. A cross-sectional view taken along the dashed line A3-A4 is shown in FIG. 24(B), and a cross-sectional view taken along the dashed line A3-A4 is shown in FIG. 24(C). .

[0068] In the transistor 20 shown in FIG. 24, the conductive film 21 and the conductive film 30 are electrically connected via the conductive film 34. The structure differs from that of the transistor 20 shown in FIG. The conductive film 34 is formed on the insulating film 22, and an opening 32a is formed in the insulating film 22. The conductive film 30 is in contact with the conductive film 21 at the insulating film 26 to the insulating film 29. The conductive film 34 is in contact with the formed opening 32b.

[0069] The transistor 20 shown in FIGS. 20, 21 and 24 has the same structure as the transistor shown in FIG. Similarly, the insulating film 26 and the insulating film 27 may be partially removed.

[0070] In addition, in the transistor 20 illustrated in FIGS. 2, 19, 20, and 21, an oxide semiconductor film 23 is not necessarily composed of a single oxide semiconductor film, but is composed of a stack of multiple oxide semiconductors. In FIG. 23A, the oxide semiconductor film 23 is a three-layer stack. 23A shows an example in which the insulating film is formed of an oxide semiconductor film having a thickness of 100 nm to 150 nm. In the transistor 20 shown in FIG. 1, the oxide semiconductor film 23 includes oxide semiconductor films 23a to 23b. The compound semiconductor film 23c is laminated in order from the insulating film 22 side.

[0071] The oxide semiconductor film 23a and the oxide semiconductor film 23c constitute the oxide semiconductor film 23b. The element contains at least one metal element that forms an oxide. The energy of the conduction band minimum is The difference is 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0.05 eV or more, more preferably 0.07 eV or more, more preferably 0.1 eV or more, more preferably ... .15 eV or more and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less, true The oxide semiconductor film 23b is an oxide film close to a vacant level. It is preferable for the compound to contain the compound to have a high carrier mobility.

[0072] Note that the oxide semiconductor film 23c is formed by arranging the conductive film 24 and the conductive film 25 as shown in FIG. It may be configured so as to overlap the insulating film 22 at the upper layer.

[0073] Next, a transistor having a pair of gate electrodes overlapping with a semiconductor film sandwiched therebetween is The circuit symbol is shown in FIG. 22(A). In the circuit symbol shown in FIG. 22(A), a pair of gate electrodes are F The gate electrodes are indicated by G and BG, the source electrode is indicated by S, and the drain electrode is indicated by D. In the circuit symbol, a conductive film 30 functioning as a gate electrode and a source electrode or a drain electrode There is no limitation on the positional relationship between the conductive film 24 and the conductive film 25 that function as the conductive film 24 and the conductive film 25 .

[0074] FIG. 22B1 shows a conductive film 24 functioning as a source electrode or a drain electrode and a conductive film 25 is partially connected to the conductive film 30 functioning as a gate electrode on the oxide semiconductor film 23. The circuit symbol of the transistor 20 overlapping the transistor 20 shown in FIG. In the circuit symbol shown in FIG. 22(A), a pair of gate electrodes are indicated by FG ​​and BG, and the source The source electrode is indicated by S and the drain electrode is indicated by D.

[0075] FIG. 22(B2) shows a cross section of a transistor 20 corresponding to the circuit symbol shown in FIG. 22(B1). The figure is shown as an example. The transistor 20 shown in FIG. The distance Wsd between the ends of the conductive film 24 and the conductive film 25 is the distance W between the ends of the conductive film 30. In the cross-sectional view in the channel length direction, the pair of ends of the conductive film 30 The portion overlaps with the conductive film 24 and the conductive film 25.

[0076] In addition, in FIG. 22(C1), a conductive film 24 and a The conductive film 25 is formed on the oxide semiconductor film 23 so as to form a conductive film 30 functioning as a gate electrode. The circuit symbol for the non-overlapping transistor 20 is shown in FIG. In the circuit symbol shown in FIG. 22(A), a pair of gate electrodes are indicated by FG ​​and BG, and the source The source electrode is indicated by S and the drain electrode is indicated by D.

[0077] FIG. 22C2 shows a cross section of a transistor 20 corresponding to the circuit symbol shown in FIG. 22C1. The figure is shown as an example. The transistor 20 shown in FIG. The distance Wsd between the ends of the conductive film 24 and the conductive film 25 is the distance W between the ends of the conductive film 30. In the cross-sectional view in the channel length direction, the pair of ends of the conductive film 30 The portion does not overlap with the conductive film 24 and the conductive film 25.

[0078] In the drawings attached to this specification, the circuit symbol shown in FIG. 22(A) corresponds to the circuit symbol shown in FIG. 22(B1). A transistor 20 having a structure represented by the symbol and a transistor 21 having a structure represented by the circuit symbol in FIG. and transistor 20.

[0079] <Measurement of the electrical characteristics of a transistor> Next, a transistor having a channel formation region in an oxide semiconductor film was irradiated with light. The measurement results of the electrical characteristics of the transistors will be described.

[0080] First, the structure of the transistor used in the measurement is described. and a pair of gate electrodes overlapping each other with a semiconductor film interposed therebetween. A second transistor was used.

[0081] The first transistor has a gate electrode made of a 200 nm thick tungsten film on an insulating surface. On the electrode and the gate electrode, a silicon nitride film having a thickness of 400 nm and a nitriding oxide film having a thickness of 50 nm were formed. The first transistor had a gate insulating film in which a silicon nitride film and a silicon oxide film were stacked in sequence. A 35 nm thick In-Ga-Zn The first transistor had a gate insulating film having a thickness of 100 nm-100 nm on the oxide semiconductor film. A tungsten film with a thickness of 50 nm, an aluminum film with a thickness of 400 nm, and an aluminum film with a thickness of 200 nm The source electrode and the drain electrode were laminated in this order with a titanium film of 1000 nm. A silicon oxynitride film having a thickness of 50 nm is formed on the semiconductor film and the source and drain electrodes. A silicon oxynitride film having a thickness of 400 nm and a silicon nitride film having a thickness of 100 nm are laminated in this order. It was set up so that

[0082] The second transistor is a 100 nm thick indium oxide doped silicon nitride film. The second transistor has the same structure as the first transistor only in that it further has a gate electrode using a silicon tin oxide film. The second transistor had a gate electrode made of tungsten. The gate electrode made of an indium tin oxide film containing silicon oxide is electrically connected to the It was being done.

[0083] In the first and second transistors, an In-Ga-Zn oxide semiconductor is used. The film was made by using a target with a composition (atomic ratio) of In, Ga, and Zn of 1:1:1. The first transistor and the second transistor are formed by a sputtering method. The silicon oxynitride film with a thickness of 50 nm was formed by silane with a flow rate of 20 sccm and 3000 s. The source gas was nitrous oxide (N2O) at 1.0 ccm, the pressure in the processing chamber was 200 Pa, and the substrate temperature was 350° C. A 27.12MHz high-frequency power source was used to generate 150W (power density 2.5×10 -2 W / cm 2 The film was formed by plasma CVD, in which high-frequency power of 1000 Hz was supplied to parallel plate electrodes. In the first and second transistors, a silicon oxynitride film having a thickness of 400 nm is used. The film was prepared by mixing silane at a flow rate of 160 sccm and dinitrogen monoxide at a flow rate of 4000 sccm. The pressure in the processing chamber was 200 Pa, the substrate temperature was 220°C, and a high frequency of 27.12 MHz was used. A 1500W (power density 2.5×10 -1 W / cm 2 ) high frequency power in parallel The first transistor and the second transistor are formed by a plasma CVD method. In the second transistor, a silicon nitride film having a thickness of 100 nm is formed by silane at a flow rate of 50 sccm. The raw material gases were nitrogen at a flow rate of 5000 sccm and ammonia at a flow rate of 100 sccm. The pressure in the processing chamber was 100 Pa, the substrate temperature was 350° C., and a high-frequency power source of 27.12 MHz was used. Using a power density of 1.6×10 -1 W / cm 2 ) high frequency power is The film was formed by plasma CVD using a material supplied to the electrode.

[0084] The first transistor and the second transistor have a channel length L of 6 μm and a channel width W was 50 μm.

[0085] The electrical characteristics of the first and second transistors are measured by applying stress. Measurement of drain current before the stress application process (measurement 1), and measurement of drain current after the stress application process (measurement 2) in that order. The stress application process was carried out in a darkroom without light exposure. The substrate temperature was kept at 60° C. and the gate voltage Vg was kept at −30 V for 1 hour. In general, the drain current measurements in Measurement 1 and Measurement 2 were performed without illumination in a dark room. The measurement was performed under the same conditions with the substrate temperature at 60°C. The gate voltage Vg was set at -1 The voltage between the source and drain electrodes is changed in increments of 0.25 V between 5 V and 30 V. Vds was set to 0.1V or 10V.

[0086] FIG. 17A shows the gate voltage Vg and drain The relationship between the current Id and the voltage Vds is shown in Fig. 1. Furthermore, when the voltage Vds is 10 V, the calculated The field effect mobility μFE obtained by the measurement is also shown in FIG. , the relationship between the gate voltage Vg and the drain current Id of the second transistor. The calculated field effect mobility μFE when ds is 10 V is also shown. From FIG. 17(A) and FIG. 17(B), it is clear that the second transistor has a larger current than the first transistor. , the drain current Id and the field effect mobility μFE were found to be large.

[0087] The following Table 1 shows the first transistor (Single Gate e), the threshold voltage (Vth) of the second transistor (Dual Gate), and the shift value ( The shift value is the gate voltage when the drain current rises. Specifically, the logarithmic scale voltage is defined as the gate voltage on the linear scale. In the semi-logarithmic graph showing the relationship between drain current and drain current, the slope of the drain current changes most steeply. At the point where the tangent line to the drain current of 1e-12[A] intersects with the scale line The shift value is defined as the voltage at which the shift occurs when the voltage Vds is 10 V.

[0088] [Table 1]

[0089] As shown in Table 1, in the first transistor, the threshold voltage is -4. It was found that the voltage shifted by -6.80V and the voltage shifted by 48V. Also, the second transistor The threshold voltage shifted by 0.27 V and the shift value shifted by 0.25 V due to the stress application process. Therefore, it was found that the second transistor has a higher threshold voltage than the first transistor. It was found that the negative shift in pressure and shift value was suppressed.

[0090] Therefore, by the above measurement, it was found that a pair of gate electrodes sandwiching a semiconductor film therebetween It was found that this could prevent the transistor's threshold voltage from shifting in the negative direction. In addition, by applying the same potential to a pair of gate electrodes, the drain current can be increased. I found out that...

[0091] Dual Gate Drive Channel Etch Transistor and Channel Protection Transistor Comparison of transistors Here, the channel etch type transistor and the channel protection type transistor are Here, the field effect mobility and on-state current of the MOSFET with an oxide semiconductor film sandwiched therebetween are compared. The opposing gate electrodes are connected to each other and are at the same potential, forming a dual gate driven transistor. The field-effect mobility of the FE ) and on-current (Ion).

[0092] Regarding the electrical characteristics of channel-etched transistors and channel-protected transistors, The calculation was performed using the above method. Figure 29(A) shows the structure of the channel protection transistor used in the calculation. The calculations were performed using the device simulation software Atlas (Silvaco). was used.

[0093] In the channel protection type transistor, a gate insulating film GI_1 is formed on a gate electrode GE_1. Thus, an oxide semiconductor film OS is formed on the gate insulating film GI_1. A source electrode S and a drain electrode D are formed on the oxide semiconductor film OS. Between the ends of the source electrode S and the drain electrode D and the oxide semiconductor film OS, a channel protective film CS is provided. The oxide semiconductor film OS, the source electrode S, the drain electrode D, and the channel A gate insulating film GI_2 is formed on the protective film CS. The gate electrode GE_1 and the gate electrode GE_2 are formed. In an opening (not shown) formed in the insulating film GI_1 and the gate insulating film GI_2, , connect.

[0094] In the channel etch type transistor, the channel protective film CS is not provided, and the source electrode S and The end of the drain electrode D is in contact with the oxide semiconductor film OS.

[0095] The conditions used in the calculation are shown in Table 2.

[0096] [Table 2]

[0097] FIG. 29(A) shows a transistor driven by a dual gate. Regarding the single gate driven transistor without the gate electrode GE_2, The same calculations were performed as for the dual gate driven transistor.

[0098] In a channel-protection transistor, an oxide semiconductor film is formed through a channel protection film CS. The length of the region where the OS and the source electrode S or the drain electrode D overlap is defined as Sov. , the source electrode S and the drain electrode D are formed of an oxide semiconductor via a channel protective film CS. The region overlapping with the film OS is called the Sov region. The relationship between Sov and the field effect mobility was calculated. The results are shown in Figure 29(B), and the results of calculating the relationship between Sov and on-current are shown in Figure 29(C). show.

[0099] In addition, in the case of a channel-etch type transistor, Sov is set to 0 μm, and the field-effect transition The mobility and on-state current were calculated. The calculation results are shown in Fig. 29(B) and Fig. 29(C), respectively. As shown in.

[0100] FIG. 29B shows the results when the drain voltage Vd is set to 1 V. (C) shows the result when the drain voltage Vd is 1V and the gate voltage Vg is 10V.

[0101] As shown in FIG. 29(B), in a channel-etched transistor (Sov is 0 μm), Compared to single gate driven transistors, dual gate driven transistors The field effect mobility of the channel-protected transistor is about twice as high. So, the field effect mobility of a dual gate driven transistor increases as the length of Sov increases. The relationship between the number of

[0102] Also, as shown in FIG. 29(C), a channel etch type transistor (Sov is 0 μm) So, what is the difference between a Dual Gate driven transistor and a Single Gate driven transistor? The on-state current of the transistor is about twice as high. On the other hand, the channel protection type transistor So, the on-current of a dual gate driven transistor increases as the length of Sov increases. The decrease is in accordance with

[0103] In a channel-protected transistor, the Sov region at the source electrode S and the drain electrode D The gate electrode GE_2 is shielded from the electric field of the gate electrode GE_2. The area where the carrier density cannot be controlled by the voltage of the gate electrode GE_2 is expanded. It is considered that as the length of Sov increases, the field effect mobility decreases and the on-current becomes smaller. From the above, compared with the channel protection type transistor, The effect of increasing the field effect mobility in dual gate drive is The current amplification effect is effective.

[0104] <Improvement of current driving capability by dual gate driving> The gate electrodes facing each other across the oxide semiconductor film are connected and have the same potential. In the driving transistor, the current driving force is improved by reducing the channel length L. This section explains what we will do.

[0105] <<On the saturation mobility in an ideal model>> First, we performed simulations using an ideal model that does not take into account the effects of interface states and interface scattering. Figure 30 shows the model of the transistor used in the calculation. The calculation was performed using the device simulation software Atlas (manufactured by Silvaco). Ta.

[0106] In the transistor shown in FIG. 30, a gate insulating film GI_1 is formed on a gate electrode GE_1. The oxide semiconductor film OS is formed on the gate insulating film GI_1. A source electrode S and a drain electrode D are formed on the oxide semiconductor film OS. A gate insulating film GI_2 is formed on the film OS, the source electrode S, and the drain electrode D. A gate electrode GE_2 is formed on the gate insulating film GI_2. The gate electrode GE_2 is formed by an opening formed in the gate insulating film GI_1 and the gate insulating film GI_2. The connection is made at a mouth portion (not shown).

[0107] The conditions used in the calculation are shown in Table 3.

[0108] [Table 3]

[0109] The gate electrode GE_1 and the gate electrode GE_2 are connected to each other and therefore always have the same potential. In addition, since this model uses two-dimensional simulation, the effect in the channel width direction is not clear. The Vg-Id characteristics when the drain voltage (Vd) is 10 V are not taken into consideration. By substituting the values ​​into Equation 1, the saturation mobility μ FE Here, the saturated region is The field effect mobility in the region is explained as the saturation mobility. The maximum value is in the saturation region (gate voltage (Vg) < drain voltage (Vd) + threshold voltage (Vth ) is an index of current driving force in the oxide semiconductor film, and is an approximation of the mobility as a physical property value of the oxide semiconductor film. Different from the value.

[0110]

number

[0111] In formula 1, W is the channel width of the transistor, and C Bottom Is, game The capacitance per unit area between the gate electrode GE_1 and the oxide semiconductor film OS is In the case of a gate-driven transistor, a gate electrode GE_2 and an oxide semiconductor film OS Although capacitance is also formed between the saturation mobility and the current driving capability, Therefore, the capacitance of the gate electrode GE_2 side of the dual gate drive transistor is omitted. Dual Gate drive transistors are also single gate drive transistors. The same formula 1 is used.

[0112] The calculation results for the dual gate driven transistor are shown in FIG. The calculation results for a single-gate driven transistor without E_2 are shown in Figure 31(B). As shown in.

[0113] As shown in Figure 31, the dual gate drive transistor and the single gate drive transistor In each of the transistors, a sharp peak in saturation mobility was obtained. The shorter the length, the higher the peak value of the saturated mobility.

[0114] Here, as the channel length L becomes shorter, the saturation mobility improves. The following explains how this corresponds to an improvement in the current driving force of the capacitor.

[0115] In the results obtained from the simulation of the ideal model, the gate voltage Vg=Vt The on-current is plotted against the L length at h+5 and Vg=Vth+10. The graph is shown in FIG. 32. The upper part of FIG. 32 shows the on-current, and the lower part of FIG. 32 shows the on-current. × channel length. In FIG. 32, the left column shows the results when the drain voltage (Vd) is 1V. The right column shows the calculation results when the drain voltage (Vd) is 10V.

[0116] The on-current shown in FIG. 32 is inversely proportional to the channel length (L). This is because it is inversely proportional to the channel length (L).

[0117] If the on-current is completely inversely proportional to the channel length, the value of on-current x channel length is In Figure 32, when the drain voltage (Vd) is 1V, The value of on-current x channel length is constant with respect to the channel length (L). When the drain voltage (Vd) is 10 V, the on-state current decreases as the channel length (L) becomes shorter. The value of current × channel length increases. This is because, when the drain voltage (Vd) is 10 V, The effective channel length (to be described later) is the channel length (So) defined in FIG. This indicates that the distance between the source electrode S and the drain electrode D is shorter than the distance between the source electrode S and the drain electrode D.

[0118] <<Theory of Bulk Current>> Below, the saturation mobility of an ideal model transistor peaks at low gate voltages. The causes of this will be explained.

[0119] In the transistor illustrated in FIG. 30, the electron density in the oxide semiconductor film OS is It is assumed that the semiconductor film OS is represented by a constant value n0(y) in the thickness direction. y is the oxide semiconductor The figure shows an arbitrary position in the channel length direction in the film OS. The potential φ at the gate electrode GE_1 is expressed by the formula 2 and is constant. The gate voltage Vg_1 and the gate voltage Vg_2 of the gate electrode GE_2 are at the same potential. The flat band voltages on both the electrode GE_1 side and the gate electrode GE_2 side are Band voltage V FB Assume that.

[0120]

number

[0121] At this time, in a transistor having an accumulation type oxide semiconductor film, the drain current I d is the bulk current I bulk is given approximately by

[0122]

number

[0123] In Formula 3, t is the thickness of the oxide semiconductor film, μ is the electron mobility of the oxide semiconductor film, k B is the Boltzmann constant, T is the absolute temperature, L eff is the effective channel length. The channel length is the distance between the source electrode and the drain electrode, and the effective channel length is In the oxide semiconductor film, an n-type region extending from under the source electrode and an n-type region extending from under the drain electrode are This represents the distance between the n-regions in the n-channel region. In particular, when the channel length is short or the drain voltage is high, In this case, the effective channel length is shorter than the channel length.

[0124] Note that n0(0) is the effective channel length at the source electrode side end of the region determined by the effective channel length. The electron density is expressed by the formula 4. Also, n0(L eff ) is the effective channel length mentioned above The electron density at the drain electrode side end of the region defined by is expressed by Equation 5. In Formula 4 and Formula 5, N D is the donor density in the channel region of the oxide semiconductor film. where q is the elementary charge.

[0125]

number

[0126]

number

[0127] In the saturated region where Vd>Vg-Vth and Vg>Vth, the drain voltage Vd is Vg-V Since it is replaced with th, formula 3 becomes formula 6.

[0128]

number

[0129] For the drain current Id obtained by Equation 6, the saturation mobility μ FE sat Calculating the formula The number is 7.

[0130]

number

[0131] In Equation 7, if Vg is changed to Vth, the denominator becomes 0, and the saturation mobility μ FE sat No This property leads to a low gate charge at saturation mobility as shown in FIG. This is the cause of the peak at the voltage Vg. That is, the bulk current flowing inside the oxide semiconductor film OS The more the drain current is dominated by the current, the more the saturation current at the channel length of 2 μm in Figure 31 increases. As with the sum mobility, a more pronounced peak appears.

[0132] Another factor that increases the saturation mobility is the effective channel length L eff Channel For example, in the oxide semiconductor film OS, The n-region expands near the area in contact with the source electrode S and the drain electrode D. Effective channel length L eff becomes shorter than the channel length L. This effect is expressed by the saturation transfer degree μ FE sat L / L eff This is also clear from the proportional relationship to

[0133] Current density in the oxide semiconductor film OS The effect of bulk current on saturation mobility was confirmed in a study using an oxide semiconductor film, which is an accumulation type device. This phenomenon is specific to transistors that use silicon films as semiconductor films. In an inverted device such as

[0134] Next, a graph plotting the current density distribution obtained by device simulation is shown. The Vg-I calculated with a drain voltage of 10 V is shown in FIG. 33B and 33C show the cross-sectional view of the oxide semiconductor film taken along the line A1-A2. The current density distribution in the saturation region (Vg = 0.5 V) is shown in Fig. 33(B), and the current density distribution in the saturation region (Vg = 0.5 V) is shown in Fig. 33(C). The current density distribution in the linear region (Vg = 15 V) is shown. The channel length L / channel width W of the transistor is 2 μm / 50 μm, and the drain voltage Vd is 10 V. It was decided.

[0135] As shown in FIG. 33B, in the saturation region (low gate voltage Vg), almost On the other hand, as shown in Figure 33(C), the current density is uniformly distributed in the linear region (high gain region). At the gate voltage Vg, the current flowing near the surface of the oxide semiconductor film OS is dominant. As shown in FIG. 33B, in the saturation region, the current density in the oxide semiconductor film OS is almost Since the saturation mobility is almost uniformly distributed, one of the reasons for the peak in the saturation mobility is the bulk It is clear that it is an electric current.

[0136] On the other hand, the current density of the semiconductor film of the inverted type device obtained by device simulation 34 shows the distribution of the oxide semiconductor film OS of the transistor shown in FIG. -The calculation results are for a semiconductor film (silicon) containing a pn junction. The channel area is 1×17 / cm 3 We assume an acceptor-type impurity with a density of

[0137] FIG. 34(A) shows the Vg-Id characteristics calculated with a drain voltage of 10 V. 34(B) and 34(C) are current densities in the cross-sectional direction of the semiconductor film taken along line A1-A2 of FIG. FIG. 34(B) shows the distribution of the saturation region (Vg=0.5V), and FIG. 34(C) shows the distribution of the linear region ( The current density distribution at Vg = 15 V is shown in Fig. 1. The channel of the transistor used in the calculation The channel length L / channel width W was 2 μm / 50 μm, and the drain voltage Vd was 10V.

[0138] Unlike a transistor having an oxide semiconductor film, which is an accumulation type device, As shown in FIG. 34B, a transistor having a certain semiconductor film has a threshold voltage of 100V. In the case of the accumulation-type device, the current flowing through the surface of the semiconductor film is large, and the contribution of the bulk current is large. It is smaller than a vise.

[0139] From the above, in a transistor including an oxide semiconductor film, which is an accumulation type device, In an ideal model, the bulk current produces a sharp peak in the saturation mobility. .

[0140] As the channel length L becomes shorter, the peak value of the saturation mobility caused by the bulk current becomes The reason for this is that the oxide semiconductor film OS has a source electrode S and a drain electrode D. In the vicinity of the adjacent region, the n region expands, and the effective channel length L eff Channel It is considered that the channel length L is shorter than the source electrode S. The conduction band minimum energy (Ec) of the oxide semiconductor film OS is low due to the influence of the drain electrode D. The conduction band edge energy approaches the Fermi energy (CBL effect). The duction band lowering effect Long L eff It is considered that the saturation mobility is expressed by the following formula 7: As mentioned above, the effective channel length L eff As L / L becomes smaller, eff Large in proportion to This effect is more pronounced as the channel length L becomes smaller. It is considered that the saturation mobility is improved as the

[0141] Model assuming shallow electron trap levels Next, to approximate the saturation mobility of an actual transistor, an ideal model transistor was In the gate insulating film GI_1, electrons are trapped at the interface between the gate insulating film GI_1 and the oxide semiconductor film OS. Then, the calculation was performed assuming a negatively charged acceptor-type level, i.e., a shallow electron trap level. The results are shown in Figure 35.

[0142] FIG. 35A shows an electron transport pattern assumed at the interface between the gate insulating film GI_1 and the oxide semiconductor film OS. The DOS (density of state) of the wrap level is shown.

[0143] Next, we compare the dual gate drive transistor and the single gate drive transistor. The saturation mobility of each transistor was calculated. The results are shown in FIG. 35(B), which shows the calculation results for a single-gate driven transistor. As shown in 35(C).

[0144] As shown in FIG. 35(B) and FIG. 35(C), the dual gate driven transistor and the sin The saturation mobility of a gle gate driven transistor obtained using an ideal model In addition, as shown in Figure 35(C), the single gate drive In a transistor with a saturation mobility of 1000 Ω, the peak value is approximately 100 Ω, and does not depend much on the channel length L. On the other hand, in the case of a dual gate driven transistor, the channel length L is small. The smaller the diameter, the higher the peak value of the saturation mobility, which was 15 to just under 20. The results show the same tendency as the results of the examples described later.

[0145] For this reason, in a dual gate driven transistor, the channel length L is made small. It can be seen that the higher the concentration, the higher the saturation mobility.

[0146] <Configuration Example of Semiconductor Display Device> Next, a structural example of a semiconductor display device according to one embodiment of the present invention will be described.

[0147] In the semiconductor display device 70 shown in FIG. 6A, a pixel section 71 includes a plurality of pixels 55 and a pixel For each row, wiring GL1 to wiring GLy (y is a natural number) are used to select and wirings SL1 to SLx (x is a line) for supplying image signals to the selected pixels 55. The signal input to the wiring GL is provided by the driving circuit. The input of the image signal to the wiring SL is controlled by a driving circuit 73. The pixels 55 are connected to at least one of the lines GL and at least one of the lines SL. Each is connected to the other.

[0148] The type and number of wirings provided in the pixel section 71 depend on the configuration, number and arrangement of the pixels 55. Specifically, in the case of the pixel section 71 shown in FIG. The pixels 55 are arranged in a matrix, and the wirings SL1 to SLx and the wirings GL1 to A case where the leading wiring GLy is arranged inside the pixel section 71 is illustrated.

[0149] In FIG. 6A, the driver circuit 72 and the driver circuit 73 are mounted on the same substrate as the pixel section 71. 1, the driving circuit 72 and the driving circuit 73 are formed on the pixel section 7. 1 may be formed on a different substrate.

[0150] 6B shows an example of the configuration of a pixel 55. Each pixel 55 includes a liquid crystal element 60 and A transistor 56 for controlling the supply of an image signal to the liquid crystal element 60 and a The liquid crystal element 60 has a capacitance element 57 for holding a voltage between the pixel electrode and the common electrode. The liquid crystal display includes a pixel electrode, a common electrode, and a liquid crystal material to which a voltage is applied between the pixel electrode and the common electrode. and a liquid crystal layer.

[0151] The transistor 56 controls whether or not the potential of the wiring SL is applied to the pixel electrode of the liquid crystal element 60. A predetermined potential is applied to the common electrode of the liquid crystal element 60.

[0152] The specific connection configuration between the transistor 56 and the liquid crystal element 60 will be described below. ) the gate of the transistor 56 is connected to one of the wirings GL1 to GLy. One of the source and drain of the transistor 56 is connected to the wiring SL1. x, and the other of the source and drain of the transistor 56 is connected to the liquid crystal element The pixel electrode of the pixel 60 is connected to the pixel electrode of the pixel 60.

[0153] In the liquid crystal element 60, the voltage applied between the pixel electrode and the common electrode changes depending on the voltage contained in the liquid crystal layer. The orientation of the liquid crystal molecules contained in the liquid crystal element 60 changes, and the transmittance changes. The transmittance of the pixel is controlled by the potential of the image signal applied to the pixel, thereby displaying gray scales. In each of the pixels 55 in the pixel section 71, a liquid crystal element The gray scale of the pixel 60 is adjusted in accordance with an image signal having image information, so that an image is displayed on the pixel section 71. is displayed.

[0154] In FIG. 6B, a pixel 55 has a switch for controlling the input of an image signal to the pixel 55. As an example, a single transistor 56 is used as a switch. A number of functional transistors may be used in pixel 55 .

[0155] In one embodiment of the present invention, a transistor 56 having an extremely low off-state current is used as a It is preferable to use the transistor 56 as a switch to control the input to the A small value prevents charge from leaking through transistor 56. The potential of the image signal applied to the liquid crystal element 60 and the capacitance element 57 can be more reliably held. Therefore, the transmittance of the liquid crystal element 60 changes due to leakage of electric charges within one frame period. This prevents the display of images from being blurred, thereby improving the quality of the images displayed. When the off-current of the transistor 56 is small, the charge leakage through the transistor 56 is prevented. Therefore, during the period when a still image is displayed, the driving circuits 72 and 73 With the above configuration, the supply of the image signal to the pixel section 71 may be stopped. This reduces the number of times the signal is written, thereby reducing the power consumption of the semiconductor display device.

[0156] For example, a transistor including an oxide semiconductor in a semiconductor film has an extremely small off-state current. This is suitable for use as transistor 56.

[0157] In FIG. 6B, the transistor 56 is a pair of transistors overlapping each other with a semiconductor film sandwiched therebetween. The pair of gate electrodes are electrically connected to each other. In one embodiment of the present invention, the above structure increases the on-state current of the transistor 56. Moreover, the reliability of the transistor 56 can be improved.

[0158] 6C shows another example of the pixel 55. The pixel 55 is a pixel having an image signal a transistor 95 for controlling the input of the light emitting element 98; A transistor 96 for controlling the current value supplied to the Element 97.

[0159] The light emitting element 98 is a light emitting diode (LED) or an organic light emitting diode (OLED). current or voltage, such as a photovoltaic (Pb) or photovoltaic (Pb) light emitting diode (Pb) The category includes devices whose luminance is controlled by the light emitting diode (ELD) layer. For example, an OLED includes an EL layer and The device has at least an anode and a cathode. The EL layer is provided between the anode and the cathode. The layer is made up of a single layer or multiple layers, each of which contains a luminescent material. It includes at least a light emitting layer.

[0160] In addition, the EL layer is turned on when the potential difference between the cathode and the anode becomes equal to or exceeds the threshold voltage of the light emitting element 98. When the current is applied, electroluminescence is obtained. There are two types of emission: fluorescence when returning from the singlet excited state to the ground state and fluorescence when returning from the triplet excited state. This includes light emission (phosphorescence) when the compound returns to the ground state.

[0161] Either the anode or the cathode of the light emitting element 98 is connected to an image signal input to the pixel 55. Therefore, the potential is controlled. The potential of the anode and the cathode is controlled according to the image signal. The electrode to be controlled is a pixel electrode, and the other electrode is a common electrode. A predetermined potential is applied to the electrode, and the brightness of the light-emitting element 98 is determined by the potential between the pixel electrode and the common electrode. Therefore, the luminance of the light emitting element 98 is determined by the potential difference between the pixel electrodes. By controlling the pixel area, it is possible to display gradations. In each of the above-mentioned embodiments, the gradation of the light-emitting element 98 is adjusted according to an image signal having image information. As a result, an image is displayed on the pixel section 71 .

[0162] Next, the transistor 95, the transistor 96, the capacitor element 97, the light emitting element 98, and the like included in the pixel 55 are The connection configuration of the element 98 will now be described.

[0163] The transistor 95 has one of a source and a drain connected to a wiring SL. The other drain is connected to the gate of transistor 96. The transistor 96 has a source and a drain that are connected to the wiring GL. It is connected to the power supply line VL, and the other of the source and the drain is connected to the light emitting element 98. Specifically, the other of the source and drain of the transistor 96 is connected to the anode of the light emitting element 98. Either the anode or the cathode of the light emitting element 98 is connected to A predetermined potential is applied to either one of them.

[0164] In FIG. 6C, the transistor 96 is a pair of gates overlapping with a semiconductor film sandwiched between them. The pair of gate electrodes are electrically connected to each other. In one embodiment of the present invention, the above structure increases the on-state current of the transistor 96. Furthermore, the reliability of the transistor 96 can be improved.

[0165] Pixel Structure Next, a liquid crystal display device, which is one of the semiconductor display devices 70 shown in FIG. 6A, will be taken as an example. A configuration example of the pixel 55 will now be described. A top view of a pixel 55 formed on the plate 31 is shown as an example. Note that in FIG. In order to clarify the layout, various insulating films are omitted. FIG. 5 shows a cross-sectional view of a liquid crystal display device formed using an element substrate having the pixel electrode 55. In the liquid crystal display device shown in FIG. 4, an element substrate including a substrate 31 is shown in FIG. This corresponds to a surface view.

[0166] 4 and 5 includes a transistor 56 and a capacitor 57. The pixel 55 shown in FIG.

[0167] The transistor 56 is provided on the substrate 31 having an insulating surface, and has a function as a gate electrode. A conductive film 40 and an insulating film located on the conductive film 40, which has a function as a gate insulating film. a conductive film 40 formed on the insulating film 22; an oxide semiconductor film 41 overlapping the conductive film 40 on the insulating film 22; A conductive electrode electrically connected to the body membrane 41 and functioning as a source electrode or a drain electrode. The conductive film 40 has a function as the wiring GL shown in FIG. In addition, the conductive film 43 functions as a wiring SL shown in FIG.

[0168] The pixel 55 also has a metal oxide film 42 on the insulating film 22. The metal oxide film 42 is The metal oxide film 42 is a conductive film that is transparent to visible light. A conductive film 61 is provided which is electrically connected to the metal film 42. The conductive film 61 is a metal oxide It functions as a wiring that supplies a predetermined potential to the film 42 .

[0169] 5, the oxide semiconductor film 41, the conductive film 43, and the conductive film 44, and the metal oxide film 4 An insulating film 26 and an insulating film 27 are provided on the conductive film 61 in this order. The transistor 56 may include the insulating film 26 and the insulating film 27 as components thereof. In addition, in FIG. 5, the insulating film 26 and the insulating film 27 are illustrated as being laminated in this order. Instead of the film 26 and the insulating film 27, a single-layer insulating film may be used, or a laminated insulating film may be used. Three or more insulating layers may be used.

[0170] The insulating film 26 and the insulating film 27 have an opening 58 at a position where they overlap with the metal oxide film 42. The opening 58 is formed in a region different from the oxide semiconductor film 41, the conductive film 43, and the conductive film 44. and is provided in a region overlapping with the metal oxide film 42.

[0171] 5, the metal oxide film 42 on the insulating film 26 and the insulating film 27 and in the opening 58 On the upper side, a nitride insulating film 28 and an insulating film 29 are provided in this order.

[0172] Note that an oxide semiconductor film is formed on the insulating film 22, and a nitride By forming the insulating film 28, the electrical conductivity of the oxide semiconductor film can be increased. As a result, the oxide semiconductor film with increased conductivity can be used as the metal oxide film 42. The conductivity of the oxide semiconductor film increases when the opening 58 is formed or when the nitride insulating film 2 During the formation of the nitride insulating film 28, oxygen vacancies are formed in the oxide semiconductor film, and the oxygen diffuses from the nitride insulating film 28. This is thought to be because the hydrogen atom that is released binds to the oxygen vacancy to generate a donor. The resistivity of the metal oxide film 42 is typically 1×10 -3 Ωcm or more 1×10 4 Ωcm More preferably, the resistivity is less than 1×10 -3 Ωcm or more 1×10 -1 Less than Ωcm It would be good to do so.

[0173] The metal oxide film 42 preferably has a higher hydrogen concentration than the oxide semiconductor film 41. In the film 42, secondary ion mass spectrometry (SIMS) was used. The hydrogen concentration obtained by assemblage spectrometry was 8×10 19 atom s / cm 3 More than 1×10 20 atoms / cm 3 More preferably, 5x 10 20 atoms / cm 3 The above is the case. In the oxide semiconductor film 41, the secondary ion mass The hydrogen concentration obtained by the analytical method is 5×10 19 atoms / cm 3 Less than 5, preferably ×10 18 atoms / cm 3 Less than 1 x 10 18 atoms / cm 3 below, More preferably, 5×10 17 atoms / cm 3 Less than 1×10, more preferably 16 a toms / cm 3 The following is the result.

[0174] The nitride insulating film 28 may be, for example, silicon nitride, silicon oxynitride, or aluminum nitride. The nitride insulating film using the above-mentioned material may be aluminum oxide nitride. 28 is less susceptible to external impurities than oxide insulating films such as silicon oxide and aluminum oxide. Substances such as water, alkali metals, and alkaline earth metals diffuse into the oxide semiconductor film 41. This can prevent the following:

[0175] In addition, an opening 62 is provided in the nitride insulating film 28 and the insulating film 29 at a position where the conductive film 44 overlaps. A transparent insulating film that is transparent to visible light is formed on the nitride insulating film 28 and the insulating film 29. The conductive film 45 has an opening and functions as a pixel electrode. At the opening 62, the conductive film 45 is electrically connected to the conductive film 44. At 58, the conductive film 45 overlaps with the metal oxide film 42. The overlapping portion sandwiching the oxide insulating film 28 and the insulating film 29 functions as a capacitance element 57. .

[0176] The capacitor 57 includes a metal oxide film 42 and a conductive film 45 which function as a pair of electrodes, and a dielectric The nitride insulating film 28 and the insulating film 29 functioning as a film are transparent to visible light. Therefore, the capacitor 57 is transparent to visible light, and the capacitance of the capacitor The aperture ratio of the pixel 55 can be increased compared to pixels having low translucency to visible light. This allows the capacitance required to obtain high image quality to be secured while minimizing light loss within the panel. Therefore, the power consumption of the semiconductor device can be reduced.

[0177] As described above, the insulating film 29 is not necessarily provided, but it is preferable to provide the insulating film 29 more than the nitride insulating film 28. The insulating film 29 using an insulating material having a lower relative dielectric constant than the nitride insulating film 28 is used as a dielectric film together with the nitride insulating film 28. By using the nitride insulating film 28, the dielectric constant of the dielectric film of the capacitance element 57 is increased. It is possible to adjust the value to a desired value without any need for adjustment.

[0178] On the conductive film 45, an alignment film 52 is provided.

[0179] A substrate 46 is provided so as to face the substrate 31. and a colored layer 48 that transmits visible light in a specific wavelength range. A resin film 50 is provided on the shielding film 47 and the colored layer 48. A conductive film 59 having a function as a common electrode is provided on the film 50. An alignment film 51 is provided on 59 .

[0180] Between the substrate 31 and the substrate 46, a liquid crystal layer is disposed so as to be sandwiched between the alignment film 52 and the alignment film 51. The liquid crystal element 60 includes a conductive film 45, a conductive film 59, and a liquid crystal layer 53 including a conductive film 59. and a liquid crystal layer 53 .

[0181] In addition, in FIG. 4 and FIG. 5, the liquid crystal driving method is TN (Twisted Nematic ) mode is used as an example of driving the liquid crystal, but FFS (Fringe Field Switching) mode, STN (Super Twisted Ne matic) mode, VA (Vertical Alignment) mode, MVA ( Multi-domain Vertical Alignment mode, IPS ( In-Plane Switching mode, OCB (Optically Com pensated birefringence mode, blue phase mode, TBA(T transverse bend alignment mode, VA-IPS mode, E CB(Electrically Controlled Birefringence) ) mode, FLC (Ferroelectric Liquid Crystal) mode AFLC (AntiFerroelectric Liquid Crystal) Mode, PDLC (Polymer Dispersed Liquid Crystal l) mode, PNLC (Polymer Network Liquid Crystal l) mode, guest host mode, ASV (Advanced Super View) It is also possible to apply a mode.

[0182] In the liquid crystal display device according to one embodiment of the present invention, the liquid crystal layer may include, for example, a thermotropic Liquid crystal materials classified as lyotropic or lyotropic liquid crystals can be used. The liquid crystal layer may be, for example, a nematic liquid crystal, a smectic liquid crystal, a cholesteric liquid crystal, or A liquid crystal material classified as a discotic liquid crystal can be used for the liquid crystal layer. For example, liquid crystal materials classified as ferroelectric liquid crystal or antiferroelectric liquid crystal can be used. Alternatively, the liquid crystal layer may be made of, for example, a main chain type polymer liquid crystal, a side chain type polymer liquid crystal, or By using liquid crystal materials classified as polymer liquid crystals such as composite polymer liquid crystals or low molecular weight liquid crystals, Alternatively, the liquid crystal layer may be, for example, a polymer dispersed liquid crystal (PDLC). A liquid crystal material may be used.

[0183] In addition, a liquid crystal exhibiting a blue phase without using an alignment film may be used in the liquid crystal layer. When the temperature of a cholesteric liquid crystal is increased, the cholesteric phase changes to the isotropic phase. The blue phase appears only in a narrow temperature range, so The temperature range is improved by adding chiral agents and UV-curable resins. The liquid crystal composition containing the above has a short response time of 1 msec or less and is optically isotropic, so that alignment is possible. This is preferable because no processing is required and the viewing angle dependency is small.

[0184] FIG. 5 shows a liquid crystal display device that displays color images by using color filters. As shown in the example, the liquid crystal display device according to one embodiment of the present invention has a plurality of LEDs emitting light of different hues. The light sources may be sequentially turned on to display a color image.

[0185] <Example 2 of sequential circuit configuration> Next, a configuration example of a sequential circuit according to one embodiment of the present invention, which is different from that in FIG. 1, will be described.

[0186] FIG. 7A illustrates a configuration example of a sequential circuit 10 according to one embodiment of the present invention. The sequential circuit 10 includes transistors 80 to 86. The signals RES, LIN, RIN, CK1, and CK2 are input to In addition, a high-level potential VDD and a low-level potential VSS are supplied to the sequential circuit 10. In accordance with the potential of the signal, transistors 80 to 8 6 are respectively selected to be conductive or non-conductive, so that the output terminals A and From the output terminal B, a signal including the potential VSS or the potential VDD is output.

[0187] Specifically, the gate of the transistor 80 is connected to a line through which the signal LIN is input. The transistor 80 has a source and a drain, one of which is connected to the output terminal A. The other end is connected to a wiring to which a potential VDD is applied. The transistor 81 has a source and a drain, one of which is connected to the output terminal B. One end is connected to the wiring to which the potential VSS is applied, and the other end is connected to the output terminal A. The gate of the transistor 82 is connected to a wiring to which a signal CK2 is input. The source and drain of the transistor 82 are connected to the source and drain of the transistor 83. The other end is connected to a wiring to which a potential VDD is applied. The gate of the transistor 83 is connected to a wiring to which a signal CK1 is input. One of the source and drain of 83 is connected to the output terminal B, and the other is connected to the transistor. The gate of transistor 84 is connected to one of the source and drain of transistor 82. The source of the transistor 84 is connected to a wiring to which a signal RIN is input. The drain is connected to the output terminal B at one end and to the potential VDD at the other end. The gate of the transistor 85 is connected to the line through which the signal LIN is input. The transistor 85 has a source and a drain, one of which is connected to the potential VSS. The other end is connected to the wiring connected to the output terminal B. The gate of the transistor 86 is connected to a wiring to which a signal RES is input. The source and drain of the MOSFET are connected to the output terminal B at one end and to the potential VDD at the other end. It is connected to the wiring.

[0188] The output terminal A of the sequential circuit 10 shown in FIG. 7A corresponds to the output terminal OUT, and the transistor 80 has the function of the transistor 12 in FIG. The transistor 81 functions as the transistor 13 in FIG. The transistors 82 to 86 function as the circuit 11 in FIG.

[0189] In one embodiment of the present invention, the transistors 80, 82, and 83 At least one of the transistors 84, 85, and 86 A pair of gate electrodes are electrically connected to each other and overlap with a semiconductor film sandwiched between them. In FIG. 7A, transistors 80, 82, and Transistor 83, transistor 84, transistor 85, and transistor 86 are all The figure illustrates an example of a pair of gate electrodes electrically connected to each other. By providing an electrode to one or all of the plurality of transistors, Even if a positive fixed charge is generated, the fixed charge creates a negative charge near the surface of the semiconductor film. This prevents the threshold voltage of the transistor from shifting in the negative direction. Therefore, the reliability of the sequential circuit 10 and, in turn, the reliability of the semiconductor device using the sequential circuit 10 can be improved. It can improve sexuality.

[0190] In addition, by electrically connecting a pair of gate electrodes, a single gate electrode is formed on only one of the pair of gate electrodes. Unlike the case where a constant potential is applied, the same potential is applied to a pair of gate electrodes, so The channel forming area is increased, and the drain current of the transistor can be increased. Therefore, the size of the transistor can be reduced while suppressing the decrease in the on-state current. Therefore, the area of ​​the sequential circuit 10 and, in turn, the area of ​​the driving circuit using the sequential circuit 10 can be reduced. This can be done.

[0191] In addition, by providing a pair of electrically connected gate electrodes, a depletion layer is unlikely to be formed in the semiconductor film. This makes it possible to improve the S value (subthreshold value) of the above transistor. do.

[0192] FIG. 8 shows a shift register configured by connecting the sequential circuit 10 shown in FIG. 7(A) in multiple stages. The gyroscope is shown as an example.

[0193] The shift register shown in FIG. 8 includes sequential circuits 10_1 to 10_y. The sequential circuits 10_1 to 10_y are the same as the sequential circuit 10 shown in FIG. However, in the sequential circuits 10_1 to 10_y shown in FIG. As the signal K1 and the signal CK2, any two of the signals CLK1 to CLK8 are The shift register shown in FIG. The buffer BUF has a number of buffers BUF indicated by BUF_y. The output signals from the sequential circuits 10_1 to 10_y are input to the BUF_y. Furthermore, the shift register shown in FIG. 8 is a sequential circuit 10_D used as a dummy. The output signal from the sequential circuit 10_DUM is The data is input to the buffer BUF_DUM.

[0194] Specifically, in the sequential circuit 10_8m+1, the signal CLK is used as the signal CK1 and the signal CK2. In the sequential circuit 10_8m+2, the signal CK1 As the signal CK2, the signal CLK3 and the signal CLK4 are used, respectively. In the path 10_8m+3, the signals CLK8 and CLK In the sequential circuit 10_8m+4, the signals CK1 and CK2 are used. The signals CLK5 and CLK6 are used for the sequential circuit 10_8m+5. In this example, the signals CLK2 and CLK3 are used as the signals CK1 and CK2, respectively. In the sequential circuit 10_8m+6, the signal CLK is used as the signal CK1 and the signal CK2. In the sequential circuit 10_8m+7, the signal CK1 As the signal CK1, the signal CLK4 and the signal CLK5 are used, respectively. In the path 10_8m, the signals CLK1 and CLK2 are input as the signals CK1 and CK2. However, 8m to 8m+7 indicate that the total number of sequential circuits 10 is y. Let be any natural number that satisfies.

[0195] In the sequential circuit 10_DUM, the signals used as the signals CK1 and CK2 are For example, if there is a sequential circuit 10_8m+1 in the previous stage, In this case, the sequential circuit 10_DUM uses signals CLK3 and CLK4 as signals CK1 and CK2. and signal CLK4 are used. When a sequential circuit 10_8m+2 is present in the preceding stage, In the sequential circuit 10_DUM, the signals CK1 and CK2 are the signal CLK8 and the signal C LK1 is used. If there is a sequential circuit 10_8m+3 in the previous stage, In 10_DUM, the signals CLK5 and CLK6 are used as the signals CK1 and CK2. When the sequential circuit 10_8m+4 exists in the previous stage, the sequential circuit 10_D In the UM, the signals CLK2 and CLK3 are used as the signals CK1 and CK2, respectively. When the sequential circuit 10_8m+5 exists in the previous stage, the sequential circuit 10_DUM As the signals CK1 and CK2, the signals CLK7 and CLK8 are used, respectively. When the sequential circuit 10_8m+6 exists in the previous stage, the sequential circuit 10_DUM receives the signal C The signals CLK4 and CLK5 are used as the signals K1 and CK2, respectively. When a sequential circuit 10_8m+7 exists in the sequential circuit 10_DUM, the signals CK1 and The signal CLK1 and the signal CLK2 are used as the signal CK2. When the circuit 10_8m exists, the sequential circuit 10_DUM has signals CK1 and CK2. For this purpose, signals CLK6 and CLK7 are used, respectively.

[0196] In the shift register shown in FIG. 8, a sequential circuit 10_j (j is a natural number equal to or smaller than y) The positions of the wiring connected to the 1st and 2nd terminals are shown in Fig. 7(B). In this way, in the sequential circuit 10_j, the output of the preceding sequential circuit 10_j-1 is used as the signal LIN. The output terminal GOUT5(j -2) The output signal from +5 is used. However, in the first stage sequential circuit 10_1, the signal As LIN, the signal SP is used.

[0197] In the sequential circuit 10_j, the signal RIN is input to the output terminal of the subsequent sequential circuit 10_j+1. The output terminal GOUT5j+2 of the buffer BUF connected to the output terminal A and the output terminal B However, in the y-th stage sequential circuit 10_y, the output signal from the sequential circuit 10_D The output terminal of the buffer BUF_DUM connected to the output terminal A and the output terminal B of UM The output signal from the output OUT2 is used.

[0198] In addition, in the shift register shown in FIG. 8, the positions of the wirings connected to the buffer BUF are As shown in FIG. 9(A), the buffer BUF stores sequential In addition to the output signals from output terminals A and B of circuit 10, signals CK1 to CK5 The buffer BUF receives the signals CK1 to CK5 as the signals CLK. Five of the signals CLK1 through CLK8 are used.

[0199] Specifically, in the buffer BUF_8m+1, the signals CK1 to CK5 are the signal CL In the buffer BUF_8m+2, the signal C As signals CK1 to CK5, signals CLK6 to CLK8, and signals CLK1 and C In the buffer BUF_8m+3, the signals CK1 to LK2 are used. As CK5, signals CLK3 to CLK7 are used. In the case of _8m+4, the signals CK1 to CK5 are the signal CLK8 and the signals CLK1 to In the buffer BUF_8m+5, the signals CK1 and CLK4 are used. As the clock signal CK5, the signals CLK5 to CLK8 and the signal CLK1 are used. In the buffer BUF_8m+6, the signals CK1 to CK5 are the signal CL In the buffer BUF_8m+7, the signal C As signals CLK1 to CK5, signals CLK7 and CLK8, and signals CLK1 to C In the buffer BUF_8m, the signals CK1 to CK5 are used. As the clocks, signals CLK4 to CLK8 are used, respectively.

[0200] In the shift register shown in FIG. 8, each of the arrays connected to the buffer BUF_DUM The position of the line is shown in FIG. 9(B). As shown in FIG. 9(B), the buffer BUF_D In addition to the output signals from the output terminals A and B of the sequential circuit 10, the UM also receives the signal CK 1 and signal CK2 are input to the buffer BUF_DUM. As CK2, any two of the signals CLK1 to CLK8 are used. do.

[0201] In the buffer BUF_DUM, the signals used as the signals CK1 and CK2 are For example, if there is a buffer BUF_8m+1 in the previous stage, In this case, the buffer BUF_DUM receives the signal CLK6 as the signal CK1 and the signal CK2. and signal CLK7 are used, respectively. In this case, the buffer BUF_DUM receives the signals CLK3 and CLK4 as the signals CK1 and CK2. When a buffer BUF_8m+3 is present in the previous stage, In the buffer BUF_DUM, the signal CLK8 and the signal CLK1 are used as the signal CK1 and the signal CK2. If there is a buffer BUF_8m+4 in the previous stage, In the BUF_DUM, the signals CK1 and CK2 are the signals CLK5 and CL If there is a buffer BUF_8m+5 in the previous stage, the buffer In BUF_DUM, the signals CK1 and CK2 are the signals CLK2 and CLK3. If there is a buffer BUF_8m+6 in the previous stage, In F_DUM, the signals CLK7 and CLK8 are used as the signals CK1 and CK2. If there is a buffer BUF_8m+7 in the previous stage, the buffer BUF_ In DUM, the signals CLK4 and CLK5 are used as the signals CK1 and CK2, respectively. If there is a buffer BUF_8m in the previous stage, it is used with the buffer BUF_DUM. In this example, the signals CLK1 and CLK2 are used as the signals CK1 and CK2, respectively. can be.

[0202] The buffers BUF_1 to BUF_y are connected to output terminals OUT1 to OUT All the outputs of the buffers BUF_1 to BUF_y are The output signals GOUT1 to GOUTy are output from the input terminals OUT1 to OUT5. The buffer BUF_DUM outputs the DUMOUT1 and DUMOUT2 outputs. Has child DUMOUT2.

[0203] FIG. 9C shows an example of a more specific configuration of the buffer BUF. The BUF has five buffers 90. Each buffer 90 is connected to the output of the sequential circuit 10. In addition to the output signal from terminal A and output terminal B, any one of signals CK1 to CK5 The output terminals of the five buffers 90 are connected to the buffers 91 and 92. These correspond to the output terminals OUT1 to OUT5 of BUF, respectively.

[0204] In addition, in FIG. 8, FIG. 9(A) and FIG. 9(C), the buffer BUF includes five buffers 90. However, the number of buffers 90 in the buffer BUF may be any number other than five. The number of buffers 90 included in the buffer BUF may be a number or a single number. The more the number of sequential circuits 10 in the shift register, the smaller the number of sequential circuits 10. The area of ​​the driver circuit having the shift register is reduced, realizing a narrower frame for the semiconductor display device. It is possible.

[0205] FIG. 9(D) shows an example of a more specific configuration of the buffer BUF_DUM. The buffer BUF_DUM shown in D) has two buffers 90. In addition to the output signals from the output terminals A and B of the sequential circuit 10_DUM, the signal C Either one of the signals K1 and CK2 is input. The output terminals of the buffer BUF_DUM are the output terminal OUT1 and the output terminal OUT 2. In addition, in FIG. 8, FIG. 9(B) and FIG. 9(D), the buffer BUF In the example shown, the buffer BUF_DU The number of buffers 90 that M has may be a number other than two or may be a single number.

[0206] FIG. 10 shows a more specific example of the configuration of the buffer 90. The buffer 90 shown in FIG. The transistor 91 has a gate connected to a potential V The transistor 91 is connected to a wiring to which a DD is applied. One of the inputs is connected to the output terminal B of the sequential circuit 10_DUM, and the source and drain The other end of the transistor 92 is connected to the gate of the transistor 92. One of the drains is connected to one of the output terminals OUT1 to OUT5 of the buffer 90. The source and drain of the The other is that any one of the signals CK1 to CK5 (shown as signal CK in FIG. 10) The gate of the transistor 93 is connected to the input wiring. The transistor 93 is connected to the output terminal A of the M. One of the source and drain terminals is connected to a wiring to which a potential VSS is applied, and the other of the source and drain terminals is connected to an output terminal. One of the output terminals OUT1 to OUT5 (in FIG. 10, the output terminal OUT The NI 8116 is connected to the NI 8116-1.

[0207] In one aspect of the present invention, a transistor in which a signal CK is applied to the other of the source and the drain is A pair of transistors 92 are electrically connected and overlapped with a semiconductor film sandwiched therebetween. A pair of electrically connected gate electrodes is defined as a transistor 9 By providing the element at 2, even if a positive fixed charge occurs near the surface of the element substrate, the fixed charge does not This prevents negative charges from being generated near the surface of the semiconductor film, and the threshold voltage of the transistor 92 is Therefore, the buffer BUF and the In other words, the reliability of the semiconductor device using the buffer BUF can be improved.

[0208] In addition, by electrically connecting a pair of gate electrodes, a single gate electrode is formed on only one of the pair of gate electrodes. Unlike the case where a constant potential is applied, the same potential is applied to a pair of gate electrodes, so As a result, the drain current of the transistor 92 can be increased. Therefore, the size of the transistor 92 can be reduced while suppressing the decrease in the on-state current. Therefore, the area of ​​the buffer BUF and, in turn, the area of ​​the driver circuit using the buffer BUF can be reduced. In particular, the transistor 92 provided on the output side of the buffer BUF has a transistor Since a current supply capability larger than that of the transistor 91 is required, the transistor 92 is By having a pair of gate electrodes as described above, when the same configuration is applied to transistor 91, In this case, the effect of reducing the area of ​​the buffer BUF or the driver circuit is large. .

[0209] In addition, by providing a pair of electrically connected gate electrodes, a depletion layer is unlikely to be formed in the semiconductor film. Therefore, the S value (subthreshold value) of the transistor 92 can be improved. do.

[0210] Semiconductor Films In addition, impurities such as moisture and hydrogen, which act as electron donors, are reduced, and the acid The reduced electron vacancies result in a highly purified oxide semiconductor. Since the source of carrier generation is small, the i-type (intrinsic semiconductor) Therefore, a highly purified oxide semiconductor can be obtained. A transistor having a channel formation region in a film has a significantly small off-state current and is highly reliable. In addition, a transistor in which a channel formation region is formed in the oxide semiconductor film has a threshold voltage The electrical characteristics tend to be such that the applied voltage becomes positive (also called normally-off characteristics).

[0211] Specifically, the present invention relates to an on-state transistor having a channel formation region in a highly purified oxide semiconductor film. The small fringe current can be proven by various experiments. For example, 0 6 Even with a device with a channel length of 10 μm, the voltage between the source and drain electrodes is In the drain voltage range of 1V to 10V, the off-state current was measured by the semiconductor parameter analyzer. Below the riser measurement limit, i.e. 1×10 -13 It is possible to obtain a characteristic of A or less. In this case, the off-state current normalized by the transistor channel width is 100zA / μm or less. In addition, by connecting the capacitance element and the transistor, The off-state current is measured using a circuit that controls the charge flowing out of the capacitor with the transistor. In the measurement, a highly purified oxide semiconductor film was used as a channel of the transistor. The on / off state of the transistor is determined based on the change in the charge amount per unit time of the capacitance element. The current was measured. As a result, the voltage between the source and drain electrodes of the transistor was 3V. It was found that an even smaller off-current of several tens of yA / μm can be obtained in the case of In addition, a transistor in which a highly purified oxide semiconductor film is used for a channel formation region has an off-state current The current is significantly smaller than that of a transistor using crystalline silicon.

[0212] In the case where an oxide semiconductor film is used as the semiconductor film, the oxide semiconductor film should be at least It is preferable that the oxide semiconductor contains indium (In) or zinc (Zn). As a stabilizer to reduce the variation in the electrical characteristics of transistors using In addition to these, it is preferable to have gallium (Ga). It is preferable to use hafnium (Hf) as a stabilizer. It is preferable that the stabilizer contains aluminum (Al). It is also preferable that zirconium (Zr) is contained as a stabilizer.

[0213] Among oxide semiconductors, In-Ga-Zn oxides and In-Sn-Zn oxides are carbon Unlike silicon nitride, gallium nitride, or gallium oxide, sputtering and wet deposition methods This makes it possible to create transistors with excellent electrical characteristics, and is also suitable for mass production. Also, unlike silicon carbide, gallium nitride, or gallium oxide, The In-Ga-Zn oxide is used to form a transistor having excellent electrical characteristics on a glass substrate. It is also possible to manufacture larger substrates.

[0214] Other stabilizers include the lanthanides lanthanum (La) and cerium ( Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), hol Ho, Erbium, Thulium, Ytterbium, Ru It may contain one or more of the elements tetraethium (Lu).

[0215] For example, oxide semiconductors include indium oxide, gallium oxide, tin oxide, zinc oxide, and I n-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, S n-Mg oxide, In-Mg oxide, In-Ga oxide, In-Ga-Zn oxide (also written as IGZO), In-Al-Zn oxide, In-Sn-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, Sn-Al-Zn oxide, I n-Hf-Zn oxide, In-La-Zn oxide, In-Pr-Zn oxide, In -Nd-Zn oxide, In-Ce-Zn oxide, In-Sm-Zn oxide, In- Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide, In-D Y-Zn oxide, In-Ho-Zn oxide, In-Er-Zn oxide, In-Tm -Zn-based oxide, In-Yb-Zn-based oxide, In-Lu-Zn-based oxide, In-Sn- Ga-Zn oxide, In-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide In-Sn-Al-Zn oxides, In-Sn-Hf-Zn oxides, In-Hf- Al-Zn based oxides can be used.

[0216] For example, In-Ga-Zn oxide means an oxide containing In, Ga, and Zn. The ratio of In, Ga, and Zn is not important. In addition, metal elements other than In, Ga, and Zn In-Ga-Zn oxides have a sufficiently high resistance when no electric field is present, and therefore, The flow can be made sufficiently small and the mobility is also high.

[0217] For example, high mobility can be obtained relatively easily with In-Sn-Zn oxides. Therefore, in the case of In-Ga-Zn oxides, the mobility can be increased by reducing the defect density in the bulk. It can be done.

[0218] The structure of the oxide semiconductor film will be described below.

[0219] Oxide semiconductor films are roughly classified into single-crystal oxide semiconductor films and non-single-crystal oxide semiconductor films. The single crystal oxide semiconductor film includes an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, a polycrystalline oxide semiconductor film, and a polycrystalline oxide semiconductor film. These include semiconductor films and CAAC-OS films.

[0220] The amorphous oxide semiconductor film has an irregular atomic arrangement in the film and is an oxide film that does not have a crystalline component. The film is a compound semiconductor film. It does not have any crystalline parts even in a microscopic area, and the entire film has a completely amorphous structure. A typical example is an oxide semiconductor film.

[0221] The microcrystalline oxide semiconductor film is, for example, a microcrystal having a size of 1 nm or more and less than 10 nm (nanocrystal). Therefore, the microcrystalline oxide semiconductor film has a lower atomic number than the amorphous oxide semiconductor film. Therefore, the microcrystalline oxide semiconductor film has a higher molecular weight than the amorphous oxide semiconductor film. Also, the defect level density is low.

[0222] The CAAC-OS film is one of the oxide semiconductor films that has multiple crystal parts. The crystal part is so large that it fits inside a cube with one side less than 100 nm. The crystals contained in the S film are in the form of cubes with sides of less than 10 nm, 5 nm, or 3 nm. The CAAC-OS film has a smaller defect density than a microcrystalline oxide semiconductor film. The CAAC-OS film is characterized by a low density of recessed states. Observe using a transmission electron microscope. A clear boundary between the crystals, i.e., the grain boundary, was confirmed. Therefore, the CAAC-OS film has a low electron mobility due to the grain boundaries. It can be said that a decline is unlikely to occur.

[0223] The CAAC-OS film was observed by TEM from a direction roughly parallel to the sample surface (cross-sectional TEM observation ) It can be confirmed that the metal atoms are arranged in layers in the crystal part. Each layer has a surface on which the CAAC-OS film is formed (also called a surface on which the film is formed) or a top surface having irregularities. The shape of the CAAC-OS film reflects this, and the CAAC-OS film is aligned parallel to the surface on which the film is formed or the top surface.

[0224] In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. refers to the state in which two straight lines are arranged at an angle between 80° and 100°. This includes cases where the angle is between 85° and 95°.

[0225] On the other hand, the CAAC-OS film was observed by TEM from a direction roughly perpendicular to the sample surface (planar TEM). When the metal atoms were observed, they were found to be arranged in triangular or hexagonal shapes in the crystals. However, no regularity was observed in the arrangement of metal atoms between different crystal parts. stomach.

[0226] Cross-sectional and planar TEM observations revealed that the crystals in the CAAC-OS film had an orientation. It is clear that there are

[0227] X-ray diffraction (XRD) was performed on the CAAC-OS film. For example, a CAAC-OS film with InGaZnO4 crystals was In the out-of-plane analysis, a peak was observed at a diffraction angle (2θ) of approximately 31°. This peak is attributed to the (009) plane of the InGaZnO4 crystal. This indicates that the crystals in the CAAC-OS film have a c-axis orientation, and the c-axis is generally aligned on the surface on which the film is formed or on the upper surface. It can be seen that it is oriented in a substantially vertical direction.

[0228] On the other hand, in-plane X-ray irradiation is performed on the CAAC-OS film in a direction perpendicular to the c-axis. In the analysis by the ane method, a peak may appear at 2θ around 56°. This peak is This is attributed to the (110) plane of the InGaZnO4 crystal. In the case of a semiconductor film, 2θ is fixed at around 56°, and the normal vector of the sample surface is set as the axis (φ axis). When the sample is rotated and analyzed (φ scan), the crystal plane equivalent to the (110) plane is In contrast, in the case of the CAAC-OS film, the 2θ is set to 5 Even when the φ is fixed at around 6° and scanned, no clear peak appears.

[0229] From the above, it is considered that the a-axis and b-axis orientations are inconsistent between different crystal regions in the CAAC-OS film. The crystal is regular, but has a c-axis orientation, and the c-axis is parallel to the normal vector of the surface on which the crystal is formed or the upper surface. Therefore, the layered arrangement confirmed by the cross-sectional TEM observation mentioned above is consistent with the above. Each layer of aligned metal atoms is a plane parallel to the ab plane of the crystal.

[0230] The crystalline portion is formed when the CAAC-OS film is formed or when a crystallization process such as a heat treatment is performed. As described above, the c-axis of the crystal is aligned along the surface on which the CAAC-OS film is formed or along the surface on which the CAAC-OS film is formed. The orientation of the CAAC-OS film is parallel to the normal vector of the top surface. When the shape of the CAAC-OS film is changed by etching, the c-axis of the crystal is aligned with the surface on which the CAAC-OS film is formed. Or it may not be parallel to the normal vector of the upper surface.

[0231] In addition, the degree of crystallinity in the CAAC-OS film may not be uniform. When the crystal part of the CAAC-OS film is formed by crystal growth from the vicinity of the top surface, The adjacent regions may have a higher degree of crystallinity than the regions adjacent the surface to be formed. When impurities are added to a C-OS film, the crystallinity of the region to which the impurities are added changes, resulting in partial In some cases, regions of differing crystallinity may be formed.

[0232] In addition, the out-of-plane method of CAAC-OS film with InGaZnO4 crystals In the analysis by , in addition to the peak at 2θ near 31°, a peak also appeared at 2θ near 36°. The peak at 2θ of around 36° may be due to the c-axis orientation in some parts of the CAAC-OS film. The CAAC-OS film contains crystals that do not have a 2θ of around 31°. It is preferred that the spectrum exhibits a peak and does not exhibit a peak at 2θ of around 36°.

[0233] The electrical characteristics of transistors using CAAC-OS films change when irradiated with visible or ultraviolet light. Therefore, the transistor has high reliability.

[0234] The oxide semiconductor film may be, for example, an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, or a CA The AC-OS film may be a laminate film having two or more kinds of films.

[0235] In addition, the following conditions are preferably applied to form the CAAC-OS film.

[0236] By reducing the amount of impurities mixed in during film formation, it is possible to prevent the crystal state from being destroyed by impurities. For example, the concentration of impurities (hydrogen, water, carbon dioxide, nitrogen, etc.) present in the processing chamber is In addition, the impurity concentration in the deposition gas may be reduced. A deposition gas having a temperature of -80°C or lower, preferably -100°C or lower, is used.

[0237] In addition, by increasing the substrate heating temperature during film formation, the migration of sputtered particles after they reach the substrate is reduced. Specifically, the substrate heating temperature is set to 100° C. or higher and 740° C. or lower, preferably The deposition temperature is set to 200°C or higher and 500°C or lower. When plate- or pellet-shaped sputtered particles reach the substrate, they migrate on the substrate. Sputtering occurs and the flat surface of the sputtered particle adheres to the substrate.

[0238] In addition, by increasing the oxygen ratio in the deposition gas and optimizing the power, plasma damage during deposition is reduced. The oxygen ratio in the deposition gas is preferably 30% by volume or more, and more preferably 100% by volume or more. The product is %.

[0239] As an example of the target, an In-Ga-Zn oxide target will be described below.

[0240] InO X powder, GaO Y Powder and ZnO Z The powders are mixed in a specified molar ratio and pressurized. By heat treatment at a temperature between 1000 and 1500℃, polycrystalline In-Ga The target is a Zn-based oxide target. X, Y, and Z are any positive numbers. The molar ratio of the specified amount is, for example, InO X powder, GaO Y Powder and ZnO Z The powder is mixed in a ratio of 2:1: 3, 2:2:1, 8:4:3, 3:1:1, 1:1:1, 4:2:3 or 3:1:2 The type of powder and the molar ratio of the powder to be mixed depend on the target to be produced. Please change it as appropriate.

[0241] Note that alkali metals are not elements that constitute an oxide semiconductor and are therefore considered impurities. In particular, lithium-earth metals are impurities when they are not elements constituting an oxide semiconductor. Among the alkali metals, Na is preferable when the insulating film in contact with the oxide semiconductor film is an oxide. Diffusion into the insulating film + In addition, Na is an element that is contained in the oxide semiconductor film. It breaks the bond between the metal and oxygen that make up the conductor, or interrupts that bond. As a result, For example, the threshold voltage shifts in the negative direction, resulting in a normally-on state and a decrease in mobility. This causes degradation of the electrical characteristics of the transistors, such as deterioration of the electrical characteristics of the transistors, and also causes variations in the characteristics. Specifically, the measured Na concentration by secondary ion mass spectrometry was 5×10 16 / cm 3 below , preferably 1 x 10 16 / cm 3 More preferably, 1×10 15 / cm 3 The following Similarly, the measured Li concentration is 5×10 15 / cm 3 Below, preferably 1×1 0 15 / cm 3 Similarly, the measured value of K concentration should be 5×10 15 / cm 3 Below Lower, preferably 1×10 15 / cm 3 The following should be used.

[0242] In addition, when a metal oxide containing indium is used, the bond energy with oxygen is Silicon and carbon, which are larger than indium, break the bond between indium and oxygen, creating an oxygen vacancy. Therefore, when silicon or carbon is mixed into the oxide semiconductor film, As with alkali and alkaline earth metals, degradation of the electrical characteristics of transistors occurs. Therefore, it is preferable that the concentrations of silicon and carbon in the oxide semiconductor film be low. Specifically, the measured values ​​of C concentration or Si concentration by secondary ion mass spectrometry is 1 x 10 18 / cm 3 With the above configuration, the electrical characteristics of the transistor are preferably as follows. This makes it possible to prevent deterioration of the electrical conductivity of the semiconductor device, thereby improving the reliability of the semiconductor device.

[0243] In addition, depending on the conductive material used for the source electrode and the drain electrode, The metal in the drain electrode may extract oxygen from the oxide semiconductor film. The region of the nitride semiconductor film in contact with the source electrode and the drain electrode is depleted due to the formation of oxygen vacancies. It is made n-type.

[0244] The n-type region functions as a source region or a drain region, so the oxide semiconductor The contact resistance between the film and the source and drain electrodes can be reduced. Therefore, the formation of an n-type region increases the mobility and on-current of the transistor. This makes it possible to realize high-speed operation of a semiconductor device using transistors. This can be done.

[0245] The extraction of oxygen by the metal in the source and drain electrodes This can occur when forming the drain electrode by sputtering or the like, and can occur when forming the source electrode and drain electrode. This can also occur due to a heat treatment carried out after the formation of the rain electrode.

[0246] In addition, the region to be made n-type is made of a conductive material that easily bonds with oxygen as the source electrode and the drain electrode. The conductive material is, for example, Al, C. Examples of these include R, Cu, Ta, Ti, Mo, and W.

[0247] In addition, the oxide semiconductor film is not limited to being composed of a single metal oxide film, but may be composed of a stack of metal oxide films. It may be composed of a plurality of metal oxide films. For example, the first to third metal oxide films are formed in order. In the case of a semiconductor film stacked in a layered manner, the first metal oxide film and the third metal oxide film are The metal oxide film has at least one metal element as a component thereof, and has a conduction band below The edge energy is 0.05 eV or more, 0.07 eV or more, 0. 1 eV or more, or 0.15 eV or more, and 2 eV or less, 1 eV or less, 0.5 eV or less The second metal oxide film is an oxide film with a potential of 0.4 eV or less, close to the vacuum level. It is preferable that at least indium is contained since the carrier mobility is increased.

[0248] When a transistor has a semiconductor film having the above structure, a voltage is applied to a gate electrode. When an electric field is applied to the semiconductor film, the second gold layer in the semiconductor film, which has a lower energy at the bottom of the conduction band, A channel region is formed in the second metal oxide film. The third metal oxide film is provided between the first and second gate insulating films. A channel region can be formed in the metal oxide film of 2.

[0249] The third metal oxide film contains at least one of the metal elements constituting the second metal oxide film. Since the second metal oxide film and the third metal oxide film contain Therefore, the movement of carriers is not easily hindered at the interface. The field effect mobility of the transistor is increased.

[0250] In addition, when an interface state is formed at the interface between the second metal oxide film and the first metal oxide film, Since a channel region is also formed in the neighboring region, the threshold voltage of the transistor changes. However, the first metal oxide film contains at least one of the metal elements constituting the second metal oxide film. Since both of them contain one of these elements, they are formed at the interface between the second metal oxide film and the first metal oxide film. Therefore, the above-mentioned configuration reduces the threshold voltage of the transistor and the like. The variation in electrical characteristics can be reduced.

[0251] In addition, the presence of impurities between the metal oxide films causes carrier flow at the interface between the films. A plurality of oxide semiconductor films are stacked to prevent the formation of an interfering interface state. If impurities exist between the layers of the laminated metal oxide film, the metal oxide film may be The continuity of the energy at the bottom of the conduction band at the interface is lost, and the carriers are transported near the interface. The impurities between the films are either picked up or disappear due to recombination. By reducing the amount of the metal oxide film, it is possible to form a plurality of metal oxide films each having at least one metal as a main component. In this case, the energy of the conduction band minimum is higher than that of the other films. In this case, a state in which the well structure changes continuously (a U-shaped well structure) is easily formed.

[0252] To form continuous junctions, a multi-chamber deposition system equipped with a load lock chamber is required. (Sputtering equipment) is used to continuously stack each film without exposing it to the air. Each chamber in the sputtering equipment must be free of impurities for oxide semiconductors. In order to remove as much water as possible, a vacuum pump of the adsorption type like a cryopump is used. High vacuum pumping (5×10 -7 Pa~1×10 -4 It is preferable to set the temperature to about 10 Pa. Alternatively, a turbomolecular pump and cold trap can be combined to vent the gas from the exhaust system to the chamber. It is preferable to prevent gas from flowing back into the tank.

[0253] In order to obtain a high-purity intrinsic oxide semiconductor, it is not enough to evacuate each chamber to a high vacuum. In addition, it is also important to increase the purity of the gas used in sputtering. The dew point of gas or argon gas is -40°C or less, preferably -80°C or less, more preferably - By keeping the temperature at 100°C or less and using highly purified gas, moisture and other substances are prevented from being absorbed into the oxide semiconductor film. Specifically, the second metal oxide film is In- In the case of M-Zn oxide (M is Ga, Y, Zr, La, Ce, or Nd), the second metal In the target used for depositing the oxide film, the atomic ratio of metal elements is In:M: If Zn=x1:y1:z1, 、 x1 / y1 is between 1 / 3 and 6, and between 1 and 6 or less, and z1 / y1 is preferably 1 / 3 or more and 6 or less, and more preferably 1 or more and 6 or less. In addition, by setting z1 / y1 to 1 or more and 6 or less, it is possible to form a CA AC-OS film is easily formed. A typical example of the atomic ratio of the metal elements in the target is , In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=3 :1:2 etc.

[0254] Specifically, the first metal oxide film and the third metal oxide film are In-M-Zn oxide (M is G a, Y, Zr, La, Ce, or Nd), the first metal oxide film, the third metal oxide film In the target used to deposit the metal film, the atomic ratio of metal elements is In:M:Zn If we set =x2:y2:z2 、 x2 / y2 <x1 / y1であって、z2 / y2は、1 / 3 It is preferable that z2 / y2 is 1 or more and 6 or less, and more preferably 1 or more and 6 or less. By setting the following, the CAAC-OS film can be used as the first metal oxide film and the third metal oxide film. A typical example of the atomic ratio of the target metal elements is In:M:Z. n=1:3:2, In:M:Zn=1:3:4, In:M:Zn=1:3:6, In:M :Zn=1:3:8 etc.

[0255] The thickness of the first metal oxide film and the third metal oxide film is 3 nm or more and 100 nm or less. The thickness of the second metal oxide film is preferably 3 nm or more and 50 nm or less. m is from 0.01 to 200 nm, preferably from 0.01 to 200 nm, more preferably from 0.01 to 200 nm, and even more preferably from 0.01 to 200 nm. Between 3nm and 50nm.

[0256] In the three-layered semiconductor film, the first metal oxide film, the second metal oxide film, and the third metal oxide film are amorphous or The second metal oxide on which the channel region is formed may be either amorphous or crystalline. The crystalline nature of the material film provides stable electrical characteristics to the transistor. Therefore, the second metal oxide film is preferably crystalline.

[0257] Note that the channel formation region is a region of the semiconductor film of a transistor that overlaps with a gate electrode. The channel region is the region sandwiched between the source electrode and the drain electrode. This refers to the region in the core formation region through which current mainly flows.

[0258] For example, the first metal oxide film and the third metal oxide film are formed by a sputtering method. When an In-Ga-Zn oxide film formed by the above method is used, the first metal oxide film and the third metal oxide film are The In-Ga-Zn oxide (In:Ga:Zn=1:3:2 [atomic number The film forming conditions are, for example, a film forming gas containing The gas was argon at 30 sccm and oxygen at 15 sccm, the pressure was 0.4 Pa, and the substrate temperature was The temperature is set to 200°C and the DC power is set to 0.5kW.

[0259] In addition, when the second metal oxide film is a CAAC-OS film, the second metal oxide film is formed by is an In-Ga-Zn oxide (In:Ga:Zn=1:1:1 [atomic ratio]), It is preferable to use a target containing a polycrystalline In-Ga-Zn oxide. For example, argon gas at 30 sccm and oxygen gas at 15 sccm are used as the deposition gas. The pressure was set to 0.4 Pa, the substrate temperature to 300° C., and the DC power to 0.5 kW. Cut.

[0260] Note that the transistor may have a structure in which the end portion of the semiconductor film is inclined. The end of the membrane may have a rounded structure.

[0261] In addition, when a semiconductor film having a plurality of stacked metal oxide films is used for a transistor, In the above structure, the regions in contact with the source electrode and the drain electrode may be n-type. The present invention provides a semiconductor device using a transistor, which has improved mobility and on-current. Furthermore, a semiconductor having a plurality of laminated metal oxide films can be used. When the conductive film is used in a transistor, the region to be made n-type is the second gold layer which becomes the channel region. The fact that the metal oxide film is reached increases the mobility and on-current of the transistor, and This is more preferable in terms of achieving higher speed operation of the device.

[0262] <Production Method> Next, a method for manufacturing a semiconductor display device according to one embodiment of the present invention will be described with reference to a liquid crystal display device. An example of this will be described with reference to Figs. 11 to 14. 5 and the transistor 56 of the driver circuit shown in FIG. A method for manufacturing an element substrate having a resistor 20 will be described.

[0263] As shown in FIG. 11(A), a conductive film is formed on a substrate 31, and then the conductive film is etched. The conductive film 21 and the conductive film 40 are formed by processing (patterning) the shape by the above-mentioned methods. .

[0264] The substrate 31 is preferably a substrate having a heat resistance sufficient to withstand the subsequent manufacturing steps. For example, a glass substrate, a quartz substrate, a ceramic substrate, a sapphire substrate, etc. may be used.

[0265] The conductive film 21 and the conductive film 40 may be made of aluminum, titanium, chromium, cobalt, nickel, etc. Ru, copper, yttrium, zirconium, molybdenum, ruthenium, silver, tantalum and tantalum It is preferable to use a film made of a conductive material containing one or more types of tin. For example, the conductive film 21 and the conductive film 40 may be formed by laminating a copper film on a tungsten nitride film. A conductive film or a single-layer tungsten film can be used. In this embodiment, the conductive film 21 The conductive film 40 is a tungsten film having a thickness of 200 nm.

[0266] Next, as shown in FIG. 11(B), an insulating film 2 is formed so as to cover the conductive film 21 and the conductive film 40. After forming the insulating film 22, the oxide semiconductor film 23, the oxide semiconductor film 41, and the oxide The semiconductor film 42a is formed. Note that the oxide semiconductor film 23 is formed in a position overlapping with the conductive film 21. The oxide semiconductor film 41 is formed at a position overlapping with the conductive film 40 .

[0267] The insulating film 22 may be made of aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, Silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, dioxide One or more of: lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide The insulating film containing the insulating film may be used as a single layer or a stacked layer.

[0268] In this specification, an oxynitride is a material having a composition in which the oxygen content is higher than that of nitrogen. Nitrogen oxide refers to a material that contains more nitrogen than oxygen in its composition. Point.

[0269] For example, when the insulating film 22 has a two-layer structure, the first layer is a silicon nitride film and the second layer is a silicon oxide film. The second silicon oxide film can be a silicon oxynitride film. In addition, the first silicon nitride film can be a silicon nitride oxide film. A silicon nitride film with a thickness of 400 nm and a silicon oxynitride film with a thickness of 50 nm are laminated in this order to form an insulating film. It is used as the veneer 22.

[0270] It is preferable to use a silicon oxide film having a small defect density. The g value in ESR (Electron Spin Resonance) is 2.0 The spin density of the spins originating from the 01 signal is 3×10 17 spins / cm 3 The following are the preferred Or 5×10 16 spins / cm 3 The silicon oxide film used is as follows: It is preferable to use a silicon oxide film having an excess of oxygen. A silicon nitride film is preferably used because of the presence of hydrogen and ammonia. A silicon nitride film with low emission is used. The amount of hydrogen and ammonia released is measured by TDS (Therm Thermal Desorption Spectroscopy (TDA) analysis It is sufficient to measure it.

[0271] The oxide semiconductor film 23, the oxide semiconductor film 41, and the oxide semiconductor film 42a are each formed of an oxide semiconductor. The oxide semiconductor film 23 and the oxide semiconductor film 41 may be formed of an oxide semiconductor film. When a large amount of hydrogen is contained in the oxide semiconductor film, the hydrogen is bonded to the oxide semiconductor. Some of them become donors and generate electrons as carriers. This causes transistor 2 0 and the threshold voltage of the transistor 56 is shifted in the negative direction. After the oxide semiconductor film is formed, a dehydration treatment (dehydrogenation treatment) is performed to convert the oxide semiconductor film into It is preferable to remove hydrogen or moisture to minimize the amount of impurities contained.

[0272] In this embodiment, the atomic ratio of metal elements is In:Ga:Zn=3:1:2. A 35 nm thick In-Ga-Zn oxide semiconductor was formed using a target consisting of The conductor film is an oxide semiconductor film 23, an oxide semiconductor film 41, and an oxide semiconductor film 42a. Use.

[0273] The oxide semiconductor film 23, the oxide semiconductor film 41, and the oxide semiconductor film 42a each have a thickness of 1 nm. More preferably, the thickness is 1 nm or more and 50 nm or less, and even more preferably, the thickness is 1 nm or more and 100 nm or less. It is preferable that the thickness is at most 30 nm, and more preferably from 3 nm to 20 nm.

[0274] Note that the dehydration treatment (dehydrogenation treatment) of the oxide semiconductor film causes the oxide semiconductor film to lose its oxygen. Therefore, the oxide semiconductor film is preferably subjected to a dehydration treatment (dehydrogenation treatment) In order to compensate for oxygen vacancies increased by the above-mentioned treatment, oxygen is added to the oxide semiconductor film. is preferred.

[0275] In this manner, hydrogen or moisture is removed from the oxide semiconductor film by the dehydration treatment (dehydrogenation treatment). By adding oxygen to the material, the oxygen vacancies are compensated for, resulting in an i-type (intrinsic) or An oxide semiconductor film that is nearly i-type and is substantially i-type (intrinsic) can be obtained.

[0276] Next, the oxide semiconductor film 23, the oxide semiconductor film 41, the oxide semiconductor film 42a, and the insulating film After forming a conductive film on the film 22, the shape of the conductive film is processed by etching or the like. As a result, the conductive film 24 and the conductive film 25 in contact with the oxide semiconductor film 23 and the oxide semiconductor film 41 are A conductive film 43 and a conductive film 44 are formed in contact with each other (see FIG. 12(A)). The conductive film 25, the conductive film 43, and the conductive film 44 are made of the same conductive material as the conductive film 21 and the conductive film 40. Fees may be used.

[0277] In this embodiment, a tungsten film having a thickness of 50 nm and an aluminum film having a thickness of 400 nm are used. A conductive film 24 and a conductive film 25 are laminated in this order, and a titanium film having a thickness of 200 nm are laminated in this order. The conductive film 43 and the conductive film 44 are used.

[0278] Next, an oxide film or an insulating film is formed so as to cover the substrate 31. In FIG. The case where the insulating film 26 and the insulating film 27 are formed by stacking them in this order will be illustrated.

[0279] The insulating film 27 is preferably formed continuously after the insulating film 26 is formed without exposing it to the air. After the insulating film 26 is formed, the flow rate, pressure, high frequency power, and the like of the source gas are adjusted without exposing the insulating film 26 to the atmosphere. By adjusting one or more of the temperature of the substrate and the temperature of the insulating film 27, the insulating film 26 and The impurity concentration at the interface between the insulating film 27 and the silicon oxide film 21 can be reduced. The oxygen contained in the oxide semiconductor film 23 can be transferred to the oxide semiconductor film 41. In this way, the amount of oxygen vacancies in the oxide semiconductor film 23 and the oxide semiconductor film 41 can be reduced.

[0280] The substrate placed in the evacuated processing chamber of the plasma CVD device is heated to 180°C or higher (up to 400°C). The temperature is preferably kept at 200° C. or higher and 370° C. or lower, and the raw material gas is introduced into the processing chamber. The pressure in the processing chamber is set to 30 Pa or more and 250 Pa or less, and more preferably 40 Pa or more. The pressure is set to 200 Pa or less, and the insulation is achieved by supplying high-frequency power to the electrodes installed in the treatment chamber. As the insulating film 26, a silicon oxide film or a silicon oxynitride film is formed.

[0281] As the source gas for the insulating film 26, a deposition gas containing silicon and an oxidizing gas are used. Representative examples of deposition gases containing silicon include silane, disilane, trisilane, and Examples of oxidizing gases include oxygen, ozone, nitrous oxide, and fluorinated silane. Nitrogen, etc.

[0282] By using the above conditions, an oxide insulating film that transmits oxygen can be formed as the insulating film 26. In addition, by providing the insulating film 26, in the process of forming the insulating film 27 to be formed later, As a result, damage to the oxide semiconductor film 23, the oxide semiconductor film 41, and the oxide semiconductor film 42a may be reduced. Reduction is possible.

[0283] In addition, by increasing the amount of oxidizing gas to 100 times the amount of deposition gas containing silicon, It is possible to reduce the hydrogen content in the insulating film 26 and to prevent the hydrogen content in the insulating film 26 from being increased. The oxygen that moves from the insulating film 27 is transferred to the insulating film 28. Since the dangling bonds contained in the insulating film 27 may capture the The oxygen contained in the oxide semiconductor film 23 and the oxide semiconductor film 41 is efficiently transferred to the oxide semiconductor film 23 and the oxide semiconductor film 41. It is possible to compensate for oxygen vacancies contained in the conductive film 23 and the oxide semiconductor film 41. As a result, the amount of hydrogen entering the oxide semiconductor film 23 and the oxide semiconductor film 41 can be reduced. In addition, oxygen vacancies in the oxide semiconductor film 23 and the oxide semiconductor film 41 can be reduced. Therefore, the negative shift of the threshold voltages of the transistors 20 and 56 is suppressed. In addition, the off-state current of the transistor 20 and the transistor 56 can be reduced. It is possible to improve the electrical characteristics of the transistor.

[0284] In this embodiment, the insulating film 26 is made of silane at a flow rate of 20 sccm and 3000 sccm. The source gas was nitrous oxide with a flow rate of 1.0 cm, the pressure in the processing chamber was 200 Pa, and the substrate temperature was 350°C. A 27.12MHz high-frequency power source was used to supply 100W of high-frequency power to the parallel plate electrodes. A silicon oxynitride film with a thickness of 50 nm is formed by the plasma CVD method. The CVD device has an electrode area of ​​6000 cm 2 This is a parallel plate type plasma CVD device. The power supplied is converted to power per unit area (power density) of 1.6×10 -2 W / cm 2 Under these conditions, a silicon oxynitride film that is permeable to oxygen can be formed. .

[0285] The insulating film 27 is formed by insulating a substrate placed in a processing chamber of a plasma CVD apparatus that has been evacuated to a vacuum. The temperature is kept at 180° C. or higher and 260° C. or lower, and more preferably 180° C. or higher and 230° C. or lower. The pressure in the treatment chamber is adjusted to 100 Pa or more and 250 Pa or less by introducing a feed gas. The pressure should be between 100 and 200 Pa, and the pressure applied to the electrodes in the treatment chamber should be 0.17 W / cm 2 More than 0.5W / cm 2 Less than or equal to 0.25 W / cm 2 More than 0.35W / c m 2 A silicon oxide film or a silicon oxynitride film is formed under the following conditions for supplying high frequency power: do.

[0286] The deposition conditions for the insulating film 27 are as follows: high frequency power with the above power density in a reaction chamber with the above pressure. By supplying the gas, the decomposition efficiency of the source gas in the plasma increases, the oxygen radicals increase, and the source gas is decomposed. As the oxidation of the gas proceeds, the oxygen content in the insulating film 27 becomes higher than the stoichiometric composition. However, when the substrate temperature is the above temperature, the bonding strength between silicon and oxygen is weak. As a result, more oxygen than meets the stoichiometric composition is present. It is possible to form an oxide insulating film that contains a large amount of oxygen and from which part of the oxygen is released by heating. In addition, an insulating film is formed on the oxide semiconductor film 23, the oxide semiconductor film 41, and the oxide semiconductor film 42a. Since the insulating film 26 is provided, in the step of forming the insulating film 27, the insulating film 26 is not an oxide semiconductor. The insulating film 23 has a function of protecting the oxide semiconductor film 41 and the oxide semiconductor film 42a. As a result, damage to the oxide semiconductor film 23, the oxide semiconductor film 41, and the oxide semiconductor film 42a was prevented. The insulating film 27 can be formed using high-frequency power with high power density while reducing the image. can.

[0287] In this embodiment, the insulating film 27 is formed by reacting silane at a flow rate of 160 sccm as a raw material gas. The chamber pressure was 200 Pa, the substrate temperature was 220°C, and a 27.12 MHz high frequency power source was used. A 4 mm thick film was formed by plasma CVD using a parallel plate electrode with 1500 W of high frequency power. The plasma CVD device is used to form a silicon oxynitride film with a thickness of 6000 nm. cm 2 This is a parallel plate type plasma CVD device, and the power supplied is This is converted to power (power density) of 2.5 x 10 -1 W / cm 2 It is.

[0288] Next, at least the insulating film 27 is formed, and then a heat treatment is performed to form the insulating film 26 or the insulating film The oxygen contained in the oxide semiconductor film 27 is transferred to the oxide semiconductor film 23 and the oxide semiconductor film 41. It is preferable to fill the oxygen vacancies in the conductive film 23 and the oxide semiconductor film 41. The treatment is a heating treatment for dehydrogenating or dehydrating the oxide semiconductor film 23 and the oxide semiconductor film 41. Specifically, in this embodiment, the following treatment is performed in a nitrogen and oxygen atmosphere: Heat treatment is carried out at 350°C for 1 hour.

[0289] Through the above series of steps, the transistor 20 and the transistor 56 are formed.

[0290] Next, as shown in FIG. 13(A), the insulating film 26 and the insulating film 27 are partially etched. In the opening 58, the oxide semiconductor film 42a is partially Or everything is exposed.

[0291] Next, the nitride insulating film 28 and the nitride insulating film 29 are formed on the insulating film 26 and the insulating film 27 so as to cover the opening 58. The nitride insulating film 28 and the insulating film 29 are formed in this order. It is in contact with the oxide semiconductor film 42a.

[0292] The nitride insulating film 28 is, for example, silicon nitride, nitride, etc., formed by using a CVD method or the like. Silicon oxide, aluminum nitride, aluminum oxide nitride, etc. can be used. The nitride insulating film 28 made of the above-mentioned material is an oxide insulating film such as silicon oxide or aluminum oxide. Compared to the above, impurities from the outside, such as water, alkali metals, and alkaline earth metals, The opening can prevent the diffusion of the fluorine atom into the organic semiconductor film 23 and the oxide semiconductor film 41. In the step 58, the nitride insulating film 28 is formed so as to be in contact with the oxide semiconductor film 42a. The conductivity of the oxide semiconductor film 42a can be increased. The film 42a is shown as the metal oxide film 42 in FIG.

[0293] In this embodiment, the nitride insulating film 28 is made of silane at a flow rate of 50 sccm and The raw material gases were nitrogen at a flow rate of 0 sccm and ammonia at a flow rate of 100 sccm, and the pressure in the processing chamber was The pressure was set to 100 Pa, the substrate temperature was set to 350°C, and a 27.12 MHz high frequency power supply was used for 100 0W (power density is 1.6×10 -1 W / cm 2 ) high frequency power is applied to parallel plate electrodes. A silicon nitride film having a thickness of 100 nm is formed by the plasma CVD method using the above-mentioned method.

[0294] The insulating film 29 is an insulating film having a lower relative dielectric constant and smaller internal stress than the nitride insulating film 28. Specifically, the insulating film 29 is preferably a silicon oxide film or a silicon oxynitride film. , aluminum oxide, etc. can be used.

[0295] For example, the insulating film 29 is a silicon oxide film formed by a CVD method using an organic silane gas. As the organic silane gas, ethyl silicate (TEOS: chemical formula Si( OC2H5)4), tetramethylsilane (TMS: chemical formula Si(CH3)4), Tylcyclotetrasiloxane (TMCTS), Octamethylcyclotetrasiloxane (O MCTS), hexamethyldisilazane (HMDS), triethoxysilane (SiH(OC 2H5)3), trisdimethylaminosilane (SiH(N(CH3)2)3), etc. It is possible.

[0296] In this embodiment, the insulating film 29 is formed by a CVD method using ethyl silicate. A 200 nm silicon oxide film is used.

[0297] Next, as shown in FIG. 14(A), the nitride insulating film 28 and the insulating film 29 are partially etched. In the opening 62, at least the conductive film 44 is Some are exposed.

[0298] Next, as shown in FIG. 14(B), a transparent conductive film is formed on the insulating film 29, and then the transparent conductive film is etched or otherwise processed. The conductive film 30 and the conductive film 45 are formed by processing the shape of the transparent conductive film with the above-mentioned method. The conductive film 30 is provided at a position overlapping with the conductive film 21 with the oxide semiconductor film 23 interposed therebetween. Moreover, the conductive film 45 is connected to the conductive film 44 in the opening 62 .

[0299] The transparent conductive film used to form the conductive film 21 and the conductive film 45 is a tantalum oxide film. Indium oxide containing tungsten, indium zinc oxide containing tungsten oxide, Indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin Oxide, Indium Zinc Oxide, Zinc Oxide, Zinc Oxide Doped with Gallium, Silicon Oxide Doped A conductive film containing added indium tin oxide or the like can be used.

[0300] In this embodiment, a 100 nm thick indium tin oxide film containing silicon oxide is used. The conductive film 21 and the conductive film 45 are formed using a conductive film.

[0301] After the conductive film 21 and the conductive film 45 are formed, heat treatment may be performed. The heat treatment may be performed in a nitrogen atmosphere at 250° C. for one hour.

[0302] Next, an alignment film 52 is formed on the conductive film 45 as shown in FIG. 5, thereby forming an element substrate. It is possible.

[0303] The alignment film 52 is formed using an organic resin such as polyimide or polyvinyl alcohol. The surface of the film can be subjected to an orientation treatment such as rubbing to align the liquid crystal molecules in a certain direction. The rubbing treatment is performed by wrapping a cloth such as nylon around the alignment film 52. This can be done by rotating a roller and rubbing the surface of the alignment film 52 in a certain direction. In addition, inorganic materials such as silicon oxide are used, and alignment characteristics can be achieved by deposition without alignment treatment. It is also possible to directly form the alignment film 52 having the above structure.

[0304] After the element substrate and the opposing substrate are formed, a liquid crystal layer is formed between the substrate 31 and the substrate 46 as shown in FIG. By sealing the liquid crystal layer 53, a panel of a liquid crystal display device can be formed. The liquid crystal injection for this purpose can be done by using a dispenser (dropping method) or by dip The pumping type may also be used.

[0305] <Top view and cross-sectional view of semiconductor display device> Next, the appearance of a semiconductor display device according to one embodiment of the present invention will be described using a liquid crystal display device as an example. This will be described with reference to FIG. 15. FIG. 15 shows a substrate 4001 and a substrate 4006 sealed with a sealing material 40. 15. Also, FIG. 16 is a top view of the liquid crystal display device bonded by the broken line C in FIG. This corresponds to the cross-sectional view taken along line 1-C2.

[0306] A pixel portion 4002 and a pair of driver circuits 4004 are provided on a substrate 4001. A sealing material 4005 is provided on the pixel portion 4002 and the driver circuit 4004. Therefore, the pixel portion 4002 and the driver circuit 4004 are connected to a substrate 4006. It is sealed by 4001 , a sealing material 4005 and a substrate 4006 .

[0307] In addition, the driving force is applied to an area other than the area surrounded by the sealing material 4005 on the substrate 4001. An operating circuit 4003 is implemented.

[0308] In addition, a pixel portion 4002 and a driver circuit 4004 provided on a substrate 4001 are made of transistors. In FIG. 16, a transistor 4010 included in a pixel portion 4002 is illustrated. On the transistor 4010, an insulating layer made of various insulating films including a nitride insulating film is formed. An insulating film 4020 is provided, and the transistor 4010 is In the opening, it is connected to a pixel electrode 4021 on the insulating film 4020 .

[0309] In addition, a resin film 4059 is provided on the substrate 4006, and a common An electrode 4060 is provided. A pixel electrode is provided between the substrate 4001 and the substrate 4006. A liquid crystal layer 4028 is provided so as to be sandwiched between the electrode 4021 and the common electrode 4060. The liquid crystal element 4023 includes a pixel electrode 4021, a common electrode 4060, and a liquid crystal layer 4028. do.

[0310] In the liquid crystal element 4023, the value of the voltage applied between the pixel electrode 4021 and the common electrode 4060 Accordingly, the orientation of the liquid crystal molecules contained in the liquid crystal layer 4028 changes, and the transmittance changes. The liquid crystal element 4023 changes its pixel voltage in response to the potential of the image signal applied to the pixel electrode 4021. By controlling the transmittance, it is possible to display gradations.

[0311] As shown in FIG. 16, in one embodiment of the present invention, the insulating film 4020 is In the region where the insulating film 4020 has been removed, the conductive film 4 The conductive film 4050 and the source or drain of the transistor 4010 are formed. The conductive film that functions as an insulating film can be formed by etching a conductive film. do.

[0312] Conductive particles 4061 having conductivity are dispersed between the substrate 4001 and the substrate 4006. The conductive film 4050 is provided with a resin film 4062 dispersed therein. That is, the common electrode 4060 and the conductive particles 4061 are electrically connected to each other. The film 4050 is electrically connected to the panel at the edge via conductive particles 4061. The resin film 4062 is made of a thermosetting resin or an ultraviolet-curing resin. The conductive particles 4061 can be made of, for example, spherical organic resin with Au, Ni, Co, etc. Particles coated with a thin film of metal such as those mentioned above can be used.

[0313] Although the alignment film is not shown in FIG. 16, the alignment film is formed on the pixel electrode 4021 and the common electrode 4022. When the conductive film 4050 is provided on the common electrode 4060, the conductive particles 4061, and the conductive film 4050 are In order to electrically connect the common electrode 4060 and the alignment film, a part of the alignment film is removed from the area where the alignment film overlaps the common electrode 4060. In this case, the alignment film may be partially removed from a portion overlapping with the conductive film 4050 .

[0314] In the liquid crystal display device according to one embodiment of the present invention, a color filter is used to display a color image. An image may be displayed, or multiple light sources emitting light of different hues may be sequentially turned on. A color image may be displayed.

[0315] In addition, image signals from the driver circuit 4003 and various control signals and potentials from the FPC 4018 are 4004 or the pixel section 400 2 is given.

[0316] <Configuration Example of Electronic Device Using Semiconductor Device> A semiconductor device according to one aspect of the present invention includes a display device, a personal computer, and a recording medium. Image playback devices with advanced functions (typically DVD: Digital Versatile Disc (Devices having a display capable of playing back recording media such as 3D models and displaying the images) In addition, an electronic device in which the semiconductor device according to one embodiment of the present invention can be used Mobile phones, handheld game consoles, personal digital assistants, e-books, video cameras, digital cameras, etc. Cameras such as TasStill cameras, goggle-type displays (head-mounted displays) ), navigation systems, audio playback devices (car audio, digital audio players) Years, etc.), copiers, facsimiles, printers, printer-combination machines, automated teller machines Examples of such electronic devices include ATMs and vending machines. vinegar.

[0317] FIG. 18A shows a portable game machine, which includes a housing 5001, a housing 5002, a display unit 5003, Display unit 5004, microphone 5005, speaker 5006, operation keys 5007, The display unit 5003 or the display unit 5004 and other integrated circuits A semiconductor device according to one embodiment of the present invention can be used for the semiconductor device shown in FIG. The portable game machine has two display units 5003 and 5004. The number of display units that the game machine has is not limited to this.

[0318] FIG. 18B shows a portable information terminal, which includes a first housing 5601, a second housing 5602, a first display unit, and a 5603, a second display unit 5604, a connection unit 5605, and operation keys 5606. The display unit 5603 is provided in the first housing 5601, and the second display unit 5604 is provided in the second housing 5602. The first housing 5601 and the second housing 5602 are connected to each other via a connection portion 5602. 5605, and the angle between the first housing 5601 and the second housing 5602 is The image on the first display unit 5603 can be changed by the connection unit 5 The structure is such that the switch is performed according to the angle between the first housing 5601 and the second housing 5602 at 605. The first display portion 5603 or the second display portion 5604 or other integrated circuits may be formed. In this case, the semiconductor device according to one embodiment of the present invention can be used.

[0319] FIG. 18C shows a notebook personal computer, which includes a housing 5401 and a display unit 5402. The display unit 5402 and the like include a keyboard 5403 and a pointing device 5404. The semiconductor device according to one embodiment of the present invention can be used for these and other integrated circuits.

[0320] FIG. 18D shows a wristwatch, which includes a housing 5201, a display unit 5202, an operation button 5203, and a backlight. The display portion 5202 and other integrated circuits according to one embodiment of the present invention may include a display unit 5202 and other integrated circuits. A semiconductor device having such a structure can be used.

[0321] FIG. 18E shows a video camera, which includes a first housing 5801, a second housing 5802, and a display unit 58. 03, operation keys 5804, a lens 5805, a connection part 5806, etc. 4 and a lens 5805 are provided in a first housing 5801, and a display unit 5803 is provided in a second housing. The first housing 5801 and the second housing 5802 are connected to each other via a connection portion. The first housing 5801 and the second housing 5802 are connected by a joint 5806. The video on the display unit 5803 can be changed by the video input unit 5806. , according to the angle between the first housing 5801 and the second housing 5802 at the connection portion 5806. The semiconductor device according to one embodiment of the present invention may be provided in the display portion 5803 or other integrated circuits. A body device can be used.

[0322] FIG. 18F shows a mobile phone. A housing 5901 includes a display unit 5902, a microphone 5907, and a speaker. Speaker 5904, camera 5903, external connection part 5906, and operation button 5905 are provided. The semiconductor device according to one embodiment of the present invention is used for the display portion 5902 and other integrated circuits. In addition, the semiconductor device according to one embodiment of the present invention can be formed on a flexible substrate. In the case where the semiconductor device is formed in the display portion 5902 having a curved surface as shown in FIG. It is possible to apply the position. EXAMPLES

[0323] In this example, a transistor was fabricated and its Vg-Id characteristics and reliability were evaluated. The results will be explained.

[0324] [Sample preparation] In this example, Samples 1 and 2 according to an embodiment of the present invention and Sample 3 for comparison were prepared. More specifically, as a sample 1 according to one embodiment of the present invention, a transistor having a structure shown in FIG. As sample 2 according to one embodiment of the present invention, a transistor having a structure corresponding to that shown in FIG. For comparison, sample 3 was fabricated using the same structure as that shown in FIG. A transistor having a configuration without the conductive film 30 was fabricated.

[0325] [Sample 1] First, a glass substrate was used as the substrate, and a gate electrode was formed on the substrate.

[0326] A 200 nm thick tungsten film was formed as the gate electrode by sputtering. A mask is formed on the tungsten film by a lithography process, and the tungsten film is The GaN film was partially etched away.

[0327] Next, a gate insulating film was formed on the gate electrode.

[0328] As the gate insulating film, a silicon nitride film with a thickness of 400 nm and a silicon oxynitride film with a thickness of 50 nm are used. It was formed by laminating.

[0329] The silicon nitride film includes a first silicon nitride film, a second silicon nitride film, and a third silicon nitride film. It has a three-layer laminated structure.

[0330] The first silicon nitride film was formed using silane at a flow rate of 200 sccm and nitrogen at a flow rate of 2000 sccm. and ammonia gas at a flow rate of 100 sccm was used as the source gas for the plasma CVD apparatus. The pressure in the treatment chamber was controlled to 100 Pa, and a high-frequency power source of 27.12 MHz was used. The second silicon nitride was formed to a thickness of 50 nm by supplying a power of 2000 W to the silicon nitride film. The base film was prepared by mixing silane at a flow rate of 200 sccm, nitrogen at a flow rate of 2000 sccm, and 000sccm of ammonia gas was supplied as a source gas to the processing chamber of the plasma CVD device. The pressure in the processing chamber was controlled to 100 Pa, and a high frequency power source of 27.12 MHz was used to generate 200 The third silicon nitride film was formed to a thickness of 300 nm by supplying a power of 0 W. The source gases used were silane at a flow rate of 200 sccm and nitrogen at a flow rate of 5000 sccm. The gas was supplied to the processing chamber of the plasma CVD device, and the pressure in the processing chamber was controlled to 100 Pa. A 2MHz high-frequency power supply was used to supply 2000W of power, and the thickness was set to 50nm. In addition, when the first silicon nitride film, the second silicon nitride film, and the third silicon nitride film were formed, The substrate temperature was set to 350°C.

[0331] The silicon oxynitride film was prepared by using silane at a flow rate of 20 sccm and dioxygen at a flow rate of 3000 sccm. Nitrogen was supplied as a source gas to the processing chamber of the plasma CVD device, and the pressure in the processing chamber was set to 40 Pa. The device was controlled to a temperature of 400° C., and a high-frequency power source of 27.12 MHz was used to supply 100 W of power to the device to perform oxidization and nitridation. The silicon oxynitride film was formed at a substrate temperature of 350° C.

[0332] Next, an oxide semiconductor film was formed so as to overlap with the gate electrode with the gate insulating film interposed therebetween.

[0333] In this embodiment, a 35-nm-thick oxide semiconductor film is formed on a gate insulating film by a sputtering method. Successful.

[0334] The oxide semiconductor film was formed by sputtering a target of In:Ga:Zn=1:1:1 (atomic number The sputtering was performed using a target of 100 sccm and oxygen as the sputtering gas. The pressure in the treatment chamber was controlled to 0.6 Pa, and a direct current of 5 kW was applied. The oxide semiconductor film was formed at a substrate temperature of 170° C. .

[0335] Next, a source electrode and a drain electrode in contact with the oxide semiconductor film were formed.

[0336] First, a conductive film was formed over the gate insulating film and the oxide semiconductor film. An aluminum film having a thickness of 400 nm is formed on a tungsten film having a thickness of 50 nm. A titanium film with a thickness of 200 nm was then formed on the titanium film by a photolithography process. A mask is formed on the conductive film, and a part of the conductive film is etched using the mask to form a source electrode. A positive electrode and a drain electrode were formed.

[0337] Next, the substrate is moved to a depressurized processing chamber, heated at 350° C., and then A high-frequency power of 150 W was supplied to the top electrode using a 27.12 MHz high-frequency power source to generate monooxygen. The oxide semiconductor film was exposed to oxygen plasma generated in a dinitrogen chloride atmosphere.

[0338] Next, a protective film was formed on the oxide semiconductor film, the source electrode, and the drain electrode. The protective film is a three-layer structure consisting of a first oxide insulating film, a second oxide insulating film, and a nitride insulating film. The structure was as follows.

[0339] The first oxide insulating film was formed using silane at a flow rate of 20 sccm and dinitrogen at a flow rate of 3000 sccm. Nitrogen was used as the source gas, the pressure in the processing chamber was 200 Pa, the substrate temperature was 350°C, and the The film was formed by the plasma CVD method in which high frequency power was supplied to parallel plate electrodes.

[0340] The second oxide insulating film was formed using silane at a flow rate of 160 sccm and monoxide at a flow rate of 4000 sccm. Dinitrogen was used as the source gas, the pressure in the processing chamber was 200 Pa, the substrate temperature was 220°C, and The film was formed by the plasma CVD method in which a high-frequency power of 100 MW was supplied to parallel plate electrodes. As a result, the mixture contains more oxygen than the stoichiometric composition, and some of the oxygen is removed by heating. A silicon oxynitride film can be formed to separate the insulating film.

[0341] Next, heat treatment is performed to remove water, nitrogen, and oxygen from the first oxide insulating film and the second oxide insulating film. At the same time, part of oxygen contained in the second oxide insulating film is transferred to the oxide semiconductor film. In this embodiment, the heat treatment was performed in a nitrogen and oxygen atmosphere at 350° C. for 1 hour. .

[0342] Next, a nitride insulating film having a thickness of 100 nm was formed on the second oxide insulating film. The film was prepared by mixing silane at a flow rate of 50 sccm, nitrogen at a flow rate of 5000 sccm, and The source gas was ammonia gas of 100 m, the pressure in the processing chamber was 100 Pa, and the substrate temperature was 350°C. The film was formed by the plasma CVD method in which 1000 W of high frequency power was supplied to parallel plate electrodes. .

[0343] Next, in a region where the oxide semiconductor film, the source electrode, and the drain electrode are not provided, An opening reaching the gate electrode was formed in a part of the gate insulating film and the protective film. A mask is formed on the protective film by a photolithography process, and the mask is used to form a gate insulating film. The insulating film and a part of the protective film were etched away to form the insulating film.

[0344] Next, a gate electrode was formed on the protective film. The gate electrode was a gate insulating film and a protective film. The gate electrode is electrically connected to the oxide semiconductor film through an opening provided in a part of the oxide semiconductor film. In the following, the gate electrode on the protective film is called a backgate electrode.

[0345] In this embodiment, a 100 nm thick oxide film was formed by sputtering as a back gate electrode. A conductive film of indium oxide-tin oxide compound (ITO-SiO2) containing silicon was formed. The composition of the target used for the conductive film was In2O3:SnO2:SiO2=85:1. 0:5 [wt %]. After that, heat treatment was performed at 250°C for 1 hour in a nitrogen atmosphere. .

[0346] Through the above steps, Sample 1 of this example was obtained.

[0347] [Sample 2] Sample 2 is different from Sample 1 in the structure of the protective film and the back gate electrode. More specifically, In the channel width direction of the transistor, the first oxide insulating film and the second oxide insulating film The side surface of the semiconductor layer is covered with the back gate electrode.

[0348] The sample 2 was fabricated by the same process as the sample 1 except that the first oxide insulating film and the second oxide insulating film were formed. After forming an insulating film and performing a heat treatment, a second oxide film is formed by a photolithography process. A mask was formed on the oxide insulating film. Then, a first oxide insulating film and a second oxide insulating film were formed using the mask. The other steps were the same as those for Sample 1. Therefore, the description of Sample 1 can be used.

[0349] [Sample 3] The sample 3 for comparison has a different configuration from the sample 1 in that it does not have a back gate electrode. It was decided.

[0350] The fabrication of sample 3 was carried out by omitting the back gate electrode formation process from the fabrication process of sample 1 described above. The other steps were the same as those for Sample 1. The description in 1 can be cited.

[0351] In addition, in the above-mentioned samples 1 to 3, the channel length (L) is 2 μm, 3 μm, or 6 μm. m. Samples 1 to 3 each contained three types of transistors. All the transistors included had a channel width (W) of 50 μm.

[0352] [Vg-Id characteristics] Next, as the initial characteristics of the transistors of Samples 1 to 3, the Vg-Id characteristics were measured. In this embodiment, the substrate temperature is set to 25° C., and the potential difference between the source and drain (hereinafter, referred to as drain potential) is The potential difference between the source and back gate electrodes (hereinafter, When the gate voltage (Vg) is changed from -15V to 15V, the source-drain The change in the current (hereinafter referred to as drain current, Id) flowing between the gates of the transistors, i.e., Vg-I The d characteristic was measured.

[0353] In Samples 1 and 2, the gate electrode and the back gate electrode are electrically short-circuited. The driving method used was to apply the gate voltage in the state where the gate was turned on. The gate voltage of the gate electrode and the back gate electrode are always equal.

[0354] FIG. 26 shows the Vg-Id characteristics of sample 3. FIGS. 26(A), (B), and (C) show, respectively, The results are for transistors with channel lengths (L) of 2 μm, 3 μm, and 6 μm. Similarly, FIG. 27 shows the Vg-Id characteristics of sample 1, and FIG. 28 shows the Vg-Id characteristics of sample 2. are shown respectively.

[0355] In each of FIG. 26, FIG. 27, and FIG. 28, the horizontal axis represents the gate voltage Vg, and the first vertical axis represents the The first vertical axis represents the drain current Id, and the second vertical axis represents the field effect mobility. The field-effect mobility is calculated at Vd = 10 V to show the value in the saturation region. It shows.

[0356] In the comparative sample 3 shown in FIG. 26, the field effect mobility value was It was found that the drain current is almost constant. The results show that the threshold voltage shifts in the negative direction as the voltage Vd increases.

[0357] On the other hand, in the case of Sample 1 according to one embodiment of the present invention shown in FIG. 27, under all channel length (L) conditions, It was confirmed that the field effect mobility was improved compared to Sample 3. It was found that the smaller the channel length (L), the higher the field effect mobility. Even when the channel length (L) is small (L = 2 μm), the threshold for the drain voltage Vd It was found that the change in the low voltage was extremely small compared to sample 3.

[0358] In the sample 2 according to one embodiment of the present invention shown in FIG. 28, the It was confirmed that the field effect mobility was improved compared to Sample 3. It was found that the smaller the channel length (L), the higher the field effect mobility. Even when the channel length (L) is small (L = 2 μm), the threshold for the drain voltage Vd It was found that the change in the low voltage was extremely small compared to sample 3.

[0359] In Sample 1 and Sample 2, the dual gate drive formed a larger channel than in Sample 3. This makes it possible to apply an electric field more effectively to the oxide semiconductor that is being channeled. Even when the length (L) is small, the change in the threshold voltage with respect to the drain voltage Vd is small. For the same reason, the D The dual gate drive makes it less susceptible to the effects of the drain voltage Vd, and The saturation property can also be improved.

[0360] From the above results, in the semiconductor device according to one aspect of the present invention, the channel length (L The smaller the θ is, the higher the field effect mobility is. It was confirmed that the threshold voltage can be set to a good value even in such a case. By using such a transistor, it is possible to realize a narrower frame of a semiconductor display device. . [Explanation of symbols]

[0361] 10 sequential circuits 10_DUM sequential circuit 10_j Sequential circuit 10_j-1 Sequential circuit 10_y sequential circuit 10_1 Sequential circuit 10_8m sequential circuit 11 Circuit 12 Transistor 13. Transistor 14 Transistor 15 Transistor 16 Transistors 17 Transistor 20 Transistor 21 Conductive film 22 Insulating film 23 Oxide semiconductor film 23a Oxide semiconductor film 23b Oxide semiconductor film 23c Oxide semiconductor film 24 Conductive Film 25 Conductive Film 26 Insulating Film 27 Insulating Film 28 Nitride insulating film 29 Insulating Film 30 Conductive Film 31 Substrate 32 Opening 32a opening 32b opening 34 Conductive Film 40 Conductive Film 41 Oxide Semiconductor Film 42 Metal oxide film 42a Oxide semiconductor film 43 Conductive Film 44 Conductive Film 45 Conductive Film 46 Substrate 47 Shielding membrane 48 Colored layer 50 Resin Film 51 Orientation film 52 Orientation film 53 Liquid crystal layer 55 pixels 56 Transistor 57 Capacitive element 58 Opening 59 Conductive Film 60 Liquid crystal element 61 Conductive Film 62 Opening 70 Semiconductor display device 71 Pixel section 72 Drive circuit 73 Drive circuit 80 Transistor 81 Transistor 82 Transistor 83 Transistor 84 Transistors 85 Transistors 86 Transistor 90 Buffer 91 Transistor 92 Transistor 93 Transistor 95 Transistors 96 Transistors 97 Capacitive element 98 Light emitting element 4001 Substrate 4002 Pixel section 4003 Drive circuit 4004 Drive circuit 4005 Encapsulating material 4006 Substrate 4010 Transistor 4018 FPC 4020 Insulating film 4021 Pixel electrode 4023 Liquid crystal element 4028 Liquid crystal layer 4030 Wiring 4050 Conductive film 4059 Resin film 4060 Common electrode 4061 Conductive particles 4062 Resin film 5001 Case 5002 Case 5003 Display section 5004 Display section 5005 Microphone 5006 Speaker 5007 Operation key 5008 Stylus 5201 Case 5202 Display section 5203 Operation button 5204 Band 5401 Case 5402 Display section 5403 Keyboard 5404 Pointing Device 5601 Case 5602 Case 5603 Display section 5604 Display section 5605 Connection 5606 Operation key 5801 Case 5802 Case 5803 Display section 5804 Operation key 5805 Lens 5806 Connection 5901 Case 5902 Display section 5903 Camera 5904 Speaker 5905 Button 5906 External connection part 5907 Mike

Claims

1. a transistor, a display element, a capacitor, and a first wiring; a display device in which one of a source and a drain of the transistor is electrically connected to the display element and the capacitor element, an oxide semiconductor film having a channel formation region of the transistor; a metal oxide film having a function as one electrode of the capacitor element; a first conductive film having a region in contact with an upper surface of the metal oxide film and functioning as the first wiring; a first insulating film having a region in contact with an upper surface of the oxide semiconductor film and a region in contact with an upper surface of the metal oxide film; a second conductive film having a region disposed above the metal oxide film, functioning as a pixel electrode of the display element and functioning as the other electrode of the capacitance element; having the metal oxide film has a first region overlapping the second conductive film without the first insulating film therebetween; the first region does not overlap with the first conductive film; Display device.

2. a transistor, a display element, a capacitor, and a first wiring; a display device in which one of a source and a drain of the transistor is electrically connected to the display element and the capacitor element, an oxide semiconductor film having a channel formation region of the transistor; a metal oxide film having a function as one electrode of the capacitor element; a first conductive film having a region in contact with an upper surface of the metal oxide film and functioning as the first wiring; a first insulating film having a region in contact with an upper surface of the oxide semiconductor film and a region in contact with an upper surface of the metal oxide film; a second conductive film having a region disposed above the metal oxide film, functioning as a pixel electrode of the display element and functioning as the other electrode of the capacitance element; a third conductive film having a region located under the oxide semiconductor film and functioning as a gate electrode of the transistor; having the metal oxide film has a first region overlapping the second conductive film without the first insulating film therebetween; the first region does not overlap with the first conductive film; Display device.

3. a transistor, a display element, a capacitor, and a first wiring; a display device in which one of a source and a drain of the transistor is electrically connected to the display element and the capacitor element, an oxide semiconductor film having a channel formation region of the transistor; a metal oxide film having a function as one electrode of the capacitor element; a first conductive film having a region in contact with an upper surface of the metal oxide film and functioning as the first wiring; a first insulating film having a region in contact with an upper surface of the oxide semiconductor film and a region in contact with an upper surface of the metal oxide film; a second insulating film having a region disposed above the first insulating film; a second conductive film having a region disposed above the metal oxide film, functioning as a pixel electrode of the display element and functioning as the other electrode of the capacitance element; having the metal oxide film has a first region overlapping the second conductive film without the first insulating film and through the second insulating film; the first region does not overlap with the first conductive film; Display device.

4. a transistor, a display element, a capacitor, and a first wiring; a display device in which one of a source and a drain of the transistor is electrically connected to the display element and the capacitor element, an oxide semiconductor film having a channel formation region of the transistor; a metal oxide film having a function as one electrode of the capacitor element; a first conductive film having a region in contact with an upper surface of the metal oxide film and functioning as the first wiring; a first insulating film having a region in contact with an upper surface of the oxide semiconductor film and a region in contact with an upper surface of the metal oxide film; a second insulating film having a region disposed above the first insulating film; a second conductive film having a region disposed above the metal oxide film, functioning as a pixel electrode of the display element and functioning as the other electrode of the capacitance element; a third conductive film having a region located under the oxide semiconductor film and functioning as a gate electrode of the transistor; having the metal oxide film has a first region overlapping the second conductive film without the first insulating film and through the second insulating film; the first region does not overlap with the first conductive film; Display device.

5. In any one of claims 1 to 4, each of the oxide semiconductor film and the metal oxide film contains In, Ga, and Zn; Display device.

Images