Semiconductor device manufacturing method

Abstract

To provide a method for manufacturing a semiconductor device capable of easily changing a collector layer and a cathode layer to desired characteristics.SOLUTION: A method for manufacturing a semiconductor device includes the steps of: preparing a processed member 100 constituting a semiconductor substrate; ion-implanting a first impurity for forming a collector layer of a first conductivity type constituting an IGBT element into a portion serving as an IGBT region of the processed member 100; ion-implanting a second impurity for forming a cathode layer of a second conductivity type constituting an FWD element into a portion serving as an FWD region of the processed member 100; and performing laser annealing for forming a collector layer by irradiating the processed member 100 with laser beams L1 to L3 and activating the first impurity and forming a cathode layer by activating the second impurity. The step of performing laser annealing changes conditions for laser beam to be irradiated to the portion serving as the IGBT region and conditions for laser beam to be irradiated to the portion serving as the FWD region, and irradiates the portions with laser beams.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present invention relates to a semiconductor device in which an insulated gate bipolar transistor (hereinafter referred to as IGBT) element having an insulated gate structure and a free wheel diode (hereinafter referred to as FWD) element are formed on a common semiconductor substrate. [Background technology]

[0002] Conventionally, for example, as a switching element used in an inverter or the like, a semiconductor device has been proposed in which an IGBT region having an IGBT element and an FWD region having an FWD element are formed on a common semiconductor substrate (see, for example, Patent Document 1).

[0003] Specifically, in this semiconductor device, n - A base layer is formed on one surface of a semiconductor substrate constituting a drift layer of a mold, and a plurality of trenches are formed so as to penetrate the base layer. Each trench is extended so that one direction in the surface direction of the semiconductor substrate is the longitudinal direction. A gate insulating film and a gate electrode are formed in order in each trench.

[0004] The surface of the base layer is made of n + The other surface of the semiconductor substrate has a p-type emitter region. + collector layer and n + A cathode layer of the mold is formed.

[0005] An upper electrode is formed on one surface of the semiconductor substrate, the upper electrode being electrically connected to the emitter region and the base layer, and a lower electrode is formed on the other surface of the semiconductor substrate, the lower electrode being electrically connected to the collector layer and the cathode layer.

[0006] In such a semiconductor device, the region where the collector layer is formed is the IGBT region, and the region where the cathode layer is formed is the FWD region. In the FWD region, due to the above configuration, an FWD element having a pn junction is formed by the n-type cathode layer and drift layer and the p-type base layer.

[0007] The collector layer and the cathode layer in such a semiconductor device are formed as follows: p-type impurities are ion-implanted from the other surface side of the semiconductor substrate into the portion that will become the IGBT region, and n-type impurities are ion-implanted into the portion that will become the FWD region. Then, by irradiating a laser from the other surface side of the semiconductor substrate and performing laser annealing, the p-type impurities are activated to form the collector layer, and the n-type impurities are activated to form the cathode layer. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] International Publication No. 2019 / 244665 Summary of the Invention [Problem to be solved by the invention]

[0009] However, in the above-described manufacturing method of the collector layer and the cathode layer, laser annealing is performed by irradiating the layers with a laser beam having the same characteristics, which may make it difficult to give both the collector layer and the cathode layer desired characteristics.

[0010] SUMMARY OF THE PRESENT DISCLOSURE In view of the above, an object of the present invention is to provide a method for manufacturing a semiconductor device that can easily impart desired characteristics to a collector layer and a cathode layer. [Means for solving the problem]

[0011] Claim 1 to achieve the above object and 2In the present invention, a method for manufacturing a semiconductor device in which an IGBT region (1) having an IGBT element including a collector layer (21) and an FWD region (2) having an FWD element including a cathode layer (22) are formed on a common semiconductor substrate (10) includes the steps of: preparing a workpiece (100) constituting the semiconductor substrate; ion-implanting a first impurity for forming a collector layer of a first conductivity type constituting the IGBT element into a portion of the workpiece that will become the IGBT region; ion-implanting a second impurity for forming a cathode layer of a second conductivity type constituting the FWD element into a portion of the workpiece that will become the FWD region; and performing laser annealing by irradiating the workpiece with laser beams (L1 to L3) to activate the first impurity to form the collector layer and activating the second impurity to form the cathode layer. In the laser annealing, the laser beam is irradiated under different conditions between the portion that will become the IGBT region and the portion that will become the FWD region. In claim 1, in the step of ion-injecting a first impurity and the step of ion-injecting a second impurity, the first impurity and the second impurity are ion-injected so that the impurity concentration in the cathode layer is higher than that in the collector layer, and in the step of irradiating a laser beam to the portion that will become the IGBT region and the step of irradiating a laser beam to the portion that will become the FWD region, a pulsed laser is irradiated, and when the laser beam is irradiated to the portion that will become the IGBT region, the laser beam irradiated to the portion that will become the IGBT region overlaps, and when the laser beam is irradiated to the portion that will become the FWD region, the laser beam is irradiated so that the amount of overlap of the laser beam irradiated to the portion that will become the FWD region is less than the amount of overlap of the laser beam when the laser beam is irradiated to the portion that will become the IGBT region, and the energy of the laser beam is greater than that of the laser beam irradiated to the portion that will become the IGBT region. In claim 2, in the step of ion-injecting a first impurity and the step of ion-injecting a second impurity, the first impurity and the second impurity are ion-injected so that the impurity concentration in the cathode layer is higher than that in the collector layer, and in the step of irradiating a laser beam to the portion that will become the IGBT region and the step of irradiating a laser beam to the portion that will become the FWD region, a pulsed laser is irradiated, and when irradiating the portion that will become the IGBT region with the laser beam, the laser beam irradiated to the portion that will become the IGBT region is made to overlap, and when irradiating the portion that will become the FWD region with the laser beam, the laser beam is irradiated so that the amount of overlap of the laser beam irradiated to the portion that will become the FWD region is greater than the amount of overlap of the laser beam when irradiating the portion that will become the IGBT region, and the energy of the laser beam is smaller than that of the laser beam irradiated to the portion that will become the IGBT region.

[0012] According to this, the conditions of the laser beam irradiated to the portion that will become the IGBT region and the conditions of the laser beam irradiated to the portion that will become the FWD region are different, so that the conditions of the laser beam for forming the collector layer and the cathode layer can be adjusted separately, making it easier to give both the collector layer and the cathode layer the desired characteristics.

[0013] Note that the reference symbols in parentheses attached to each component indicate an example of the correspondence between the component and specific components described in the embodiments described below. [Brief description of the drawings]

[0014] [Figure 1] 4 is a plan view of the other surface side of the semiconductor device in the first embodiment. FIG. [Diagram 2] FIG. 2 is a cross-sectional view taken along line II-II in FIG. [Diagram 3] FIG. 1 is a schematic plan view of a semiconductor wafer for manufacturing a semiconductor device. [Figure 4] FIG. 1 is a schematic diagram showing a laser device. [Diagram 5] FIG. 2 is a schematic diagram illustrating a laser beam being irradiated onto a semiconductor wafer. [Figure 6] 1 is a schematic diagram showing a state where a laser beam is irradiated onto a portion of a device formation region that will become an IGBT region. [Figure 7] 1 is a schematic diagram showing a state where a laser beam is irradiated onto a portion of a device formation region that will become a FWD region. [Figure 8] 13 is a schematic diagram showing a state where a laser beam is irradiated onto a portion of a device formation region that will become an IGBT region in the second embodiment. FIG. [Figure 9] 13 is a schematic diagram showing a state where a laser beam is irradiated to a portion that becomes a FWD region in a device formation region in the second embodiment. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be denoted by the same reference numerals.

[0016] (First embodiment) DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment will be described with reference to the drawings. The semiconductor device of the present embodiment is suitable for use as a power switching element used in power supply circuits such as inverters and DC / DC converters.

[0017] As shown in FIG. 1, the semiconductor device of this embodiment is an RC (i.e., reverse conducting)-IGBT in which an IGBT region 1 in which an IGBT element is formed and an FWD region 2 in which an FWD element is formed are formed on a common semiconductor substrate 10. Although not particularly limited, in this embodiment, the FWD region 2 is extended in one direction and is formed at a predetermined interval in a direction intersecting the extending direction. The IGBT region 1 is a region different from the FWD region 2. Note that, as will be described later in detail, in this embodiment, the portion on a collector layer 21 described later is the IGBT region 1, and the portion on a cathode layer 22 described later is the FWD region 2. In the following, the direction intersecting the longitudinal direction of the FWD region 2 is the width direction of the FWD region 2. In FIG. 1, the vertical direction of the paper surface is the longitudinal direction of the FWD region 2, and the horizontal direction of the paper surface is the width direction of the FWD region 2.

[0018] As shown in FIG. 2, the semiconductor substrate 10 is - The semiconductor substrate 10 has a p-type drift layer 11. The semiconductor substrate 10 is formed of, for example, a silicon substrate. A p-type base layer 12 is formed on the drift layer 11. In the following description, a surface of the semiconductor substrate 10 closer to the base layer 12 than the drift layer 11 is referred to as one surface 10a of the semiconductor substrate 10, and a surface of the semiconductor substrate 10 opposite to the one surface 10a is referred to as 10b.

[0019] A plurality of trenches 13 are formed in the semiconductor substrate 10 so as to penetrate the base layer 12 and reach the drift layer 11. As a result, the base layer 12 is separated into a plurality of pieces by the trenches 13. In this embodiment, the plurality of trenches 13 are formed in each of the IGBT region 1 and the FWD region 2, and are formed in stripes at equal intervals along one of the planar directions of one surface 10a of the semiconductor substrate 10. In FIG. 2, each trench 13 is formed along the direction perpendicular to the paper surface.

[0020] Each trench 13 is filled with a gate insulating film 14 formed so as to cover the wall surface of each trench 13, and a gate electrode 15 made of polysilicon or the like formed on this gate insulating film 14. This forms a trench gate structure.

[0021] The surface layer of the base layer 12 in the IGBT region 1 (i.e., the surface 10a side of the semiconductor substrate 10) is made of n-type impurity doped with n-type impurities having a higher impurity concentration than the drift layer 11. + The p-type emitter region 16 and the base layer 12 are doped with a higher impurity concentration. + A contact region 17 of a type is formed in the base layer 12. Specifically, the emitter region 16 is formed so as to terminate in the base layer 12 and to contact the side surface of the trench 13. Similarly to the emitter region 16, the contact region 17 is formed so as to terminate in the base layer 12.

[0022] More specifically, the emitter region 16 is structured to extend in a rod shape in the region between the trenches 13 along the longitudinal direction of the trench 13 so as to contact the side surface of the trench 13, and to terminate inside the tip of the trench 13. The contact region 17 is sandwiched between the two emitter regions 16 and extends in a rod shape along the longitudinal direction of the trench 13 (i.e., the emitter regions 16). The contact region 17 is formed deeper than the emitter regions 16 with respect to one surface 10a of the semiconductor substrate 10.

[0023] A contact region 17 similar to that in the IGBT region 1 is formed in a surface layer portion of the base layer 12 in the FWD region 2. Note that, in this embodiment, an example in which the emitter region 16 is not formed in the FWD region 2 will be described, but the emitter region 16 similar to that in the IGBT region 1 may be formed in the FWD region 2.

[0024] An interlayer insulating film 18 made of BPSG (abbreviation of boron phosphorus silicon glass) or the like is formed on one surface 10a of the semiconductor substrate 10. A first contact hole 18a is formed in the interlayer insulating film 18 in the IGBT region 1 to expose the emitter region 16 and the contact region 17. A second contact hole 18b is formed in the interlayer insulating film 18 in the FWD region 2 to expose the base layer 12 and the contact region 17.

[0025] An upper electrode 19 is formed on the interlayer insulating film 18. The upper electrode 19 is formed so as to be electrically connected to the emitter region 16 and the contact region 17 through a first contact hole 18a formed in the interlayer insulating film 18. The upper electrode 19 is also formed so as to be electrically connected to the base layer 12 and the contact region 17 through a second contact hole 18b formed in the interlayer insulating film 18. In other words, the upper electrode 19 is formed on the interlayer insulating film 18, and functions as an emitter electrode in the IGBT region 1 and as an anode electrode in the FWD region 2.

[0026] In this embodiment, the upper electrode 19 serves as a first electrode. In this embodiment, the gate electrode 15 formed in the FWD region 2 is connected to the upper electrode 19 in a cross section different from that in FIG. 2 and is maintained at the potential of the upper electrode 19.

[0027] An n-type field stop layer (hereinafter referred to as an FS layer) 20 having a higher impurity concentration than the drift layer 11 is formed on the side of the drift layer 11 opposite to the base layer 12 side (i.e., the other surface 10b side of the semiconductor substrate 10).

[0028] In the IGBT region 1, the p + In the FWD region 2, an n-type collector layer 21 is formed on the side opposite to the drift layer 11 with the FS layer 20 interposed therebetween. +A cathode layer 22 of a type is formed on the FS layer 20. That is, on the opposite side of the drift layer 11 with the FS layer 20 interposed therebetween, a collector layer 21 and a cathode layer 22 are formed adjacent to each other. The IGBT region 1 and the FWD region 2 are defined by whether a layer formed on the other surface 10b side of the semiconductor substrate 10 is the collector layer 21 or the cathode layer 22. That is, in this embodiment, the portion on the collector layer 21 is the IGBT region 1, and the portion on the cathode layer 22 is the FWD region 2.

[0029] Here, when the n-type cathode layer 22 has the same impurity concentration as the p-type collector layer 21, the contact resistance with the lower electrode 23 described later is likely to be higher than that of the p-type collector layer 21. For this reason, in this embodiment, in order to reduce the contact resistance with the lower electrode 23 described later, the impurity concentration of the cathode layer 22 is made higher than that of the collector layer 21. For example, the cathode layer 22 has an impurity concentration of 1.0×10 20 cm -3 The collector layer 21 has an impurity concentration of about 1.0×10 18 cm -3 It is said to be about that level.

[0030] A lower electrode 23 electrically connected to the collector layer 21 and the cathode layer 22 is formed on the side opposite to the drift layer 11 (i.e., the other surface 10b of the semiconductor substrate 10) with the collector layer 21 and the cathode layer 22 sandwiched therebetween. That is, the lower electrode 23 is formed to function as a collector electrode in the IGBT region 1 and to function as a cathode electrode in the FWD region 2. In this embodiment, the lower electrode 23 serves as a second electrode.

[0031] With this configuration, an IGBT element is configured in the IGBT region 1, with the base layer 12 as a base, the emitter region 16 as an emitter, and the collector layer 21 as a collector. Also, in the FWD region 2, an FWD element is configured with a pn junction, with the base layer 12 and the contact region 17 as an anode, and the drift layer 11, the FS layer 20, and the cathode layer 22 as a cathode.

[0032] The above is the configuration of the semiconductor device in this embodiment. In this embodiment, the IGBT region 1 and the FWD region 2 are formed in the common semiconductor substrate 10 in this manner. + type, n - The first conductivity type is p-type, p + The semiconductor substrate 10 has the second conductivity type. Due to the above-described configuration, the semiconductor substrate 10 includes the drift layer 11, the base layer 12, the emitter region 16, the contact region 17, the FS layer 20, the collector layer 21, the cathode layer 22, and the like.

[0033] Next, a method for manufacturing the above-mentioned semiconductor device will be described. Hereinafter, a method for manufacturing the collector layer 21 and the cathode layer 22 in the semiconductor device will be specifically described with reference to FIGS.

[0034] 3, a semiconductor wafer 100 is prepared in which a plurality of device formation regions R are partitioned by dicing lines DL. The semiconductor wafer 100 constitutes the above-mentioned semiconductor substrate 10 by dividing the device formation regions R by the dicing lines DL. In this embodiment, the semiconductor wafer 100 corresponds to a workpiece.

[0035] Next, although not specifically shown, a typical semiconductor manufacturing process is performed on each device formation region R to form a base layer 12, a trench 13, a gate insulating film 14, a gate electrode 15, an emitter region 16, a contact region 17, an interlayer insulating film 18, an upper electrode 19, etc.

[0036] Next, a mask (not shown) is placed on each device formation region R, and p-type impurities are ion-implanted into a portion of the IGBT region 1 where the collector layer 21 is to be formed. Another mask is placed on each device formation region R, and n-type impurities are ion-implanted into a portion of the FWD region 2 where the cathode layer 22 is to be formed. In this embodiment, the p-type impurities correspond to the first impurities, and the n-type impurities correspond to the second impurities.

[0037] Thereafter, laser annealing is performed to activate the p-type impurities to form the collector layer 21, and to activate the n-type impurities to form the cathode layer 22. The laser annealing of this embodiment will be specifically described below.

[0038] First, the laser device LS for performing laser annealing according to this embodiment will be described with reference to Fig. 4. As shown in Fig. 4, the laser device LS according to this embodiment includes first to third oscillators 101 to 103 for oscillating first to third laser beams L1 to L3. The first to third oscillators 101 to 103 output, for example, a green laser having a wavelength of about 530 nm or a near-infrared laser having a wavelength of about 808 nm. The first to third oscillators 101 to 103 output, for example, the first to third laser beams L1 to L3 having a frequency of 0 to 5 KHz, a pulse width of 0 to 50 μsec, and an irradiation pitch of 0 to 100 μm.

[0039] However, the first to third oscillators 101 to 103 of this embodiment output the first to third laser beams L1 to L3 having at least different energies. For example, the first oscillator 101 outputs the first laser beam L1 having an energy of 1.0 J. The second oscillator 102 outputs the second laser beam L2 having an energy of 1.5 J. The third oscillator 103 outputs the third laser beam L3 having an energy of 2.0 J. Note that the first to third laser beams L1 to L3 output from the first to third oscillators 101 to 103 may differ in frequency, pulse width, etc. in addition to energy. Similarly, the first to third laser beams L1 to L3 output from the first to third oscillators 101 to 103 may be the same type of laser or different types of lasers.

[0040] The first to third laser beams L1 to L3 each have a specified spot diameter. Specifically, as described later, the first to third laser beams L1 to L3 are irradiated in sequence along the width direction of the FWD region 2. The first and second laser beams L1 and L2 are irradiated onto the IGBT region 1, and the third laser beam L3 is irradiated onto the FWD region 2. For this reason, the spot diameters of the first and second laser beams L1 and L2 are set shorter than the length of the IGBT region 1 located between adjacent FWD regions 2 in the width direction of the FWD region 2 (hereinafter, also referred to as the interval between adjacent FWD regions 2). The third laser beam L3 is set shorter than the length of the FWD region 2 in the width direction.

[0041] The laser device LS also includes first to third opening / closing members 111 to 113 each configured with a shutter or the like that can be switched between an open state in which the first to third laser beams L1 to L3 are output to the outside and a closed state in which the first to third laser beams L1 to L3 are blocked from being output to the outside. Note that Fig. 4 is a schematic diagram in which the first opening / closing member 111 is in the open state and the second opening / closing member 112 and the third opening / closing member 113 are in the closed state.

[0042] Furthermore, the laser device LS is configured to include a stage 120 on which the semiconductor wafer 100 is placed, a control unit 130, and the like. The laser device LS is configured to allow the first to third laser beams L1 to L3 to move relative to the stage 120 (i.e., the semiconductor wafer 100). The laser device LS may be configured to allow the first to third laser beams L1 to L3 to be scanned by rotating a mirror or the like arranged in the laser device LS.

[0043] The control unit 130 is composed of a microcomputer or the like equipped with a CPU and storage units such as a ROM, RAM, and non-volatile RAM, and is connected to the first to third oscillators 101 to 103, the first to third opening and closing members 111 to 113, and a displacement mechanism (not shown) that displaces the stage 120. The control unit 130 realizes various control operations by the CPU reading and executing programs from the ROM or non-volatile RAM.

[0044] In addition, the ROM or non-volatile RAM stores various data (for example, initial values, lookup tables, maps, etc.) used when executing the program. In this embodiment, the position and width of the FWD region 2, conditions of the first to third laser beams L1 to L3, etc. are appropriately stored as various data. However, although not shown in the figure, an imaging unit or the like capable of recognizing the semiconductor wafer 100 placed on the stage 120 may be provided, and the control unit 130 may recognize the position and width of the FWD region 2, etc. based on the imaging result of the imaging unit. In addition, the storage medium such as the ROM is a non-transient substantial storage medium. CPU is an abbreviation for Central Processing Unit, ROM is an abbreviation for Read Only Memory, and RAM is an abbreviation for Random Access Memory.

[0045] The above is the configuration of the laser device LS. As shown in Fig. 5, the control unit 130 performs laser annealing by irradiating the first to third laser beams L1 to L3 along the arrow A in the figure so that each device formation region R is scanned in order. In this case, as shown in Figs. 6 and 7, the first to third laser beams L1 to L3 are irradiated along the arrow B in the figure in each device formation region R. Note that in Figs. 6 and 7, for ease of understanding, the portion before laser annealing is also shown as the IGBT region 1 or the FWD region 2.

[0046] 6, the first opening / closing member 111 or the second opening / closing member 112 is opened, and the third opening / closing member 113 is closed, and the first laser beam L1 or the second laser beam L2 is irradiated onto the portion that will become the IGBT region 1 to perform laser annealing to form the collector layer 21. Note that in this process, taking into consideration the position and width of the FWD region 2, the entire portion that will become the IGBT region 1 is laser annealed in sequence while preventing the FWD region 2 from being irradiated with the first laser beam L1 and the second laser beam L2.

[0047] In this embodiment, the laser beams are irradiated so as to overlap the portion that will become the IGBT region 1. In this embodiment, the first laser beam L1 and the second laser beam L2 are irradiated in this order, so that the first laser beam L1 and the second laser beam L2 overlap. However, the order in which the first laser beam L1 and the second laser beam L2 are irradiated and the amount of overlap can be changed as appropriate, and are changed as appropriate depending on the impurity concentration of the collector layer 21 and the energy of the first laser beam L1 and the second laser beam L2, etc.

[0048] 7, the third opening / closing member 113 is opened, and the first opening / closing member 111 and the second opening / closing member 112 are closed, and the third laser beam L3 is irradiated onto the portion that will become the FWD region 2, thereby performing laser annealing to form the cathode layer 22. In this step, taking into consideration the position and width of the FWD region 2, the entire portion that will become the FWD region 2 is sequentially laser annealed while preventing the IGBT region 1 from being irradiated with the third laser beam L3. That is, in this embodiment, after laser annealing is performed on the entire portion that will become the IGBT region 1, laser annealing is performed on the entire portion that will become the FWD region 2.

[0049] In this embodiment, the portion that will become the FWD region 2 is irradiated with the third laser beam L3 once along the width direction of the FWD region 2. That is, when performing laser annealing on the portion that will become the FWD region 2, the amount of overlap of the irradiated laser beams is made smaller than that of the laser annealing on the portion that will become the IGBT region 1. In this case, in this embodiment, as described above, the cathode layer 22 has a higher impurity concentration than the collector layer 21. Therefore, the third laser beam L3 has higher energy than the first laser beam L1 and the second laser beam L2 in order to sufficiently activate the cathode layer 22.

[0050] The boundary between the portion that will become the IGBT region 1 and the portion that will become the FWD region 2 may be irradiated with the first laser beam L1 or the second laser beam L2, or may be irradiated with the third laser beam L3. Also, the boundary may be overlapped between the first laser beam L1 or the second laser beam L2 and the third laser beam L3.

[0051] After that, although not shown, lower electrodes 23 are formed, and then the device formation regions R are divided along dicing lines DL, thereby manufacturing the semiconductor device shown in FIG.

[0052] According to the present embodiment described above, the conditions of the first and second laser beams L1, L2 applied to the portion that will become the IGBT region 1 are different from the conditions of the third laser beam L3 applied to the portion that will become the FWD region 2. This makes it possible to adjust the conditions of the laser beams for forming the collector layer 21 and the cathode layer 22 separately, making it easier to give both the collector layer 21 and the cathode layer 22 the desired characteristics.

[0053] (1) In this embodiment, the entire portion that will become the IGBT region 1 is sequentially laser annealed, and then the entire portion that will become the FWD region 2 is sequentially laser annealed. This makes it possible to reduce switching between the first and second laser beams L1, L2 that are irradiated onto the portion that will become the IGBT region 1 and the third laser beam L3 that is irradiated onto the portion that will become the FWD region 2, thereby suppressing an increase in the number of manufacturing steps.

[0054] (2) In this embodiment, the impurity concentration of the cathode layer 22 is higher than that of the collector layer 21. When the portion that will become the FWD region 2 is laser annealed, the overlapping amount of the portion irradiated with the laser beam is made smaller and the energy of the irradiated laser beam is made larger than when the portion that will become the IGBT region 1 is laser annealed. For this reason, it is possible to prevent the impurities constituting the cathode layer 22 from being insufficiently activated, compared to when, for example, the overlapping amount of the portion irradiated with the laser beam is smaller and the energy of the irradiated laser beam is smaller than when the portion that will become the IGBT region 1 is laser annealed.

[0055] Second embodiment A second embodiment will be described. In this embodiment, a mask is disposed in comparison with the first embodiment. As the rest is similar to the first embodiment, a description thereof will be omitted here.

[0056] 8, in this embodiment, when irradiating the portion that will become the IGBT region 1, a first mask 141 is placed to cover the portion that will become the FWD region 2. Similarly, when irradiating the portion that will become the FWD region 2, a second mask 142 is placed to cover the portion that will become the IGBT region 1, as shown in FIG.

[0057] The first mask 141 and the second mask 142 are made of a metal or the like capable of blocking the first to third laser beams L1 to L3. Although Fig. 8 and Fig. 9 are plan views, the first mask 141 or the second mask 142 is hatched for ease of understanding.

[0058] According to the present embodiment described above, the conditions for the first and second laser beams L1 and L2 irradiated onto the portion that will become the IGBT region 1 are different from the conditions for the third laser beam L3 irradiated onto the portion that will become the FWD region 2. Therefore, it is possible to obtain the same effects as in the first embodiment.

[0059] (1) In this embodiment, when the portion that will become the IGBT region 1 is laser annealed, a first mask 141 is disposed to cover the portion that will become the FWD region 2. When the portion that will become the FWD region 2 is laser annealed, a second mask 142 is disposed to cover the portion that will become the IGBT region 1. This makes it possible to prevent the first and second laser beams L1 and L2 from being irradiated onto the FWD region 2 when the portion that will become the IGBT region 1 is laser annealed. Similarly, it makes it possible to prevent the third laser beam L3 from being irradiated onto the IGBT region 1 when the portion that will become the FWD region 2 is laser annealed. This makes it possible to further prevent the collector layer 21 and the cathode layer 22 from deviating from the desired characteristics.

[0060] (Other embodiments) Although the present disclosure has been described based on the embodiment, it is understood that the present disclosure is not limited to the embodiment or structure. The present disclosure also encompasses various modifications and modifications within the equivalent range. In addition, various combinations and forms, as well as other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and concept of the present disclosure.

[0061] For example, in the above first embodiment, a method for manufacturing a semiconductor device in which the first conductivity type is n-type and the second conductivity type is p-type has been described, but the method for manufacturing a semiconductor device in which the first conductivity type is p-type and the second conductivity type is n-type may also be used.

[0062] In each of the above embodiments, when performing laser annealing, the open and closed states of the first to third opening and closing members 111 to 113 may be controlled in detail, and the portion that will become the IGBT region 1 and the portion that will become the FWD region 2 may be alternately laser annealed. That is, for example, along the arrow B in Figures 6 and 7, the portion that will become the IGBT region 1 and the portion that will become the FWD region 2 may be alternately laser annealed. In each of the above embodiments, the entire portion that will become the FWD region 2 may be laser annealed, and then the entire portion that will become the IGBT region 1 may be laser annealed.

[0063] In each of the above embodiments, when laser annealing the portion that will become the FWD region 2, the amount of overlap of the irradiated third laser beam L3 may be greater than that of the laser annealing of the portion that will become the IGBT region 1. In this case, since the n-type impurities are more easily activated by increasing the amount of overlap, the energy of the third laser beam L3 may be smaller than that of the first laser beam L1 and the second laser beam L2.

[0064] Furthermore, in each of the above embodiments, the first to third laser beams L1 to L3 may be CW (abbreviation of Continuous Wave) lasers instead of pulsed lasers.

[0065] In addition, in each of the above embodiments, an example has been described in which a semiconductor device is manufactured using the semiconductor wafer 100. However, in each of the above embodiments, a semiconductor device can also be manufactured using a semiconductor substrate 10 that has been divided into chip units in advance. In this case, the semiconductor substrate 10 corresponds to the workpiece.

[0066] Furthermore, in each of the above embodiments, the number of oscillators and opening / closing members provided in the laser device LS can be changed as appropriate. For example, when laser annealing the FWD region 2, multiple laser beams may be irradiated. Also, when laser annealing the IGBT region 1, one laser beam may be irradiated.

[0067] The control unit and the method described in the present disclosure may be implemented by a special-purpose computer provided by configuring a processor and a memory programmed to execute one or more functions embodied in a computer program. Alternatively, the control unit and the method described in the present disclosure may be implemented by a special-purpose computer provided by configuring a processor with one or more dedicated hardware logic circuits. Alternatively, the control unit and the method described in the present disclosure may be implemented by one or more special-purpose computers configured by a combination of a processor and a memory programmed to execute one or more functions and a processor configured with one or more hardware logic circuits. The computer program may also be stored in a computer-readable non-transitory tangible recording medium as instructions executed by the computer. [Explanation of symbols]

[0068] 1 IGBT area 2 FWD area 21 Collector layer 22 Cathode layer 100 Semiconductor wafers (workpieces) L1~L3 Laser beam

Claims

1. A method for manufacturing a semiconductor device in which an IGBT region (1) having an IGBT element including a collector layer (21) and an FWD region (2) having an FWD element including a cathode layer (22) are formed on a common semiconductor substrate (10), comprising the steps of: preparing a workpiece (100) constituting the semiconductor substrate; ion-implanting a first impurity into a portion of the workpiece that will become the IGBT region to form the collector layer of a first conductivity type that constitutes the IGBT element; ion-implanting a second impurity into a portion of the workpiece that will become the FWD region to form the cathode layer of a second conductivity type that constitutes the FWD element; performing laser annealing by irradiating the workpiece with laser beams (L1 to L3) to activate the first impurity to form the collector layer and activate the second impurity to form the cathode layer; In the laser annealing, the laser beam is irradiated under different conditions to the portion that will become the IGBT region and the portion that will become the FWD region; In the ion implantation of the first impurity and the ion implantation of the second impurity, the first impurity and the second impurity are ion implanted so that an impurity concentration of the cathode layer is higher than an impurity concentration of the collector layer; The irradiating of the laser beam to the portion that will become the IGBT region and the irradiating of the laser beam to the portion that will become the FWD region include irradiating a pulse laser, When the laser beam is irradiated onto the portion that will become the IGBT region, the laser beam is made to overlap with the portion that will become the IGBT region; A method for manufacturing a semiconductor device, in which, when the laser beam is irradiated onto the portion that will become the FWD region, an amount of overlap of the laser beam irradiated onto the portion that will become the IGBT region is smaller than an amount of overlap of the laser beam when the laser beam is irradiated onto the portion that will become the IGBT region, and the energy of the laser beam is greater than that of the laser beam irradiated onto the portion that will become the IGBT region.

2. A method for manufacturing a semiconductor device in which an IGBT region (1) having an IGBT element including a collector layer (21) and an FWD region (2) having an FWD element including a cathode layer (22) are formed on a common semiconductor substrate (10), comprising the steps of: preparing a workpiece (100) constituting the semiconductor substrate; ion-implanting a first impurity into a portion of the workpiece that will become the IGBT region to form the collector layer of a first conductivity type that constitutes the IGBT element; ion-implanting a second impurity into a portion of the workpiece that will become the FWD region to form the cathode layer of a second conductivity type that constitutes the FWD element; performing laser annealing by irradiating the workpiece with laser beams (L1 to L3) to activate the first impurity to form the collector layer and activate the second impurity to form the cathode layer; In the laser annealing, the laser beam is irradiated under different conditions to the portion that will become the IGBT region and the portion that will become the FWD region; In the ion implantation of the first impurity and the ion implantation of the second impurity, the first impurity and the second impurity are ion implanted so that an impurity concentration of the cathode layer is higher than an impurity concentration of the collector layer; The irradiating of the laser beam to the portion that will become the IGBT region and the irradiating of the laser beam to the portion that will become the FWD region include irradiating a pulse laser, When the laser beam is irradiated onto the portion that will become the IGBT region, the laser beam is made to overlap with the portion that will become the IGBT region; A method for manufacturing a semiconductor device, in which, when irradiating the portion that will become the FWD region with the laser beam, an amount of overlap of the laser beam irradiated to the portion that will become the IGBT region is greater than an amount of overlap of the laser beam when irradiating the portion that will become the IGBT region, and the energy of the laser beam is smaller than that of the laser beam irradiated to the portion that will become the IGBT region.

3. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the laser annealing includes performing laser annealing on an entirety of one of the portion that will become the IGBT region and the portion that will become the FWD region, and then performing laser annealing on an entirety of the other of the portion that will become the IGBT region and the portion that will become the FWD region.

4. In order to perform laser annealing on the entirety of one of the portions to be the IGBT region and the portion to be the FWD region, the laser beam is irradiated in a state in which a mask (141) that covers the other portion is placed; 4. The method for manufacturing a semiconductor device according to claim 1, wherein, in performing laser annealing on the entirety of the other of the portion that will become the IGBT region and the portion that will become the FWD region, the laser beam is irradiated in a state in which a mask (142) that covers one of the portions is placed.

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