Logic state determination method and logic state determination circuit

Abstract

To provide a logical state determination method and a logical state determination circuit, capable of determining a logical state without increasing a measurement current limit circuit.SOLUTION: A logical state determination method includes steps for applying a signal to a bus line (6), releasing the signal application to the bus line (6), and determining a logical state for a signal level of the bus line (6) held by a bus hold part (5).SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a logic state determination method and a logic state determination circuit. [Background technology]

[0002] As a conventional technique for distinguishing between the high state, low state, and Hi-Z state in a logic input / output circuit, for example, there is a logic state determination circuit described in Patent Document 1. This circuit uses a measurement current limiting circuit configured with an RC circuit to distinguish the logic state in the logic input / output circuit. Note that the Hi-Z state is an electrically insulated state, and is treated as an open state that is neither a high state nor a low state. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 63-316516 Summary of the Invention [Problem to be solved by the invention]

[0004] A measurement current limiting circuit cannot be configured in a logic input / output circuit such as a microcomputer, a complex programmable logic device (CPLD), or a field programmable gate array (FPGA). For this reason, the logic state determination circuit described in Patent Document 1 requires the addition of a new measurement current limiting circuit for determining the logic state, which poses a problem of increasing the number of components.

[0005] The present disclosure is devised to solve the above-mentioned problems, and has an object to provide a logic state determination method and a logic state determination circuit that can determine a logic state without increasing the number of measurement current limiting circuits. [Means for solving the problem]

[0006] The logic state determination method according to the present disclosure includes the steps of applying a signal to a bus line and releasing the application of the signal to the bus line. Current The signal level of the bus line is held by the bus hold section. , applied in the step of applying a signal to the bus line If the signal level is the same, When it is determined that the signal level of the bus line is high, determining that the state of the bus line is an open state or a pulled up state; The signal applied in the step of applying the signal to the bus line a step of applying a signal having a level different from the previous signal level to the bus line, thereby causing the signal level of the bus line to be reversed from that immediately before, and a step of releasing the application of the signal to the bus line; A step in which the signal level of the bus line is reversed from the previous level The signal level of , current Bus Line of if the signal level is different, determining that the state of the bus line is a pull-down state or a pull-up state according to the signal level applied to the bus line; A step in which the signal level of the bus line is reversed from the previous level The signal level of , current Bus Line of and determining that the bus line is in an open state if the detected signal level is the same as the detected signal level. Effect of the Invention

[0007] According to the present disclosure, a signal is applied to a bus line, the application of the signal to the bus line is released, and the logic state of the signal level of the bus line held by the bus hold unit is determined. In this way, the logic state determination method according to the present disclosure can determine the logic state without adding a measurement current limiting circuit. [Brief description of the drawings]

[0008] [Figure 1] 1 is a block diagram showing a configuration of a logic state determination circuit according to a first embodiment. [Diagram 2] 1 is a circuit diagram showing a circuit (example 1) whose logic state is to be determined by a logic state determination circuit according to a first embodiment. [Diagram 3] 4 is a circuit diagram showing a circuit (example 2) whose logic state is to be determined by the logic state determination circuit according to the first embodiment. FIG. [Figure 4]10 is a circuit diagram showing a circuit (example 3) whose logic state is to be determined by the logic state determination circuit according to the first embodiment. FIG. [Diagram 5] 4 is a flowchart showing a logic state determination method according to the first embodiment. [Figure 6] 4 is a timing diagram showing a logic state determination (example 1) according to the first embodiment. FIG. [Figure 7] 11 is a timing diagram showing a logic state determination (example 2) according to the first embodiment. FIG. [Figure 8] 11 is a timing diagram showing a logic state determination (example 3) according to the first embodiment. FIG. [Figure 9] 11 is a circuit diagram showing a circuit (example 4) whose logic state is to be determined by the logic state determination circuit according to the first embodiment. FIG. [Figure 10] 11 is a circuit diagram showing a circuit (example 5) whose logic state is to be determined by the logic state determination circuit according to the first embodiment. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Embodiment 1 1 is a block diagram showing the configuration of a logic state judgment circuit 1 according to embodiment 1. The logic state judgment circuit 1 is a circuit that judges the logic state of a signal at a measurement point M, and includes a timing control unit 2, a judgment level supply unit 3, a three-state buffer 4, a bus hold unit 5, a bus line 6, a comparison unit 7, and a judgment unit 8.

[0010] The timing control section 2 controls the supply of the evaluation level by the evaluation level supply section 3 to the three-state buffer 4 and the timing of the evaluation by the evaluation section 8. The evaluation level supply section 3 outputs an output signal (OUT) to the three-state buffer 4 and sets an output enable signal (OE). The output signal is a first signal of a high level (hereinafter referred to as H level) or a low level (hereinafter referred to as L level). Similarly, the output enable signal is a second signal of an H level or an L level.

[0011] The three-state buffer 4 receives the output signal output from the evaluation level supplying unit 3, and when an output enable signal is set by the evaluation level supplying unit 3, it applies a signal of a level corresponding to the levels of both signals to the bus line 6. The bus hold unit 5 holds the signal level applied to the bus line 6. The bus line 6 is connected to a measurement point M, and is in the same signal level state as that of the measurement point M.

[0012] The comparator 7 judges whether the signal level of the bus line 6 is H level or L level.

[0013] The determination unit 8 determines whether the state of the bus line 6 is a pull-down state, a pull-up state, or an open state based on the determination result by the comparison unit 7. In addition, the determination unit 8 outputs a signal indicating the determination result of the logical state of the bus line 6.

[0014] The measurement point M, whose logic state is judged by the logic state judgment circuit 1, includes the following circuits. 2 is a circuit diagram showing a circuit (example 1) whose logic state is to be judged by the logic state judgment circuit 1. In FIG. 2, the measurement point M in FIG. 1 is a pull-down resistor R pd 1. The buffer 9 holds an input signal (IN) used to check the state of the bus line 6. The input signal (IN) is a signal that indicates the signal level of the bus line 6.

[0015] 3 is a circuit diagram showing a circuit (example 2) to be judged by the logic state judgment circuit 1. In FIG. 3, the measurement point M in FIG. 1 is a pull-up resistor R pa This is a circuit that pulls up the bus line 6 to the potential of the power supply 11 via.

[0016] Fig. 4 is a circuit diagram showing a circuit (example 3) to be judged by the logic state judgment circuit 1. In Fig. 4, the measurement point M in Fig. 1 is the open end 12 that puts the bus line 6 in an open state.

[0017] In Figures 2, 3 and 4, the three-state buffer 4 has a resistor R b is connected, and the bus line 6 can be put into one of three states: L level, H level, or open state. For example, the three-state buffer 4 enables the output when an H level output enable signal (OE) is set. That is, when an H level output signal (OUT) is input to the three-state buffer 4, the three-state buffer 4 applies an H level signal to the bus line 6, and when an L level output signal (OUT) is input, the three-state buffer 4 applies an L level signal to the bus line 6. Also, when an L level output enable signal is set, the three-state buffer 4 sets the output to an open state. Note that when the output is enabled, a current I b is the drive current.

[0018] The bus hold unit 5 operates to output a high-level signal when the state of the bus line 6 is high, and to output a low-level signal when the state of the bus line 6 is low. The bus hold unit 5 is composed of two inverters whose input and output terminals are connected to each other, and a resistor R h is connected.

[0019] The effect of the bus hold section 5 on the state of the bus line 6 is determined by the resistance R h Current I flows through a high resistance h This is reduced by making the holding current very small. As a result, even if the element (measurement point M) that drives the bus line 6 is opened, the bus hold section 5 holds the level of the bus line 6 just before it was opened.

[0020] current I pd is the pull-down resistor R pd This is the upper limit of the current flowing through the pull-down resistor R pd is R h >>R pd >>R b And I b >>Ipd >>I h In other words, the pull-down resistor R pd The holding current I h The drive current I of the three-state buffer 4 must be set to a value that can cancel out the current b A value that is not affected by is selected.

[0021] current I pa is the pull-up resistor R pa This is the minimum current value required to keep the signal level of the bus line 6 at the H level. pa is R h >>R pa >>R b And I b >>I pa >>I h In other words, the pull-up resistor R pa The holding current I h The drive current I of the three-state buffer 4 must be set to a value that can cancel out the current b In addition, at the open end 12 shown in FIG. h >>R b The relationship holds.

[0022] The logic state determination method according to the first embodiment is as follows. Fig. 5 is a flowchart showing a logic state determination method according to the embodiment 1. Fig. 6 is a timing chart showing a logic state determination (example 1) according to the embodiment 1. The determination level supplying unit 3 outputs an H-level output signal (OUT) and an H-level output enable signal (OE) to the three-state buffer 4 in the period (1) of Fig. 6 under the control of the timing control unit 2 (step ST1).

[0023] Next, under the control of the timing control section 2, the evaluation level supply section 3 sets the output enable signal (OE) of L level to the three-state buffer 4 during the period (2) in FIG. 6 (step ST2). Note that the output signal (OUT) is not specified to be H level or L level. As a result, the three-state buffer 4 is disabled from output and is in the open state (I b ≈0. Next, the comparator 7, under the control of the timing controller 2, determines whether the input signal (IN) is at the H level or the L level (step ST3).

[0024] At the timing A when the state of the bus line 6 is determined, if the result that the input signal (IN) is at the L level (step ST3; Low), the determination unit 8 determines that the measurement point M is in a pull-down connection (step ST4). If the measurement point M is at the L level, a current I pd Since the current flowing through the bus line 6 is not sufficient to maintain the H level, it is determined that the state of the bus line 6 has become L level. b The current I b is almost 0 (I b ≒0), the current when bus line 6 is at the L level is I pd The current has the following value:

[0025] 7 is a timing diagram showing a logic state determination (example 2) according to the first embodiment. When the signal (IN) is at H level during the period (2) in FIG. 7 (step ST3; High), the bus hold unit 5 can maintain the H level state of the bus line 6 (timing B). That is, the bus line 6 is not pulled down. When the bus line 6 is not pulled down, it is in an open state (Hi-Z) or in a pulled-up state.

[0026] 7(3) to the three-state buffer 4 (step ST5). When the output enable signal (OE) of the three-state buffer 4 is set to the H level, the output of the three-state buffer 4 is enabled, but since the output signal (OUT) is at the L level, the L level state opposite to that immediately before is applied to the bus line 6.

[0027] Next, the evaluation level supplying section 3 sets the output enable signal (OE) of L level to the three-state buffer 4 during the period (4) in FIG. 7 under the control of the timing control section 2 (step ST6). The output signal (OUT) is not regulated to be H level or L level. As a result, the three-state buffer 4 is disabled from output and is in the open state (I b ≈0. Next, the comparator 7, under the control of the timing controller 2, determines whether the input signal (IN) is at the H level or the L level (step ST7).

[0028] At the timing C when the state of the bus line 6 is determined, if the input signal (IN) is found to be at H level (step ST7; High), the determination unit 8 determines that the measurement point M is in a pull-up connection (step ST8). If the measurement point M is at H level, the bus hold unit 5 is unable to maintain the L level of the bus line 6, and therefore the state of the bus line 6 is determined to be a current I h The current I pa The following current is used to determine the H level: b The current I b is almost 0 (I b ≒0), the current that makes bus line 6 high level is I h That's all I pa The current has the following value:

[0029] 8 is a timing diagram showing a logic state determination (example 3) according to the first embodiment. In the period (4) of FIG. 8, when the input signal (IN) is at L level, the bus hold unit 5 can maintain the L level of the bus line 6. That is, the bus line 6 receives a pull-up current I pa Since the bus line 6 is not at the H level due to the above, it can be determined that it is not pulled up. Since it is determined in step ST3 that the bus line 6 is in an open state (Hi-Z) or a pulled-up state, if it is not in a pulled-up state, it can be determined that it is in an open state (Hi-Z).

[0030] At timing D, when the result that the input signal (IN) is at L level (step ST7; Low), the determining section 8 determines that the measurement point M is in an open state (Hi-Z) (step ST9).

[0031] During the period (1) of Fig. 6, the period (1) of Fig. 7, and the period (1) of Fig. 8, the judgment level supplying unit 3 may set an H-level output enable signal (OE) to the three-state buffer 4 and cause the three-state buffer 4 to input an L-level output signal (OUT), or during the period (3) of Fig. 7 and the period (3) of Fig. 8, the judgment level supplying unit 3 may set an H-level output enable signal (OE) to the three-state buffer 4 and cause the three-state buffer 4 to input an H-level output signal (OUT). In this case, the judgment unit 8 judges the logic state of the measurement point M during the period (2) of Fig. 6, the period (4) of Fig. 7, or the period (4) of Fig. 8.

[0032] Fig. 9 is a circuit diagram showing a circuit (example 4) whose logic state is to be judged by the logic state judgment circuit 1. In Fig. 9, switch 13 is a measurement point M, and switches to either a circuit that pulls down bus line 6 to ground 10, a circuit that pulls up bus line 6 to the potential of power supply 11, or an open end 12 that puts bus line 6 in an open state. The logic state of the circuit switched by switch 13 is judged by the series of processes shown in Fig. 5.

[0033] Fig. 10 is a circuit diagram showing a circuit (example 5) whose logic state is to be judged by the logic state judgment circuit 1. In Fig. 10, when the jumper switch 14a is turned on, it connects to the bus line 6 a circuit that pulls up the bus line 6 to the potential of the power source 11, and when it is turned off, it disconnects the pull-up connection from the bus line 6. When the jumper switch 14b is turned on, it connects to the bus line 6 a circuit that pulls down the bus line 6 to the ground 10, and when it is turned off, it disconnects the pull-down connection from the bus line 6.

[0034] When the jumper switches 14a and 14b are both off, the end of the bus line 6 becomes an open end 12. The logical state of the circuit switched by the jumper switches 14a and 14b is determined by a series of processes shown in FIG.

[0035] As described above, the logic state determination method according to the first embodiment applies a signal to the bus line 6, releases the signal application to the bus line 6, and determines the signal level of the bus line 6 held in the bus hold unit 5 to determine whether the state of the measurement point M is in a pull-up state, a pull-down state, or an open state (Hi-Z). In this way, the logic state determination method according to the first embodiment can determine the logic state without adding a measurement current limiting circuit.

[0036] Any of the components of the embodiments may be modified or omitted. [Explanation of symbols]

[0037] 1 logic state judgment circuit, 2 timing control section, 3 judgment level supply section, 4 three-state buffer, 5 bus hold section, 6 bus line, 7 comparison section, 8 judgment section, 9 buffer, 10 ground, 11 power supply, 12 open end, 13 switch, 14a, 14b jumper switches.

Claims

1. applying a signal to a bus line; releasing the application of a signal to the bus line; a step of determining that the state of the bus line is an open state or a pull-up state when it is determined that the signal level of the bus line is a high level if the current signal level of the bus line is held in a bus hold unit and is the same as the signal level applied in the step of applying a signal to the bus line; a step of applying a signal to the bus line at a level different from the signal level applied in the step of applying a signal to the bus line, thereby causing the signal level of the bus line to be reversed from that immediately before; releasing the application of a signal to the bus line; a step of determining that the state of the bus line is a pull-down state or a pull-up state according to the signal level applied to the bus line when the signal level in the step of changing the signal level of the bus line to a level opposite to that immediately before is different from the current signal level of the bus line; determining that the bus line is in an open state when the signal level in the step of changing the signal level of the bus line to a level opposite to that immediately before is the same as the current signal level of the bus line; A method for determining a logic state comprising:

2. a bus hold section for holding a signal level applied to a bus line; a three-state buffer that receives a first signal and a second signal, and applies a signal having a level according to values ​​of the first signal and the second signal to the bus line; a decision level supply unit that outputs the first signal to the three-state buffer and sets the second signal; a determination unit that determines whether the logic state of the bus line is a pull-down state, a pull-up state, or an open state; Equipped with The three-state buffer is performing a step of applying a signal to the bus line; Next, a step of releasing the application of signals to the bus line is performed; The determination unit is execute a step of determining that the state of the bus line is an open state or a pull-up state when it is determined that the signal level of the bus line is a high level if the current signal level of the bus line is held in the bus hold unit and is the same as the signal level applied in the step of applying a signal to the bus line; The three-state buffer is Next, a step of applying a signal to the bus line at a level different from the signal level applied in the step of applying a signal to the bus line, and changing the signal level of the bus line to a level opposite to that immediately before is executed; performing a step of releasing the application of a signal to the bus line; The determination unit is execute a step of determining that the state of the bus line is a pull-down state or a pull-up state according to the signal level applied to the bus line, when the signal level in the step of changing the signal level of the bus line executed by the three-state buffer to a level opposite to that immediately before is different from the current signal level of the bus line; If the signal level of the step of changing the signal level of the bus line by the three-state buffer to a level opposite to that immediately before is the same as the current signal level of the bus line, a step of determining that the bus line is in an open state is performed. A logic state determination circuit comprising:

3. A switch for switching between the presence or absence of a pull-up resistor or a pull-down resistor is connected to the bus line.

3. The logic state determination circuit according to claim 2, wherein:

4. A jumper switch for switching between the presence or absence of a pull-up resistor or a pull-down resistor is connected to the bus line.

3. The logic state determination circuit according to claim 2, wherein:

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