Semiconductor device and its manufacturing method

Abstract

To provide a semiconductor device capable of securing sufficient voltage resistance in the vicinity of a termination of a cell part, and a manufacturing method thereof.SOLUTION: A cell part CEL includes: a first cell column region CL and a second cell column region CL which are adjacent to each other; and a first cell trench gate GE and a second cell trench gate GE which are disposed between the first cell column region CL and the second cell column region CL. An outside part PER includes: an outer peripheral trench gate GET connected to ends of the first cell trench gate GE and the second cell trench gate GE; and a first outer peripheral column region PC1 which is disposed at the side of the cell part CEL with respect to the outer peripheral trench gate GET and extends over the first cell trench gate GE and the second cell trench gate GE in a planar view.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof, and can be suitably used for a semiconductor device having an insulated gate field effect transistor, for example, and a manufacturing method thereof. [Background technology]

[0002] A vertical insulated gate field effect transistor having a superjunction structure (hereinafter referred to as an SJ structure) is a power semiconductor device that controls high voltage and large current. It is desirable for this semiconductor device to have a low on-resistance and a high breakdown voltage. A semiconductor device having a vertical insulated gate field effect transistor and an SJ structure is disclosed, for example, in JP 2021-82770 A (Patent Document 1).

[0003] In Patent Document 1, multiple trench gates are provided between two adjacent p-type column regions in a vertical insulated gate field effect transistor having an SJ structure. By providing multiple trench gates, the current path during on-state is increased, which is expected to reduce the on-resistance. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent Publication No. 2021-82770 Summary of the Invention [Problem to be solved by the invention]

[0005] However, in the structure described in Patent Document 1, there are areas near the end of the cell section that are not locally depleted, making it impossible to ensure a sufficient breakdown voltage near the end of the cell section.

[0006] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0007] A semiconductor device according to one embodiment includes a cell section having an insulated gate field effect transistor and an outer section located outside the cell section. The cell section includes a first cell column region and a second cell column region adjacent to each other, and a first cell trench gate and a second cell trench gate disposed between the first cell column region and the second cell column region. The outer section includes a peripheral trench gate connected to each end of the first cell trench gate and the second cell trench gate, and a first peripheral column region disposed on the cell section side with respect to the peripheral trench gate and extending across the first cell trench gate and the second cell trench gate in a plan view.

[0008] A semiconductor device according to another embodiment includes a cell portion having an insulated gate field effect transistor and an outer portion located outside the cell portion. The cell portion includes a first cell column region and a second cell column region adjacent to each other, and a first cell trench gate and a second cell trench gate disposed between the first cell column region and the second cell column region. The outer portion includes a peripheral trench gate connected to each end of the first cell trench gate and the second cell trench gate, and a peripheral column region disposed directly below the peripheral trench gate.

[0009] According to a method for manufacturing a semiconductor device according to one embodiment, a first cell trench gate and a second cell trench gate adjacent to each other in a plan view are formed in a cell portion, and a peripheral trench gate connected to each end of the first cell trench gate and the second cell trench gate in a plan view is formed in an outer portion. A first cell column region and a second cell column region sandwiching the first cell trench gate and the second cell trench gate in a plan view are formed in a semiconductor substrate of the cell portion, and a peripheral column region is formed in the semiconductor substrate in the outer portion on the cell portion side with respect to the peripheral trench gate. The peripheral column region is formed to extend across the first cell trench gate and the second cell trench gate in a plan view.

[0010] According to a manufacturing method of a semiconductor device according to another embodiment, a first cell trench gate and a second cell trench gate adjacent to each other in a plan view are formed in a cell portion, and a peripheral trench gate connected to each end of the first cell trench gate and the second cell trench gate in a plan view is formed in an outer portion. A first cell column region and a second cell column region sandwiching the first cell trench gate and the second cell trench gate in a plan view are formed in a semiconductor substrate of the cell portion, and a peripheral column region is formed in the semiconductor substrate in the outer portion directly below the peripheral trench gate. Effect of the Invention

[0011] According to the above embodiment, it is possible to realize a semiconductor device capable of ensuring a sufficient breakdown voltage near the end of the cell section, and a method for manufacturing the same. [Brief description of the drawings]

[0012] [Figure 1] 1 is a plan view showing a configuration of a semiconductor device according to a first embodiment in a chip state. [Diagram 2] 2 is an enlarged plan view showing a region II in FIG. 1. [Diagram 3] 3A is a cross-sectional view taken along line IIIA-IIIA in FIG. 2, FIG. 3B is a cross-sectional view taken along line IIIB-IIIB, and FIG. 3C is a cross-sectional view taken along line IIIC-IIIC in FIG. [Figure 4] 2 is a cross-sectional view showing a first step of the method for manufacturing the semiconductor device according to the first embodiment. [Diagram 5] 5 is a cross-sectional view showing a second step of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 6] 5 is a cross-sectional view showing a third step of the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 7] 5 is a cross-sectional view showing a fourth step of the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 8] 5 is a cross-sectional view showing a fifth step of the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 9]FIG. 1 is a plan view showing a configuration of a semiconductor device according to a first comparative example. [Figure 10] FIG. 10 is a cross-sectional view taken along line XX in FIG. [Figure 11] FIG. 11 is a plan view showing a configuration of a semiconductor device according to Comparative Example 2. [Figure 12] 12 is a cross-sectional view taken along line XII-XII in FIG. 11. [Figure 13] 3 is a diagram showing a state in which a depletion layer extends in a cross section taken along line IIIB-IIIB in FIG. 2. [Figure 14] FIG. 11 is a plan view showing the configuration of a semiconductor device according to a second embodiment in a chip state. [Figure 15] 15 is an enlarged plan view of region XV in FIG. 14. FIG. [Figure 16] 16A is a cross-sectional view taken along line XVIA-XVIA in FIG. 15, FIG. 16B is a cross-sectional view taken along line XVIB-XVIB, and FIG. 16C is a cross-sectional view taken along line XVIC-XVIC in FIG. [Figure 17] 10 is a cross-sectional view showing a first step of a method for manufacturing a semiconductor device according to a second embodiment. [Figure 18] 10 is a cross-sectional view showing a second step of the method for manufacturing a semiconductor device according to the second embodiment. [Figure 19] 10 is a cross-sectional view showing a third step of the method for manufacturing the semiconductor device according to the second embodiment. FIG. [Figure 20] 16 is a diagram showing how a depletion layer extends in a cross section taken along line XVIB-XVIB in FIG. 15. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Hereinafter, the embodiments of the present disclosure will be described in detail with reference to the drawings. In the specification and drawings, the same or corresponding components are denoted by the same reference numerals, and redundant explanations will not be repeated. In addition, in the drawings, for convenience of explanation, the configuration or manufacturing method may be omitted or simplified. In addition, at least a part of each embodiment may be arbitrarily combined with each other.

[0014] The semiconductor device in the embodiments described below is not limited to a semiconductor chip, but may be a semiconductor wafer before being divided into semiconductor chips, or may be a semiconductor package in which the semiconductor chip is sealed with resin. In addition, a plan view in this specification means a viewpoint seen from a direction perpendicular to the main surface (first surface FS) of the semiconductor substrate.

[0015] (Embodiment 1) <Configuration of Semiconductor Device in Chip State> First, the configuration of the semiconductor device according to the first embodiment in a chip state will be described with reference to FIG.

[0016] As shown in Fig. 1, the semiconductor device SC according to the first embodiment is a power semiconductor device. The semiconductor device SC has a vertical insulated gate field effect transistor having an SJ structure. The insulated gate field effect transistor is, for example, a MOS (Metal Oxide Semiconductor) transistor. However, the gate insulating film of the insulated gate field effect transistor is not limited to a silicon oxide film, and may be another insulating film. Therefore, the insulated gate field effect transistor may be a MIS (Metal Insulator Semiconductor) transistor.

[0017] The semiconductor device SC has a cell part CEL and an outer part PER in a plan view. The cell part CEL has an insulated gate field effect transistor. The insulated gate field effect transistor has a plurality of cell trench gates GE and a plurality of cell column regions CL.

[0018] The multiple cell column regions CL run side by side by extending in the same direction in a plan view. The multiple cell trench gates GE run side by side by extending in the same direction in a plan view. In a plan view, the direction in which each of the multiple cell trench gates GE extends is the same as the direction in which each of the multiple cell column regions CL extends.

[0019] The multiple cell column regions CL have a first cell column region CL and a second cell column region CL adjacent to each other in a plan view. The multiple cell trench gates GE have a first cell trench gate GE and a second cell trench gate GE arranged between the first cell column region CL and the second cell column region CL adjacent to each other. Note that three or more cell trench gates GE may be arranged between the first cell column region CL and the second cell column region CL adjacent to each other.

[0020] The semiconductor device SC has a source electrode SE. The source electrode SE is electrically connected to a source region of the insulated gate field effect transistor. The source electrode SE is arranged so as to overlap the cell portion CEL in a plan view. In FIG. 1, the cell portion CEL is provided in a region surrounded by a dashed line marked with the symbol CEL.

[0021] The outer portion PER is located outside the cell portion CEL in a plan view. The outer portion PER surrounds the outer periphery of the cell portion CEL in a plan view. The outer portion PER has a plurality of outer peripheral column regions PC1, PC2, PC3, and PC4 and an outer peripheral trench gate GET. In FIG. 1, the outer portion PER is a region surrounded by a dashed line with the symbol PER and a dashed line with the symbol CEL.

[0022] The outer circumferential column regions PC1, PC2, PC3, and PC4 are arranged so as to surround the entire outer circumferential circumference of the cell unit CEL in a plan view. The outer circumferential column regions PC1, PC2, PC3, and PC4 are arranged in this order from the inner circumferential side to the outer circumferential side. In other words, of the outer circumferential column regions PC1, PC2, PC3, and PC4, the outer circumferential column region PC1 is located on the innermost side, and the outer circumferential column region PC4 is located on the outermost side.

[0023] The peripheral trench gate GET is connected to the end of each of the multiple cell trench gates GE in a plan view. The peripheral trench gate GET is electrically connected to the gate electrode wiring GEL through a conductive layer BC2. The conductive layer BC2 fills a contact hole CH2 provided in an interlayer insulating layer (not shown).

[0024] The gate electrode wiring GEL has a ring shape in a plan view and is arranged so as to surround the periphery of the source electrode SE. The gate electrode wiring GEL has a gate electrode pad GP for connection to the outside. The gate electrode wiring GEL is arranged in a region surrounded by two dashed lines in FIG.

[0025] The peripheral column region PC1 (first peripheral column region) extends continuously and uninterrupted over the entire direction in which the peripheral trench gate GET extends (the longitudinal direction of the peripheral trench gate GET in plan view) in plan view. The peripheral column region PC1 extends over the entire width direction of the cell unit CEL in plan view. The width direction of the cell unit CEL in the above description is the direction in which the multiple cell trench gates GE are lined up and the direction in which the peripheral trench gate GET extends.

[0026] The periphery column region PC2 (second periphery column region) sandwiches the periphery trench gate GET between itself and the periphery column region PC1 in plan view. The periphery column region PC2 extends continuously and uninterrupted over the entire direction in which the periphery trench gate GET extends in plan view. The periphery column region PC2 extends over the entire width direction of the cell unit CEL in plan view. As a result, the periphery trench gate GET is sandwiched between the periphery column region PC1 and the periphery column region PC2 over the entire length direction in plan view.

[0027] 2, the peripheral column region PC1 is disposed on the cell unit CEL side with respect to the peripheral trench gate GET in a plan view. The peripheral column region PC1 extends across the multiple cell trench gates GE in a plan view. That is, the peripheral column region PC1 intersects with each of the multiple cell trench gates GE in a plan view.

[0028] 3A, the semiconductor substrate SB has a first surface FS (main surface) and a second surface SS. The first surface FS and the second surface SS face each other. The semiconductor substrate SB is made of, for example, single crystal silicon.

[0029] An insulated gate field effect transistor is formed on the semiconductor substrate SB in the cell unit CEL. The insulated gate field effect transistor is a vertical transistor that passes a current between a first surface FS and a second surface SS of the semiconductor substrate SB.

[0030] Insulated gate field effect transistors are + A drain region DR, an n-type drift region DRI, a p-type base region BA, and a p + Contact area CR and n + It has a source region SR, a p-type cell column region CL, and a cell trench gate GE.

[0031] n + The drain region DR is disposed on the second surface of the semiconductor substrate SB. The n-type drift region DRI is + It is disposed on the first surface FS side with respect to the drain region DR, and n + The n-type drift region DRI is in contact with the drain region DR. + It has an n-type impurity concentration lower than the n-type impurity concentration of the drain region DR.

[0032] The p-type base region BA is disposed on the first surface FS side with respect to the n-type drift region DRI, and forms a pn junction with the n-type drift region DRI. + The contact region CR is in contact with the p-type base region BA.+ The contact region CR has a p-type impurity concentration higher than the p-type impurity concentration of the p-type base region BA. + The source region SR forms a pn junction with the p-type base region BA, and is disposed on the first surface FS of the semiconductor substrate SB.

[0033] The p-type cell column region CL is connected to the p-type base region BA at the end of the p-type base region BA on the second surface SS side. The p-type cell column region CL extends from the end of the p-type base region BA on the second surface SS side toward the second surface SS. As a result, the p-type cell column region CL protrudes from the end of the p-type base region BA on the second surface SS side to the second surface SS. The p-type cell column region CL forms a pn junction with the n-type drift region DRI. The p-type cell column region CL has a p-type impurity concentration that is approximately the same as the p-type impurity concentration of the p-type base region BA. The p-type cell column region CL extends to a position closer to the second surface SS than the cell trench gate GE. By the protrusion of a plurality of p-type cell column regions CL into the n-type drift region DRI, a periodically repeated structure of p-type regions and n-type regions is formed, and an SJ structure is formed.

[0034] The semiconductor substrate SB has a cell trench TR1 in the first surface FS. The cell trench TR1 is n + The cell trench TR1 is formed of a gate insulating layer GI, which penetrates through the source region SR and the p-type base region BA to reach the n-type drift region DRI. The gate insulating layer GI is disposed along the wall surface of the cell trench TR1. The gate insulating layer GI is made of, for example, a silicon oxide film, but is not limited to this.

[0035] The cell trench gate GE fills the cell trench TR1. The cell trench gate GE is made of, for example, polycrystalline silicon (doped polysilicon) doped with impurities. The cell trench gate GE faces the p-type base region BA via a gate insulating layer GI. A plurality of (for example, two) cell trench gates GE are disposed between adjacent p-type cell column regions CL.

[0036] An interlayer insulating layer II is disposed on the first surface FS of the semiconductor substrate SB. The interlayer insulating layer II is made of, for example, a silicon oxide film. The interlayer insulating layer II has a boro-phosphosilicate glass (BPSG) film formed using tetra ethyl ortho silicate (TEOS) as a raw material.

[0037] A contact hole CH1 is provided in the interlayer insulating layer II. The contact hole CH1 penetrates the interlayer insulating layer II and reaches the semiconductor substrate SB. The contact hole CH1 has a bottom located closer to the second surface SS side than the first surface FS of the semiconductor substrate SB. + A contact region CR is arranged.

[0038] A conductive layer BC1 is buried in the contact hole CH1. The conductive layer BC1 has an n + Source regions SR and p + The conductive layer BC1 is connected to each of the contact regions CR. The conductive layer BC1 includes a barrier metal layer and a buried conductive layer. The barrier metal layer is formed along the wall surface of each of the contact holes CH1 and CH2 and is made of, for example, a laminated film of titanium (Ti) and titanium nitride (TiN). The buried conductive layer fills the inside of each of the contact holes CH1 and CH2. The buried conductive layer is made of, for example, tungsten (W).

[0039] A source electrode SE is disposed on the interlayer insulating layer II. The source electrode SE is connected to the n-type ... + Source regions SR and p + It is electrically connected to each of the contact regions CR.

[0040] A drain electrode DE is disposed on the second surface SS of the semiconductor substrate SB. The drain electrode DE has an n + By contacting the drain region DR, + It is electrically connected to the drain region DR.

[0041] 3B, the peripheral trench TR2 located in the outer portion PER extends from the first surface FS of the semiconductor substrate SB through the p-type base region BA to the n-type drift region DRI. A gate insulating layer GI is disposed along the wall surface of the peripheral trench TR2. The gate insulating layer GI is made of, for example, a silicon oxide film, but is not limited to this.

[0042] The peripheral trench gate GET fills the peripheral trench TR2 and is made of, for example, doped polysilicon.

[0043] In the outer portion PER, each of the peripheral column regions PC1, PC2 is connected to the p-type base region BA at an end portion on the second surface SS side of the p-type base region BA. Each of the peripheral column regions PC1, PC2 extends from an end portion on the second surface SS side of the p-type base region BA toward the second surface SS. As a result, each of the peripheral column regions PC1, PC2 protrudes from an end portion on the second surface SS side of the p-type base region BA toward the second surface SS. Each of the peripheral column regions PC1, PC2 forms a pn junction with the n-type drift region DRI. Each of the peripheral column regions PC1, PC2 has a p-type impurity concentration that is approximately the same as the p-type impurity concentration of the p-type base region BA.

[0044] Although not shown, each of the outer circumferential column regions PC3 and PC4 has a configuration similar to that of the outer circumferential column regions PC1 and PC2.

[0045] The periphery trench gate GET is disposed between the adjacent periphery column regions PC1, PC2. Each of the periphery column regions PC1, PC2 extends to a position closer to the second surface SS than the periphery trench TR2 in which the periphery trench gate GET is embedded. In other words, the end of each of the periphery column regions PC1, PC2 on the second surface SS side is located closer to the second surface SS than the end of the periphery trench TR2 on the second surface SS side.

[0046] A contact hole CH2 is provided in the interlayer insulating layer II on the first surface FS of the semiconductor substrate SB. The contact hole CH2 penetrates the interlayer insulating layer II to reach the semiconductor substrate SB. The contact hole CH2 has a bottom located closer to the second surface SS side than the first surface FS of the semiconductor substrate SB. The contact hole CH1 reaches the peripheral trench gate GET.

[0047] A conductive layer BC2 is buried in the contact hole CH2. The conductive layer BC2 is connected to the outer periphery trench gate GET. The conductive layer BC2 has a similar structure to the conductive layer BC1.

[0048] A gate electrode wiring GEL is disposed on the interlayer insulating layer II. The gate electrode wiring GEL is electrically connected to the peripheral trench gate GET via a conductive layer BC2.

[0049] 3C, in the outer portion PER, the outer circumferential column region PC1 extends across a plurality of cell trench gates GE. The outer circumferential column region PC1 extends to a position closer to the second surface SS than the cell trench TR1 in which the cell trench gate GE is embedded. In other words, the end of the outer circumferential column region PC1 on the second surface SS side is located closer to the second surface SS than the end of the cell trench TR1 on the second surface SS side. Therefore, the outer circumferential column region PC1 contacts the bottom surface of the cell trench TR1.

[0050] <Method of Manufacturing Semiconductor Device> Next, a method for manufacturing the semiconductor device of this embodiment will be described with reference to FIGS. 3(A) and 3(B) to 8(A) and 8(B).

[0051] 4A and 4B, a semiconductor substrate SB is first prepared. A plurality of cell trenches TR1 and a plurality of peripheral trenches TR2 are formed on a first surface FS of the semiconductor substrate SB. The plurality of cell trenches TR1 are formed to run parallel to each other in a plan view. The peripheral trench TR2 is formed to be connected to the ends of each of the plurality of cell trenches TR1 in a plan view.

[0052] A gate insulating layer GI is formed on each wall surface of the cell trench TR1 and the peripheral trench TR2. A cell trench gate GE is formed in the cell trench TR1, and a peripheral trench gate GET is formed in the peripheral trench TR2. The multiple cell trench gates GE are formed to have a first cell trench gate GE and a second cell trench gate GE adjacent to each other in a planar view. The peripheral trench gate GET is formed to be connected to the end of each of the multiple cell trench gates GE in a planar view.

[0053] Thereafter, a p-type base region BA is formed on the first surface FS of the semiconductor substrate SB. The p-type base region BA is formed shallower than each of the cell trench TR1 and the peripheral trench TR2.

[0054] 5A and 5B, n-type impurities such as arsenic are ion-implanted into the first surface FS of the semiconductor substrate SB in the cell unit CEL. + A source region SR is formed.

[0055] 6A and 6B, a silicon oxide film IL1, a silicon nitride film IL2, a silicon oxide film IL3, and a silicon oxide film IL4 are laminated in this order on a first surface FS of a semiconductor substrate SB. A photoresist PR1 is applied onto the silicon oxide film IL4. After that, the photoresist PR1 is patterned by photolithography (exposure, development, etc.).

[0056] Using the patterned photoresist PR1 as a mask, the silicon oxide films IL4 and IL3 are plasma etched, whereby the silicon oxide films IL4 and IL3 are selectively etched away, exposing a part of the silicon nitride film IL2.

[0057] In this state, p-type impurities such as boron are ion-implanted from the first surface FS side of the semiconductor substrate SB. As a result, a plurality of cell column regions CL are formed in the cell portion CEL, and a plurality of peripheral column regions PC1-PC4 are formed in the outer portion PER. In a plan view, the adjacent cell column regions CL are formed in the semiconductor device SB so as to sandwich, for example, two cell trench gates GE. Furthermore, the peripheral column region PC1 is formed on the cell portion CEL side of the peripheral trench gate GET. The adjacent peripheral column regions PC1, PC2 are formed so as to sandwich the peripheral trench gate GET. Furthermore, the peripheral column region PC1 is formed so as to extend across the multiple cell trench gates GE.

[0058] Thereafter, the photoresist PR1 is stripped and removed, the silicon oxide films IL4 and IL3 are removed by etching, and the silicon nitride film IL2 is removed by wet etching.

[0059] Thereafter, for example, a BPSG film formed using TEOS as a raw material is formed on the silicon oxide film IL1.

[0060] As shown in FIGS. 7A and 7B, an interlayer insulating layer II is formed on the first surface FS of the semiconductor substrate SB from a silicon oxide film IL1, a BPSG film, and the like.

[0061] As shown in Figures 8A and 8B, contact holes CH1 and CH2 are formed in the interlayer insulating layer II by photolithography and etching. The contact hole CH1 not only penetrates the interlayer insulating layer II, but also + The contact hole CH2 is formed so as to penetrate the source region SR and reach the p-type base region BA. The contact hole CH2 is formed so as to penetrate the interlayer insulating layer II and reach the peripheral trench gate GET.

[0062] Thereafter, boron fluoride is ion-implanted into the semiconductor substrate SB through the contact hole CH1. + A contact region CR is formed.

[0063] As shown in Figures 3(A) and (B), conductive layers BC1 and BC2 are formed in the contact holes CH1 and CH2, respectively. Each of the conductive layers BC1 and BC2 includes a barrier metal layer and a buried conductive layer. The barrier metal layer is formed along the wall surface of each of the contact holes CH1 and CH2 and is made of, for example, a laminated film of titanium and titanium nitride. The buried conductive layer fills the inside of each of the contact holes CH1 and CH2. The buried conductive layer is made of, for example, tungsten.

[0064] A conductive layer made of, for example, aluminum or aluminum-copper is formed on the interlayer insulating layer II. This conductive layer is patterned by photolithography and etching techniques. As a result, a source electrode SE and a gate electrode wiring GEL are formed from the conductive layer. The source electrode SE is connected to an n-type semiconductor layer BC1 via a conductive layer BC1. + Source regions SR and p + The gate electrode wiring GEL is electrically connected to each of the contact regions CR. The gate electrode wiring GEL is electrically connected to the outer periphery trench gate GET with a conductive layer BC2 interposed therebetween.

[0065] In this manner, the semiconductor device according to this embodiment shown in FIG. 3 is manufactured. <Effects> Next, the effects of this embodiment will be described in comparison with Comparative Example 1 shown in FIGS. 9 and 10 and Comparative Example 2 shown in FIGS.

[0066] Comparative Example 1 shown in Fig. 9 has the configuration shown in Fig. 23 of Patent Document 1. In Comparative Example 1 shown in Fig. 9, the ends of two cell trench gates GE sandwiched between adjacent cell column regions CL are connected by a termination trench gate GET.

[0067] In the configuration of Comparative Example 1, the cell column region CL is not arranged on the cell section side of the termination trench gate GET. Also, the distance L between the center position of the two cell trench gates GE and the cell column region CL is relatively large. Therefore, if the line width of the cell column region CL varies, as shown in Figure 10, the depletion layer DL is less likely to extend near the cell section side of the peripheral trench gate GET, which makes it easier for electric field concentration to occur and the breakdown voltage to decrease.

[0068] Comparative Example 2 shown in Fig. 11 has the configuration shown in Fig. 9 and Fig. 18 of Patent Document 1. In Comparative Example 2 shown in Fig. 11, a plurality of dot column regions PCL are arranged between the cell column region CL and the peripheral trench gate GET. In addition, a plurality of dot column regions PCL are also arranged on the outer periphery side of the peripheral trench gate GET.

[0069] In the configuration of Comparative Example 2, the dot column regions PCL are arranged in a scattered manner on the cell portion side of the peripheral trench gate GET. Therefore, if the planar dimensions of the dot column regions PCL vary, the depletion layer DL is less likely to extend near the peripheral trench gate GET away from the dot column regions PCL as shown in FIG. 12, which makes it easier for electric field concentration to occur and reduces the breakdown voltage.

[0070] As described above, in both Comparative Examples 1 and 2, the depletion layer DL is unlikely to extend near the peripheral trench gate GET (particularly near the cell portion side of the peripheral trench gate GET), and the breakdown voltage is likely to decrease.

[0071] In contrast, in this embodiment, as shown in Fig. 2, the peripheral column region PC1 is disposed on the cell unit CEL side with respect to the peripheral trench gate GET, and extends across multiple cell trench gates GE in a plan view. This allows the peripheral column region PC1 to extend along the peripheral trench gate GET. Therefore, even if the line width of the peripheral column region PC1 varies, as shown in Fig. 13, the depletion layer DL is likely to extend near the cell unit CEL side of the peripheral trench gate GET, improving the breakdown voltage.

[0072] 2, in this embodiment, the peripheral column region PC1 extends over the entire width of the cell unit CEL in plan view, which makes it easier for the depletion layer DL to extend to the vicinity of the cell unit CEL side of the peripheral trench gate GET over the entire width of the cell unit CEL, further improving the breakdown voltage.

[0073] 2, in this embodiment, the peripheral column region PC1 surrounds the outer periphery of the cell unit CEL in plan view, which makes it easier for the depletion layer DL to extend to the vicinity of the cell unit CEL side of the peripheral trench gate GET over the entire outer periphery of the cell unit CEL, thereby further improving the breakdown voltage.

[0074] According to this embodiment, the peripheral column region PC2 sandwiches the peripheral trench gate GET between itself and the peripheral column region PC1 in plan view, and extends across the entire width of the cell unit CEL, as shown in Fig. 3. This makes it easier for the depletion layer DL to extend to the vicinity of the outer portion PER side of the peripheral trench gate GET, as shown in Fig. 13, thereby further improving the breakdown voltage.

[0075] (Embodiment 2) <Configuration of Semiconductor Device in Chip State> Next, the configuration of the semiconductor device according to the second embodiment in a chip state will be described with reference to FIGS.

[0076] 14 and 15, the semiconductor device SC according to the second embodiment is different from the configuration of the semiconductor device according to the first embodiment shown in FIG. 1 in the arrangement position of the outer periphery column region PC1.

[0077] In this embodiment, the periphery column region PC1 is disposed immediately below the periphery trench gate GET. The periphery column region PC1 is disposed immediately below the periphery trench gate GET over the entire length of the periphery trench gate GET.

[0078] In this embodiment, no other periphery column region is arranged on the cell unit CEL side with respect to each of the periphery trench gate GET and the periphery column region PC1. However, as in the first embodiment, also in this embodiment, a periphery column region may be added on the cell unit CEL side with respect to each of the periphery trench gate GET and the periphery column region PC1.

[0079] 16B, the width W1 of the periphery column region PC1 is larger than the width W2 of the periphery trench TR2. Therefore, the periphery column region PC1 contacts the entire bottom surface of the periphery trench TR2 in the width direction. In addition, the periphery column region PC1 contacts both the side surface of the periphery trench TR2 on the cell part CEL side and the side surface of the periphery trench TR2 on the outer part PER side.

[0080] As shown in FIG. 16(C), the periphery column region PC1 contacts the entire bottom surface of the periphery trench TR2 in the longitudinal direction.

[0081] Other than the above, the configuration of this embodiment is almost the same as that of the first embodiment, so the same elements are given the same reference numerals and the description thereof will not be repeated.

[0082] <Method of Manufacturing Semiconductor Device> Next, a method for manufacturing the semiconductor device of this embodiment will be described with reference to FIGS. 17(A) and 17(B) to 19(A) and 19(B).

[0083] The method for manufacturing the semiconductor device according to this embodiment first goes through the same manufacturing steps as those of the first embodiment shown in Figures 4 and 5. Then, as shown in Figure 17, a silicon oxide film IL1, a silicon nitride film IL2, a silicon oxide film IL3, and a silicon oxide film IL4 are stacked in this order on the first surface FS of the semiconductor substrate SB. A photoresist PR2 is applied onto the silicon oxide film IL4. Then, the photoresist PR2 is patterned by photolithography (exposure, development, etc.).

[0084] Using the patterned photoresist PR2 as a mask, the silicon oxide films IL4 and IL3 are subjected to plasma etching, whereby the silicon oxide films IL4 and IL3 are selectively etched away, exposing a part of the silicon nitride film IL2.

[0085] In this state, p-type impurities such as boron are ion-implanted from the first surface FS side of the semiconductor substrate SB, thereby forming a cell column region CL in the cell portion CEL, and peripheral column regions PC1 to PC3 in the outer portion PER.

[0086] The periphery column region PC1 is formed to be located directly below the periphery trench TR2. Specifically, the periphery column region PC1 is formed to be in contact with the entire bottom surface of the periphery trench TR2 and to be in contact with both the side surface of the periphery trench TR2 on the cell part CEL side and the side surface of the periphery trench TR2 on the outer part PER side.

[0087] Thereafter, the photoresist PR2 is stripped and removed, the silicon oxide films IL4 and IL3 are removed by etching, and the silicon nitride film IL2 is removed by wet etching.

[0088] Thereafter, a boro-phosphosilicate glass (BPSG) film or the like is formed on the silicon oxide film IL1 using tetra ethyl ortho silicate (TEOS) as a raw material.

[0089] As shown in FIGS. 18A and 18B, an interlayer insulating layer II is formed on the first surface FS of the semiconductor substrate SB from a silicon oxide film IL1, a BPSG film, and the like.

[0090] As shown in Figures 19(A) and 19(B), contact holes CH1 and CH2 are formed in the interlayer insulating layer II by photolithography and etching. The contact hole CH1 not only penetrates the interlayer insulating layer II, but also +The contact hole CH2 is formed so as to penetrate the source region SR and reach the p-type base region BA. The contact hole CH2 is formed so as to penetrate the interlayer insulating layer II and reach the peripheral trench gate GET.

[0091] Thereafter, boron fluoride is ion-implanted into the semiconductor substrate SB through the contact hole CH1. + A contact region CR is formed.

[0092] As shown in Figures 16(A) and (B), conductive layers BC1 and BC2 are formed in the contact holes CH1 and CH2, respectively. Each of the conductive layers BC1 and BC2 includes a barrier metal layer and a buried conductive layer. The barrier metal layer is formed along the wall surface of each of the contact holes CH1 and CH2 and is made of a laminated film of, for example, Ti and TiN. The buried conductive layer fills the inside of each of the contact holes CH1 and CH2.

[0093] A conductive layer made of, for example, aluminum or aluminum-copper is formed on the interlayer insulating layer II. This conductive layer is patterned by photolithography and etching techniques. As a result, a source electrode SE and a gate electrode wiring GEL are formed from the conductive layer. The source electrode SE is connected to an n-type semiconductor layer BC1 via a conductive layer BC1. + Source regions SR and p + The gate electrode wiring GEL is electrically connected to each of the contact regions CR. The gate electrode wiring GEL is electrically connected to the outer periphery trench gate GET with a conductive layer BC2 interposed therebetween.

[0094] In this manner, the semiconductor device of this embodiment shown in FIG. 16 is manufactured. <Effects> Next, the effects of this embodiment will be described.

[0095] 16B and 16C, in this embodiment, the periphery column region PC1 is disposed directly below the periphery trench TR2. Therefore, even if the line width of the periphery column region PC1 varies, the depletion layer DL tends to spread near the periphery trench gate GET as shown in FIG. 20, improving the breakdown voltage.

[0096] 16B and 16C, the peripheral column region PC1 is in contact with the entire bottom surface of the peripheral trench TR2, which makes it easier for the depletion layer DL to expand near the peripheral trench TR2, thereby further improving the breakdown voltage.

[0097] 16(B), the peripheral column region PC1 contacts both the side surface of the peripheral trench TR2 on the cell part CEL side and the side surface of the peripheral trench TR2 on the outer part PER side, which makes it easier for the depletion layer DL to expand near the peripheral trench TR2, thereby further improving the breakdown voltage.

[0098] 14, in this embodiment, the peripheral column region PC1 extends over the entire width of the cell unit CEL in plan view, which makes it easier to deplete the peripheral trench gate GET near the cell unit CEL side over the entire width of the cell unit CEL, further improving the breakdown voltage.

[0099] 14, in this embodiment, the peripheral column region PC1 surrounds the outer periphery of the cell unit CEL in plan view, which makes it easier to deplete the peripheral trench gate GET near the cell unit CEL side over the entire outer periphery of the cell unit CEL, further improving the breakdown voltage.

[0100] The invention made by the inventor has been specifically described above based on an embodiment, but it goes without saying that the present invention is not limited to the above embodiment and can be modified in various ways without departing from the gist of the invention. [Explanation of symbols]

[0101] BA p-type base region, BC1, BC2 conductive layer, CEL cell section, CH1, CH2 contact hole, CL cell column region, CR contact region, DE drain electrode, DL depletion layer, DR n + Drain region, DRI n-type drift region, FS first surface, GE cell trench gate, GEL gate electrode wiring, GET peripheral trench gate, GI gate insulation layer, GP gate electrode pad, II interlayer insulation layer, IL1, IL3, IL4 silicon oxide film, IL2 silicon nitride film, PC1, PC2, PC3, PC4 peripheral column region, PCL dot column region, PER outer part, PR1, PR2 photoresist, SB semiconductor substrate, SC semiconductor device, SE source electrode, SS second surface, SR source region, TR1 cell trench, TR2 peripheral trench.

Claims

1. a semiconductor substrate having a main surface; a cell section having an insulated gate field effect transistor formed on the semiconductor substrate; an outer portion located outside the cell portion on the main surface, The cell portion is a first cell column region and a second cell column region that are disposed on the semiconductor substrate and adjacent to each other in a plan view; a first cell trench gate and a second cell trench gate disposed between the first cell column region and the second cell column region in a plan view; The outer portion is a peripheral trench gate connected to each end of the first cell trench gate and the second cell trench gate in a plan view; a first outer peripheral column region disposed on the cell portion side with respect to the outer peripheral trench gate and extending across the first cell trench gate and the second cell trench gate in a plan view.

2. The semiconductor device according to claim 1 , wherein said first outer column region extends across the entire width of said cell portion in a plan view.

3. The semiconductor device according to claim 2 , wherein said first outer peripheral column region surrounds an outer periphery of said cell portion in a plan view.

4. the outer portion further comprises a second outer circumferential column region; 2 . The semiconductor device according to claim 1 , wherein said second outer column region sandwiches said outer trench gate between said first outer column region and said second outer column region in a plan view, and extends across the entirety of said cell portion in a width direction.

5. 1. A method for manufacturing a semiconductor device having a cell portion having an insulated gate field effect transistor formed in a semiconductor substrate having a main surface, and an outer portion located outside the cell portion on the main surface, comprising: forming a first cell trench gate and a second cell trench gate adjacent to each other in a plan view in the cell portion, and forming a peripheral trench gate connected to each end of the first cell trench gate and the second cell trench gate in a plan view in the outer portion; forming a first cell column region and a second cell column region in the semiconductor substrate of the cell portion, the first cell trench gate and the second cell trench gate being sandwiched therebetween in a plan view, and forming a peripheral column region in the semiconductor substrate on the cell portion side and in the outer portion with respect to the peripheral trench gate; a first cell trench gate formed on the first insulating film and a second cell trench gate formed on the second insulating film;

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