Stacked structure, semiconductor device and system

Abstract

[Problem] To provide a laminate structure that has excellent crystallinity, a semiconductor device, and methods by which it is possible to produce the same in an industrially advantageous manner. [Solution] The present invention involves laminating a buffer layer that includes, on a semiconductor crystal substrate, a crystal film containing Hf and / or Zr and having a cubic structure, and laminating an epitaxial film made of a compound semiconductor on the buffer layer directly or with another layer therebetween, to produce a Schottky barrier diode (SBD), a junction barrier Schottky diode (JBS), a metal-semiconductor field-effect transistor (MESFET), a high-electron-mobility transistor (HEMT), a metal-oxide-semiconductor field-effect transistor (MOSFET), a static induction transistor (SIT), a junction field-effect transistor (JFET), an insulated-gate bipolar transistor (IGBT), a light-emitting diode (LED), or a semiconductor device including a combination thereof.

Description

[Technical field]

[0001] The present invention relates to a laminated structure, a semiconductor device, and a method for manufacturing the same. [Background technology]

[0002] Conventionally, heteroepitaxial growth processes for growing gallium nitride crystal films on sapphire substrates have been considered, but due to differences in thermal expansion coefficients and lattice mismatch issues, it is not easy to form high-quality epitaxial films, and the epitaxial film formation process has become complicated and sophisticated, leading to increased costs.

[0003] In recent years, epitaxial substrates with an adjusted coefficient of thermal expansion (CTE) that substantially matches the epitaxial layer have been studied (for example, Patent Document 1). However, the manufacturing process of such epitaxial substrates has become complicated and advanced, and the fundamental problems have not been solved. In addition, there are problems such as the need to perform surface treatment and polishing after peeling off the epitaxial substrate, and further attach electrodes. Therefore, a method for easily forming an epitaxial film of a compound semiconductor such as gallium nitride and further easily manufacturing a semiconductor device has been awaited. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2020-161833 A Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to provide a laminated structure having excellent crystallinity, a semiconductor device having excellent semiconductor characteristics, and a manufacturing method by which these can be obtained in an industrially advantageous manner. [Means for solving the problem]

[0006] As a result of intensive research into achieving the above-mentioned object, the inventors have found that when a buffer layer is stacked on a semiconductor crystal substrate and an epitaxial film made of a compound semiconductor is stacked on the buffer layer directly or via another layer, if a crystalline film of a nitride or oxynitride of Hf and / or Zr having a cubic crystal structure is used as the buffer layer, a good quality conductive crystalline film can be easily obtained, that the conductive crystalline film is useful as a buffer layer, and that an epitaxial film made of a high quality compound semiconductor film can be easily formed. Furthermore, they have found that with such a stacked structure, the formed conductive crystalline film can also be used as an electrode layer, etc., and that a semiconductor device can be easily fabricated. They have therefore found that the stacked structure can solve the conventional problems in one fell swoop. After obtaining the above findings, the present inventors conducted further studies and completed the present invention.

[0007] That is, the present invention relates to the following inventions. [1] A laminated structure in which an epitaxial film made of a compound semiconductor is formed on a buffer layer directly or via another layer, characterized in that the buffer layer includes a crystalline film containing Hf and / or Zr and having a cubic crystal structure. [2] The laminate structure according to [1] above, wherein the crystalline film is a conductive crystalline film containing a nitride or oxynitride of Hf and / or Zr. [3] The layered structure according to [1] or [2], wherein the epitaxial film has a cubic crystal structure. [4] The stacked structure according to any one of [1] to [3] above, wherein the compound semiconductor is a wide band gap semiconductor. [5] The stacked structure according to any one of [1] to [4], wherein the compound semiconductor is a nitride semiconductor. [6] The laminate structure according to any one of [1] to [5] above, wherein the buffer layer is laminated on a semiconductor single crystal substrate directly or via another layer. [7] The laminated structure according to [6], wherein the buffer layer is laminated on the semiconductor single crystal substrate by crystal growth. [8] The stacked structure according to [6] or [7], wherein the semiconductor single crystal substrate is a Si substrate. [9] A semiconductor device including a laminated structure, wherein the laminated structure is the laminated structure according to any one of [1] to [8].

[10] The semiconductor device according to [9] above, which is a vertical device.

[11] The semiconductor device according to [9] or

[10] , which is a Schottky barrier diode (SBD), a junction barrier Schottky diode (JBS), a merged PiN Schottky diode (MPS), a metal semiconductor field effect transistor (MESFET), a high electron mobility transistor (HEMT), a metal oxide semiconductor field effect transistor (MOSFET), a static induction transistor (SIT), a junction field effect transistor (JFET), an insulated gate bipolar transistor (IGBT), a light emitting diode (LED), or a combination thereof.

[12] A method for manufacturing a laminated structure, comprising stacking a buffer layer on a semiconductor crystal substrate, and stacking an epitaxial film made of a compound semiconductor on the buffer layer directly or via another layer, wherein the buffer layer includes a crystal film containing Hf and / or Zr and having a cubic crystal structure.

[13] The method according to

[12] , wherein the semiconductor crystal substrate is a Si substrate and the compound semiconductor is a nitride semiconductor.

[14] A method for manufacturing a semiconductor device using a laminated structure, wherein the laminated structure is the laminated structure according to any one of [1] to [8].

[15] A system including a semiconductor device, wherein the semiconductor device is the semiconductor device according to any one of [9] to

[11] above. Effect of the Invention

[0008] The layered structure and semiconductor device of the present invention have excellent crystallinity, and the manufacturing method of the present invention has the effect of making it possible to obtain the layered structure and the semiconductor device in an industrially advantageous manner. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a diagram showing a schematic diagram of an example of a preferred embodiment of a laminated structure of the present invention. [Diagram 2] 3 is a schematic diagram for explaining a buffer layer forming step in the method for producing the laminated structure of the present invention. FIG. [Diagram 3] 1 is a diagram showing a schematic diagram of an example of a preferred embodiment of a semiconductor device (SBD) of the present invention; [Figure 4] FIG. 1 is a diagram showing a schematic diagram of an example of a preferred embodiment of a semiconductor device (JBS) of the present invention. [Diagram 5] 1 is a diagram showing a schematic diagram of an example of a preferred embodiment of a semiconductor device (MESFET) of the present invention; [Figure 6] 1 is a diagram showing a schematic diagram of an example of a preferred embodiment of a semiconductor device (HEMT) of the present invention. [Figure 7] FIG. 1 is a diagram illustrating an example of a preferred embodiment of a semiconductor device (MOSFET) of the present invention. [Figure 8] 1 is a diagram showing a schematic diagram of an example of a preferred embodiment of a semiconductor device (SIT) of the present invention; [Figure 9] FIG. 1 is a diagram showing a schematic diagram of an example of a preferred embodiment of a semiconductor device (JFET) of the present invention. [Figure 10] 1 is a diagram showing a schematic diagram of an example of a preferred embodiment of a semiconductor device (IGBT) of the present invention; [Figure 11] FIG. 1 is a diagram showing a schematic diagram of an example of a preferred embodiment of a semiconductor device (LED) of the present invention. [Figure 12] FIG. 1 is a diagram illustrating a preferred example of a power supply system. [Figure 13] FIG. 1 is a diagram illustrating a preferred example of a system device. [Figure 14]FIG. 1 is a diagram illustrating a preferred example of a power supply circuit diagram of a power supply device. [Figure 15] FIG. 2 is a schematic diagram showing a film forming apparatus preferably used in the examples. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] The laminated structure of the present invention is a laminated structure in which an epitaxial film made of a compound semiconductor is formed on a buffer layer directly or via another layer, and the buffer layer includes a crystalline film containing Hf and / or Zr and having a cubic crystal structure. Fig. 1 shows a suitable example of the laminated structure, in which the buffer layer 5 is laminated on a crystalline substrate 9, and an epitaxial film 1 made of a compound semiconductor is further laminated on the buffer layer 5. In this specification, the terms "film" and "layer" may be interchanged depending on the case or situation.

[0011] In the laminated structure of the present invention, as shown in FIG. 2, it is preferable to form the buffer layer 5 on a crystal substrate 9 using a known crystal growth means using nitrogen. The crystal growth means may be a known means, and may be either a vapor phase crystal growth means or a liquid phase crystal growth means. Examples of the crystal growth means include a vapor deposition method, a CVD method, and a sputtering method. In the present invention, after the buffer layer 5 is formed, it is preferable to form an epitaxial film made of a compound semiconductor on the buffer layer using the crystal growth means. By forming the epitaxial film in this manner, as shown in FIG. 1, the buffer layer is transformed in the crystal growth direction to form a peak-valley structure at the interface with the epitaxial film, and the peak-valley structure makes it possible to easily obtain the epitaxial film of high quality with excellent crystallinity.

[0012] The crystal substrate (hereinafter, simply referred to as "substrate") is not particularly limited as long as the object of the present invention is not hindered by the substrate material, etc., and may be a known crystal substrate. It may be an organic compound or an inorganic compound. In the present invention, it is preferable that the crystal substrate contains an inorganic compound. In the present invention, it is preferable that the substrate has crystals on a part or all of the surface, more preferably a crystal substrate having crystals on all or a part of the main surface on the crystal growth side, and most preferably a crystal substrate having crystals on the entire main surface on the crystal growth side. The crystals preferably have a cubic crystal structure, and more preferably are crystals oriented in (100) or (200). In addition, the crystal substrate may have an off-angle, and examples of the off-angle include an off-angle of 0.2° to 12.0°. Here, the "off-angle" refers to the angle between the substrate surface and the crystal growth surface. The shape of the substrate is not particularly limited as long as it is plate-like and serves as a support for the insulating film. The substrate may be an insulating substrate or a semiconductor substrate, but in the present invention, the substrate is preferably a Si substrate, more preferably a crystalline Si substrate, and most preferably a crystalline Si substrate oriented in (100). In addition to a Si substrate, examples of the substrate material include one or more metals belonging to Groups 3 to 15 of the periodic table, or oxides of these metals. The shape of the substrate is not particularly limited, and may be substantially circular (e.g., circular, elliptical, etc.) or polygonal (e.g., triangular, square, rectangular, pentagonal, hexagonal, heptagonal, octagonal, nonagonal, etc.), and various shapes can be suitably used.

[0013] In the present invention, the crystal substrate preferably has a flat surface, but it is also preferable that the crystal substrate has an uneven shape on a part or all of the surface. The crystal substrate having the uneven shape may have an uneven portion consisting of a concave or convex portion formed on a part or all of the surface, and the uneven portion is not particularly limited as long as it is composed of a convex or concave portion, and may be an uneven portion consisting of a convex portion, an uneven portion consisting of a concave portion, or an uneven portion consisting of a convex portion and a concave portion. The uneven portion may be formed from regular convex portions or concave portions, or may be formed from irregular convex portions or concave portions. In the present invention, it is preferable that the uneven portion is formed periodically, and it is more preferable that the uneven portion is patterned periodically and regularly. The shape of the uneven portion is not particularly limited, and examples thereof include a stripe shape, a dot shape, a mesh shape, and a random shape, but in the present invention, a dot shape or a stripe shape is preferable, and a dot shape is more preferable. In addition, when the unevenness is patterned periodically and regularly, the pattern shape of the unevenness is preferably a polygonal shape such as a triangle, a quadrangle (for example, a square, a rectangle, or a trapezoid), a pentagon, or a hexagon, a circle, or an ellipse. In addition, when the unevenness is formed in a dot shape, the lattice shape of the dots is preferably a lattice shape such as a square lattice, an oblique lattice, a triangular lattice, or a hexagonal lattice, and more preferably a triangular lattice shape. The cross-sectional shape of the concave or convex part of the unevenness is not particularly limited, but examples thereof include a U-shape, an inverted U-shape, a wave shape, or a polygonal shape such as a triangle, a quadrangle (for example, a square, a rectangle, or a trapezoid), a pentagon, or a hexagon. In addition, the thickness of the crystal substrate is not particularly limited, but is preferably 50 to 2000 μm, and more preferably 100 to 1000 μm.

[0014] The buffer layer is not particularly limited as long as it contains a crystalline film containing Hf and / or Zr and having a cubic crystal structure, but in the present invention, the crystalline film is preferably a conductive crystalline film containing a nitride or oxynitride of Hf and / or Zr. The conductive crystalline film preferably contains HfN and / or ZrN, more preferably contains HfN. When the conductive crystalline film contains HfN, even if the epitaxial film is formed by crystal growth of two or more layers, transformation occurs in each layer, and the crystallinity of the epitaxial film can be further improved. In addition, the conductive crystalline film preferably has a cubic crystal structure, and more preferably contains crystals oriented in (100) or (200). The buffer layer can be suitably formed on the crystal substrate by a known crystal growth method such as a sputtering method using a Hf source and / or a Zr source and nitrogen gas at, for example, 350°C to 700°C. The buffer layer may also include a mixed crystal film. The mixed crystal film is not particularly limited as long as it is a crystal film made of a mixed crystal, and a suitable example of the mixed crystal is, for example, a mixed crystal containing, in addition to a nitride or oxynitride of Hf and / or Zr, one or more nitrides or oxynitrides selected from Ti, Al, Y and Ce. Such a preferable mixed crystal not only improves the stress relaxation effect of the buffer layer, but also improves the film quality of the epitaxial film.

[0015] The epitaxial film is not particularly limited as long as it is a crystal growth film made of a compound semiconductor. The compound semiconductor is also not particularly limited and may be a known compound semiconductor. Examples of the compound semiconductor include nitride semiconductors, carbide semiconductors (e.g., SiC, etc.), oxide semiconductors, InP, or GaAs. In the present invention, the compound semiconductor is preferably a wide band gap semiconductor, and more preferably a nitride semiconductor. Examples of the nitride semiconductor include III-V group semiconductors (aluminum nitride (AlN), gallium nitride (GaN), indium nitride (InN), etc.), or boron nitride (BN). In the present invention, the epitaxial film preferably has a cubic crystal structure, and more preferably is a crystal growth film made of a cubic semiconductor. Examples of the cubic semiconductor include c-BN, c-AlN, c-GaN, c-InN, c-SiC, GaAs, AlAs, InAs, GaP, AlP, InP, or mixed crystal semiconductors thereof.

[0016] The laminated structure obtained as described above can be used in a semiconductor device as it is or after further processing, etc., according to a conventional method. In the present invention, the buffer layer in the laminated structure can be suitably used as an electrode or buffer layer for ohmic contact or electron emission in the semiconductor device, and the epitaxial film in the laminated structure can be suitably used as a semiconductor layer in the semiconductor device. When the laminated structure is used in a semiconductor device, it may be used in the semiconductor device as it is, or may be used after forming other layers (e.g., an insulator layer, a semi-insulator layer, a conductor layer, a semiconductor layer, a buffer layer, or other intermediate layers). The crystal substrate may be peeled off from the semiconductor device using a known peeling means.

[0017] The semiconductor device is not particularly limited as long as it does not impede the object of the present invention, and may be a known semiconductor device. It may be a vertical device or a horizontal device, but in the present invention, the semiconductor device is preferably a vertical device. Examples of the semiconductor device include a diode or a transistor, and more specifically, suitable examples include a Schottky barrier diode (SBD), a junction barrier Schottky diode (JBS), a high electron mobility transistor (HEMT), a metal semiconductor field effect transistor (MESFET), a metal oxide semiconductor field effect transistor (MOSFET), a static induction transistor (SIT), a junction field effect transistor (JFET), an insulated gate bipolar transistor (IGBT), a light emitting diode (LED), or a combination thereof.

[0018] Hereinafter, preferred examples of the laminated structure being applied to a semiconductor device, more specifically, the buffer layer in the laminated structure being applied to an electrode or buffer layer for ohmic contact or electron emission in the semiconductor device, and the epitaxial film in the laminated structure being applied to a semiconductor layer in the semiconductor device will be described with reference to the drawings, but the present invention is not limited to these examples. Note that the semiconductor devices exemplified below may further include other layers (e.g., an insulating layer, a semi-insulating layer, a conductor layer, a semiconductor layer, a buffer layer, or other intermediate layers, etc.) as long as they do not impede the object of the present invention, and may also omit a crystal substrate, a buffer layer (buffer layer), etc. as appropriate.

[0019] (SBD) Fig. 3 shows an example of a Schottky barrier diode (SBD) according to the present invention. The SBD in Fig. 3 includes an n-type semiconductor layer 101, an n-type semiconductor layer 101a, an n+ type semiconductor layer 101b, an insulator layer 104, a Schottky electrode 105a, and an ohmic electrode 105b.

[0020] The material of the electrodes such as the Schottky electrode may be a known electrode material, and examples of the electrode material include metals such as Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd, and Ag, or alloys thereof; conductive metal oxide films such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), and indium zinc oxide (IZO); organic conductive compounds such as polyaniline, polythiophene, and polypyrrole, and mixtures thereof.

[0021] The electrode can be formed by a known method such as vacuum deposition or sputtering. More specifically, for example, when forming a Schottky electrode, a layer made of Mo and a layer made of Al are laminated, and the layer made of Mo and the layer made of Al are patterned by using a photolithography method.

[0022] Examples of materials for the insulator layer 104 include GaO, AlGaO, InAlGaO, AlInZnGaO4, AlN, Hf2O3, SiN, SiON, Al2O3, MgO, GdO, SiO2, and Si3N4. The insulator layer 104 is provided between the n-type semiconductor layer 101 and the Schottky electrode 105a. The insulator layer can be formed by a known method such as a sputtering method, a vacuum deposition method, or a CVD method.

[0023] 3, a depletion layer (not shown) spreads into n-type semiconductor layer 101a, resulting in a high-voltage SBD. When a forward bias is applied, electrons flow from ohmic electrode 105b to Schottky electrode 105a. An SBD using the above-described semiconductor structure is thus excellent for high-voltage and large-current applications, has fast switching speed, excellent voltage resistance and reliability, excellent insulation properties, and higher current controllability.

[0024] (JBS) Fig. 4 shows a junction barrier Schottky diode (JBS) which is one of the preferred embodiments of the present invention. The semiconductor device in Fig. 4 includes an n-type semiconductor layer 101, an n-type semiconductor layer 101a, an n+ type semiconductor layer 101b, a p-type semiconductor layer 102, a Schottky electrode 105a, an ohmic electrode 105b, and a guard ring 106. The semiconductor device includes an n-type semiconductor layer 101a, a Schottky electrode 105a which is provided on the n-type semiconductor layer 101a and capable of forming a Schottky barrier between the n-type semiconductor layer 101a, and a p-type semiconductor layer 102 which is provided between the Schottky electrode 105a and the n-type semiconductor layer 101a and capable of forming a Schottky barrier with a barrier height larger than the barrier height of the Schottky barrier of the Schottky electrode 105a between the n-type semiconductor layer 101a. The p-type semiconductor layer 102 is embedded in the n-type semiconductor layer 101a. In the present invention, it is preferable that the p-type semiconductor layers 102 are provided at regular intervals, and it is more preferable that the p-type semiconductor layers 102 are provided between both ends of the Schottky electrode 105a and the n-type semiconductor layer 101a. With such a preferable embodiment, the JBS is configured to have better thermal stability and adhesion, a reduced leakage current, and better semiconductor properties such as breakdown voltage.

[0025] (MESFET) Fig. 5 shows an example of a metal semiconductor field effect transistor (MESFET) according to the present invention. The MESFET in Fig. 5 includes an n-type semiconductor layer 111a, an n+ type semiconductor layer 111b, a buffer layer 118, a crystal substrate 119, a semi-insulating layer 114, a gate electrode 115a, a source electrode 115b, and a drain electrode 115c.

[0026] The materials of the gate electrode, drain electrode and source electrode may be known electrode materials, and examples of the electrode materials include metals such as Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd or Ag, or alloys thereof, metal oxide conductive films such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), indium zinc oxide (IZO), or organic conductive compounds such as polyaniline, polythiophene or polypyrrole, or mixtures thereof. The gate electrode, drain electrode and source electrode can be formed by known means such as vacuum deposition or sputtering.

[0027] Semi-insulating layer 114 may be made of a semi-insulating material, and examples of the semi-insulating material include a semi-insulating material that includes a semi-insulating dopant and a semi-insulating material that is not doped.

[0028] In the MESFET of FIG. 5, a good depletion layer is formed under the gate electrode, so that the current flowing from the drain electrode to the source electrode can be efficiently controlled.

[0029] (HEMT) Fig. 6 shows an example of a high-energy electron mobility transistor (HEMT) according to the present invention. The HEMT in Fig. 6 includes an n-type semiconductor layer 121a having a wide band gap, an n-type semiconductor layer 121b having a narrow band gap, an n+ type semiconductor layer 121c, an electron transit layer 123, a semi-insulating layer 124, a gate electrode 125a, a source electrode 125b, a drain electrode 125c, a buffer layer 128, and a crystal substrate 129.

[0030] The materials of the gate electrode, drain electrode and source electrode may each be a known electrode material, and examples of the electrode materials include metals such as Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd or Ag, or alloys thereof, metal oxide conductive films such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), indium zinc oxide (IZO), or the like, organic conductive compounds such as polyaniline, polythiophene or polypyrrole, or mixtures thereof. The gate electrode, drain electrode and source electrode can be formed by known means such as vacuum deposition or sputtering.

[0031] The n-type semiconductor layer under the gate electrode is composed of at least a wide band gap layer 121a and a narrow band gap layer 121b, and the semi-insulating layer 124 may be composed of a semi-insulating material, and examples of the semi-insulating material include a semi-insulating material containing a semi-insulating dopant and a semi-insulating material that has not been doped. For example, when GaN, a nitride semiconductor, is used as the semiconductor, the electron transit layer 123 formed on the semi-insulating layer 124 may be made of i (intentionally undoped)-GaN or the like.

[0032] In the HEMT shown in Fig. 6, a good depletion layer is formed under the gate electrode, so that the current flowing from the drain electrode to the source electrode can be efficiently controlled. In addition, in the present invention, a recess structure is further provided, so that a normally-off mode can be realized.

[0033] (MOSFET) An example of the semiconductor device of the present invention being a MOSFET is shown in Fig. 7. Fig. 7 shows a preferred example of a metal oxide semiconductor field effect transistor (MOSFET) including an n-type semiconductor layer 131a, a first n+ type semiconductor layer 131b, a second n+ type semiconductor layer 131c, a p-type semiconductor layer 132, a p+ type semiconductor layer 132a, a gate insulating film 134, a gate electrode 135a, a source electrode 135b, and a drain electrode 135c. The p+ type semiconductor layer 132a may be a p-type semiconductor layer or may be the same as the p-type semiconductor layer 132.

[0034] An n+ type semiconductor layer 131b having a thickness of, for example, 100 nm to 100 μm is formed on the drain electrode 135c made of the conductive crystal film, and an n- type semiconductor layer 131a having a thickness of, for example, 100 nm to 100 μm is formed on the n+ type semiconductor layer 131b.

[0035] Further, a plurality of trenches each having a depth reaching partway through the n-type semiconductor layer 131a are formed in the n-type semiconductor layer 131a and the p-type semiconductor layer 132. A gate electrode 135a is embedded in the trench via a gate insulating film 134 having a thickness of, for example, 10 nm to 1 μm.

[0036] 7, when a voltage is applied between the source electrode 135b and the drain electrode 135c and a positive voltage is applied to the gate electrode 135a with respect to the source electrode 135b, a channel layer is formed on the side surface of the n-type semiconductor layer 131a, electrons are injected into the n-type semiconductor layer, and the MOSFET is turned on. When the voltage of the gate electrode is set to 0V, no channel layer is formed and the n-type semiconductor layer is filled with a depletion layer, turning the MOSFET off.

[0037] 7, an etching mask is provided in a predetermined region of the n-type semiconductor layer 131a, the p-type semiconductor 132, and the n+ type semiconductor layer 131c, and anisotropic etching is performed by reactive ion etching or the like using the etching mask as a mask to form a trench groove having a depth reaching from the surface of the n+ type semiconductor layer 131c to the middle of the n-type semiconductor layer 131a. Next, a gate insulating film 134 having a thickness of, for example, 50 nm to 1 μm is formed on the side and bottom surfaces of the trench groove by a known means such as thermal oxidation, vacuum deposition, sputtering, or CVD, and then a gate electrode material such as polysilicon is formed in the trench groove to a thickness equal to or less than the thickness of the n-type semiconductor layer by CVD, vacuum deposition, sputtering, or the like.

[0038] Then, the source electrode 135b is formed on the n+ type semiconductor layer 131c by using a known means such as a vacuum deposition method, a sputtering method, a CVD method, etc., to manufacture a power MOSFET. The electrode material of the source electrode may be a known electrode material, and examples of the electrode material include metals such as Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd, and Ag, or alloys thereof, metal oxide conductive films such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), and indium zinc oxide (IZO), organic conductive compounds such as polyaniline, polythiophene, and polypyrrole, and mixtures thereof.

[0039] The MOSFET obtained in this way has a higher breakdown voltage than the conventional trench MOSFET. Although Fig. 7 shows an example of a trench vertical MOSFET, the present invention is not limited to this and can be applied to various MOSFET configurations. For example, the depth of the trench groove in Fig. 7 may be deepened to a depth reaching the bottom surface of the n-type semiconductor layer 131a to reduce the series resistance.

[0040] (SIT) Fig. 8 shows an example of the semiconductor device of the present invention being an SIT. The SIT in Fig. 8 includes an n-type semiconductor layer 141a, n+ type semiconductor layers 141b and 141c, a gate electrode 145a, a source electrode 145b, and a drain electrode 145c.

[0041] An n+ type semiconductor layer 141b having a thickness of, for example, 100 nm to 100 μm is formed on the drain electrode 145c made of a conductive crystal film, and an n- type semiconductor layer 141a having a thickness of, for example, 100 nm to 100 μm is formed on the n+ type semiconductor layer 141b. Furthermore, an n+ type semiconductor layer 141c is formed on the n- type semiconductor layer 141a, and a source electrode 145b is formed on the n+ type semiconductor layer 141c.

[0042] In addition, a plurality of trenches are formed in the n-type semiconductor layer 141a, each of which penetrates the n+ type semiconductor layer 141c and has a depth reaching halfway through the n-type semiconductor layer 141a. A gate electrode 145a is formed on the n-type semiconductor layer in the trench. 8, when a voltage is applied between the source electrode 145b and the drain electrode 145c and a positive voltage is applied to the gate electrode 145a with respect to the source electrode 145b, a channel layer is formed in the n-type semiconductor layer 141a, electrons are injected into the n-type semiconductor layer, and the device is turned on. When the voltage of the gate electrode is set to 0V, the channel layer is not formed and the n-type semiconductor layer is filled with a depletion layer, resulting in the device being turned off.

[0043] A known means can be used to manufacture the SIT shown in FIG. 8. For example, in the same manner as in the manufacturing process of the above-mentioned MOSFET, an etching mask is provided in a predetermined region of the n-type semiconductor layer 141a and the n+ type semiconductor layer 141c, and anisotropic etching is performed by, for example, reactive ion etching using the etching mask as a mask to form a trench groove having a depth reaching from the surface of the n+ type semiconductor layer 141c to the middle of the n- type semiconductor layer. Next, a gate electrode material such as polysilicon is formed in the trench groove to a thickness equal to or less than the thickness of the n- type semiconductor layer by CVD, vacuum deposition, sputtering, or the like. Then, a source electrode 145b is formed on the n+ type semiconductor layer 141c, and a drain electrode 145c is formed on the n+ type semiconductor layer 141b by known means such as vacuum deposition, sputtering, or CVD, to manufacture the SIT shown in FIG. 8.

[0044] The electrode material of the source electrode may be a known electrode material, and examples of the electrode material include metals such as Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd, and Ag, or alloys thereof; conductive metal oxide films such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), and indium zinc oxide (IZO); organic conductive compounds such as polyaniline, polythiophene, and polypyrrole, and mixtures thereof.

[0045] FIG. 9 shows a preferred example of a junction field effect transistor (JFET) including an n-type semiconductor layer 141a, a first n+ type semiconductor layer 141b, a second n+ type semiconductor layer 141c, a p-type semiconductor layer 142, a gate electrode 145a, a source electrode 145b, and a drain electrode 145c.

[0046] FIG. 10 shows a preferred example of an insulated gate bipolar transistor (IGBT) including an n-type semiconductor layer 151, an n-type semiconductor layer 151a, an n+ type semiconductor layer 151b, a p-type semiconductor layer 152, a gate insulating film 154, a gate electrode 155a, an emitter electrode 155b, and a collector electrode 155c.

[0047] (LED) An example of the semiconductor device of the present invention being a light emitting diode (LED) is shown in Fig. 11. The semiconductor light emitting device of Fig. 11 includes an n-type semiconductor layer 161 on a second electrode 165b, and a light emitting layer 163 is laminated on the n-type semiconductor layer 161. A p-type semiconductor layer 162 is laminated on the light emitting layer 163. A light-transmitting electrode 167 that transmits light generated by the light emitting layer 163 is provided on the p-type semiconductor layer 162, and a first electrode 165a is laminated on the light-transmitting electrode 167. The semiconductor light emitting device of Fig. 11 may be covered with a protective layer except for the electrode portion.

[0048] Examples of materials for the translucent electrode include conductive oxide materials containing indium (In) or titanium (Ti). More specifically, examples include In2O3, ZnO, SnO2, Ga2O3, TiO2, CeO2, or mixed crystals of two or more of these, or doped materials thereof. The translucent electrode can be formed by providing these materials by a known means such as sputtering. After the translucent electrode is formed, thermal annealing may be performed to make the translucent electrode transparent.

[0049] In the semiconductor light-emitting element of FIG. 11, the first electrode 165a is a positive electrode and the second electrode 165b is a negative electrode, and by passing a current through both of them to the p-type semiconductor layer 162, the light-emitting layer 163, and the n-type semiconductor layer 161, the light-emitting layer 163 emits light.

[0050] Examples of materials for the first electrode 165a include metals such as Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd, or Ag, or alloys thereof, metal oxide conductive films such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), or indium zinc oxide (IZO), organic conductive compounds such as polyaniline, polythiophene, or polypyrrole, or mixtures thereof. The method for forming the electrode is not particularly limited, and the electrode can be formed according to a method appropriately selected from wet methods such as printing, spraying, and coating, physical methods such as vacuum deposition, sputtering, and ion plating, and chemical methods such as CVD and plasma CVD, taking into consideration the suitability of the material.

[0051] In addition to the above, the semiconductor device of the present invention can be suitably used as a semiconductor device such as a power module, inverter, or converter by using known means, and can also be suitably used in a semiconductor system using a power supply device as a semiconductor device. The power supply device can be fabricated by connecting the semiconductor device to a wiring pattern or the like by using known means. FIG. 12 shows an example of a power supply system. FIG. 12 shows a power supply system using a plurality of the power supplies and a control circuit. The power supply system can be used in a system device in combination with an electronic circuit as shown in FIG. 13. FIG. 14 shows an example of a power supply circuit diagram of a power supply device. FIG. 14 shows a power supply circuit of a power supply device consisting of a power circuit and a control circuit, in which a DC voltage is switched at high frequency by an inverter (composed of MOSFETs A to D) and converted to AC, then insulated and transformed by a transformer, rectified by rectifier MOSFETs (A to B'), smoothed by DCL (smoothing coils L1, L2) and a capacitor, and a DC voltage is output. At this time, a voltage comparator compares the output voltage with a reference voltage, and a PWM control circuit controls the inverter and rectifier MOSFET so as to obtain a desired output voltage. EXAMPLES

[0052] Example 1 The crystal growth surface side of the Si substrate (100) was treated by RIE, and nitrogen was used in a vapor deposition method to thermally react the metals (Hf, Zr) of the vapor deposition source with nitrogen, forming a crystal film made of crystalline nitride on the Si substrate. XPS revealed that the obtained crystal film contained HfN and ZrN, each having a cubic crystal structure. In addition, the obtained crystal film was examined by a four-terminal method and found to have good electrical conductivity. Next, a GaN film was formed as a semiconductor film on the crystal film by a sputtering method. XPS revealed that the obtained semiconductor film was a c-GaN single crystal film. In addition, when the interface was observed using a cross-sectional STEM image, a mountain-valley structure was formed in which the crystal growth direction was transformed and the angles between the adjacent vertices and bottom points were different, and it was found that the buffer layer exhibited good stress relaxation properties during the formation of the semiconductor film. In addition, when the obtained semiconductor film was observed using an X-ray crystal lattice image, it was found to be a defect-free large-area semiconductor film, and the crystallinity of the laminated structure of the present invention was good.

[0053] The deposition apparatus used in Example 1 is shown in Fig. 15. The deposition apparatus in Fig. 15 includes at least metal sources 1101a-1101b, earths 1102a-1102h, ICP electrodes 1103a-1103b, cut filters 1104a-1104b, DC power sources 1105a-1105b, RF power sources 1106a-1106b, lamps 1107a-1107b, Ar source 1108, reactive gas source 1109, power source 1110, substrate holder 1111, substrate 1112, cut filter 1113, ICP ring 1114, vacuum chamber 1115, and rotation shaft 1116. The ICP electrodes 1103a-1103b in Fig. 15 have a substantially concave curved shape or a parabolic shape curved toward the center of substrate 1112.

[0054] As shown in FIG. 15, the substrate 1112 is fixed on the substrate holder 1111. Next, the rotating shaft 1116 is rotated using the power supply 1110 and a rotating mechanism (not shown) to rotate the substrate 1112. The substrate 112 is heated by the lamps 1107a-1107b, and the inside of the vacuum chamber 1115 is evacuated to a vacuum or reduced pressure by a vacuum pump (not shown). Then, Ar gas is introduced from the Ar source 1108 into the vacuum chamber 1115, and argon plasma is formed on the substrate 1112 using the DC power supplies 1105a-1105b, the RF power supplies 1106a-1106b, the ICP electrodes 1103a-1103b, the cut filters 1104a-1104b, and the earths 1102a-1102h, thereby cleaning the surface of the substrate 1112.

[0055] Ar gas is introduced into the vacuum chamber 1115, and a reactive gas is introduced using a reactive gas source 1109. At this time, lamps 1107a to 1107b, which are lamp heaters, are alternately turned on and off repeatedly, so that a crystal growth film of better quality can be formed. [Industrial Applicability]

[0056] The laminated structure of the present invention can be used in a wide variety of fields, including semiconductors (eg, compound semiconductor electronic devices), electronic components, electrical equipment components, optical and electrophotographic related devices, and industrial materials, and is preferably used in semiconductor devices. [Explanation of symbols]

[0057] 1. Epitaxial film (compound semiconductor) 5. Oxide film 9 Crystal Substrate 101 n-type semiconductor layer 101a n-type semiconductor layer 101b n+ type semiconductor layer 102 p-type semiconductor layer 104 Insulator Layer 105a Schottky electrode 105b Ohmic electrode 106 Guard Ring 111a n-type semiconductor layer 111b n+ type semiconductor layer 114 Semi-insulating layer 115a Gate electrode 115b Source electrode 115c Drain electrode 118 Buffer Layer 119 Crystal Substrate 121a Wide band gap n-type semiconductor layer 121b Narrow band gap n-type semiconductor layer 121c n+ type semiconductor layer 123 Electron Transport Layer 124 Semi-insulating layer 125a Gate electrode 125b Source electrode 125c Drain electrode 128 buffer layer 129 Crystal Substrate 131a n-type semiconductor layer 131b First n+ type semiconductor layer 131c second n+ type semiconductor layer 132 p-type semiconductor layer 134 Gate insulating film 135a Gate electrode 135b Source electrode 135c Drain electrode 141a n-type semiconductor layer 141b First n+ type semiconductor layer 141c second n+ type semiconductor layer 142 p-type semiconductor layer 145a Gate electrode 145b Source electrode 145c Drain electrode 151 n-type semiconductor layer 151a n-type semiconductor layer 151b n+ type semiconductor layer 152 p-type semiconductor layer 154 Gate insulating film 155a Gate electrode 155b Emitter electrode 155c Collector electrode 161 n-type semiconductor layer 162 p-type semiconductor layer 163 Light-emitting layer 165a First electrode 165b Second electrode 167 Translucent electrode 1101a~101b Metal source 1102a~102j Earth 1103a~103b ICP electrode 1104a~104b Cut Filter 1105a~105b DC power supply 1106a~106b RF power supply 1107a~107b Lamp 1108 Ar source 1109 Reactive Gas Source 1110 Power supply 1111 PCB holder 1112 Substrate 1113 Cut Filter 1114 ICP Ring 1115 Vacuum chamber 1116 Rotating shaft

Claims

1. A laminated structure in which an epitaxial film made of a compound semiconductor is formed on a substrate via a buffer layer, the substrate is a (100) oriented Si substrate; the buffer layer includes a conductive crystalline film containing nitrides of Hf and Zr, and one or two nitrides selected from Y and Ce, having a cubic crystal structure, and oriented in a (100) plane; The epitaxial film has a cubic crystal structure and contains c-BN, c-AlN, c-InN, c-SiC, GaAs, AlAs, InAs, GaP, AlP or InP.

2. A laminated structure as described in claim 1, in which a peak-valley structure is formed at the interface between the buffer layer and the epitaxial film, in which adjacent vertices and bottoms have different angles.

3. A laminated structure in which an epitaxial film made of a compound semiconductor is formed on a substrate via a buffer layer, the substrate is a (100) oriented Si substrate; the buffer layer includes an oxynitride of Hf and Zr, and one or more oxynitrides selected from Ti, Al, Y, and Ce, has a cubic crystal structure, and includes a conductive crystalline film oriented in (100); The epitaxial film has a cubic crystal structure and contains c-BN, c-AlN, c-InN, c-SiC, GaAs, AlAs, InAs, GaP, AlP or InP.

4. A laminated structure as described in claim 3, in which a peak-valley structure is formed at the interface between the buffer layer and the epitaxial film, in which adjacent vertices and bottoms have different angles.

5. A semiconductor device including a laminated structure, characterized in that the laminated structure is the laminated structure according to any one of claims 1 to 4.

6. 6. The semiconductor device according to claim 5, which is a vertical device.

7. 6. The semiconductor device according to claim 5, which is a Schottky barrier diode (SBD), a junction barrier Schottky diode (JBS), a metal semiconductor field effect transistor (MESFET), a high electron mobility transistor (HEMT), a metal oxide semiconductor field effect transistor (MOSFET), a static induction transistor (SIT), a junction field effect transistor (JFET), an insulated gate bipolar transistor (IGBT), a light emitting diode (LED), or a combination thereof.

8. A system including a semiconductor device, the semiconductor device being the semiconductor device according to claim 5.

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