Ceramic electronic components and their manufacturing method

Abstract

To provide a ceramic electronic component capable of increasing its humidity resistance while reducing an equivalent serial resistor (ESR) and a manufacturing method of the ceramic electronic component.SOLUTION: A ceramic electronic component has a lamination structure in which a plurality of dielectric layers mainly made of ceramic and three or more internal electrode layers are alternately laminated, the three or more internal electrode layers containing Ni and Sn, and with respect to the relation between at least two layers of the three or more internal electrode layers, an internal electrode layer on an end side in a lamination direction having a Sn concentration higher than an internal electrode layer on a center side in the lamination direction.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present invention relates to a ceramic electronic component and a method for manufacturing the same. [Background technology]

[0002] As electronic devices become smaller, ceramic electronic components such as multilayer ceramic capacitors mounted on electronic devices are also required to be smaller. To increase the capacitance, which is a basic characteristic, there are three possible methods: (1) increasing the dielectric constant of the dielectric layer, (2) increasing the capacitance-specified area, or (3) making the dielectric layer thinner. When the dielectric constant and element size are fixed, a thinner dielectric layer is advantageous because it allows a higher capacitance value per layer, and by making the dielectric layers and internal electrode layers thinner, it is possible to increase the number of layers to be stacked within a given thickness. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2007-258646 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, when the internal electrode layer is made thin, the internal electrode layer becomes more likely to break during the firing process. When moisture from the external environment penetrates into the broken part and reaches the functional area, defects such as poor insulation occur. If the dielectric layer is thin, this defect will be further accelerated. Patent Document 1 describes a method for making the internal electrode layer less likely to break by adjusting the addition ratio of nickel (Ni) paste and co-material for forming the internal electrode layer and the particle size. By arranging the internal electrode layer that is less likely to break as the outermost layer in the stacking direction, the intrusion of moisture from the outside is prevented and moisture resistance is improved. However, when the internal electrode layer becomes thin, the above method becomes insufficient in effect, and other measures are required.

[0005] One solution is to add tin (Sn) to the internal electrode layers. However, adding Sn to the internal electrode layers increases the ESR (equivalent series resistance) although it improves the moisture resistance.

[0006] The present invention has been made in view of the above-mentioned problems, and has an object to provide a ceramic electronic component that can improve moisture resistance while suppressing ESR, and a method for manufacturing the same. [Means for solving the problem]

[0007] The ceramic electronic component according to the present invention has a laminated structure in which a plurality of dielectric layers mainly composed of ceramic and three or more internal electrode layers are alternately laminated, the three or more internal electrode layers contain Ni and Sn, and is characterized in that, for at least two of the three or more internal electrode layers, the internal electrode layer at the end of the stacking direction has a higher Sn concentration than the internal electrode layer at the center of the stacking direction.

[0008] The ceramic electronic component may have an inner electrode layer at the center in the lamination direction to an inner electrode layer at the outermost end in the lamination direction, the inner electrode layer at the outermost end having the highest Sn concentration.

[0009] In the ceramic electronic component, the Sn concentration of each of the internal electrode layers from the outermost ends toward the center in the stacking direction may be higher than the Sn concentration of each of the remaining internal electrode layers toward the center in the stacking direction.

[0010] In the above ceramic electronic component, the Sn concentration of each internal electrode layer from the internal electrode layer at the center of the stacking direction to the internal electrode layer at the end of the stacking direction may increase stepwise or gradually from the internal electrode layer at the center of the stacking direction to the internal electrode layer at the end of the stacking direction.

[0011] In the ceramic electronic component, the three or more internal electrode layers may have a thickness of 1 μm or less.

[0012] In the three or more internal electrode layers of the ceramic electronic component, the Sn concentration may be 10 at % or less.

[0013] In the three or more internal electrode layers of the ceramic electronic component, the Sn concentration may be 0.1 at % or more.

[0014] In the ceramic electronic component, a ratio of a maximum Sn concentration to a minimum Sn concentration in each of the three or more internal electrode layers may be greater than 1 and less than or equal to 100.

[0015] In the internal electrode layer of the ceramic electronic component, a concentration of Sn may be higher in the vicinity of the interface with the dielectric layer than in a central portion in the thickness direction.

[0016] A method for manufacturing a ceramic electronic component according to the present invention includes the steps of forming a laminate unit by forming an internal electrode pattern containing Ni and Sn on a dielectric green sheet, forming a laminate by stacking three or more of the laminate units, and firing the laminate, and is characterized in that, in at least two layers of the internal electrode patterns before firing, the Sn concentration of the internal electrode patterns at the ends of the lamination direction is made higher than that of the internal electrode patterns at the center of the lamination direction. Effect of the Invention

[0017] According to the present invention, it is possible to provide a ceramic electronic component that can suppress ESR while improving moisture resistance, and a method for manufacturing the same. [Brief description of the drawings]

[0018] [Figure 1] FIG. 2 is a partial cross-sectional perspective view of a multilayer ceramic capacitor. [Diagram 2] 2 is a cross-sectional view taken along line AA in FIG. 1. [Diagram 3] FIG. 2 is a cross-sectional view taken along line BB in FIG. [Figure 4] 13(a) and (b) are diagrams illustrating the Sn concentration. [Diagram 5] FIG. 13 is a diagram illustrating an example of Sn concentration. [Figure 6] 4 is a diagram illustrating an example of the Sn concentration in an internal electrode layer. [Figure 7] 1A to 1C are diagrams illustrating a flow of a method for manufacturing a multilayer ceramic capacitor. [Figure 8] 1(a) and (b) are diagrams illustrating the lamination process. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] Hereinafter, an embodiment will be described with reference to the drawings.

[0020] (Embodiment) FIG. 1 is a partial cross-sectional perspective view of a multilayer ceramic capacitor 100 according to an embodiment. FIG. 2 is a cross-sectional view taken along line AA in FIG. 1. FIG. 3 is a cross-sectional view taken along line BB in FIG. 1. As illustrated in FIGS. 1 to 3, the multilayer ceramic capacitor 100 includes a laminated chip 10 having a substantially rectangular parallelepiped shape, and external electrodes 20a, 20b provided on any two opposing end faces of the laminated chip 10. Of the four faces of the laminated chip 10 other than the two end faces, the two faces other than the top and bottom faces in the stacking direction are referred to as side faces. The external electrodes 20a, 20b extend on the top, bottom and two side faces in the stacking direction of the laminated chip 10. However, the external electrodes 20a, 20b are spaced apart from each other.

[0021] The laminated chip 10 has a configuration in which a dielectric layer 11 containing a ceramic material that functions as a dielectric and three or more internal electrode layers 12 containing a base metal material are alternately laminated. The edges of the internal electrode layers 12 are alternately exposed to the end face on which the external electrode 20a of the laminated chip 10 is provided and the end face on which the external electrode 20b is provided. As a result, each internal electrode layer 12 is alternately conductive to the external electrode 20a and the external electrode 20b. As a result, the laminated ceramic capacitor 100 has a configuration in which a plurality of dielectric layers 11 are laminated via the internal electrode layers 12. In addition, in the laminate of the dielectric layers 11 and the internal electrode layers 12, the internal electrode layer 12 is disposed on the outermost layer in the lamination direction, and the upper and lower surfaces of the laminate are covered by the cover layer 13. The cover layer 13 is mainly composed of a ceramic material. For example, the material of the cover layer 13 is the same as that of the dielectric layers 11 and the ceramic material.

[0022] The size of the multilayer ceramic capacitor 100 is, for example, 0.25 mm in length, 0.125 mm in width, and 0.125 mm in height, or 0.4 mm in length, 0.2 mm in width, and 0.2 mm in height, or 0.6 mm in length, 0.3 mm in width, and 0.3 mm in height, or 1.0 mm in length, 0.5 mm in width, and 0.5 mm in height, or 3.2 mm in length, 1.6 mm in width, and 1.6 mm in height, or 4.5 mm in length, 3.2 mm in width, and 2.5 mm in height, but is not limited to these sizes.

[0023] The dielectric layer 11 is mainly composed of a ceramic material having a perovskite structure represented by the general formula ABO3. 3-α For example, the ceramic material includes BaTiO3 (barium titanate), CaZrO3 (calcium zirconate), CaTiO3 (calcium titanate), SrTiO3 (strontium titanate), BaTiO3 (strontium titanate) which forms a perovskite structure, 1-x-y Ca x Sr y Ti 1-z Zr zO3 (0≦x≦1, 0≦y≦1, 0≦z≦1), etc. can be used. The thickness of each dielectric layer 11 is, for example, 0.05 μm or more and 5 μm or less, or 0.1 μm or more and 3 μm or less, or 0.2 μm or more and 1 μm or less.

[0024] 2, a region where the internal electrode layer 12 connected to the external electrode 20a and the internal electrode layer 12 connected to the external electrode 20b face each other is a region that generates capacitance in the multilayer ceramic capacitor 100. Therefore, the region that generates capacitance is referred to as a capacitance region 14. In other words, the capacitance region 14 is a region where adjacent internal electrode layers 12 connected to different external electrodes face each other.

[0025] The region where the internal electrode layers 12 connected to the external electrode 20a face each other without an internal electrode layer 12 connected to the external electrode 20b being interposed therebetween is referred to as the end margin 15. The region where the internal electrode layers 12 connected to the external electrode 20b face each other without an internal electrode layer 12 connected to the external electrode 20a being interposed therebetween is also the end margin 15. In other words, the end margin 15 is a region where the internal electrode layers 12 connected to the same external electrode face each other without an internal electrode layer 12 connected to a different external electrode being interposed therebetween. The end margin 15 is a region that does not generate capacitance.

[0026] 3, in the laminated chip 10, the regions extending from the two side surfaces of the laminated chip 10 to the internal electrode layers 12 are referred to as side margins 16. That is, the side margins 16 are regions provided to cover the ends of the multiple internal electrode layers 12 stacked in the above-mentioned laminated structure that extend to the two side surfaces. The side margins 16 are also regions that do not generate electrical capacitance.

[0027] All the internal electrode layers 12 contain Ni and Sn. For example, each internal electrode layer 12 is mainly composed of Ni and also contains Sn. When the internal electrode layers 12 contain Ni and Sn, the moisture resistance of the multilayer ceramic capacitor 100 can be improved. For example, it is considered that the moisture resistance of the multilayer ceramic capacitor 100 is improved by changing the state of the interface between the internal electrode layer 12 and the dielectric layer 11 due to the alloying of Ni and Sn.

[0028] However, when the internal electrode layer 12 contains Sn in addition to Ni, the electrical resistance of the internal electrode layer 12 may increase. As a result, the ESR of the entire multilayer ceramic capacitor 100 may increase. Therefore, the multilayer ceramic capacitor 100 according to this embodiment has a configuration that improves moisture resistance while suppressing the ESR.

[0029] As a result of intensive research by the present inventor, it was found that the shorter the distance from the external environment, the easier moisture penetrates into the multilayer ceramic capacitor 100. Therefore, the multilayer ceramic capacitor 100 according to this embodiment has a configuration in which the internal electrode layer 12 with a high Sn concentration is arranged at the end side of the stacking direction relative to the internal electrode layer 12 with a low Sn concentration in at least two layers in the range from the internal electrode layer 12 at the center of the stacking direction to the internal electrode layer 12 at the end of the stacking direction. With this configuration, the Sn concentration of the internal electrode layer 12, which is close to the external environment and easily penetrates moisture, is high, so that the effect of improving the moisture resistance of the multilayer ceramic capacitor 100 is enhanced. In addition, since the Sn concentration of the internal electrode layer 12, which is long from the external environment and difficult for moisture to penetrate, is low, the ESR can be suppressed while suppressing the decrease in moisture resistance of the multilayer ceramic capacitor 100. From the above, it is possible to improve the moisture resistance while suppressing the ESR of the multilayer ceramic capacitor 100. Note that, if the number of layers of the internal electrode layers 12 is an even number, the internal electrode layer at the center of the stacking direction refers to the two internal electrode layers at the center of the stacking direction. If the number of stacked internal electrode layers 12 is an odd number, the internal electrode layer at the center in the stacking direction refers to one internal electrode layer at the center in the stacking direction.

[0030] For example, as illustrated in Fig. 4(a), it is preferable that the Sn concentration of the inner electrode layer 12 at the end of the stacking direction is the highest from the inner electrode layer 12 at the center to the inner electrode layer 12 at the end of the stacking direction. In this configuration, the Sn concentration of the inner electrode layer 12 that is closest to the external environment is the highest, which enhances the effect of improving the moisture resistance of the multilayer ceramic capacitor 100. In Fig. 4(a), the inner electrode layer 12 at the end of the stacking direction is drawn black to indicate that the Sn concentration of the inner electrode layer 12 at the end is the highest.

[0031] For example, as illustrated in Fig. 4(b), it is preferable that the Sn concentration of each of the multiple internal electrode layers 12 (internal electrode layers 12 in the outer layer region) from the outermost layer to the center in the stacking direction is higher than the Sn concentration of each of the remaining internal electrode layers 12 (internal electrode layers 12 in the center region) on the center side in the stacking direction. In this configuration, the Sn concentration of each internal electrode layer 12 in the outer layer region, which is closer to the external environment, is higher, which enhances the effect of improving the moisture resistance of the multilayer ceramic capacitor 100. In Fig. 4(b), the internal electrode layers 12 are shaded from white to black to indicate the magnitude relationship of the Sn concentration.

[0032] In the configuration of Fig. 4(b), if the outer layer region where the Sn concentration is high is too narrow, the ESR may be low but sufficient moisture resistance may not be obtained. Therefore, it is preferable to set a lower limit for the range of the outer layer region. For example, the outer layer region is more than 0% and preferably 5% or more, more preferably 10% or more, of all the internal electrode layers 12 from the upper and lower ends to the center in the stacking direction.

[0033] On the other hand, if the outer layer region where the Sn concentration is high is too wide, sufficient moisture resistance can be obtained, but the ESR may become large. Therefore, it is preferable to set an upper limit on the range of the outer layer region. For example, the outer layer region is preferably 45% or less, more preferably 30% or less, and even more preferably 20% or less of the total internal electrode layer 12 from the upper and lower ends to the center in the stacking direction.

[0034] For example, as illustrated in FIG. 5, it is preferable that the Sn concentration of each internal electrode layer 12 from the internal electrode layer 12 at the center of the stacking direction to the internal electrode layer 12 at the end of the stacking direction increases stepwise or gradually from the internal electrode layer 12 at the center of the stacking direction to the internal electrode layer 12 at the end. In this configuration, the Sn concentration of the internal electrode layer 12 that is close to the external environment and easily penetrates moisture is high, so the effect of improving the moisture resistance of the multilayer ceramic capacitor 100 is enhanced. In addition, the Sn concentration of the internal electrode layer 12 that is long from the external environment and is difficult for moisture to penetrate is low, so that the ESR can be suppressed while suppressing the deterioration of the moisture resistance of the multilayer ceramic capacitor 100. Note that "gradually increasing" includes a continuous increase (monotonous increase) and also includes an overall increase while repeating ups and downs when the Sn concentration is measured at multiple sample points from the internal electrode layer 12 at the center of the stacking direction to the internal electrode layer 12 at the end.

[0035] The thickness of each internal electrode layer 12 is, for example, 0.01 μm to 5 μm, or 0.05 μm to 3 μm, or 0.1 μm to 1 μm. For example, if the thickness of the internal electrode layer 12 is 1 μm or less, the continuity rate is likely to decrease due to fracture during firing, so that the effect of the configuration according to this embodiment is significantly exhibited. In the multilayer ceramic capacitor 100, the number of layers of the internal electrode layer 12 is, for example, 10 to 5000, 50 to 4000, or 100 to 3000.

[0036] If the Sn concentration of each internal electrode layer 12 is too high, the ESR of the multilayer ceramic capacitor 100 may become high, or the internal electrode layer 12 may dissolve during firing. Therefore, it is preferable to set an upper limit for each Sn concentration. For example, the Sn concentration of each internal electrode layer 12 is preferably 10 at% or less, more preferably 5 at% or less, and even more preferably 1 at% or less. Note that the at% of Sn refers to the atomic concentration ratio of Sn when the total amount of Ni and Sn is 100 at%.

[0037] On the other hand, if the Sn concentration of each internal electrode layer 12 is too low, sufficient moisture resistance may not be obtained for the multilayer ceramic capacitor 100. Therefore, it is preferable to set a lower limit for each Sn concentration. For example, the Sn concentration of each internal electrode layer 12 is preferably 0.01 at% or more, more preferably 0.05 at% or more, and even more preferably 0.1 at% or more.

[0038] For example, for each Sn concentration in each internal electrode layer 12, the ratio of the maximum Sn concentration to the minimum Sn concentration is preferably greater than 1 and not greater than 1000, more preferably 1.5 to 100, and even more preferably 2 to 50.

[0039] In addition, it is preferable that the Sn concentration is high in the internal electrode layer 12 near the interface with the dielectric layer 11. This is because the reliability is determined not by the entire internal electrode layer, but only by the vicinity of the interface between the dielectric layer 11 and the internal electrode layer 12. Therefore, as illustrated in Fig. 6, it is preferable that the internal electrode layer 12 has a concentration gradient such that the Sn concentration is low in the center in the thickness direction and high near the interface with the dielectric layer 11.

[0040] Since the internal electrode layers 12 contain Sn in addition to Ni, the mechanical strength of each internal electrode layer 12 is improved. Since all the internal electrode layers 12 contain Sn in addition to Ni, the mechanical strength of the multilayer ceramic capacitor 100 is improved.

[0041] Next, a description will be given of a method for manufacturing the multilayer ceramic capacitor 100. FIG.

[0042] (Raw powder production process) First, a dielectric material for forming the dielectric layer 11 is prepared. The A-site elements and B-site elements contained in the dielectric layer 11 are usually contained in the dielectric layer 11 in the form of a sintered body of ABO3 particles. For example, BaTiO3 is a tetragonal compound having a perovskite structure and exhibits a high dielectric constant. This BaTiO3 can generally be obtained by synthesizing barium titanate by reacting a titanium raw material such as titanium dioxide with a barium raw material such as barium carbonate. Various methods have been known so far as a method for synthesizing the main component ceramic of the dielectric layer 11, such as a solid-phase method, a sol-gel method, a hydrothermal method, and the like. In this embodiment, any of these methods can be adopted.

[0043] A predetermined additive compound is added to the obtained ceramic powder according to the purpose. The additive compound may be an oxide of magnesium (Mg), manganese (Mn), vanadium (V), chromium (Cr), rare earth elements (yttrium (Y), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm) and ytterbium (Yb)), or an oxide containing cobalt (Co), nickel (Ni), lithium (Li), boron (B), sodium (Na), potassium (K) or silicon (Si), or a glass containing cobalt, nickel, lithium, boron, sodium, potassium or silicon.

[0044] For example, a compound containing an additive compound is wet-mixed with a ceramic raw material powder, and then dried and pulverized to prepare a ceramic material. For example, the ceramic material obtained as described above may be pulverized as necessary to adjust the particle size, or may be combined with a classification process to adjust the particle size. Through the above steps, a dielectric material is obtained.

[0045] (Lamination process) Next, a binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol or toluene, and a plasticizer are added to the obtained dielectric material and wet mixed. The obtained slurry is used to coat a dielectric green sheet 52 on a substrate 51 by, for example, a die coater method or a doctor blade method, and then dried. The substrate 51 is, for example, a PET (polyethylene terephthalate) film.

[0046] Next, as illustrated in FIG. 8(a), an internal electrode pattern 53 is formed on a dielectric green sheet 52. In FIG. 8(a), as an example, four layers of internal electrode patterns 53 are formed on the dielectric green sheet 52 at predetermined intervals. The film formation method is not particularly limited, but for example, an electrode paste containing NiSn alloy powder or a mixture of Ni powder and Sn powder is used. Alternatively, vacuum film formation such as sputtering using a NiSn alloy target, simultaneous sputtering using individual targets of Ni and Sn, etc. may be used. The dielectric green sheet 52 on which the internal electrode pattern 53 is formed is regarded as a lamination unit.

[0047] Next, while peeling off the dielectric green sheet 52 from the substrate 51, three or more lamination units are laminated as shown in Fig. 8(b). In this case, in at least two layers of each internal electrode pattern, the Sn concentration of the internal electrode pattern on the end side in the lamination direction is made higher than that of the internal electrode pattern on the center side in the lamination direction. The Sn concentration of each internal electrode pattern may be adjusted so as to obtain the Sn concentration distributions in Figs. 4(a) to 5.

[0048] Next, a predetermined number of cover sheets (e.g., 2 to 10 layers) are laminated on the top and bottom of the laminate obtained by laminating the lamination units, and are thermocompression bonded, and then cut into a predetermined chip size (e.g., 1.0 mm x 0.5 mm). In the example of Fig. 8(b), cutting is performed along the dotted lines. The cover sheet may have the same components as the dielectric green sheet 52, or may have a different additive compound.

[0049] (Firing process) The ceramic laminate thus obtained was subjected to binder removal treatment in a N2 atmosphere, after which a metal paste that would become the undercoat layers of the external electrodes 20a and 20b was applied thereto by a dipping method, and the ceramic laminate was then subjected to a dipping treatment in a nitrogen atmosphere under an oxygen partial pressure of 10 -5 ~10 -8 The laminated ceramic capacitor 100 is thus obtained, and is then fired in a reducing atmosphere of 1 atm at 1100 to 1300° C. for 10 minutes to 2 hours.

[0050] (Reoxidation treatment process) After that, a re-oxidation treatment may be performed at 600°C to 1000°C in an N2 gas atmosphere.

[0051] (Plating process) Thereafter, the external electrodes 20a, 20b may be coated with a metal such as Cu, Ni, Sn, etc. by plating.

[0052] According to the manufacturing method of this embodiment, in at least two layers ranging from the internal electrode layer 12 at the center in the stacking direction to the internal electrode layer 12 at the end of the stacking direction, the internal electrode layer 12 with a high Sn concentration is disposed closer to the end in the stacking direction than the internal electrode layer 12 with a low Sn concentration. This makes it possible to improve the moisture resistance while suppressing the ESR of the multilayer ceramic capacitor 100.

[0053] In the above embodiments, a multilayer ceramic capacitor has been described as an example of a ceramic electronic component, but the present invention is not limited to this. For example, other electronic components such as a varistor or a thermistor may be used. EXAMPLES

[0054] The multilayer ceramic capacitor according to the embodiment was fabricated and its characteristics were examined.

[0055] Example 1 Additives were added to the barium titanate powder, and the mixture was thoroughly wet mixed and pulverized in a ball mill to obtain a dielectric material. A butyral-based organic binder, toluene and ethyl alcohol were added to the dielectric material as a solvent, and a dielectric green sheet was applied onto a PET substrate by the doctor blade method. The thickness of the dielectric green sheet was 1 μm.

[0056] Next, an internal electrode pattern was formed on the dielectric green sheet using a paste containing a Ni--Sn alloy.

[0057] Next, the laminate units were stacked while peeling off the dielectric green sheet from the substrate. The number of stacks was 1000. Next, a predetermined number of cover sheets were stacked on the top and bottom of the laminate obtained by stacking the laminate units, and were thermocompression bonded. After that, it was cut to the predetermined chip dimensions (1.0 mm x 0.5 mm x 0.5 mm).

[0058] The ceramic laminate thus obtained was subjected to a binder removal treatment in an N2 atmosphere, after which a metal paste that would become the base layer of the external electrodes was applied thereto by a dipping method, and then fired in a reducing atmosphere.

[0059] The thickness of each internal electrode layer 12 after firing was 0.5 μm. In the laminated chip 10, the Sn concentration of the internal electrode layers 12 in the outer layer region 20 μm from the end in the lamination direction was 3 at%. The outer layer region 20 μm from the end in the lamination direction includes 9 internal electrode layers 12. The Sn concentration of the internal electrode layers 12 in the central region excluding the outer layer region was 0.2 at%. 。

[0060] Example 2 In Example 2, the Sn concentration of the internal electrode layers 12 in the central region excluding the outer layer region 10 μm from the outermost end in the lamination direction in the laminated chip 10 was set to 0.05 at %. The other conditions were the same as those in Example 1.

[0061] Example 3 In Example 3, the Sn concentration of the internal electrode layers 12 in the outer layer region 10 μm from the end in the stacking direction of the laminated chip 10 was 10 at%. The Sn concentration of the internal electrode layers 12 in the central region excluding the outer layer region was 0.1 at%. The other conditions were the same as those of Example 1.

[0062] Comparative Example 1 In Comparative Example 1, Sn was not added to any of the internal electrode layers 12. The other conditions were the same as those in Example 1.

[0063] Comparative Example 2 In the comparative example 2, the Sn concentration was set to 3 at% in both the internal electrode layers 12 in the outer layer region 10 μm from the end in the stacking direction and the internal electrode layers 12 in the central region excluding the outer layer region in the laminated chip 10. The other conditions were the same as those in the example 1.

[0064] Comparative Example 3 In Comparative Example 3, the Sn concentration of the internal electrode layers 12 in the outer layer region 10 μm from the end in the stacking direction of the laminated chip 10 was 0.2 at%. The Sn concentration of the internal electrode layers 12 in the central region excluding the outer layer region was 3 at%. The other conditions were the same as those of Example 1.

[0065] (analysis) For each of Examples 1 to 3 and Comparative Examples 1 to 3, the humidity load life (min), flexural strength (N), and ESR (mΩ) were measured. The humidity load life was measured at a temperature of 85°C and a humidity of 85%. The flexural strength (N) was measured by placing both ends of the element on a bridge, pressing the center from above with a blade having a specified tip diameter, and measuring the load at the time when the element broke. The ESR was calculated from the frequency characteristics of the impedance. The results are shown in Table 1. Table 1 also shows the ratio of the Sn concentration in the outer layer region to the Sn concentration in the central region. [Table 1]

[0066] The humidity load life was judged to be acceptable if it exceeded 1000 min. The ESR was judged to be acceptable if it was less than 15 mΩ. In all of Examples 1 to 3, both the humidity load life and the ESR were judged to be acceptable. This is believed to be because the Sn concentration of the internal electrode layer that is close to the external environment was increased and the Sn concentration of the internal electrode layer that is long from the external environment was decreased. In addition, in all of Examples 1 to 3, a large flexural strength was obtained. This is believed to be because the mechanical strength was improved by adding Sn to the internal electrode layer together with Ni.

[0067] The humidity resistance load life was judged to be unacceptable for Comparative Example 1. This is believed to be because sufficient humidity resistance was not obtained due to the absence of Sn added to the internal electrode layers.

[0068] The ESR was judged to be unacceptable for Comparative Example 2. This is believed to be because the Sn concentration in the internal electrode layer, which is far from the external environment, was also increased.

[0069] The humidity resistance load life was judged to be unacceptable for Comparative Example 3. This is believed to be because sufficient humidity resistance was not obtained by reducing the amount of Sn in the internal electrode layer, which is close to the external environment.

[0070] Example 4 In Example 4, the Sn concentration of the inner electrode layer at the end of the lamination direction was set to 3 at%, and the Sn concentration of the inner electrode layer at the center of the lamination direction was set to 0.2 at%, so that the Sn concentration increased stepwise from the center to the end of the lamination direction. Specifically, the Sn concentration of the inner electrode layer increased stepwise for every 10 layers from the center to the end, and the Sn concentration was set to 50 steps. For Example 4, the humidity load life (min), flexural strength (N), and ESR (mΩ) were also measured. The results are shown in Table 2. As shown in Table 2, both the humidity load life and ESR were judged to be acceptable. This is believed to be because the Sn concentration of the inner electrode layer that is close to the external environment was increased and the Sn concentration of the inner electrode layer that is long from the external environment was decreased. In addition, a large flexural strength was obtained. This is believed to be because the mechanical strength was improved by adding Sn to the inner electrode layer together with Ni. [Table 2]

[0071] Although the embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and variations are possible within the scope of the gist of the present invention described in the claims. [Explanation of symbols]

[0072] 10 Stacked Chip 11 Dielectric layer 12 Internal electrode layer 13 Cover Layer 14 Capacity area 15 End Margin 16 Side Margin 20a,20b external electrode 51 Base material 52 Dielectric green sheet 53 Internal electrode pattern 100 Multilayer ceramic capacitors

Claims

1. The capacitor has a laminated structure in which a plurality of dielectric layers mainly made of ceramic and a plurality of internal electrode layers are alternately laminated, the internal electrode layers include Ni and Sn; The plurality of internal electrode layers include a plurality of internal electrode layers provided from the ends toward the center in the stacking direction, and the remaining internal electrode layers toward the center in the stacking direction, a Sn concentration of each of the plurality of internal electrode layers disposed from the outermost end toward the center in the lamination direction is higher than a Sn concentration of each of the remaining internal electrode layers toward the center in the lamination direction.

2. 2. The ceramic electronic component according to claim 1, wherein the Sn concentration of the inner electrode layer at the outermost end in the lamination direction is the highest from the inner electrode layer at the center in the lamination direction to the inner electrode layer at the outermost end in the lamination direction.

3. 2. The ceramic electronic component according to claim 1, wherein the Sn concentration of each of the internal electrode layers from the internal electrode layer at the center in the stacking direction to the internal electrode layer at the end in the stacking direction increases stepwise or gradually from the internal electrode layer at the center in the stacking direction to the internal electrode layer at the end in the stacking direction.

4. A ceramic electronic component described in any one of claims 1 to 3, characterized in that the thickness of the multiple internal electrode layers provided in the laminated structure is 1 μm or less.

5. A ceramic electronic component described in any one of claims 1 to 4, characterized in that in the internal electrode layer provided in the laminated structure, the Sn concentration is 10 at% or less.

6. A ceramic electronic component described in any one of claims 1 to 5, characterized in that the Sn concentration in the internal electrode layer provided in the laminated structure is 0.1 at% or more.

7. A ceramic electronic component described in any one of claims 1 to 6, characterized in that the ratio of the maximum Sn concentration to the minimum Sn concentration in the internal electrode layer provided in the laminated structure is greater than 1 and not greater than 100.

8. A ceramic electronic component described in any one of claims 1 to 7, characterized in that in the internal electrode layer provided in the laminated structure, the concentration of Sn is higher near the interface with the dielectric layer than in the center in the thickness direction.

9. The capacitor has a laminated structure in which a plurality of dielectric layers mainly made of ceramic and a plurality of internal electrode layers are alternately laminated, the internal electrode layers include Ni and Sn; the plurality of internal electrode layers include a plurality of internal electrode layers provided from the ends toward the center in the stacking direction, and the remaining internal electrode layers toward the center in the stacking direction, A ceramic electronic component, characterized in that the Sn concentration of each internal electrode layer from the internal electrode layer at the center of the stacking direction to the internal electrode layer at the end of the stacking direction increases stepwise or gradually from the internal electrode layer at the center of the stacking direction to the internal electrode layer at the end of the stacking direction.

10. forming an internal electrode pattern containing Ni and Sn on a dielectric green sheet to form a laminate unit; forming a laminate by stacking the laminate units; and firing the laminate. The laminate includes a plurality of lamination units provided from an end to a center side in a lamination direction, and a remaining lamination unit on a center side in the lamination direction, 13. A method for manufacturing a ceramic electronic component, comprising the steps of: (a) forming a first insulating layer on a first surface of a ceramic substrate; and (b) forming a first insulating layer on the first surface of the ceramic substrate.

11. forming an internal electrode pattern containing Ni and Sn on a dielectric green sheet to form a laminate unit; forming a laminate by stacking three or more of the laminate units; and firing the laminate. The laminate includes a plurality of lamination units provided from an end to a center side in a lamination direction, and a remaining lamination unit on a center side in the lamination direction, 4. A method for manufacturing a ceramic electronic component, comprising the steps of: increasing, before firing, a Sn concentration of each of the internal electrode patterns from a center internal electrode pattern in the lamination direction to an end internal electrode pattern in the lamination direction in a stepwise or gradually manner from the center internal electrode pattern in the lamination direction to the end internal electrode pattern in the lamination direction.

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