Semiconductor device and its manufacturing method

Abstract

To provide a semiconductor device with improved reliability.SOLUTION: A semiconductor device includes a clip CLL that is electrically connected to a source pad SPL for a main transistor through a silver paste 50B and connected to a lead 60A through a silver paste 50C. This clip CLL includes a first part P1 in contact with the silver paste 50B, a second part P2 in contact with the silver paste 50C, and a third part P3 present between the first part P1 and the second part P2. On a surface of the source pad SPL for the main transistor, a protrusion member 100 is formed. The first part P1 is in contact with the protrusion member 100.SELECTED DRAWING: Figure 7

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly to a technique that is effective when applied to a semiconductor device that is a component of an inverter, for example, and a manufacturing technique thereof. [Background technology]

[0002] Japanese Patent Laid-Open Publication No. 2018-121035 (Patent Document 1) describes a technology related to a packaging structure of a semiconductor device that is a component of an inverter.

[0003] Japanese Patent Application Laid-Open Publication No. 2009-200338 (Patent Document 2) describes a technology for electrically connecting a semiconductor chip on which a power MOSET (Metal Oxide Semiconductor Field Effect Transistor) is formed and a lead serving as an external terminal to each other and electrically using a plate-like member called a "Cu clip," in which the plate-like member is electrically connected to a source pad of the semiconductor chip via a conductive member such as a solder material or silver paste. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2018-121035 A [Patent Document 2] JP 2009-200338 A Summary of the Invention [Problem to be solved by the invention]

[0005] For example, there exists a semiconductor device that encapsulates a semiconductor chip on which a power transistor is formed, in which leads and electrodes called pads formed on the surface of the semiconductor chip are connected by a plate-like member called a "clip." In this semiconductor device, it is desirable to improve the connection reliability between the pads and the plate-like member. [Means for solving the problem]

[0006] A semiconductor device according to one embodiment includes a plate-like member electrically connected to a first electrode via a first conductive member and connected to a lead via a second conductive member. The plate-like member has a first portion with which the first conductive member contacts, a second portion with which the second conductive member contacts, and a third portion located between the first and second portions. A protruding member is formed on a surface of the first electrode, and the first portion contacts the protruding member.

[0007] A semiconductor device according to one embodiment includes a plate-like member electrically connected to a first electrode via a first conductive member and connected to a lead via a second conductive member. The plate-like member has a first portion with which the first conductive member contacts, a second portion with which the second conductive member contacts, and a third portion located between the first and second portions. A protruding member is formed on a protective film covering a peripheral portion of the first electrode, the protruding member contacting the third portion.

[0008] In one embodiment, a method for manufacturing a semiconductor device includes a step of electrically connecting the first electrode and the lead to each other via the plate-shaped member by placing a first portion of the plate-shaped member on a first electrode via a first conductive member, and placing a second portion of the plate-shaped member on the lead via a second conductive member.

[0009] In this process, the plate-shaped member is placed on the first electrode and the lead with the first portion positively inclined so that the height of the protruding member is greater than the height between the tip of the plate-shaped member included in the first portion and the surface of the first electrode by contacting the first portion or the third portion of the plate-shaped member with the protruding member. Effect of the Invention

[0010] According to one embodiment, the reliability of the semiconductor device can be improved. [Brief description of the drawings]

[0011] [Figure 1] FIG. 1 is a diagram illustrating a schematic configuration of a 12-phase brushless DC motor control system. [Diagram 2] FIG. 2 is a diagram showing a circuit configuration of an inverter circuit. [Diagram 3] FIG. 1 is a diagram showing a mounting configuration of a semiconductor device that realizes an inverter circuit. [Figure 4] FIG. 13 is a cross-sectional view illustrating a molding process for forming a sealing body, which is a view for explaining room for improvement newly found by the present inventors. [Diagram 5] FIG. 13 shows the clip in a "reverse tilt" state. [Figure 6] FIG. 1 is a schematic diagram showing a related art. [Figure 7] FIG. 2 is a schematic diagram showing a specific embodiment. [Figure 8] FIG. 13 is a diagram for explaining an example of a dimensional relationship. [Figure 9] FIG. 13 is a diagram for explaining an example of a dimensional relationship. [Figure 10] FIG. 13 is a diagram for explaining an example of a dimensional relationship. [Figure 11] 1A to 1C are cross-sectional views showing a manufacturing process of a semiconductor chip. [Figure 12] 12A to 12C are cross-sectional views showing the manufacturing process of the semiconductor chip following FIG. [Figure 13] 13 is a cross-sectional view showing a manufacturing process of the semiconductor chip following FIG. 12. [Figure 14] 14 is a cross-sectional view showing a manufacturing process of the semiconductor chip following FIG. 13. [Figure 15] 1 is a flowchart illustrating an assembly process of a semiconductor device. [Figure 16] 16 is a diagram illustrating a connecting process of the clip in FIG. 15. FIG. [Figure 17] FIG. 15 is a diagram illustrating a resin sealing step. [Figure 18] 13(a) to 13(g) are diagrams showing planar variations of the protruding member. [Figure 19] 13A and 13B are diagrams illustrating an example of the configuration of a protruding member in Modification 3. [Figure 20]13A and 13B are diagrams illustrating another configuration example of the protruding member in the third modification. [Figure 21] FIG. 13 is a schematic diagram showing a fourth modified example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] In all the drawings for explaining the embodiments, the same members are generally designated by the same reference numerals, and the repeated explanations thereof will be omitted. In addition, hatching may be applied even to plan views in order to make the drawings easier to understand.

[0013] <12-phase brushless DC motor control system> A 12-phase brushless DC motor control system that controls a 12-phase brushless DC motor uses four sets of conventional three phases (U phase, V phase, and W phase).

[0014] An inverter circuit is used as a circuit to control each phase, and the AC power supplied from this inverter circuit is supplied to the coils of each phase of the brushless DC motor. For this reason, a brushless DC motor control system that controls a 6-phase brushless DC motor or a 12-phase brushless DC motor uses 6 or 12 inverter circuits.

[0015] FIG. 1 is a diagram illustrating a schematic configuration of a 12-phase brushless DC motor control system.

[0016] The motor MOT shown in FIG. 1 is a 12-phase brushless DC motor and has 12 coils CL. Each coil CL is connected to an inverter circuit INV. That is, an inverter circuit INV is provided for each of the 12 coils of the motor MOT. Therefore, the 12-phase brushless DC motor control system shown in FIG. 1 has a total of 12 inverter circuits INV. Each inverter circuit INV is connected to a control circuit CT provided in an MCU (Micro Controller Unit), and each inverter circuit is controlled by this control circuit CT. Then, each inverter circuit INV controlled by the control circuit CT supplies AC power to the coils CL connected to the respective inverter circuits INV, thereby driving the motor MOT.

[0017] <Inverter circuit configuration> Next, a circuit configuration of the inverter circuit INV, which is a component of the above-mentioned 12-phase brushless DC motor control system, will be described.

[0018] FIG. 2 is a diagram showing a circuit configuration of the inverter circuit INV.

[0019] 2, the inverter circuit INV has a high-side switching circuit 10, a low-side switching circuit 20, and a control circuit 30.

[0020] The high-side switching circuit 10 includes a main transistor 11 which is a power transistor, and a sense transistor 12 .

[0021] On the other hand, the low-side switching circuit 20 includes a main transistor 21 made of a power transistor, and a sense transistor 22 .

[0022] In the high-side switching circuit 10 and the low-side switching circuit 20 configured in this manner, the main transistor 11 included in the high-side switching circuit 10 and the main transistor 21 included in the low-side switching circuit 20 are connected in series between a power supply potential VIN and a ground potential GND.

[0023] 2, the connection node between the main transistor 11 and the main transistor 21 is "OUT", and this connection node is connected to the coil CL shown in FIG.

[0024] Next, the control circuit 30 includes, for example, a pre-driver that applies a gate voltage to the gate electrode of the main transistor 11 and the gate electrode of the sense transistor 12, and a pre-driver that applies a gate voltage to the gate electrode of the main transistor 21 and the gate electrode of the sense transistor 22. In this manner, the inverter circuit INV is configured.

[0025] The control circuit 30 is configured to control the on / off of the main transistor 11 included in the high-side switching circuit 10 and to control the on / off of the main transistor 21 included in the low-side switching circuit 20, based on a control signal from the control circuit CT shown in Fig. 1. That is, the control circuit 30 controls the on / off of the main transistor 11 by switching the gate voltage applied to the gate electrode of the main transistor 11, and controls the on / off of the main transistor 21 by switching the gate voltage applied to the gate electrode of the main transistor 21.

[0026] In this manner, by controlling the main transistor 11 on / off and the main transistor 21 on / off, AC power is supplied from the connection node ("OUT") between the main transistor 11 and the main transistor 21 to the coil CL shown in FIG.

[0027] The inverter circuit INV is configured as described above.

[0028] <Package structure> Next, the mounting configuration of the inverter circuit INV will be described.

[0029] FIG. 3 is a diagram showing a mounting configuration of a semiconductor device PKG that realizes an inverter circuit.

[0030] 3, the semiconductor device PKG has a sealing body MR having a rectangular planar shape. The sealing body MR has a side S1 which is a long side, a side S2 which faces the side S1, a side S3 which is a short side intersecting the sides S1 and S2, and a side S4 which faces the side S3. The leads LD protrude from the long sides S1 and S2.

[0031] 3, the outline of the sealing body MR is indicated by a dashed line, and components sealed inside the sealing body MR are illustrated. The internal configuration of the sealing body MR will be described below.

[0032] The semiconductor device PKG has a die pad DPC which is a chip mounting portion, a die pad DPL which is a chip mounting portion, and a die pad DPH which is a chip mounting portion. Specifically, the die pad DPL, the die pad DPC, and the die pad DPH are arranged in this order in the x direction. In other words, the die pad DPL is arranged on the left side, the die pad DPC is arranged in the center, and the die pad DPH is arranged on the right side.

[0033] A semiconductor chip CPC is mounted on the die pad DPC. A control circuit 30 shown in FIG. 2 is formed on this semiconductor chip CPC. A plurality of pads including, for example, a plurality of pads PDC1 and a plurality of pads PDC2 are formed on the surface of the semiconductor chip CPC. In this manner, the semiconductor chip CPC mounted on the die pad DPC is disposed in the center of the semiconductor device PKG.

[0034] Next, the semiconductor chip CPL is mounted on the die pad DPL. The low-side switching circuit 20 shown in FIG. 2 is formed on this semiconductor chip CPL. That is, the main transistor 21 and the sense transistor 22 constituting the low-side switching circuit 20 are formed on the semiconductor chip CPL. The main transistor 21 and the sense transistor 22 are composed of vertical trench power transistors that pass a current in the thickness direction of the semiconductor chip CPL. Then, a plurality of pads PDL are formed on the surface of the semiconductor chip CPL together with a source pad SPL for the main transistor. The plurality of pads PDL include a source pad for the sense transistor and a gate pad common to the main transistor 21 and the sense transistor 22.

[0035] As shown in Fig. 3, a clip CLL, which is a plate-like member made of copper, is disposed on the main transistor source pad SPL. As shown in Fig. 3, the clip CLL is electrically connected to the leads LDL. Meanwhile, each of the pads PDL is electrically connected to each of the pads PDC2 formed on the surface of the semiconductor chip CPC by a bonding wire W.

[0036] Next, the semiconductor chip CPH is mounted on the die pad DPH. The high-side switching circuit 10 shown in Fig. 2 is formed on this semiconductor chip CPH. Here, in this embodiment, the semiconductor chip CPL on which the low-side switching circuit 20 is formed and the semiconductor chip CPH on which the high-side switching circuit 10 is formed are the same type of semiconductor chip. For this reason, the description of the semiconductor chip CPH will be omitted.

[0037] In this embodiment, the planar shape of the semiconductor device PKG is substantially rectangular (specifically, a rectangle with each corner chamfered) as shown in Fig. 3. In this embodiment, the planar shape of each semiconductor chip is also rectangular as shown in Fig. 3. In this embodiment, the semiconductor chip CPC, the semiconductor chip CPL, and the semiconductor chip CPH are arranged so that the short side of each semiconductor chip is aligned with the long side of the semiconductor device PKG as shown in Fig. 3. This reduces the size of each semiconductor chip and the size of the semiconductor device PKG.

[0038] In this manner, a semiconductor device PKG is implemented and configured, which is composed of a SiP (System in Package) in which the semiconductor chip CPC, on which the circuit that constitutes the inverter circuit INV is formed, the semiconductor chip CPL, and the semiconductor chip CPH are implemented in a single package structure.

[0039] <Consideration of improvements> In the following, the clip CLL is taken up as an example of a plate-like member, and room for improvement in the semiconductor device PKG is described. However, as shown in Fig. 3, the semiconductor device PKG has not only the clip CLL, but also the clip CLH. There is room for improvement in this clip CLH as well, similar to the clip CLL, but in the following description of the specification, the room for improvement in the semiconductor device PKG is described with a focus on the clip CLL.

[0040] In the above-mentioned semiconductor device PKG, in order to improve the heat dissipation efficiency, a configuration is sometimes adopted in which the back surface of the die pad DPL (die pad DPC, die pad DPH) is exposed from the lower surface of the sealing body MR. In the semiconductor device PKG having such a configuration, the present inventors have newly found that there is room for improvement as described below.

[0041] FIG. 4 is a cross-sectional view illustrating a molding process for forming a sealing body MR, which is a diagram for explaining room for improvement newly found by the present inventor. In FIG. 4, the leads 60A and 60B present in the lead frame are sandwiched between a lower mold 70A and an upper mold 70B. Then, in the cavity CAV, the die pad DPL, the semiconductor chip CPL mounted on the die pad DPL via the silver paste 50A, and the clip CLL mounted on the main transistor source pad SPL formed on the semiconductor chip CPL via the silver paste 50B are arranged. In addition, this clip CLL is connected to the lead 60A via the silver paste 50C. That is, the clip CLL has a function of electrically connecting the main transistor source pad SPL and the lead 60A.

[0042] Here, in the molding process shown in Fig. 4, a sealing body is formed by injecting resin into the cavity CAV. At this time, if a gap exists between the lower mold 70A and the die pad DPL in Fig. 4, the resin also flows into this gap. For this reason, in order to prevent a gap into which the resin flows from being formed between the lower mold 70A and the die pad DPL, for example, as shown in Fig. 4, the molding process is performed while applying a force pushing the die pad DPL from the lower mold 70A toward the cavity CAV.

[0043] In this case, the leads 60A and 60B are sandwiched and fixed between the lower mold 70A and the upper mold 70B. Meanwhile, the die pad DPL is pressed into the cavity CAV by the above-mentioned pressing force. As a result, the "offset X" showing the height difference between the lead 60A (60B) and the die pad DPL shown in FIG. 4 changes in a decreasing direction. Then, a force is applied to the clip CLL connected to both the lead 60A and the semiconductor chip CPL in the direction shown by the arrow in FIG. 4.

[0044] This causes deformation of the clip CLL, for example, as shown in Fig. 5. Specifically, the clip CLL, which connects to both the main transistor source pad SPL and the lead 60A formed on the semiconductor chip CPL, is generally disposed parallel to the semiconductor chip CPL, but the above-mentioned pressing force applied to the die pad DPL causes deformation in which the tip portion of the clip CLL becomes higher than the base portion of the clip CLL.

[0045] In this specification, the shape in which the tip portion of the clip CLL is higher than the base portion of the clip CLL as shown in FIG. 5 is referred to as "reverse inclination."

[0046] In this way, in the molding process for manufacturing the semiconductor device PKG in which the back surface of the die pad DPL is exposed from the lower surface of the sealing body MR, a pressing force is applied from the lower mold 70A to the cavity CAV side of the die pad DPL so that a gap into which the resin flows is not formed between the lower mold 70A and the die pad DPL. As a result, for example, as shown in FIG. 5, the shape of the clip CLL becomes "reverse inclined."

[0047] When the shape of the clip CLL becomes "reverse inclined," the portion of the silver paste 50B in contact with the base portion 80 of the clip CLL becomes thinner than the other portions of the silver paste 50B. This causes structural stress applied to the semiconductor device, which causes peeling, for example, at a portion 90 of the silver paste 50B shown in FIG.

[0048] In this regard, the silver paste 50B has a function of electrically connecting the clip CLL and the source pad SPL for the main transistor formed on the semiconductor chip CPL, and serves as a current path through which a current flows. For this reason, if peeling occurs in the silver paste 50B that serves as the current path, the peeled area becomes a high impedance area, and the on-resistance of the semiconductor device increases. Furthermore, in the case of a semiconductor device equipped with a sense transistor, this causes a fluctuation in the sense ratio. In other words, peeling of the silver paste 50B adversely affects the performance of the semiconductor device. Therefore, it is desirable to suppress the "reverse tilt" of the clip CLL that causes the peeling of the silver paste 50B.

[0049] <Description of Related Art> Therefore, in order to suppress the "reverse tilt" of the clip CLL, there is the related technology shown below.

[0050] The term "related art" as used herein refers to art that is not publicly known, but has problems that the inventors have found, and is a technology that serves as a premise for the present invention.

[0051] FIG. 6 is a schematic diagram showing a related art.

[0052] As shown in Fig. 6, in the related technology, the tip portion of the clip CLL is shaped to be lower than the base portion of the clip CLL in advance. Here, in this specification, the shape in which the tip portion of the clip CLL is lower than the base portion of the clip CLL as shown in Fig. 6 is referred to as a "positive inclination." In this way, in the related technology, the clip CLL is processed in advance to give the shape of the clip CLL a "positive inclination."

[0053] As a result, according to the related technology, even if a pressing force is applied to the die pad DPL from the lower die 70A toward the cavity CAV side so that a gap into which the resin flows is not formed between the lower die 70A and the die pad DPL, the shape of the clip CLL is not horizontal but is already "positively inclined," so that it is possible to prevent the shape of the clip CLL from becoming "reversely inclined" due to the pressing force. Therefore, the related technology is effective from the viewpoint of preventing the "reverse inclination" of the clip CLL, which causes the peeling of the silver paste 50B.

[0054] Here, for example, a method of "positively inclining" the clip CLL may involve deforming the clip CLL. However, according to the study of the present inventor, it was newly discovered that the processing accuracy of the clip CLL is limited to ±20 μm, and it is difficult to stably "positively incline" the clip CLL. That is, the concept of the related art of "positively inclining" the clip CLL in advance is excellent from the viewpoint of suppressing the "reverse inclination" of the clip CLL, which causes the peeling of the silver paste 50B, but the related art has a drawback when focusing on the viewpoint of stably processing the clip CLL.

[0055] As described above, there is room for improvement in the related art. Therefore, in the present embodiment, a device is implemented to overcome the room for improvement in the related art. The technical idea of ​​the present embodiment that implements this device will be described below.

[0056] <Basic Concept of the Embodiment> The basic idea of ​​the present embodiment is to provide a protruding member on a partial area of ​​the surface of the main transistor source pad SPL and to bring the protruding member into contact with the "positively inclined" clip CLL when the "positively inclined" clip CLL is connected to the main transistor source pad SPL with silver paste 50B, on the premise that the clip CLL is "positively inclined" in advance. According to this basic idea, the "positively inclined" clip CLL can be supported by the protruding member, and as a result, the "positively inclined" state of the clip CLL can be stably maintained. Therefore, even if the "positive inclination" varies depending on the processing accuracy of the clip CLL, a stable "positive inclination" can be realized by the correction effect caused by the contact of the protruding member.

[0057] A specific embodiment that embodies this basic concept will be described below.

[0058] <Specific Examples> FIG. 7 is a schematic diagram showing a specific embodiment.

[0059] In particular, the upper diagram in FIG. 7 is a plan view, and the lower diagram in FIG. 7 is a cross-sectional view.

[0060] 7, a semiconductor chip CPL is mounted on a die pad DPL via a silver paste 50A. A main transistor source pad SPL (first electrode) is formed on the surface of the semiconductor chip CPL, and the periphery of the main transistor source pad SPL is covered with a protective film PAS. In other words, the surface of the main transistor source pad SPL that is not covered with the protective film PAS is exposed.

[0061] Also, the lead 60A is arranged next to the semiconductor chip CPL and spaced apart from the die pad DPL. Here, "spaced apart" means that it is spaced apart, for example, as shown in FIG. 7, the die pad DPL and the lead 60A are spaced apart. The main transistor source pad SPL and the lead 60A are electrically connected by a clip CLL, which is a plate-shaped member made of copper. Specifically, the clip CLL is electrically connected to the main transistor source pad SPL via the silver paste 50B, and is connected to the lead 60A via the silver paste 50C. The clip CLL is composed of a "first portion P1" that the silver paste 50B contacts, a "second portion P2" that the silver paste 50C contacts, and a "third portion P3" located between the "first portion P1" and the "second portion P2".

[0062] At this time, the "first portion P1" of the clip CLL is inclined so that the distance from the upper surface of the sealing body becomes shorter as it approaches the "third portion P3" of the clip CLL. In other words, the "first portion P1" of the clip CLL has a "positive inclination" in which the tip portion of the clip CLL is lower than the base portion of the clip CLL.

[0063] Here, although not shown in Fig. 7, the structure shown in Fig. 7 is sealed with a sealing body. For example, the sealing body has an upper surface and a lower surface opposite to the upper surface, and seals the semiconductor chip CPL and the clip CLL so that a part of the back surface of the die pad DPL is exposed from the lower surface and so that a part of the lead 60A is exposed.

[0064] 7, a protruding member 100 is formed on the surface of the main transistor source pad SPL exposed from the protective film PAS, protruding further toward the upper surface of the sealing body than the protective film PAS. That is, in the thickness direction of the semiconductor chip CPL, the height of the protruding member 100 from the surface of the main transistor source pad SPL to its upper surface is greater than the height of the protective film PAS from the surface of the main transistor source pad SPL to its upper surface. At this time, as shown in FIG. 7, the "first portion P1" of the clip CLL is in contact with the protruding member 100. The material constituting this protruding member 100 is not particularly limited, but is, for example, made of an insulating material.

[0065] In addition, in FIG. 7, the planar shape of the main transistor source pad SPL is a rectangle (polygon) having a "first side SD1" that intersects with the "third portion P3" of the clip CLL in a planar view, and a "second side SD2" opposite the "first side SD1", and the protruding member 100 is positioned at a position closer to the "first side SD1" than the "second side SD2" in a planar view.

[0066] <<Dimensions>> Next, an example of the dimensional relationship will be described.

[0067] FIG. 8 is a diagram for explaining an example of the dimensional relationship.

[0068] 8, in a first direction from one of the "first side SD1" and the "second side SD2" to the other, the surface of the main transistor source pad SPL has a "first region R1" located on the "first side SD1" side of the center line CL, and a "second region R2" located on the "second side SD2" side of the center line CL. Here, as shown in FIG. 8, the protruding member 100 is provided in the "first region R1" and is spaced apart from the boundary between the "first region R1" and the "second region R2", which is the center line CL.

[0069] 8, the planar shape of the protruding member 100 is a square shape, and as shown in an enlarged view of the protruding member 100 surrounded by an area RA, the protruding member 100 is composed of, for example, a silicon oxynitride film 110 (thickness: about 0.9 μm), a first polyimide film 120 (thickness: about 8 μm) formed on the silicon oxynitride film 110, and a second polyimide film 130 (thickness: about 8 μm) formed on the first polyimide film 120. The silicon oxynitride film 110 may be a silicon nitride film (SiN) or a silicon carbonitride film (SiCN), or may be a laminated film of multiple types including a silicon oxide film.

[0070] Here, the dimensions shown in FIGS. (1) "A0" = 3 mm (2) "A1" = 1 mm (3) "A2" = 2 mm (4) "L" = 70 μm (5) "L1" = 20 μm (6) "L2" = 10 μm (7) "L3" = 15 μm

[0071] Also, considering the following film thicknesses: Silicon oxynitride film 110: 0.9 μm First polyimide film 120: 8μm Second polyimide film 130: 8μm The dimensions shown in Figures 9 and 10 are as follows: (8) "A" = about 10μm (9) "B" = 10.35 μm (10) "C" = 6.9 μm

[0072] <<Structural features of specific embodiments>> Next, features of specific embodiments will be described.

[0073] The feature of this embodiment is that the basic idea of ​​providing a protruding member on a partial region of the surface of the main transistor source pad SPL and contacting the protruding member with the "positively inclined" clip CLL is embodied by the protruding member 100 having the layout arrangement and dimensions shown in, for example, FIGS. 7 to 10. As a result, the "positively inclined" clip CLL can be supported by the protruding member 100, and the "positively inclined" state of the clip CLL can be stably maintained. Therefore, even if the "positive inclination" varies depending on the processing accuracy of the clip CLL, the variation in the "positive inclination" is corrected by the corrective effect due to the contact of the protruding member 100, so that a stable "positive inclination" can be realized. As a result, according to this embodiment, the shape of the clip CLL can be prevented from becoming "reverse inclined" due to the pressing force, and therefore peeling of the silver paste 50B can be prevented. In other words, according to this embodiment, the excellent effect of improving the reliability of the semiconductor device can be obtained by preventing the peeling of the silver paste 50B.

[0074] 8, the present embodiment is also characterized in that the protruding member 100 is made of a laminated film including a first polyimide film 120 and a second polyimide film 130. This is because the protruding member 100 that comes into contact with the clip CLL is made to include a polyimide film having cushioning properties, so that even if stress occurs due to a pressing force applied to the die pad DPL in the molding process, the protruding member 100 can function as a buffer against this stress.

[0075] From the above, it can be said that this embodiment has great technical significance in that the protruding member 100 has the function of realizing a stable "positive inclination" of the clip CLL and the function of acting as a buffer material to absorb stress, and the synergistic effect of these functions can effectively suppress peeling of the silver paste 50B caused by the stress generated in the molding process.

[0076] Furthermore, in this embodiment, the protruding member 100 is disposed at a position where "A2:A1=2:1" is satisfied, for example, as shown in FIG. 7. Here, according to the new knowledge found by the present inventor, it has been found that the position where "A2:A1=2:1" is the position where peeling of the silver paste 50B is most likely to occur. Therefore, in this embodiment, taking into consideration the above-mentioned new knowledge, the protruding member 100 is disposed at a position where peeling of the silver paste 50B is most likely to occur. As a result, according to this embodiment, since the silver paste 50B is not present at the position where peeling is most likely to occur, the potential for peeling of the silver paste 50B can be reduced, and the reliability of the semiconductor device can be improved.

[0077] <<Method of manufacturing semiconductor device>> Next, a method for manufacturing the semiconductor device according to the present embodiment will be described.

[0078] <<<Semiconductor chip manufacturing process>>> First, a semiconductor wafer WF having multiple chip regions is prepared. Then, by using normal semiconductor manufacturing technology, a power transistor including a main transistor and a sense transistor is formed in each chip region, and then, as shown in Fig. 11, a main transistor source pad SPL is formed on the surface of each chip region of the semiconductor wafer WF. This main transistor source pad SPL is made of, for example, aluminum.

[0079] 11 to 14 shown below, one chip region out of a plurality of chip regions included in the semiconductor wafer WF is shown.

[0080] Next, as shown in Fig. 12, for example, a CVD (Chemical Vapor Deposition) method is used to form a silicon oxynitride film 110 covering the main transistor source pad SPL. Then, the silicon oxynitride film 110 is patterned using photolithography and etching techniques. As shown in Fig. 12, the silicon oxynitride film 110 is patterned so as to cover the periphery of the main transistor source pad SPL and to leave the silicon oxynitride film 110 in the protruding member formation region of the main transistor source pad SPL. This patterning is also performed so as to expose other regions of the main transistor source pad SPL.

[0081] Next, a first polyimide film 120 is applied to the entire surface of one side of the semiconductor wafer WF, and then the first polyimide film 120 is patterned by using a photolithography technique. The patterning of the first polyimide film 120 is performed, for example, as shown in FIG. 13, so that the first polyimide film 120 remains on the silicon oxynitride film 110 formed on the periphery of the main transistor source pad SPL and covers the silicon oxynitride film 110 formed in the protruding member formation region. As a result, a protective film PAS made of a laminated film of the silicon oxynitride film 110 and the first polyimide film 120 is formed on the periphery of the main transistor source pad SPL. Then, for example, a curing process is performed on the patterned first polyimide film 120.

[0082] 14, a second polyimide film 130 is applied to the entire surface of one side of the semiconductor wafer WF, and then the second polyimide film 130 is patterned by using a photolithography technique. The second polyimide film 130 is patterned, for example, as shown in FIG. 14, so as to cover the first polyimide film 120 formed in the protruding member formation region of the main transistor source pad SPL, and to remove the second polyimide film 130 in the other region. As a result, a protruding member 100 made of a laminated film of the silicon oxynitride film 110, the first polyimide film 120, and the second polyimide film 130 is formed in the protruding member formation region of the main transistor source pad SPL. Then, for example, a curing process is performed on the patterned second polyimide film 130.

[0083] In this embodiment, the second polyimide film 130 is patterned so as to cover the first polyimide film 120 formed in the protruding member formation region of the main transistor source pad SPL, and to remove the second polyimide film 130 in other regions, as shown in Fig. 14. However, the present invention is not limited to this, and the second polyimide film 130 may be patterned so as to remain on the first polyimide film 120 formed in the peripheral portion, for example. In this case, the protective film PAS is also composed of a laminated film of the silicon oxynitride film 110, the first polyimide film 120, and the second polyimide film 130.

[0084] Next, if necessary, a plating film such as a nickel film, a palladium film, or a gold film is formed on the exposed surface of the main transistor source pad SPL by using an electroless plating method or the like. Then, a back grinding process is performed on the semiconductor wafer WF, and the semiconductor wafer WF is then diced. As a result, the multiple chip regions of the semiconductor wafer WF are individualized and divided into multiple semiconductor chips. In this manner, the semiconductor chip of this embodiment can be manufactured.

[0085] <<<Semiconductor device assembly process>>> Next, the assembly process of the semiconductor device will be described.

[0086] FIG. 15 is a flow chart illustrating the assembly process of a semiconductor device.

[0087] First, a lead frame having a die pad and leads spaced apart from the die pad is prepared. Then, a semiconductor chip manufactured in the above-mentioned semiconductor chip manufacturing process is mounted on the die pad. Specifically, after applying silver paste onto the die pad, the semiconductor chip is mounted on the die pad via the silver paste (S101).

[0088] Next, silver paste is applied onto the main transistor source pad formed on the surface of the semiconductor chip and onto the leads (S102). After that, a clip is placed so as to connect the main transistor source pad and the leads. At this time, the clip is connected to the main transistor source pad via the silver paste, and is also connected to the leads via the silver paste. As a result, the main transistor source pad and the leads are electrically connected by the clip (S103). Then, a curing process (heat treatment at about 150°C to 300°C) is performed to harden the silver paste (S104).

[0089] Next, for example, the leads and other pads formed on the surface of the semiconductor chip are connected with gold or conductor wires. That is, wire bonding is performed with gold or copper wires between the leads and other pads formed on the surface of the semiconductor chip (S105).

[0090] Thereafter, a resin sealing (molding) is performed to form a sealing body (S106). Then, a plating layer is formed as necessary on the outer lead portions of the leads exposed from the sealing body. Next, outside the sealing body, the leads are cut at predetermined positions to separate the sealing body from the frame of the lead frame. Next, the outer lead portions of the leads protruding from the sealing body are bent. In this manner, a semiconductor device can be manufactured.

[0091] <<Production Characteristics>> In this embodiment, the structure shown in FIG. 16 is realized by S103 in FIG. 15. That is, in FIG. 16, the clip CLL is composed of a "first portion P1" that the silver paste 50B contacts, a "second portion P2" that the silver paste 50C contacts, and a "third portion P3" located between the "first portion P1" and the "second portion P2". Then, in S103 in FIG. 15, the clip CLL is placed on the main transistor source pad SPL and the lead 60A in a state where the "first portion P1" is positively inclined so that the height of the protruding member 100 is greater than the height between the tip of the clip CLL included in the "first portion P1" and the surface of the main transistor source pad SPL by bringing the "first portion P1" into contact with the protruding member 100. As a result, the "positively inclined" clip CLL can be supported by the protruding member 100, and the "positively inclined" state of the clip CLL can be stably maintained. Therefore, even if the processing accuracy of the clip CLL causes variation in the "positive inclination," the variation in the "positive inclination" is corrected by the corrective effect of the contact of the protruding member 100, thereby achieving a stable "positive inclination."

[0092] Here, a characteristic feature of the manufacturing method in this embodiment is that, for example, as shown in Figures 11 to 14, the protruding member 100 is formed by utilizing the step of forming a protective film PAS. In this case, it is only necessary to add a step of forming the second polyimide film 130 and a step of patterning the second polyimide film 130, and the burden of adding a new step of forming the protruding member 100 can be reduced, which provides the advantage that the protruding member 100 can be easily formed. In particular, with this manufacturing method, the height of the protruding member 100 can be easily adjusted by adjusting the film thickness of the second polyimide film 130.

[0093] Next, in this embodiment, S106 in FIG. 15 is performed, for example, as shown in FIG. 17. FIG. 17 is a schematic diagram showing a resin sealing step (molding step) in this embodiment. As shown in FIG. 17, the resin sealing step (S106) in this embodiment includes a step of sandwiching the lead frame after the clip connection step (S103) between the lower mold 70A and the upper mold 70B so as to form a cavity space CAV, and a step of forming a sealing body by pouring resin into the cavity space CAV. At this time, the step of sandwiching the lead frame between the lower mold 70A and the upper mold 70B is performed while applying a force by the lower mold 70A to push the die pad DPL into the inside of the cavity space CAV.

[0094] In the resin sealing step configured as above, the above-mentioned pressing force is applied, so that the intrusion of the resin into the gap between the lower mold 70A and the die pad DPL is suppressed.

[0095] However, if no measures are taken when applying a pressing force from the lower mold 70A to the cavity CAV side of the die pad DPL so as to prevent a gap from being formed between the lower mold 70A and the die pad DPL into which resin can flow, the shape of the clip CLL will become "reverse inclined," as shown in Figure 5, which may cause the silver paste 50B to peel off.

[0096] In this regard, in the present embodiment, in the clip connecting step (S103), a clip CLL that has been previously "positively inclined" is used, and the "positive inclination" of the clip CLL is stably maintained by the protruding member 100. As a result, according to the present embodiment, even if a force is applied in the resin sealing step that presses the die pad DPL toward the inside of the cavity space CAV, the "reverse inclination" of the clip CLL is suppressed.

[0097] Therefore, according to the present embodiment, the "reverse tilt" of the clip CLL can be suppressed, and therefore peeling of the silver paste 50B caused by the "reverse tilt" of the clip CLL can be suppressed. Therefore, according to the present embodiment, the reliability of the semiconductor device can be improved.

[0098] <Variation 1> FIG. 18 is a diagram showing variations in the planar shape of the protruding member 100. In FIG.

[0099] In the above embodiment, an example has been described in which the planar shape of the protrusion member 100 is a "square" (see Figure 7), but the planar shape of the protrusion member 100 is not limited to this and may be configured to have, for example, a "rectangle", a "circle", a "triangle", or a "polygon", as shown in Figures 18(a) to 18(g).

[0100] <Variation 2> In the above embodiment, an example has been described in which the protruding member 100 is composed of a laminated film of a silicon oxynitride film 110, a first polyimide film 120, and a second polyimide film 130, but this is not limiting, and the protruding member 100 can also be composed of a so-called "permanent resist."

[0101] A "permanent resist" is a resist that is left behind after processing (development) and is used, for example, in the manufacture of MEMS (Mechanical Electrical Machine Systems). A typical resist is patterned by exposure and development processing in photolithography technology, and then used in the etching process of the processed film, after which it is removed (ashed). In contrast, a "permanent resist" is a resist that is left behind without being ashed.

[0102] In this way, an advantage of forming the protruding member 100 from a "permanent resist" is that the protruding member 100 can be easily formed to any height of 10 μm or more. This is because the "permanent resist" can achieve any film thickness in the range of several μm to 100 μm by adjusting the viscosity of the resist and the coating rotation speed.

[0103] A manufacturing method for forming the protruding member 100 from a "permanent resist" is, for example, to form a protective film PAS that covers the periphery of the main transistor source pad SPL, and then to apply a "permanent resist" thicker than the protective film PAS. Then, the "permanent resist" is patterned by photolithography so that the "permanent resist" remains only in the protruding member formation region of the exposed surface of the main transistor source pad SPL.

[0104] For example, the protruding member 100 can also be made of a laminated film of a "permanent resist" and a polyimide film with excellent cushioning properties.

[0105] <Modification 3> FIG. 19 is a diagram showing a configuration example of a protruding member in the third modification.

[0106] As shown in Fig. 19, an example in which a plurality of protruding members are present is shown in Modification 3. Specifically, in Fig. 19, protruding members 100A and 100B are provided aligned in the y direction. In this case, the arrangement stability of the clip CLL can be improved.

[0107] FIG. 20 is a diagram showing another configuration example of the protruding member in the third modification.

[0108] 20, in another configuration example, the planar shape of the protruding member 100 is a rectangle with its short side in the x direction and its long side in the y direction. In this case, the placement stability of the clip CLL can be improved.

[0109] <Variation 4> In the basic concept of the above embodiment, the constituent material of the protruding member may be either a conductive material or an insulating material, and is not particularly limited. However, in a specific embodiment that embodies the basic concept, the constituent material of the protruding member 100 is an insulating material. This is in consideration of the fact that, when the protruding member 100 is made of a conductive material, it is difficult to form the protruding member 100 in a desired shape (dimensions), and that it is difficult to form the protruding member 100 by making good use of the conventional manufacturing process. On the other hand, when the protruding member 100 is made of an insulating material, it is possible to easily form the protruding member 100 by utilizing the process of forming the protective film PAS, for example, as shown in Figs. 11 to 14. For this reason, although either a conductive material or an insulating material can be adopted as the material of the protruding member 100, in consideration of practical ease of manufacturing, it is desirable that the protruding member 100 is made of an insulating material.

[0110] However, when the protruding member 100 is made of an insulating material, the protruding member 100 made of an insulating material is provided on the silver paste 50B that is the current path. This means that the current path is narrowed, and there is a risk of causing a decrease in the performance of the semiconductor device, as represented by an increase in on-resistance. In particular, when the protruding member 100 is arranged at a position of "A1:A2=1:2" as shown in FIG. 7, the protruding member 100 is arranged at a position where peeling is likely to occur, and therefore the effect of preventing peeling is considered to be large. On the other hand, the protruding member 100 becomes a major obstruction factor of the current path. Therefore, in this modification 4, the arrangement of the protruding member 100 is devised, focusing particularly on minimizing the obstruction of the current path as much as possible.

[0111] The following describes the fourth modified example that incorporates this feature.

[0112] FIG. 21 is a schematic diagram showing the fourth modified example.

[0113] In FIG. 21, the clip CLL has a "first portion P1" with which the silver paste 50B comes into contact, a "second portion P2" with which the silver paste 50C comes into contact, and a "third portion P3" located between the "first portion P1" and the "second portion P2". A protruding member 100 that comes into contact with the "third portion P3" is formed on the protective film PAS formed at the base portion of the clip CLL. Thus, in this modification 4, the protruding member 100 is not disposed at a position where it comes into contact with the "first portion P1" as shown in FIG. 7, but is disposed at a position where it comes into contact with the "third portion P3" as shown in FIG. 21. Here, the protruding member 100 is formed on the protective film PAS, which is composed of a laminated film of a silicon oxynitride film 110 and a first polyimide film 120, and the protruding member 100 is composed of a laminated film of a second polyimide film 130 and a third polyimide film 140.

[0114] At this time, the film thickness is as follows. (1) Silicon oxynitride film 110: thickness 0.9 μm (2) First polyimide film 120: film thickness 8 μm (3) Second polyimide film 130: film thickness 8 μm (4) Third polyimide film 140: film thickness 8 μm

[0115] As a result, the combined height of the protective film PAS and the protruding member 100 is 24.9 μm, which is a sufficient height. As a result, according to the present modification 4, the protruding member 100 is configured to contact the "third portion P3" without contacting the "first portion P1" that contacts the silver paste 50B, and the "positively inclined" clip CLL can be supported by the protruding member 100, and the "positively inclined" state of the clip CLL can be stably maintained. In particular, in the present modification 4, the protruding member 100 is provided avoiding the formation region of the silver paste 50B, so that the protruding member 100 can be prevented from blocking the current path of the silver paste 50B. As a result, according to the present modification 4, the "positively inclined" clip CLL can be supported by the protruding member 100 while suppressing an increase in on-resistance.

[0116] <Variation 5> In the above embodiment, a configuration in which the surface of the die pad DPL (die pad DPC, die pad DPH) is exposed from the bottom surface of the sealing body MR has been described as an example, but the basic idea of ​​the above embodiment is not limited to this and can also be applied, for example, to a configuration in which the surface of the die pad DPL (die pad DPC, die pad DPH) is exposed from the top surface of the sealing body MR.

[0117] In the configuration of this variant example 5, the resin sealing process (molding process) can be performed in a configuration in which the exposed surface of the die pad DPL is brought into contact with the lower mold, or in a configuration in which the exposed surface of the die pad DPL is brought into contact with the lower mold.

[0118] In the above embodiment, the die pad DPL is exposed from the lower surface of the sealing body, and the protruding member 100 protrudes toward the upper surface of the sealing body. In contrast, in the present modification 5, the die pad DPL is exposed from the upper surface of the sealing body, and the protruding member 100 protrudes toward the lower surface of the sealing body.

[0119] In the claims, the terms "first surface" and "second surface" are used so as to encompass the configuration of the above-described embodiment and the configuration of this modified example 5. In the configuration of the above-described embodiment, the "first surface" corresponds to the bottom surface, and the "second surface" corresponds to the top surface. On the other hand, in the configuration of this modified example 5, the "first surface" corresponds to the top surface, and the "second surface" corresponds to the bottom surface.

[0120] The invention made by the inventor has been specifically described above based on the embodiment thereof. However, it goes without saying that the present invention is not limited to the above embodiment, and various modifications can be made without departing from the spirit of the invention.

[0121] In the above embodiment, the power transistor formed on the semiconductor chip is assumed to be a power MOSFET. However, the technical ideas in the above embodiment are not limited to this, and can be widely applied to a semiconductor device using, for example, an IGBT (Insulated Gate Bipolar Transistor) as a power transistor.

[0122] In this case, the "main transistor source pad" should be read as the "main transistor emitter pad." In the claims, the term "first electrode" is used to encompass both the "main transistor source pad" and the "main transistor emitter pad." In other words, the "first electrode" in the claims is used with the intention of encompassing both the "main transistor source pad" and the "main transistor emitter pad."

[0123] In addition, although the embodiment has been described using silver paste as an example, the technical idea of ​​the embodiment is not limited to this, and can be widely applied to, for example, semiconductor devices using solder. In addition, the claims use the terms "first conductive member" and "second conductive member" as terms that encompass "silver paste" and "solder". In other words, the terms "first conductive member" and "second conductive member" in the claims are used with the intention of encompassing "silver paste" and "solder". [Explanation of symbols]

[0124] 10 High-side switching circuit 11 Main transistor 12 Sense transistor 20 Low-side switching circuit 21 Main transistor 22 Sense transistor 30 Control circuit 31 Sense circuit 50A Silver Paste 50B Silver Paste 50C Silver Paste 60A Lead 60B Lead 70A lower mold 70B upper mold 80 Base part 90 portions 100 Protruding member 100A protruding member 100B Protruding member 110 Silicon oxynitride film 120 First polyimide film 130 Second polyimide film 140 Third polyimide film CAV Cavity Space CL coil CLH Clip CLL Clip CPC Semiconductor Chip CPH Semiconductor Chip CPL Semiconductor Chip CT control circuit DPC Die Pad DPL Die Pad DPH Die Pad GND Ground potential INV Inverter circuit MR sealed body MOT motor LD Lead LDL Lead LDH Lead P1 Part 1 P2 2nd part P3 3rd part PAS protective film PDC1 Pad PDC2 Pad PDH Pad PDL Pad PKG Semiconductor device R1 1st area R2 2nd area S1 side S2 side S3 side S4 side SD1 Side 1 SD2 Side 2 SPH Main transistor source pad SPL Source pad for main transistor VIN power supply potential W Bonding Wire WF Semiconductor wafer

Claims

1. A die pad; a semiconductor chip having a first electrode and a protective film covering a peripheral portion of the first electrode and mounted on the die pad; a lead disposed adjacent to the semiconductor chip and spaced from the die pad; a plate-like member that electrically connects the first electrode and the lead to each other; a sealing body having a first surface and a second surface opposite to the first surface, the sealing body sealing the semiconductor chip and the plate-like member such that a portion of the die pad is exposed from the first surface and such that a portion of the lead is exposed; Including, the plate-like member is electrically connected to the first electrode via a first conductive member, and is connected to the lead via a second conductive member; The plate-like member is a first portion that is in contact with the first conductive member; a second portion contacted by the second conductive member; a third portion located between the first portion and the second portion; having a protruding member is formed on a surface of the first electrode exposed from the protective film, the protruding member protruding toward the second surface beyond the protective film; the first portion is in contact with the protruding member; The first portion is inclined such that a distance between the first portion and the second surface of the sealing body becomes shorter as the first portion approaches the third portion.

2. 2. The semiconductor device according to claim 1, The planar shape of the first electrode is a first side intersecting with the third portion in a plan view; A second side opposite to the first side; is a polygon having The protruding member is disposed at a position closer to the first side than to the second side in a plan view.

3. 3. The semiconductor device according to claim 2, The surface of the first electrode is In a first direction from one of the first side and the second side to the other, a first region located on the first side of the first electrode relative to a center line of the first electrode; a second region located on the second side of the first electrode relative to a center line of the first electrode; having A semiconductor device, wherein the protruding member is provided within the first region and is spaced apart from the center line, which is the boundary between the first region and the second region.

4. 2. The semiconductor device according to claim 1, The semiconductor device, wherein the protruding member is an insulating member.

5. 5. The semiconductor device according to claim 4, the protective film includes a first polyimide resin film, The protruding member is The first polyimide resin film; a second polyimide resin film formed on the first polyimide resin film; 13. A semiconductor device comprising:

6. 5. The semiconductor device according to claim 4, The semiconductor device, wherein the protruding member is made of a permanent resist.

7. 2. The semiconductor device according to claim 1, The semiconductor device includes a plurality of protruding members.

8. 2. The semiconductor device according to claim 1, The semiconductor device, wherein the plate-like member is a clip made of copper.

9. A die pad; a semiconductor chip having a first electrode and a protective film covering a peripheral portion of the first electrode and mounted on the die pad; a lead disposed adjacent to the semiconductor chip and spaced from the die pad; a plate-like member that electrically connects the first electrode and the lead to each other; a sealing body having a first surface and a second surface opposite to the first surface, the sealing body sealing the semiconductor chip and the plate-like member such that a portion of the die pad is exposed from the first surface and such that a portion of the lead is exposed; Including, the plate-like member is electrically connected to the first electrode via a first conductive member, and is connected to the lead via a second conductive member; The plate-like member is a first portion that is in contact with the first conductive member; a second portion contacted by the second conductive member; a third portion located between the first portion and the second portion; having a protruding member that contacts the third portion is formed on the protective film.

10. A method for manufacturing a semiconductor device, comprising the steps of: (a) providing a lead frame having a die pad and leads spaced from the die pad; (b) preparing a semiconductor chip having a first electrode, a protective film covering a peripheral portion of the first electrode, and a protruding member formed on a surface of the first electrode exposed from the protective film; (c) mounting the semiconductor chip on the die pad; (d) forming a first conductive member on the first electrode and a second conductive member on the lead; (e) electrically connecting the first electrode and the lead to each other via the plate-like member by disposing a first portion of the plate-like member on the first electrode via the first conductive member and disposing a second portion of the plate-like member on the lead via the second conductive member; and (f) sealing the semiconductor chip and the plate-like member; Where: The plate-like member is the first portion with which the first conductive member comes into contact; the second portion contacted by the second conductive member; a third portion located between the first portion and the second portion; having In the step (e), the plate-like member is disposed in a state in which the first portion is positively inclined by bringing the first portion or the third portion into contact with the protruding member so that a height between a tip end of the plate-like member included in the first portion and a surface of the first electrode is lower than a height of the protruding member in a cross-sectional view; The step (f) comprises: (f1) a step of sandwiching the lead frame after the step (e) between a first mold and a second mold opposed to the first mold so as to form a cavity space; (f2) forming a sealing body by pouring a resin into the cavity space; having The method for manufacturing a semiconductor device, wherein the step (f1) is performed while applying a force to the die pad by the first mold so as to press the die pad into the cavity space.

11. 11. The method of manufacturing a semiconductor device according to claim 10, In the step (f1), infiltration of the resin between the first mold and the die pad is suppressed.

12. 11. The method of manufacturing a semiconductor device according to claim 10, A manufacturing method for a semiconductor device, wherein in the step (e), by tilting the first portion positively, reverse tilt of the first portion is suppressed even when a force is applied in the step (f) to push the die pad toward the inside of the cavity space.

13. 11. The method of manufacturing a semiconductor device according to claim 10, The semiconductor chip prepared in the step (b) is obtained by the following steps (b1) to (b4): (b1) forming the first electrode in each of a plurality of chip regions of a semiconductor wafer; (b2) after the step (b1), forming a first insulating film constituting the protective film on the peripheral portion and the first region of the surface region of the first electrode; (b3) after the step (b2), forming a second insulating film on the first insulating film formed in the first region; (b4) after the step (b3), a step of obtaining a plurality of semiconductor chips by dicing the plurality of chip regions into individual chips.

14. 11. The method of manufacturing a semiconductor device according to claim 10, The semiconductor chip prepared in the step (b) is obtained by the following steps (b1) to (b4): (b1) forming the first electrode in each of a plurality of chip regions of a semiconductor wafer; (b2) forming a protective film on the peripheral portion of the first electrode after the step (b1); (b3) after the step (b2), forming an insulating film having a thickness larger than that of the protective film on a first region of the surface region of the first electrode exposed from the protective film; and (b4) after the step (b3), a step of obtaining a plurality of semiconductor chips by dicing the plurality of chip regions into individual chips.

Images