Semiconductor Device

Abstract

To provide a semiconductor device capable of suppressing damage to a gate insulation film.SOLUTION: A semiconductor device comprises: a trench gate structure that is formed so as to be deeper than a base layer 20 from one surface 10a side of a semiconductor substrate 10 to reach a drift layer 19, in which a gate insulation film 24 is arranged on a wall surface of a trench 23 formed in a state where the side surface is in contact with the base layer 20 and a first impurity region 21, and a gate electrode 25 is arranged on the gate insulation film 24; a first electrode 27 that is formed on one surface 10a side of the semiconductor substrate 10, and is electrically connected to the base layer 20 and the first impurity region 21; and a second electrode 28 that is formed on another surface 10b side of the semiconductor substrate 10, and is electrically connected to a second impurity region 11. Then, in the gate insulation film 24, a thickness of a part sandwiched between the first impurity region 21 and the gate electrode 25 is made largest in a part sandwiched between the semiconductor substrate 10 and the gate electrode 25.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device having a trench gate structure. [Background technology]

[0002] Conventionally, a semiconductor device having a trench gate structure has been proposed (for example, see Patent Document 1). + n-type substrate - A p-type drift layer is formed on the n-type base layer. + A source region of a semiconductor device is formed. A plurality of trenches are formed so as to penetrate the source region and the base layer, and a gate insulating film and a gate electrode are formed in each trench in that order. This forms a trench gate structure. In this semiconductor device, the gate insulating film is formed to have a uniform thickness along the wall surface of the trench.

[0003] In this semiconductor device, an upper electrode is formed so as to be electrically connected to the base layer and the source region, and + A lower electrode is formed in contact with the mold substrate.

[0004] In such a semiconductor device, an n-type inversion layer (i.e., a channel region) is formed in the portion of the base layer that contacts the trench by applying a voltage equal to or higher than a predetermined threshold voltage to the gate electrode. Then, in the semiconductor device, electrons are supplied from the source region to the drift layer through the inversion layer, causing a current to flow between the upper electrode and the lower electrode, turning the device into an ON state. In addition, in this semiconductor device, the inversion layer formed in the base layer disappears and the device turns into an OFF state by preventing a voltage equal to or higher than a predetermined threshold voltage from being applied to the gate electrode. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2018-60924 A Summary of the Invention [Problem to be solved by the invention]

[0006] In the above-mentioned semiconductor device, when a potential difference occurs between the gate electrode and the source electrode, such as when the device is in an on state, electric field concentration is likely to occur in the portion of the gate insulating film located between the gate electrode and the source electrode. However, in the above-mentioned semiconductor device, the thickness of the gate insulating film is uniform along the wall surface of the trench. Therefore, in the above-mentioned semiconductor device, electric field concentration occurs in the portion of the gate insulating film located between the gate electrode and the source electrode, which may cause the gate insulating film to be destroyed.

[0007] In view of the above, an object of the present invention is to provide a semiconductor device capable of suppressing breakdown of a gate insulating film. [Means for solving the problem]

[0008] In claim 1 for achieving the above object, a semiconductor device having a trench gate structure includes a drift layer (19) of a first conductivity type, a base layer (20) of a second conductivity type formed on the drift layer, a first impurity region (21) of the first conductivity type formed in a surface layer portion of the base layer and having a higher impurity concentration than the drift layer, and a second impurity region (11) of the first conductivity type or the second conductivity type formed on the side of the drift layer opposite to the base layer side, the first impurity region (21) being a first surface (10a) and a second impurity region (11) being a second surface (10b), the first impurity region (21) being a second surface (10b) formed from the first surface side of the semiconductor substrate deeper than the base layer. The semiconductor substrate includes a trench gate structure in which a gate insulating film (24) is arranged on a wall surface of a trench (23) formed in a state in which the trench reaches the drift layer and has side surfaces in contact with the base layer and the first impurity region, and a gate electrode (25) is arranged on the gate insulating film, a first electrode (27) is formed on one surface side of the semiconductor substrate and is electrically connected to the base layer and the first impurity region, and a second electrode (28) is formed on the other surface side of the semiconductor substrate and is electrically connected to the second impurity region, and the gate insulating film has a thickness that is greatest at a portion sandwiched between the semiconductor substrate and the gate electrode. The gate electrode is disposed in a state in which a portion of the gate insulating film formed on the opening side of the trench is exposed, an interlayer insulating film (26) is embedded on the opening side of the trench, and the thickness of the gate insulating film is gradually increased from the opening side of the trench toward the portion where the gate electrode is disposed in the portion in contact with the interlayer insulating film disposed in the trench. .

[0009] According to this, the gate insulating film is thickest at a portion between the semiconductor substrate and the gate electrode, where the portion is sandwiched between the first impurity region and the gate electrode, which increases the dielectric strength of the portion sandwiched between the first impurity region and the gate electrode, and prevents the portion of the gate insulating film where electric field concentration is likely to occur from being destroyed.

[0010] The reference symbols in parentheses attached to each component indicate an example of the correspondence between the component and specific components described in the embodiments described below. [Brief description of the drawings]

[0011] [Figure 1] 1 is a perspective view of a semiconductor device according to a first embodiment. [Diagram 2]2 is an enlarged cross-sectional view of the trench gate structure and its vicinity in FIG. 1. [Figure 3A] 2A to 2C are cross-sectional views showing a manufacturing process of the semiconductor device shown in FIG. [Figure 3B] 3B is a cross-sectional view showing a manufacturing process of the semiconductor device subsequent to FIG. 3A. [Figure 3C] 3C is a cross-sectional view showing a manufacturing process of the semiconductor device subsequent to FIG. 3B. [Figure 3D] 3D is a cross-sectional view showing a manufacturing process of the semiconductor device subsequent to FIG. 3C. [Figure 3E] 3D; FIG. 4 is a cross-sectional view showing a manufacturing process of the semiconductor device subsequent to FIG. 3D; [Figure 3F] 3F is a cross-sectional view showing a manufacturing process of the semiconductor device subsequent to FIG. 3E. [Figure 3G] 3F is a cross-sectional view showing a manufacturing process of the semiconductor device subsequent to FIG. 3F. [Figure 3H] 3C is a cross-sectional view showing a manufacturing process of the semiconductor device subsequent to FIG. 3G. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be denoted by the same reference numerals.

[0013] (First embodiment) The first embodiment will be described with reference to the drawings. In this embodiment, a SiC semiconductor device in which an inversion type MOSFET with a trench gate structure is formed on a semiconductor substrate made of silicon carbide (hereinafter, simply referred to as SiC) will be described. In the following, as shown in FIG. 1, one direction in the surface direction of a substrate 11 described later is defined as the X-axis direction, a direction intersecting with the one direction in the surface direction of the substrate is defined as the Y-axis direction, and a direction perpendicular to the X-axis direction and the Y-axis direction is defined as the Z-axis direction. In this embodiment, the X-axis direction and the Y-axis direction are perpendicular to each other. In FIG. 2, the left-right direction of the paper corresponds to the X-axis direction, the depth direction of the paper corresponds to the Y-axis direction, and the up-down direction of the paper corresponds to the Z-axis direction.

[0014] As shown in Fig. 1, the SiC semiconductor device is configured using a semiconductor substrate 10. Specifically, the SiC semiconductor device is configured using a n-type semiconductor substrate 10 made of SiC. + In this embodiment, the substrate 11 has an off-angle of 0 to 8° with respect to the (0001) Si surface and an n-type impurity concentration of nitrogen, phosphorus, etc. of 1.0×10 19 / cm 3 The substrate 11 has a thickness of about 300 μm. In this embodiment, the substrate 11 constitutes the drain region, and corresponds to the second impurity region.

[0015] On the surface of the substrate 11, a n-type SiC - A type buffer layer 12 is formed on the surface of the substrate 11. The buffer layer 12 is formed by epitaxial growth on the surface of the substrate 11. The buffer layer 12 has an n-type impurity concentration between that of the substrate 11 and a low concentration layer 13 described later, and has a thickness of about 1 μm.

[0016] On the surface of the buffer layer 12, for example, an n-type impurity concentration of 5.0 to 10.0×10 15 / cm 3 The thickness of the n-type SiC substrate is about 10 to 15 μm. - A low concentration layer 13 of a mold is formed. The impurity concentration of this low concentration layer 13 may be constant in the Z-axis direction, but it is preferable that the concentration distribution is gradient so that the low concentration layer 13 on the substrate 11 side has a higher concentration than the side away from the substrate 11. For example, the low concentration layer 13 has an impurity concentration of 2.0×10 15 / cm 3 It is preferable that the low concentration layer 13 has a higher internal resistance than the other portions. With this configuration, the internal resistance of the low concentration layer 13 can be reduced, and the on-resistance can be reduced.

[0017] The JFET section 14 and the first deep layer 15 are formed in the surface layer of the low concentration layer 13. In this embodiment, the JFET section 14 and the first deep layer 15 each extend along the X-axis direction and have linear portions arranged alternately and repeatedly in the Y-axis direction. That is, the JFET section 14 and the first deep layer 15 are each formed in stripes extending along the X-axis direction in the normal direction (hereinafter simply referred to as the normal direction) to the surface of the substrate 11, and are arranged alternately along the Y-axis direction. In addition, in the normal direction to the surface of the substrate 11, in other words, can be said to be when viewed from the normal direction to the surface of the substrate 11.

[0018] The JFET section 14 is of n-type with a higher impurity concentration than the low concentration layer 13, and has a depth of 1.5 to 3.0 μm. In this embodiment, the JFET section 14 has an n-type impurity concentration of 7.0×10 16 ~5.0×10 17 / cm 3 The first deep layer 15 has a p-type impurity concentration of, for example, boron, etc. of 2.0×10 17 ~2.0×10 18 / cm 3 It is said that.

[0019] Moreover, the first deep layer 15 in this embodiment is formed shallower than the JFET section 14. That is, the first deep layer 15 is formed so that its bottom is located within the JFET section 14. In other words, the first deep layer 15 is formed so that the JFET section 14 is located between the first deep layer 15 and the low concentration layer 13.

[0020] A current spreading layer 17 and a second deep layer 18 are formed on the JFET section 14 and the first deep layer 15. The current spreading layer 17 is made of an n-type impurity layer and has a thickness of 0.5 to 2 μm. The n-type impurity concentration of the current spreading layer 17 is, for example, 1.0×10 16 ~5.0×10 17 / cm 3Furthermore, the current spreading layer 17 is connected to the JFET section 14. In this embodiment, the low concentration layer 13, the JFET section 14, and the current spreading layer 17 are connected to each other, and form a drift layer 19.

[0021] The second deep layer 18 has a p-type impurity concentration of, for example, 2.0×10 17 ~2.0×10 18 / cm 3 The thickness of the second deep layer 18 is set to be equal to that of the current spreading layer 17. The second deep layer 18 is formed so as to be connected to the first deep layer 15.

[0022] The current spreading layer 17 and the second deep layer 18 are extended in a direction intersecting the longitudinal direction of the striped portion of the JFET section 14 and the first deep layer 15. In this embodiment, the current spreading layer 17 and the second deep layer 18 are extended in the Y-axis direction as the longitudinal direction, and are arranged in a layout in which a plurality of layers are alternately arranged in the X-axis direction. The formation pitch of the current spreading layer 17 and the second deep layer 18 is set to match the formation pitch of a trench gate structure described later, and the second deep layer 18 is formed to sandwich a trench 23 described later.

[0023] A P-type base layer 20 is formed on the current spreading layer 17 and the second deep layer 18. The surface layer of the base layer 20 has n + Type source region 21 and p + A contact region 22 of a type is formed in the source region 21. The source region 21 is formed so as to contact a side surface of a trench 23 described later, and the contact region 22 is formed on the opposite side of the trench 23 across the source region 21. In this embodiment, the source region 21 corresponds to a first impurity region.

[0024] The base layer 20 has a p-type impurity concentration of, for example, 3.0×10 17 / cm 3 The source region 21 has an n-type impurity concentration in the surface layer, i.e., a surface concentration of, for example, 1.0×10 21 / cm3 The contact region 22 has a p-type impurity concentration in the surface layer, i.e., a surface concentration of, for example, 1.0×10 21 / cm 3 It is said that.

[0025] In this embodiment, the semiconductor substrate 10 is configured by stacking the substrate 11, buffer layer 12, low concentration layer 13, JFET section 14, first deep layer 15, current spreading layer 17, second deep layer 18, base layer 20, source region 21, contact region 22, etc. In the following, the surface of the semiconductor substrate 10 on the substrate 11 side is referred to as the other surface 10b of the semiconductor substrate 10, and the surface on the source region 21 and contact region 22 side is referred to as one surface 10a of the semiconductor substrate 10. The source region 21 and the contact region 22 are exposed from the one surface 10a of the semiconductor substrate 10.

[0026] 1 and 2, in the semiconductor substrate 10, a trench 23 is formed from the one surface 10a side so as to penetrate the base layer 20 etc. to reach the current spreading layer 17 and have a bottom surface located within the current spreading layer 17. The trench 23 is formed so as not to reach the JFET section 14 and the first deep layer 15. In other words, the trench 23 is formed so that the JFET section 14 and the first deep layer 15 are located below the bottom surface.

[0027] Moreover, a plurality of trenches 23 are provided extending along the Y-axis direction, and are arranged at equal intervals in the X-axis direction to form stripes. That is, in this embodiment, the trenches 23 are formed so that their longitudinal direction is perpendicular to the longitudinal direction of the first deep layer 15. Moreover, the trenches 23 are formed so as to be sandwiched between the second deep layers 18 in the normal direction.

[0028] A gate insulating film 24 is formed on the inner wall surface of the trench 23. A gate electrode 25 made of doped poly-Si is formed on the surface of the gate insulating film 24. This forms a trench gate structure.

[0029] The gate insulating film 24 is formed on surfaces other than the inner wall surface of the trench 23. Specifically, the gate insulating film 24 is formed so as to cover a part of the one surface 10a of the semiconductor substrate 10. More specifically, the gate insulating film 24 is formed so as to cover a part of the surface of the source region 21. In other words, the gate insulating film 24 has a contact hole 24a that exposes the contact region 22 and the remaining part of the source region 21 in a portion different from the portion where the gate electrode 25 is disposed.

[0030] Here, the trench gate structure of this embodiment will be described in more detail. First, the gate electrode 25 of this embodiment is formed to fill the bottom side of the trench 23 and to include a portion facing the source region 21 with the gate insulating film 24 interposed therebetween. However, the gate electrode 25 is formed so that the gate insulating film 24 formed on the opening side of the trench 23 is exposed. In other words, the gate electrode 25 is formed so as not to face the portion of the source region 21 located on the one surface 10a side of the semiconductor substrate 10 with the gate insulating film 24 interposed therebetween.

[0031] The trench 23 is generally tapered so that the width narrows from the opening side toward the bottom side. In the present embodiment, the trench 23 has a step 23a between the portion in contact with the source region 21 and the portion in contact with the base layer 20, and the width on the opening side is wider than the width on the bottom side. Note that the width here refers to the length in the direction perpendicular to the longitudinal direction of the trench 23, along the surface direction of the semiconductor substrate 10, and along the X-axis direction in FIG. 2.

[0032] The gate insulating film 24 is formed in a portion located between the gate electrode 25 and the semiconductor substrate 10 as follows. First, in this embodiment, in the gate insulating film 24, a portion located between the source region 21 and the gate electrode 25 is defined as a first portion 241, and a portion located between the base layer 20 and the gate electrode 25 is defined as a second portion 242.

[0033] In this case, the gate insulating film 24 is formed such that the first portion 241 is thickest in a portion located between the gate electrode 25 and the semiconductor substrate 10. In this embodiment, the gate insulating film 24 is formed such that the second portion 242 is thinner than the first portion 241.

[0034] Furthermore, the gate insulating film 24 is tapered so that its thickness gradually increases from the opening side of the trench 23 to the portion where the gate electrode 25 is disposed. That is, the gate insulating film 24 is tapered so that its thickness gradually increases from the opening side of the trench 23 to the portion where the gate electrode 25 is disposed, in a portion where the gate insulating film 24 contacts an interlayer insulating film 26 (described later) disposed in the trench 23. In other words, the gate insulating film 24 is inclined from the opening side of the trench 23 to the portion where the gate electrode 25 is disposed. The above is the configuration of the trench gate structure in this embodiment.

[0035] An interlayer insulating film 26 is formed on one surface 10a of the semiconductor substrate 10 so as to cover the gate electrode 25, the gate insulating film 24, etc. The interlayer insulating film 26 is made of BPSG (abbreviation of borophosphosilicate glass) or the like.

[0036] The interlayer insulating film 26 is formed with a contact hole 26a that communicates with the contact hole 24a and exposes the source region 21 and the contact region 22. The contact hole 26a formed in the interlayer insulating film 26 functions as one contact hole together with the contact hole 24a formed in the gate insulating film 24. For this reason, the contact holes 24a and 26a are collectively referred to as contact holes 24b below. The pattern of the contact holes 24b is arbitrary, and examples of the pattern include a pattern in which a plurality of squares are arranged, a pattern in which rectangular lines are arranged, and a pattern in which lines are arranged. In this embodiment, the contact holes 24b are formed in a line shape along the longitudinal direction of the trench 23.

[0037] An upper electrode 27 electrically connected to the source region 21 and the contact region 22 through the contact hole 24b is formed on the interlayer insulating film 26. Although not shown, a gate wiring electrically connected to the gate electrode 25 and the like are also formed on the interlayer insulating film 26. In this embodiment, the upper electrode 27 corresponds to a first electrode.

[0038] The upper electrode 27 of this embodiment is made of a plurality of metals, such as Ni / Al. The portion of the plurality of metals that contacts the portion that constitutes the n-type SiC (i.e., the source region 21) is made of a metal that can make ohmic contact with the n-type SiC. At least the portion of the plurality of metals that contacts the p-type SiC (i.e., the contact region 22) is made of a metal that can make ohmic contact with the p-type SiC.

[0039] 1, a lower electrode 28 electrically connected to the substrate 11 is formed on the other surface 10b of the semiconductor substrate 10. In this embodiment, the lower electrode 28 corresponds to the second electrode. In the SiC semiconductor device of this embodiment, such a structure constitutes an n-channel type inversion type trench gate structure MOSFET.

[0040] The above is the configuration of the SiC semiconductor device in this embodiment. + type, n type, n - The type corresponds to the first conductivity type, and p - type, p type, p + The type corresponds to the second conductivity type. Next, the operation and effects of the above-mentioned SiC semiconductor device will be described.

[0041] In the above-described SiC semiconductor device, in the off state before the gate voltage is applied to the gate electrode 25, no inversion layer is formed in the base layer 20. Therefore, even if a positive voltage, for example, 1600 V, is applied to the lower electrode 28, electrons do not flow from the source region 21 into the base layer 20, and the SiC semiconductor device is in the off state where no current flows between the upper electrode 27 and the lower electrode 28.

[0042] Furthermore, when the SiC semiconductor device is in an off state, an electric field is applied between the drain and gate, and electric field concentration may occur at the bottom of the gate insulating film 24. However, in the above-mentioned SiC semiconductor device, the first deep layer 15 and the JFET section 14 are provided at a position deeper than the trench 23. Therefore, the depletion layer formed between the first deep layer 15 and the JFET section 14 suppresses the rise of the equipotential line due to the influence of the drain voltage, making it difficult for a high electric field to penetrate into the gate insulating film 24. Therefore, in this embodiment, it is possible to suppress the destruction of the gate insulating film 24 when the device is off.

[0043] When a predetermined gate voltage, for example, 20 V, is applied to the gate electrode 25, a channel is formed on the surface of the base layer 20 that is in contact with the trench 23. As a result, a current flows between the upper electrode 27 and the lower electrode 28, and the SiC semiconductor device is turned on. In this embodiment, since electrons that have passed through the channel pass through the current spreading layer 17, the JFET section 14, and the low concentration layer 13 and flow to the substrate 11, it can be said that a drift layer 19 having the current spreading layer 17, the JFET section 14, and the low concentration layer 13 is configured.

[0044] In this embodiment, the first portion 241, in which electric field concentration is likely to occur, of the gate insulating film 24 is made the thickest. Therefore, for example, the dielectric strength voltage of the first portion 241 can be made higher compared to a case in which the thickness of the first portion 241 is equal to the thickness of the second portion 242. Therefore, in the SiC semiconductor device of this embodiment, it is possible to suppress destruction of the first portion 241, in which electric field concentration is likely to occur when the SiC semiconductor device is turned on.

[0045] Moreover, in the present embodiment, the gate insulating film 24 has a thickness of the second portion 242 that is thinner than the thickness of the first portion 241. Therefore, compared to a case in which the thickness of the second portion 242 is equal to the thickness of the first portion 241, an increase in the threshold voltage can be suppressed, and an increase in the on-resistance can be suppressed.

[0046] Next, a method for manufacturing the above-mentioned SiC semiconductor device will be described with reference to Figures 3A to 3H, which are cross-sectional views corresponding to Figure 2.

[0047] First, as shown in Fig. 3A, a semiconductor substrate 10 is prepared in which a buffer layer 12, a low concentration layer 13, a JFET section 14, a first deep layer 15, a current spreading layer 17, a second deep layer 18, a base layer 20, a source region 21, a contact region 22, etc. are formed on a substrate 11. Note that in Fig. 3A, the substrate 11, the buffer layer 12, the low concentration layer 13, the JFET section 14, the first deep layer 15, etc. are omitted.

[0048] 3B, anisotropic etching such as RIE (short for reactive ion etching) is performed using a mask (not shown) to form trenches 23 in semiconductor substrate 10. As described above, trenches 23 are formed so that their bottom surfaces are located within current spreading layer 17. After this process is completed, trenches 23 do not have step portions 23a and their inner wall surfaces are generally flat from the opening side to the bottom side.

[0049] Next, as shown in FIG. 3C, thermal oxidation or the like is performed to form a sacrificial oxide film 30 on the wall surface of the trench 23. Here, it is known that the sacrificial oxide film 30 formed by thermal oxidation has a faster oxidation rate in the n-type impurity layer than in the p-type impurity layer, and the higher the impurity concentration, the faster the oxidation rate. For this reason, the thickness of the sacrificial oxide film 30 in contact with the source region 21 is thicker than the thickness of the parts in contact with the base layer 20, the contact region 22, the current spreading layer 17, etc. In addition, a step portion 23a is formed in the trench 23 between the part in contact with the source region 21 and the part in contact with the base layer 20, etc. In addition, in the one surface 10a of the semiconductor substrate 10, the thickness of the part in contact with the source region 21 is thicker than the thickness of the part in contact with the contact region 22. However, in FIG. 3C, the thickness of the gate insulating film 24 on the one surface 10a side of the semiconductor substrate 10 is simplified and shown as a uniform thickness.

[0050] Thereafter, as shown in FIG. 3D, the sacrificial oxide film 30 is removed using hydrofluoric acid or the like.

[0051] 3E, a gate insulating film 24 is formed on the inner wall surface of the trench 23 by a CVD (short for Chemical Vapor Deposition) method or the like. At this time, as described above, the trench 23 has a step portion 23a formed therein, and the width of the opening side is made wider than the width of the bottom side. Therefore, the gate insulating film 24 is formed thickly in the portion of the trench 23 that contacts the source region 21. The gate insulating film 24 is also formed on one surface 10a of the semiconductor substrate 10.

[0052] 3F, doped Poly-Si constituting gate electrode 25 is formed by a CVD method or the like so as to fill trench 23. In this process, doped Poly-Si is also formed on gate insulating film 24 disposed on one surface 10a of semiconductor substrate 10.

[0053] Next, as shown in FIG. 3G, a mask (not shown) is placed, and the doped poly-silicon formed on one surface 10a of the semiconductor substrate 10 is removed while leaving a portion that will become the gate wiring. The doped poly-silicon disposed on the opening side of the trench 23 is also removed. That is, the gate insulating film 24 disposed on the opening side of the trench 23 is exposed. At this time, the gate insulating film 24 is also gradually removed from the portion on the opening side of the trench 23. Therefore, the gate insulating film 24 has a tapered shape in which the thickness gradually increases from the opening side of the trench 23 to the portion where the gate electrode 25 is disposed.

[0054] 3H, the interlayer insulating film 26 is formed by low-pressure CVD or the like so as to fill the trench 23. At this time, since the gate insulating film 24 is tapered from the opening of the trench 23 to the portion where the gate electrode 25 is disposed, the embedding property of the interlayer insulating film 26 in the trench 23 can be improved.

[0055] Next, a contact hole 24b is formed penetrating the gate insulating film 24 and the interlayer insulating film 26. Thereafter, an upper electrode 27 is formed on one surface 10a of the semiconductor substrate 10 and a lower electrode 28 is formed on the other surface 10b by a PVD (short for Physical Vapor Deposition) method or the like, thereby manufacturing the SiC semiconductor device shown in FIG.

[0056] According to the present embodiment described above, the gate insulating film 24 is formed such that the first portion 241 is thickest in a portion located between the gate electrode 25 and the semiconductor substrate 10. For this reason, the dielectric strength voltage of the first portion 241 can be made higher than when the thickness of the first portion 241 is equal to the thickness of the second portion 242. Therefore, it is possible to prevent the first portion 241, which is part of the gate insulating film 24 and where electric field concentration is likely to occur, from being destroyed.

[0057] (1) In the present embodiment, the gate insulating film 24 has the second portion 242 thinner than the first portion 241. Therefore, compared to a case in which the thickness of the second portion 242 is equal to the thickness of the first portion 241, an increase in the threshold voltage can be suppressed, and the on-resistance can be reduced.

[0058] (2) In this embodiment, the gate insulating film 24 is gradually thickened from the opening side of the trench 23 in the portion in contact with the interlayer insulating film 26 disposed in the trench 23. This improves the embedding property of the interlayer insulating film 26 in the trench 23 when the interlayer insulating film 26 is disposed. This makes it easier to ensure the insulation between the gate electrode 25 and the upper electrode 27.

[0059] (Other embodiments) Although the present disclosure has been described based on the embodiment, it is understood that the present disclosure is not limited to the embodiment or structure. The present disclosure also encompasses various modifications and modifications within the equivalent range. In addition, various combinations and forms, as well as other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and concept of the present disclosure.

[0060] For example, in the first embodiment, the SiC semiconductor device made of SiC has been described, but in the semiconductor device in each of the above embodiments, the semiconductor substrate 10 may be made of a silicon substrate or the like.

[0061] In the first embodiment, an n-channel type trench gate structure MOSFET in which the first conductivity type is n-type and the second conductivity type is p-type has been described. However, this is merely one example, and a p-channel type trench gate structure MOSFET in which the conductivity types of each component are inverted from the n-channel type may also be used. Furthermore, the semiconductor device may be configured to include an IGBT having a similar structure in addition to the MOSFET. In the case of an IGBT, the n-channel type MOSFET in the first embodiment may be formed with a p-channel type trench gate structure. + The drain layer is P + Apart from changing the collector layer to a type IGBT, the vertical MOSFET is the same as that described in the first embodiment. In the case of an IGBT, the collector layer corresponds to the second impurity region.

[0062] Furthermore, in the first embodiment, the JFET section 14, the first deep layer 15, the second deep layer 18, etc. may not be formed.

[0063] In the first embodiment, the gate insulating film 24 may be formed by thermal oxidation in the step of Fig. 3E. This allows the thickness of the first portion 241 of the gate insulating film 24 to be further increased.

[0064] In the first embodiment, the gate insulating film 24 may have the second portion 242 and the first portion 241 each having the same thickness.

[0065] In addition, in the above first embodiment, the gate insulating film 24 may have a uniform thickness in the portion in contact with the interlayer insulating film 26 arranged in the trench 23 from the opening side of the trench 23 toward the portion where the gate electrode 25 is arranged. [Explanation of symbols]

[0066] 10. Semiconductor Substrate 10a one side 10b Other side 11 Substrate (second impurity region) 19 Drift Layer 20 Base Layer 21 source region (first impurity region) 23 Trench 24 Gate insulating film 25 Gate electrode 27 Upper electrode (1st electrode) 28 Lower electrode (second electrode)

Claims

1. A semiconductor device having a trench gate structure, a semiconductor substrate (10) including a drift layer (19) of a first conductivity type, a base layer (20) of a second conductivity type formed on the drift layer, a first impurity region (21) of the first conductivity type formed in a surface layer portion of the base layer and having a higher impurity concentration than the drift layer, and a second impurity region (11) of the first conductivity type or the second conductivity type formed on a side of the drift layer opposite to the base layer side, the semiconductor substrate (10) having a surface (10a) on the side of the first impurity region side and a surface (10b) on the side of the second impurity region side; the trench gate structure in which a gate insulating film (24) is disposed on a wall surface of a trench (23) formed from one surface side of the semiconductor substrate deeper than the base layer to reach the drift layer and with a side surface in contact with the base layer and the first impurity region, and a gate electrode (25) is disposed on the gate insulating film; a first electrode (27) formed on one surface side of the semiconductor substrate and electrically connected to the base layer and the first impurity region; a second electrode (28) formed on the other surface side of the semiconductor substrate and electrically connected to the second impurity region; the gate insulating film has a thickness that is greatest at a portion sandwiched between the first impurity region and the gate electrode in a portion sandwiched between the semiconductor substrate and the gate electrode, the gate electrode is disposed in a state in which a portion of the gate insulating film formed on the opening side of the trench is exposed; An interlayer insulating film (26) is embedded in the opening side of the trench, A semiconductor device in which the gate insulating film, at a portion where it contacts the interlayer insulating film arranged in the trench, has a thickness that gradually increases from the opening side of the trench toward the portion where the gate electrode is arranged.

2. 2. The semiconductor device according to claim 1, wherein the gate insulating film has a thickness that is thinner at a portion sandwiched between the base layer and the gate electrode than at a portion sandwiched between the first impurity region and the gate electrode.

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