Insulated gate semiconductor device and method for manufacturing the same

Abstract

To provide an insulating gate type semiconductor device that can reduce a variation in gate threshold voltage and prevent a deterioration in reliability of the semiconductor device, and a method for manufacturing an insulating gate type semiconductor device.SOLUTION: An insulating gate type semiconductor device comprises: a gate insulating film 5 that is formed of a SiO2 film and is provided on a top face of a channel formation region 3 formed of SiC; a nitrogen termination layer 6 that is provided on the interface between the channel formation region 3 and the gate insulating film 5 and obtained by terminating Si with N; and a gate electrode 7 that is provided on the gate insulating film 5 and controls the surface potential of the channel formation region 3. When measurement is conducted by SIMS in a depth direction from the surface of the gate insulating film 5, the integrated value of the concentration of C atoms from an interface defined at a peak position of the concentration of N atoms to a position where the concentration of C atoms becomes 1×1020 cm-3 or less in the gate insulating film 5 is 5×1015 cm-2 or less, and the width in the depth direction at which the concentration of N atoms becomes half the concentration of N atoms at the peak position is 2 nm or less.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to an insulated gate semiconductor device and a method for manufacturing an insulated gate semiconductor device, and more particularly to an insulated gate semiconductor device using silicon carbide (SiC) and a method for manufacturing an insulated gate semiconductor device. [Background technology]

[0002] In MOS field-effect transistors (FETs) using SiC, high density interface states are formed when the gate insulating film is formed on the semiconductor layer. This reduces the mobility of the channel, and the electrical characteristics of the MOSFET, such as the on-resistance, are degraded. It has been proposed to reduce the interface state density (Dit) at the gate insulating film interface and increase the mobility by performing a heat treatment in a gas containing nitrogen (N) after the gate insulating film is formed to form a high concentration nitride region at the interface between the silicon oxide (SiO2) film and the SiC layer. When such a MOSFET is actually used, the gate threshold voltage (Vth) fluctuates when positive and negative voltages are continuously applied alternately to the gate electrode. This limits the practical life of the MOSFET.

[0003] Patent Document 1 discloses a technique for suppressing a Vth shift by specifying the ratio of the integral value of the N atom concentration to the integral value of the carbon (C) atom concentration in the vicinity of the interface between the SiO2 film and SiC. Specifically, the interface state density is reduced by increasing the N atom concentration in the carbon transition layer formed by the C atoms remaining in the SiO2 film in the vicinity of the interface. However, the technique of Patent Document 1 has a problem that the N atom concentration in the SiO2 film in the vicinity of the carbon transition layer is also increased, generating an electron trap level, and making it easier for a Vth shift to occur when the MOSFET is driven. Patent Document 2 describes that impurities such as alkaline earth metals and C atoms are contained in the vicinity of the interface between the SiO2 film and SiC to suppress the leakage current of the gate insulating film. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. 2014 / 103186 [Patent Document 2] JP 2017-204644 A Summary of the Invention [Problem to be solved by the invention]

[0005] In view of the above problems, an object of the present invention is to provide an insulated gate semiconductor device and a method for manufacturing an insulated gate semiconductor device that can reduce fluctuations in gate threshold voltage and suppress deterioration of the reliability of the semiconductor device. [Means for solving the problem]

[0006] In order to achieve the above object, one aspect of the present invention is a gate insulating film comprising: (a) a silicon oxide film provided on an upper surface of a channel formation region made of silicon carbide; (b) a nitride termination layer in which silicon is terminated with nitrogen, provided at an interface between the channel formation region and the gate insulating film; and (c) a gate electrode provided on the gate insulating film and controlling a surface potential of the channel formation region, wherein when measured by secondary ion mass spectrometry in a depth direction from the surface of the gate insulating film, a carbon atom concentration in the gate insulating film is 1×10 20 cm -3 The integral of the carbon atom concentration up to the position where it is less than or equal to 5×10 15 cm -2 The present invention provides an insulated gate semiconductor device having a width of 2 nm or less in the depth direction where the nitrogen atomic concentration is half the nitrogen atomic concentration at the peak position.

[0007] Another aspect of the present invention is a method for fabricating a semiconductor device comprising the steps of: (a) forming a gate insulating film made of a silicon oxide film on an upper surface of a channel formation region made of silicon carbide; (b) doping boron atoms into the gate insulating film; and (c) heat-treating the gate insulating film with a gas containing nitrogen atoms to form a nitride termination layer at the interface between the channel formation region and the gate insulating film, and increasing the boron atom concentration in the gate insulating film to 1×10 19cm -3 5×10 or more 20 cm -3 The present invention relates to a method for manufacturing an insulated gate semiconductor device, the method including the steps as follows: (a) forming a gate electrode on a gate insulating film to control a surface potential of a channel formation region; and (b) forming a gate electrode on the gate insulating film to control a surface potential of a channel formation region. Effect of the Invention

[0008] According to the present invention, it is possible to provide an insulated gate semiconductor device capable of reducing fluctuations in gate threshold voltage and suppressing deterioration in the reliability of the semiconductor device, and a method for manufacturing the insulated gate semiconductor device. [Brief description of the drawings]

[0009] [Figure 1] 1 is a schematic cross-sectional view showing an example of an insulated gate semiconductor device according to an embodiment of the present invention. [Diagram 2] FIG. 1 is a diagram for explaining a method for evaluating an insulated gate structure by SIMS. [Diagram 3] 1A to 1C are schematic cross-sectional views for explaining an example of a process of a method for manufacturing an insulated gate semiconductor device according to Example 1 of an embodiment. [Figure 4] 4 is a schematic cross-sectional view for explaining an example of a step subsequent to FIG. 3 in the method for manufacturing an insulated gate semiconductor device according to Example 1 of the embodiment. FIG. [Diagram 5] 5 is a schematic cross-sectional view for explaining an example of a step subsequent to FIG. 4 in the method for manufacturing an insulated gate semiconductor device according to Example 1 of the embodiment. FIG. [Figure 6] 6 is a schematic cross-sectional view for explaining an example of a step subsequent to FIG. 5 in the method for manufacturing an insulated gate semiconductor device according to Example 1 of the embodiment. FIG. [Figure 7] 7 is a schematic cross-sectional view for explaining an example of a step subsequent to FIG. 6 in the method for manufacturing an insulated gate semiconductor device according to Example 1 of the embodiment. FIG. [Figure 8] 11 is a schematic cross-sectional view for explaining an example of a process of a method for manufacturing an insulated gate semiconductor device according to Example 2 of the embodiment. FIG. [Figure 9]9 is a schematic cross-sectional view for explaining an example of a step subsequent to FIG. 8 in the method for manufacturing an insulated gate semiconductor device according to Example 2 of the embodiment. [Figure 10] 10 is a schematic cross-sectional view for explaining an example of a step subsequent to FIG. 9 in the method for manufacturing an insulated gate semiconductor device according to Example 2 of the embodiment. FIG. [Figure 11] 1 is a schematic cross-sectional view showing an example of an insulated gate semiconductor device according to Comparative Example 1. FIG. [Figure 12] 4 is a diagram showing an example of a SIMS measurement result near the interface of the insulated gate structure according to Example 1. FIG. [Figure 13] FIG. 11 is a diagram showing an example of a SIMS measurement result in the vicinity of an interface of an insulated gate structure according to Example 2. [Figure 14] FIG. 13 is a diagram showing an example of a SIMS measurement result near the interface of the insulated gate structure according to Comparative Example 1. [Figure 15] 1 is a table showing an example of evaluation results of the insulated gate semiconductor device according to the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the description of the drawings, the same or similar parts are given the same or similar reference numerals, and duplicated explanations are omitted. However, the drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of thickness of each layer, etc. may differ from the actual ones. In addition, parts with different dimensional relationships and ratios may be included between the drawings. In addition, the embodiments shown below are examples of devices and methods for embodying the technical idea of ​​the present invention, and the technical idea of ​​the present invention does not specify the materials, shapes, structures, arrangements, etc. of the components as described below.

[0011] In this specification, the source region of a MOS transistor is "one main region (first main region)" that can be selected as the emitter region of an insulated gate bipolar transistor (IGBT). In addition, in a thyristor such as a MOS controlled static induction thyristor (SI thyristor), one main region can be selected as the cathode region. The drain region of a MOS transistor is "the other main region (second main region)" of a semiconductor device that can be selected as the collector region in an IGBT or as the anode region in a thyristor. In this specification, when the term "main region" is used simply, it means either the first main region or the second main region that is appropriate from the technical common sense of a person skilled in the art.

[0012] In addition, the definitions of the directions such as up and down in the following description are merely for the convenience of explanation and do not limit the technical idea of ​​the present invention. For example, if an object is rotated 90 degrees and observed, up and down are converted to left and right and read, and if it is rotated 180 degrees and observed, up and down are read inverted. In the following description, the case where the first conductivity type is p-type and the opposite second conductivity type is n-type will be described as an example. However, the conductivity types may be selected in an inverse relationship, with the first conductivity type being n-type and the second conductivity type being p-type. In addition, + and - added to n and p mean that the semiconductor region has a relatively high or low impurity density, respectively, compared to a semiconductor region without + and -. However, even if the same n and n are added to the semiconductor region, it does not mean that the impurity density of each semiconductor region is strictly the same. In addition, in the notation of Miller indices in this specification, "-" means a bar attached to the index immediately after it, and adding "-" before the index represents a negative index.

[0013] The insulated gate semiconductor device according to the embodiment of the present invention is a lateral MOSFET that uses an oxide film made of SiO2 as a gate insulating film. As shown in FIG. 1, it has a channel formation region (base region) 3 of a first conductivity type (p type), and an inversion channel is formed on the surface of the channel formation region 3. A high-impurity-density second conductivity type (n +In the channel formation region 3, main regions 4a and 4b, such as a source region (first main region) 4a and a drain region (second main region) 4b, are selectively provided. An insulated gate electrode structure (5, 7) is provided on the upper surface of the channel formation region 3 across the source region 4a and the drain region 4b, via a nitride termination layer 6 terminated with nitrogen (N). The insulated gate electrode structure (5, 7) is composed of a gate insulating film 5 made of a SiO2 film and a gate electrode (control electrode) 7 on the gate insulating film 5. The gate electrode 7 electrostatically controls the surface potential of the channel formation region 3 via the gate insulating film 5, forming an inversion channel on the surface of the channel formation region 3.

[0014] The gate insulating film 5 of the MOSFET is an oxide film made of SiO2, and may be a thermal oxide film formed by oxygen (O2) dry oxidation or wet oxidation, or a deposited oxide film formed by sputtering, thermal chemical vapor deposition (thermal CVD), plasma CVD, or the like. The gate insulating film 5 is formed by diffusing boron (B) atoms from a solid diffusion source such as boron nitride (BN) at a density of 1×10 19 cm -3 5×10 or more 20 cm -3 The concentration range is as follows: As the material of the gate electrode 7, a metal film such as aluminum (Al) or a polysilicon layer (doped polysilicon layer) to which impurities such as phosphorus (P) are added at a high concentration can be used.

[0015] As shown in FIG. 1, the channel formation region 3 is epitaxially grown on a substrate 1 made of an n-type SiC semiconductor. A source electrode 8a and a drain electrode 8b are provided so as to be in physical contact with the source region 4a and the drain region 4b, respectively. The source electrode 8a and the drain electrode 8b are ohmic-connected to the source region 4a and the drain region 4b, respectively. The source electrode 8a and the drain electrode 8b are formed of, for example, a single layer film made of Al or nickel silicide (NiSi x A metal film in which a metal film including a titanium nitride (TiN) and an Al layer is laminated in this order can be used. Although not shown in the figure, a p +A contact region is disposed in the channel forming region 3 and is separated from the source region 4a.

[0016] There are crystal polymorphs in SiC crystals, the main ones being cubic 3C, and hexagonal 4H and 6H. The band gap at room temperature has been reported to be 2.23 eV for 3C-SiC, 3.26 eV for 4H-SiC, and 3.02 eV for 6H-SiC. The insulated gate type semiconductor device according to the embodiment of the present invention will be described using 4H-SiC. In the insulated gate type semiconductor device according to the embodiment, a semiconductor substrate (SiC substrate) made of SiC is used as the substrate 1. When a SiC substrate is used, a structure in which the channel formation region 3 is made of an epitaxial layer (SiC layer) made of SiC is exemplified. The surface orientation of the SiC substrate will be described using the (0001) surface (Si surface), but the (11-20) surface (a surface), (1-100) surface (m surface), and (000-1) surface (C surface) may also be used.

[0017] 1, in the insulated gate semiconductor device according to the embodiment, a voltage is applied to the gate electrode 7 to form an inversion layer that becomes a channel at the interface between the gate insulating film 5 and the channel formation region 3. At this time, a voltage is applied between the source electrode 8a and the drain electrode 8b, so that carriers (electrons) are injected from the source region 4a into the channel. The injected carriers travel through the channel and flow into the drain region 4b.

[0018] Usually, when the oxide film used for the gate insulating film 5 is formed by a thermal oxidation method or the like, carbon (C) atoms remain at the interface between the oxide film and the SiC semiconductor layer, forming a high-density interface state. When electrons are captured at the interface state, the electron mobility decreases due to Coulomb scattering or the like. A method for reducing the interface state density by nitriding the interface between the oxide film and the SiC semiconductor layer with N atoms has been proposed. However, when a high-concentration nitrided region is formed at the interface between the oxide film and the SiC semiconductor layer, the number of N atoms in the oxide film near the interface increases. In addition, after the nitriding process of the interface, high-temperature heat treatments of 900° C. or more are performed, such as contact heat treatment for reducing the contact resistance of the source electrode 8a and the drain electrode 8b and reflow heat treatment for smoothing the interlayer insulating film (not shown). By such high-temperature heat treatment, in addition to N atoms from the nitrided region, C atoms from the SiC semiconductor are also diffused into the oxide film, and defect structures (electron trap levels and hole trap levels) are generated in the oxide film. Therefore, when the semiconductor device is AC driven by continuously applying alternate positive and negative voltages to the gate electrode with the potential of the source electrode as a reference, a gate threshold voltage fluctuation (Vth shift) occurs.

[0019] In the insulated gate semiconductor device according to the embodiment, B atoms are diffused and added into the oxide film forming the gate insulating film 5, and then a nitridation process is performed to provide a nitride termination layer 6 at the interface between the gate insulating film 5 and the channel formation region 3. 19 cm -3 5×10 or more 20 cm -3 In the gate insulating film 5 doped in the following concentration range, the diffusion of N atoms and C atoms into the gate insulating film 5 can be suppressed even during high-temperature heat treatment performed after the nitridation treatment. 20 cm -3 If the B atom concentration exceeds 1×10 19 cm -3 If the thickness is less than this, it becomes difficult to suppress the diffusion of N atoms and C atoms into the gate insulating film 5.

[0020] FIG. 2 is a schematic diagram for explaining a method of evaluating the vicinity of the interface of an insulated gate structure by secondary ion mass spectrometry (SIMS). In FIG. 2, the horizontal axis indicates depth in linear scale, and the vertical axis indicates concentration in logarithmic scale. The interface between the oxide film and the SiC semiconductor layer is taken as depth 0 on the horizontal axis of FIG. 2. The interface is defined as the peak position of the N atom concentration distribution. As shown in FIG. 2, N atoms are distributed on the SiC semiconductor layer side and the oxide film side near the interface, and C atoms are distributed so as to decrease from the SiC semiconductor layer into the oxide film. The half-width d H is the width from the interface to the position where the N atom concentration in the oxide film is half of the peak value, and can be used as an index for judging the amount of N atom diffusion into the oxide film. The transition width d is the width from the interface to the position where the C atom concentration in the oxide film is at the noise level, for example, 1×10 20 cm -3 The amount of C atoms remaining in the oxide film can be obtained by integrating the C atom concentration within the transition width d. In the embodiment, the half-width d of the N atom concentration distribution H is set to 2 nm or less, and the carbon (C) surface density, which is the integral value of the C atom concentration within the transition width d of the C atom concentration distribution, is set to 5 × 10 15 cm -2 The concentrations of N atoms and C atoms in the oxide film are reduced as follows: As a result, the generation of defect structures such as electron trap levels and hole trap levels in the oxide film can be suppressed, and fluctuations in the gate threshold voltage of the semiconductor device can be suppressed.

[0021] The nitrogen (N) surface density at the interface can be evaluated by measuring the surface of the SiC semiconductor layer from which the oxide film has been removed with an etching solution such as hydrofluoric acid (HF) using X-ray photoelectron spectroscopy (XPS). In the XPS measurement, aluminum (Al) Kα rays are used as the X-ray source, and surface analysis is performed at a detection angle of 90 degrees. The N surface density is calculated from the area intensity ratio of the XPS signals between the spectrum signal (N1s signal) due to the 1s orbital of N atoms obtained by XPS and the spectrum signal (Si2p signal) due to the 2p orbital of Si atoms. In an embodiment, the N surface density at the interface obtained by XPS measurement is 3×10 14 cm -2 More than 1×10 15 cm -2By keeping the N areal density below 3×10, the N areal density required for reducing the interface state is ensured. 14 cm -2 The characteristics of the MOSFET are significantly degraded below this value. In addition, the upper limit of the N surface density for passivation by nitridation of the interface is 1×10 15 cm -2 The N surface density at the interface was calculated by dividing the half-width d H It is also possible to evaluate it from the integral value of the N atom concentration up to the position.

[0022] <Method of Manufacturing Semiconductor Device> Next, a method for manufacturing a semiconductor device according to an embodiment will be described using a lateral MOSFET as an example. Note that the method for manufacturing a MOSFET described below is only an example, and it goes without saying that various other manufacturing methods, including modifications thereof, can be used within the scope of the spirit of the claims.

[0023] Example 1 A method for manufacturing a MOSFET according to the first embodiment will be described with reference to the process diagrams shown in FIGS. 3 to 7. First, an n-type SiC substrate (substrate) 1 doped with n-type impurities such as nitrogen (N) is prepared. The substrate 1 is a 4H-SiC substrate with a (0001) surface orientation (Si surface). First, the substrate 1 is RCA-cleaned by adding an alkali or acid to hydrogen peroxide and heating to clean it, and then treated with hydrogen fluoride (HF) and dried. A p-type channel formation region (base region) 3 is epitaxially grown on the upper surface of the substrate 1. An n-type impurity such as N is selectively implanted from the upper surface side of the channel formation region 3 by photolithography technology, ion implantation technology, or the like. The implanted n-type impurity ions are activated by heat treatment. As a result, as shown in FIG. 3, n-type impurity ions are formed in the upper part of the channel formation region 3. + The source regions 4a and n + The drain region 4b of the semiconductor layer is selectively implanted.

[0024] 4, an oxide film 5a made of SiO2 and about 50 nm thick is formed on the upper surface of the channel formation region 3 by heating in a 100% O2 gas atmosphere at a temperature of about 1200°C for about 160 minutes. Although a dry oxide film is exemplified as the oxide film 5a, a wet oxide film or a deposited oxide film by thermal CVD, plasma CVD, or the like may also be used. For example, the oxide film 5b may be deposited by low-pressure thermal CVD using silane (SiH4) gas and oxygen (O2) gas at a pressure of about 0.2 Pa and a temperature of about 600°C.

[0025] A solid diffusion source 20 made of a boron nitride (BN) wafer or the like is placed facing the upper surface of the oxide film 5a via a spacer 22 made of quartz or the like having a thickness of about 1.5 mm. The oxide film 5a is heated for about 30 minutes at a temperature of 900°C to 1200°C, for example, about 950°C, in an atmosphere of inert gas such as argon (Ar) gas or nitrogen (N2) gas at atmospheric pressure, to diffuse and add B atoms into the oxide film 5a. As a result, as shown in FIG. 5, 5×10 B atoms are added. 20 cm -3 More than 1×10 21 cm -3 The oxide film 5b containing B in the following range is formed. The B diffusion addition process may be performed in a gas atmosphere in which O2 gas is added to an inert gas by up to about 10%. Alternatively, when a deposited oxide film is used, a B atom-containing gas such as diborane (B2H6) or boron trichloride (BCl3) may be added to the film formation gas to deposit the oxide film 5b.

[0026] Next, in a gas atmosphere in which 10% nitric oxide (NO) gas is added to N2 gas, nitridation is performed by heating at a temperature of 1150°C to 1300°C, for example, about 1250°C, for about 60 minutes. By this nitridation, as shown in FIG. 6, an intermediate nitride layer 6a is formed at the interface between the oxide film 5b and the channel formation region 3, the source region 4a, and the drain region 4b. Note that N2O gas may be used instead of NO for the nitridation. Also, by performing this step, the B atom concentration in the oxide film 5b can be increased to 1×10 19 cm -3 5×10 or more 20 cm -3 The range is as follows:

[0027] After the nitridation process, source and drain contact holes are opened in the oxide film 5b by photolithography, dry etching, etc. As a result, a pattern of the gate insulating film 5 and the nitride termination layer 6 that straddle the source region 4a and the drain region 4b is selectively left on the upper surface of the channel formation region 3, as shown in FIG.

[0028] A metal layer such as a nickel (Ni) film having a thickness of about 50 nm is deposited on the upper surfaces of the gate insulating film 5, the source contact hole, and the drain contact hole by sputtering or electron beam deposition. The Ni metal layer is patterned by photolithography and RIE techniques. Then, rapid thermal annealing (RTA) is performed in an N2 gas atmosphere at a temperature of 900°C to 1000°C, for example, about 950°C, for about 3 minutes. In this way, silicide (NiSi x A contact layer made of a SiO 2 film is formed. A metal film of Al or the like having a thickness of about 100 nm is deposited by sputtering, vacuum deposition, or the like, and the Al metal film is patterned by photolithography, dry etching, or the like to form a gate electrode 7, a source electrode 8a, and a drain electrode 8b. As a result, an insulated gate electrode structure (5, 7) is formed on the upper surface of the channel formation region 3 via the nitride termination layer 6 so as to straddle a part of the ends of the source region 4a and the drain region 4b. In this manner, the MOSFET of Example 1 is completed as the insulated gate semiconductor device according to the embodiment shown in FIG. 1.

[0029] Example 2 In Example 1, B atoms are added to the gate insulating film 5 in order to suppress the diffusion of N atoms and C atoms into the oxide film, but in Example 2, the diffusion of N atoms and C atoms is suppressed by limiting the heat treatment temperature in a process that requires heat treatment performed after nitridation treatment. The method for manufacturing a MOSFET according to Example 2 will be described with reference to the process diagrams shown in Figures 8 to 10.

[0030] First, as shown in FIG. 4, an oxide film 5a is formed on the upper surface of the channel formation region 3 in which a source region 4a and a drain region 4b are selectively embedded. Then, in a gas atmosphere in which 10% of NO gas is added to N2 gas, heating is performed at a temperature of 1150°C or higher and 1300°C or lower, for example, about 1250°C for about 60 minutes to perform a nitriding treatment. By this nitriding treatment, as shown in FIG. 8, an intermediate nitride layer 6a is formed at the interface between the oxide film 5a and the channel formation region 3, the source region 4a, and the drain region 4b. Note that, instead of NO, N2O gas may be used for the nitriding treatment.

[0031] After the nitriding treatment, a source contact hole and a drain contact hole are formed in the oxide film 5a by photolithography technology, dry etching, or the like. As a result, as shown in FIG. 9, a pattern of a gate insulating film 5c and a nitride termination layer 6 that straddles the source region 4a and the drain region 4b remains selectively on the upper surface of the channel formation region 3.

[0032] A metal layer such as a Ni film having a thickness of about 50 nm is deposited on the upper surfaces of the gate insulating film 5c, the source contact hole, and the drain contact hole by sputtering, electron beam evaporation, or the like. The Ni metal layer is patterned using photolithography technology, RIE technology, or the like. Then, by performing RTA at a temperature of less than 900°C, for example, about 875°C for about 8 minutes in an N2 gas atmosphere, a contact layer made of a NiSi film is selectively formed on the upper surfaces of the source contact hole and the drain contact hole. x A metal film such as Al having a thickness of about 100 nm is deposited by sputtering, vacuum evaporation, or the like, and the Al metal film is patterned by photolithography technology, dry etching, or the like to form a gate electrode 7, a source electrode 8a, and a drain electrode 8b. As a result, as shown in FIG. 10, an insulated gate type electrode structure (5c, 7) is formed on the upper surface of the channel formation region 3 via the nitride termination layer 6 so as to straddle a part of the ends of the source region 4a and the drain region 4b. In this way, the MOSFET of Example 2 is completed.

[0033] <MOS Interface Evaluation> For the examples 1 and 2 prepared as described above, SIMS measurement, XPS measurement and AC driving test were performed using an analysis pattern (analysis TEG) prepared on the same substrate to evaluate the MOS interface characteristics. x Comparative Example 1 was also evaluated, which was fabricated by a conventional manufacturing method in which a contact layer made of a silicon nitride film was formed by RTA at about 950°C for about 3 minutes in an N2 gas atmosphere. In Comparative Example 1, as shown in FIG. 11, a gate insulating film 5d was formed on the upper surface of a channel formation region 3 via a nitride termination layer 6. FIGS. 12 to 14 show the results of SIMS analysis of the vicinity of the SiC / SiO2 interface by an analytical TEG in Example 1, Example 2, and Comparative Example 1, respectively. FIG. 15 shows the results of SIMS and XPS measurement of the vicinity of the interface, and the evaluation result of the Vth shift amount of the MOSFET by an AC application drive test.

[0034] As shown in FIG. 12, the B atom concentration in the gate insulating film 5 of Example 1 is 4.5×10 20 cm -3 About 4.5×10 or less on average 20 cm -3 12 to 14, it can be seen that the diffusion of N atoms and C atoms in the oxide film near the interface between the SiC semiconductor layer and the oxide film is suppressed in Examples 1 and 2 compared to Comparative Example 1. The diffusion of N atoms into the oxide film is suppressed by a half-value width d H The diffusion of C atoms into the oxide film is evaluated when the C atom concentration in the oxide film is at the noise level, for example, 1×10 20 cm -3 The integral value of the C atom concentration within the transition width d, which is defined as the width up to the position where

[0035] Specifically, as shown in the table of FIG. 15, in Example 1 in which B atoms are added to the oxide film corresponding to the gate insulating film 5, the half-width d HIn Example 2, in which the heat treatment temperature for forming the contact layer after the nitriding treatment was set to about 875° C., which is lower than 900° C., the half-width d H On the other hand, in Comparative Example 1 in which the heat treatment temperature for forming the contact layer was set at about 950° C., the half-width d H The area of ​​the surface of the C atoms is about 2.6 nm, which is large, and the N atom diffusion is not suppressed. In addition, the surface density of C atoms obtained from the C atom concentration distribution by SIMS is 5.7 × 10 15 cm -2 In comparison with Comparative Example 1, the 15 cm -2 In Example 2, it is 4.5 × 10 15 cm -2 In this way, by adding B atoms to the oxide film, it is possible to suppress the diffusion of N atoms and C atoms into the oxide film. In addition, by lowering the heat treatment temperature after the nitriding process, it is possible to suppress the diffusion of N atoms and C atoms into the oxide film.

[0036] In addition, the surface of the SiC semiconductor layer from which the oxide film was removed with an etching solution such as hydrofluoric acid (HF) was subjected to XPS measurement using an analytical TEG to evaluate the N surface density of the SiC semiconductor layer surface that serves as the channel formation region at the interface. As shown in the table of FIG. 15, the N surface density was 4×10 in all of Examples 1 and 2 and Comparative Example 1. 14 cm -2 The interface properties can be maintained.

[0037] For the fabricated lateral MOSFETs in Examples 1 and 2, a drive test by applying an AC voltage was performed to evaluate the Vth shift. The AC voltage drive was performed by alternately applying bias voltages of +20V and -5V, or +20V and -10V to the gate electrode at room temperature for one-to-one time and at a frequency of 200 kHz. The Vth shift amount was calculated by the difference between the Vth value after 2000 hours of AC voltage application and the initial Vth value. As shown in the table of FIG. 15, the Vth shift amount by the drive by applying +20V / -5VAC is 0.1V in Comparative Example 1, while it is 0.06V in Example 1 and 0.08V in Example 2, which are small. The Vth shift amount by the drive by applying +20V / -10VAC is also 0.1V in Comparative Example 1, while it is 0.1V in Example 1 and 0.15V in Example 2, which are small. In this way, in Examples 1 and 2, the Vth shift can be reduced, and it is possible to suppress deterioration of the reliability of the semiconductor device.

[0038] (Other embodiments) As described above, the insulated gate semiconductor device according to the embodiment of the present invention has been described, but the description and drawings forming a part of this disclosure should not be understood as limiting the present invention. Various alternative embodiments, examples, and operating techniques will be apparent to those skilled in the art from this disclosure.

[0039] As described above, in the insulated gate semiconductor device according to the embodiment, a lateral MOSFET using 4H-SiC is exemplified, but the present invention can also be applied to semiconductor devices using 6H-SiC and 3C-SiC. Furthermore, the present invention can also be applied to a planar gate vertical MOSFET and a trench gate vertical MOSFET.

[0040] Thus, the present invention naturally includes various embodiments not described here, such as configurations obtained by arbitrarily applying the configurations described in the above embodiments and modifications. Therefore, the technical scope of the present invention is determined only by the invention-specifying matters according to the scope of the claims that are appropriate from the above description. [Explanation of symbols]

[0041] 1, 2...Substrate (SiC substrate) 3...Channel formation region (base region) 4a...Source area (first main area) 4b...Drain region (second main region) 5, 5c, 5d...Gate insulating film 5a, 5b...Oxide film 6...Nitride termination layer 6a: Intermediate nitride layer 7...Gate electrode (control electrode) 8a…Source electrode 8b...Drain electrode 10…Surface electrode 11…Back electrode 20...Solid diffusion source 22…Spacer

Claims

1. a gate insulating film made of a silicon oxide film provided on an upper surface of a channel formation region made of silicon carbide; a nitride termination layer formed by terminating silicon with nitrogen, the nitride termination layer being provided at an interface between the channel formation region and the gate insulating film; a gate electrode provided on the gate insulating film for controlling a surface potential of the channel formation region; Equipped with When the gate insulating film is measured in a depth direction from the surface thereof by secondary ion mass spectrometry, the carbon atom concentration in the gate insulating film is 1×10 20 cm -3 The integral value of the carbon atom concentration up to the position where it is equal to or smaller than 5×10 15 cm -2 and the width in the depth direction where the nitrogen atomic concentration is half the nitrogen atomic concentration at the peak position is 2 nm or less.

2. When the gate insulating film is removed and the surface of the channel formation region at the interface is measured by X-ray photoelectron spectroscopy, the surface density of nitrogen atoms is 3×10 14 cm -2 Above 1 x 10 15 cm -2 2. The insulated gate semiconductor device according to claim 1, wherein:

3. The gate insulating film is doped with boron atoms at a concentration of 1×10 19 cm -3 Above 5 x 10 20 cm -3 3. The insulated gate semiconductor device according to claim 1, wherein the content is within the following range:

4. forming a gate insulating film made of a silicon oxide film on an upper surface of a channel formation region made of silicon carbide; doping the gate insulating film with boron atoms; The gate insulating film is heat-treated with a gas containing nitrogen atoms to nitride the gate insulating film, thereby forming a nitride termination layer at the interface between the channel formation region and the gate insulating film, and the boron atom concentration in the gate insulating film is 1×10 19 cm -3 Above 5 x 10 20 cm -3 The steps are as follows: forming a gate electrode on the gate insulating film to control a surface potential of the channel formation region; 2. A method for manufacturing an insulated gate semiconductor device comprising:

5. When the gate insulating film is measured in a depth direction from the surface thereof by secondary ion mass spectrometry, the carbon atom concentration in the gate insulating film is 1×10 20 cm -3 The integral value of the carbon atom concentration up to the position where it is equal to or smaller than 5×10 15 cm -2 5. The method for manufacturing an insulated gate semiconductor device according to claim 4, wherein the width in the depth direction where the nitrogen atomic concentration is half the nitrogen atomic concentration at the peak position is 2 nm or less.

6. When the surface of the channel formation region at the interface after removing the gate insulating film is measured by X-ray photoelectron spectroscopy, the nitrogen atom concentration is 3×10 14 cm -2 Above 1 x 10 15 cm -2 6. The method for manufacturing an insulated gate semiconductor device according to claim 4, wherein:

7. 7. The method for manufacturing an insulated gate semiconductor device according to claim 4, wherein the boron atoms are diffused and added at a temperature of 900° C. or higher and 1200° C. or lower using a boron nitride wafer as a solid diffusion source.

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