Semiconductor elements, semiconductor devices

Abstract

To provide a semiconductor element and a semiconductor device capable of increasing the Cgc / Cge ratio.SOLUTION: It has an active trench having a gate insulating film provided along a trench of a semiconductor substrate and an active portion provided in contact with the gate insulating film and connected to a gate electrode, the active portion is divided into two portions, upper and lower, via an intermediate insulating film, and has a first insulating film covering the upper portion of the active portion from the intermediate insulating film and a second insulating film covering the lower portion of the active portion from the intermediate insulating film, and the sidewall and bottom portions of the second insulating film are thicker than the first insulating film.SELECTED DRAWING: Figure 28

Description

[Technical field]

[0001] The present disclosure relates to semiconductor devices and semiconductor devices. [Background technology]

[0002] Patent Document 1 discloses that inside the trench, the upper stage has a gate conductive part connected to the gate potential, and the lower stage has a gate split part connected to the emitter potential. Patent Document 1 also describes that the turn-on di / dt is lowered, and when compared at the same turn-on di / dt, the turn-on loss can be reduced. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2017-147431 A Summary of the Invention [Problem to be solved by the invention]

[0004] The emitter of the p-side semiconductor element whose collector is connected to the high potential side (p-side) of the power supply, and the emitter The collector of the n-side semiconductor element that is connected to the low potential side (n-side) of the power supply may be connected to the A load is connected to the connection point between the p-side semiconductor element and the n-side semiconductor element. A free wheel diode is connected to each of the p-side semiconductor elements. The freewheeling diode connected in reverse parallel to the n-side semiconductor element is called the p-side diode. The current-carrying diode is called an n-side diode.

[0005] When a return current flows through the n-side diode, if the p-side semiconductor element is turned on, A recovery current flows through the n-side diode. For example, the recovery dV / dt of the n-side diode changes depending on the collector current of the p-side semiconductor element. Specifically, the recovery dV / dt of the n-side diode during turn-on loss at low current of the p-side IGBT is larger than the recovery dV / dt at the rated current of the p-side IGBT. Here, "low current side" means that the collector current of the p-side semiconductor element is small, and "rated current side" means that the collector current of the p-side semiconductor element is large. When the collector current of the p-side semiconductor element is small, the recovery dV / dt of the n-side diode is large, whereas when the collector current of the p-side semiconductor element is large, the recovery dV / dt of the n-side diode is small.

[0006] In this way, when the recovery dV / dt of a diode has a current dependency, the following problem occurs. That is, the gate resistance of a semiconductor element may be set so that the large recovery dV / dt becomes a predetermined value. Therefore, for example, when the gate resistance is determined so that the recovery dV / dt on the low current side is 20 kV / μs, the dV / dt on the rated current side (for evaluating the turn-on loss) will be about 10 kV / μs. As a result, the switching time of the semiconductor element becomes longer, and the turn-on loss (turn-on loss) at the time of turning on increases. In other words, when the recovery dV / dt of a diode has a current dependency, the turn-on loss increases.

[0007] The inventors of the present application have found that in order to suppress the dependency of the recovery dV / dt of the freewheeling diode on the collector current of the semiconductor element, it is effective to increase the value (Cgc / Cge) obtained by dividing the capacitance between the gate electrode and collector electrode (Cgc) of the semiconductor element by the capacitance between the gate electrode and emitter electrode (Cge). More specifically, by increasing the Cgc of the semiconductor element, the increase in the recovery dV / dt at low currents can be suppressed. Furthermore, by decreasing the Cge of the semiconductor element, the recovery dV / dt at large currents (at rated currents) can be increased. By increasing the value of Cgc / Cge, the switching time can be shortened and the turn-on loss can be reduced.

[0008] The conventional technology has a two-stage gate structure in which the polysilicon inside the trench is divided into two stages, upper and lower, and specifically, has a configuration consisting of a lower active section connected to the gate electrode and an upper dummy section whose lower section is connected to the emitter electrode.Since Cgc becomes smaller and the Cgc / Cge ratio decreases, there is a problem that when the gate resistance of the semiconductor element is set so that the large recovery dV / dt is a predetermined value, the turn-on loss increases.

[0009] The present disclosure has been made to solve the problems described above, and aims to provide a semiconductor element and a semiconductor device that can increase the Cgc / Cge ratio, suppress the dependency of the recovery dV / dt of the freewheeling diode on the collector current of the semiconductor element, and reduce turn-on loss. [Means for solving the problem]

[0010] A semiconductor device according to the present disclosure includes a semiconductor substrate, an emitter electrode formed on the semiconductor substrate, a gate electrode formed on the semiconductor substrate, a drift layer of a first conductivity type formed in the semiconductor substrate, a source layer of the first conductivity type formed on an upper surface side of the semiconductor substrate, a base layer of a second conductivity type formed on the upper surface side of the semiconductor substrate, a collector electrode formed under the semiconductor substrate, a gate insulating film provided along the trench in the semiconductor substrate, and an active trench having an active portion provided in contact with the gate insulating film and connected to the gate electrode, the active portion being divided into two portions, an upper portion and a lower portion, via an intermediate insulating film, and including a first insulating film covering a portion of the active portion above the intermediate insulating film and a second insulating film covering a portion of the active portion below the intermediate insulating film, and a sidewall portion and a bottom portion of the second insulating film being thicker than the first insulating film. and a second insulating film provided in contact with the gate insulating film and covering the upper dummy portion, the second insulating film having a sidewall portion and a bottom portion which are thicker than the third insulating film and which covers the lower active portion. It is characterized by:

[0011] Other features of the present disclosure are set forth below. Effect of the Invention

[0012] According to the present disclosure, turn-on losses can be reduced by providing a trench having a dummy portion on top and an active portion on the bottom. [Brief description of the drawings]

[0013] [Figure 1] 1 is a cross-sectional view of a semiconductor element according to a first embodiment. [Diagram 2] FIG. 2 is a plan view of a semiconductor element. [Diagram 3] FIG. 11 is a cross-sectional view of a semiconductor element according to another example. [Figure 4] FIG. 2 is a plan view of a semiconductor element. [Diagram 5] FIG. 11 is a cross-sectional view of a semiconductor element according to another example. [Figure 6] FIG. 11 is a cross-sectional view of a semiconductor element according to another example. [Figure 7] FIG. 11 is a cross-sectional view of a semiconductor element according to another example. [Figure 8] FIG. 11 is a cross-sectional view of a semiconductor element according to another example. [Figure 9] FIG. 11 is a cross-sectional view of a semiconductor element according to another example. [Figure 10] FIG. 11 is a cross-sectional view of a semiconductor element according to another example. [Figure 11] FIG. 11 is a cross-sectional view of a semiconductor element according to a second embodiment. [Figure 12] FIG. 11 is a cross-sectional view of a semiconductor element according to another example. [Figure 13] FIG. 11 is a cross-sectional view of a semiconductor element according to another example. [Figure 14] FIG. 11 is a cross-sectional view of a semiconductor element according to a third embodiment. [Figure 15] FIG. 11 is a cross-sectional view of a semiconductor element according to another example. [Figure 16] FIG. 11 is a cross-sectional view of a semiconductor element according to another example. [Figure 17] FIG. 11 is a cross-sectional view of a semiconductor element according to another example. [Figure 18] FIG. 11 is a cross-sectional view of a semiconductor element according to another example. [Figure 19] FIG. 11 is a cross-sectional view of a semiconductor element according to another example. [Figure 20]FIG. 11 is a cross-sectional view of a semiconductor element according to another example. [Figure 21] FIG. 11 is a cross-sectional view of a semiconductor element according to another example. [Figure 22] FIG. 11 is a cross-sectional view of a semiconductor element according to another example. [Diagram 23] FIG. 11 is a cross-sectional view of a semiconductor element according to another example. [Figure 24A] FIG. 11 is a cross-sectional view of a semiconductor element according to a fourth embodiment. [Figure 24B] FIG. 11 is a cross-sectional view of a semiconductor element according to another example. [Figure 24C] FIG. 11 is a cross-sectional view of a semiconductor element according to another example. [Figure 24D] FIG. 11 is a cross-sectional view of a semiconductor element according to another example. [Diagram 25] FIG. 11 is a cross-sectional view of a semiconductor element according to another example. [Figure 26] FIG. 11 is a cross-sectional view of a semiconductor element according to a fifth embodiment. [Figure 27] FIG. 11 is a cross-sectional view of a semiconductor element according to another example. [Figure 28] FIG. 11 is a cross-sectional view of a semiconductor element according to another example. [Figure 29] FIG. 11 is a cross-sectional view of a semiconductor element according to another example. [Diagram 30] FIG. 13 is a cross-sectional view of a semiconductor element according to a sixth embodiment. [Diagram 31] FIG. 11 is a cross-sectional view of a semiconductor element according to another example. [Diagram 32] FIG. 11 is a cross-sectional view of a semiconductor element according to another example. [Diagram 33] FIG. 1 is a circuit diagram showing an application example of a semiconductor element. [Diagram 34] FIG. 11 is a diagram showing the relationship between collector current and recovery dV / dt. [Diagram 35] FIG. 13 is a cross-sectional view of a semiconductor element according to a seventh embodiment. [Diagram 36] FIG. 11 is a cross-sectional view of a semiconductor element according to another example. [Figure 37] FIG. 13 is a cross-sectional view of a semiconductor element according to an eighth embodiment. [Figure 38] FIG. 11 is a cross-sectional view of a semiconductor element according to another example. [Figure 39] FIG. 11 is a cross-sectional view of a semiconductor element according to another example. [Diagram 40] FIG. 2 is a diagram showing the planar shape of a lower active section. [Diagram 41] 13 is a diagram showing a planar shape of a lower active section according to another example. FIG. [Diagram 42] 13A and 13B are diagrams showing the planar shape of a lower active section according to another example. [Diagram 43] 13A and 13B are diagrams showing the planar shape of a lower active section according to another example. [Diagram 44] 13A and 13B are diagrams showing the planar shape of a lower active section according to another example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] A semiconductor element and a semiconductor device according to an embodiment will be described with reference to the drawings. The same or corresponding components are given the same reference numerals, and repeated description may be omitted. In the following description, n and p indicate the conductivity type of the semiconductor, and in this disclosure, the first conductivity type is described as n-type and the second conductivity type is described as p-type. The conductivity type can be reversed. Also, n- indicates that the impurity concentration is lower than n, and n+ indicates that the impurity concentration is higher than n. Similarly, p- indicates that the impurity concentration is lower than p, and p+ indicates that the impurity concentration is higher than p.

[0015] Embodiment 1 FIG. 1 is a cross-sectional view of a semiconductor device 100 according to a first embodiment. This semiconductor device constitutes an insulated gate bipolar transistor (hereinafter, abbreviated as IGBT). As shown in FIG. 1, the semiconductor device 100 includes an active trench A. The active trench A includes a gate insulating film 8 provided along a trench 7 in a semiconductor substrate, and an active portion 29 provided in contact with the gate insulating film 8 and connected to a gate electrode 15. The gate insulating film 8 is, for example, an oxide film. The term "trench" refers to a hole provided in a semiconductor substrate, or a structure formed in the hole.

[0016] A two-stage dummy active trench D / A is provided in the semiconductor substrate. Inside a trench 7 of the semiconductor substrate, the two-stage dummy active trench D / A has an upper stage dummy portion 13 that is not connected to a gate electrode 15 at an upper stage, and a lower stage active portion 14 that is connected to the gate electrode 15 at a lower stage. The upper stage dummy portion 13 and the lower stage active portion 14 are each covered with a gate insulating film 8, and thus are electrically isolated from each other. According to one example, the upper stage dummy portion 13 is connected to the emitter electrode 1.

[0017] FIG. 2 is a plan view of the semiconductor device 100 at a depth including the p-type base layer 5 shown by the line AA in FIG. 1. FIG. 2 shows a termination region 24 and a peripheral region 25, which are not shown in FIG. 1. As shown in FIG. 2, when viewed in a planar manner, an active trench A and a two-stage dummy active trench D / A are provided in a stripe shape. The two-stage dummy active trench D / A and the active trench A are formed in a cell region 23, which is a region in which the base layer 5 is formed in a planar manner. According to another example, the planar arrangement of the two-stage dummy active trenches D / A can be an intersecting mesh shape or a dot-like island shape, instead of a straight line such as a stripe shape.

[0018] When the semiconductor element 100 is viewed in plan, a gate pad may be provided in a part of the cell region 23. The gate pad is a pad that is connected to a gate electrode formed on a semiconductor substrate.

[0019] 1, n+ type source layers 4 are provided on both sides of the active trench A in the width direction in contact with the gate insulating film 8. The p+ type contact layer 3 is provided between adjacent trenches 7. The n+ type source layers 4 and the p+ type contact layers 3 may be arranged alternately along the extension direction of the active trench A.

[0020] As shown in FIG. 1, the semiconductor element has an n-type drift layer 9. In FIG. 1, the semiconductor substrate ranges from the n+ type source layer 4 and the p+ type contact layer 3 to the p type collector layer 11. In FIG. 1, the upper end of the n+ type source layer 4 and the p+ type contact layer 3 on the paper surface is called the first main surface of the semiconductor substrate, and the lower end of the p type collector layer 11 on the paper surface is called the second main surface of the semiconductor substrate. The first main surface of the semiconductor substrate is the main surface on the front surface side of the semiconductor element 100, and the second main surface of the semiconductor substrate is the main surface on the back surface side of the semiconductor element 100. The semiconductor element 100 has an n-type drift layer 9 between the first main surface and the second main surface facing the first main surface in the IGBT region which is the cell region.

[0021] As shown in FIG. 1, in the IGBT region, an n-type carrier accumulation layer 6 having a higher n-type impurity concentration than the n-type drift layer 9 is provided on the first main surface side of the n-type drift layer 9. The first conductive type carrier accumulation layer 6 is provided between the base layer 5 and the drift layer 9. The n-type carrier accumulation layer 6 has a lower first conductive type impurity concentration than the source layer 4 and a higher first conductive type impurity concentration than the drift layer 9. By providing the n-type carrier accumulation layer 6, it is possible to reduce the current loss when a current flows. The n-type carrier accumulation layer 6 and the n-type drift layer 9 may be collectively referred to as a drift layer. Note that the semiconductor device 100 may have a configuration in which the n-type carrier accumulation layer 6 is not provided and the n-type drift layer 9 is also provided in the region of the n-type carrier accumulation layer 6 shown in FIG. 1.

[0022] The n-type carrier accumulation layer 6 is formed by ion-implanting n-type impurities into the semiconductor substrate constituting the n-type drift layer 9, and then diffusing the implanted n-type impurities into the semiconductor substrate that is the n-type drift layer 9 by annealing.

[0023] A p-type base layer 5 is provided on the first main surface side of the n-type carrier accumulation layer 6. The p-type base layer 5 is in contact with the gate insulating film 8 of the active trench A. An n+ type source layer 4 is provided on the first main surface side of the p-type base layer 5 in contact with the gate insulating film 8 of the active trench A, and a p+ type contact layer 3 is provided in the remaining region. The upper ends of the n+ type source layer 4 and the p+ type contact layer 3 form the first main surface of the semiconductor substrate. The p+ type contact layer 3 is a region having a higher concentration of p-type impurities than the p-type base layer 5, and when it is necessary to distinguish between the p+ type contact layer 3 and the p-type base layer 5, they may be referred to individually. The p+ type contact layer 3 and the p-type base layer 5 may be collectively referred to as a p-type base layer.

[0024] The semiconductor device 100 also includes an n-type buffer layer 10 having a higher concentration of n-type impurities than the n-type drift layer 9 on the second main surface side of the n-type drift layer 9. The n-type buffer layer 10 is provided to suppress punch-through of a depletion layer extending from the p-type base layer 5 to the second main surface side when the semiconductor device 100 is in an off state. The n-type buffer layer 10 may be formed by implanting, for example, phosphorus (P) or protons (H+), or may be formed by implanting both phosphorus (P) and protons (H+). The semiconductor device 100 may have a configuration in which the n-type buffer layer 10 is not provided, and the n-type drift layer 9 is also provided in the region of the n-type buffer layer 10 shown in FIG. 1. The n-type buffer layer 10 and the n-type drift layer 9 may be collectively referred to as a drift layer.

[0025] In the semiconductor device 100, a p-type collector layer 11 is provided on the second major surface side of the n-type buffer layer 10. That is, the p-type collector layer 11 is provided between the n- type drift layer 9 and the second major surface.

[0026] 1, in the semiconductor device 100, a trench 7 is formed which penetrates the p-type base layer 5 from the first main surface of the semiconductor substrate and reaches the n- type drift layer 9. An active portion 29 is provided in the trench 7 via a gate insulating film 8 to form an active trench A. The gate insulating film 8 of the active trench A is in contact with the p-type base layer 5 and the n+ type source layer 4. When a gate drive voltage is applied to the active portion 29, a channel is formed in the p-type base layer 5 which is in contact with the gate insulating film 8 of the active trench A.

[0027] Another trench 7 is provided to provide a two-stage dummy active trench D / A. The two-stage dummy active trench D / A is configured by providing an upper dummy portion 13 and a lower active portion 14 with a gate insulating film 8 interposed therebetween. The lower active portion 14 faces the n-type drift layer 9 with the gate insulating film 8 interposed therebetween. The upper dummy portion 13 faces the p-type base layer 5 with the gate insulating film 8 interposed therebetween. As shown in FIG. 1, an interlayer insulating film 2 is provided on an active portion 29 of the active trench A. An emitter electrode 1 is formed on a region of the first main surface of the semiconductor substrate where the interlayer insulating film 2 is not provided, and on the interlayer insulating film 2. 1, the upper end of the lower active section 14 is lower than the lower end of the base layer 5. That is, the upper end of the lower active section 14 does not reach the base layer 5. If the lower active section 14 is located within the base layer 5, holes injected into the p-type base layer 5 at the time of turn-on fluctuate the potential of the base layer 5, causing a displacement current to flow from the base layer 5 into the lower active section 14, deteriorating dV / dt controllability. Therefore, by making the upper end of the lower active section 14 not reach the base layer 5 as in the above example, the inflow of the displacement current into the lower active section 14 can be suppressed. 1, the longitudinal length of the lower active section 14 in the carrier accumulation layer 6 is shorter than the longitudinal length of the lower active section 14 in the drift layer 9. That is, the length of the lower active section 14 in the drift layer 9 is longer than the length of the lower active section 14 in the carrier accumulation layer 6. If the carrier accumulation layer 6 is made too deep, the electric field below the carrier accumulation layer 6 is strengthened and the breakdown voltage is reduced, so there is a limit to how much the lower active section 14 can be extended in the carrier accumulation layer 6. For this reason, by extending the length of the lower active section 14 in the drift layer 9, it is possible to increase Cgc with less adverse effects of a decrease in the breakdown voltage.

[0028] As shown in Figure 1, the emitter electrode 1 is in ohmic contact with the n+ type source layer 4, the p+ type contact layer 3, and the upper dummy portion 13, and is electrically connected to the n+ type source layer 4, the p+ type contact layer 3, and the upper dummy portion 13.

[0029] 1, the interlayer insulating film 2 is provided on the upper dummy portion 13, but the emitter electrode 1 may be formed directly on the upper dummy portion 13 without providing the interlayer insulating film 2. When the interlayer insulating film 2 is formed on the upper dummy portion 13 of the two-stage dummy active trench D / A as in FIG. 1, the emitter electrode 1 and the upper dummy portion 13 may be electrically connected in another cross section.

[0030] According to one example, the emitter electrode 1 can be made of an aluminum alloy such as an aluminum silicon alloy (Al-Si alloy). According to another example, the emitter electrode 1 can be an electrode made of a multi-layer metal film formed by electroless plating or electrolytic plating on an electrode made of an aluminum alloy. The plating film formed by electroless plating or electrolytic plating can be, for example, a nickel (Ni) plating film. In addition, when there is a fine region such as between adjacent interlayer insulating films 2 where the emitter electrode 1 cannot be satisfactorily embedded, tungsten, which has better embeddability than the emitter electrode 1, can be disposed in the fine region, and the emitter electrode 1 can be provided on the tungsten.

[0031] A barrier metal may be provided between the interlayer insulating film 2 and the emitter electrode 1. The barrier metal may be, for example, a conductor containing titanium (Ti), for example, titanium nitride, or TiSi, an alloy of titanium and silicon (Si). The barrier metal may be provided only on an n-type semiconductor layer such as the n+ type source layer 4. The barrier metal and the emitter electrode 1 may be collectively referred to as an emitter electrode.

[0032] A collector electrode 12 is provided on the second main surface side of the p-type collector layer 11. The collector electrode 12 is formed under the semiconductor substrate. Like the emitter electrode 1, the collector electrode 12 may be made of an aluminum alloy or an aluminum alloy and a plating film. The collector electrode 12 may have a different configuration from the emitter electrode 1. The collector electrode 12 is in ohmic contact with the p-type collector layer 11 and is electrically connected to the p-type collector layer 11.

[0033] (Manufacturing method) Next, an example of a method for manufacturing the semiconductor device according to the first embodiment will be described. First, a semiconductor substrate constituting the n-type drift layer 9 is prepared. For example, a so-called FZ wafer produced by the FZ (Floating Zone) method or a so-called MCZ wafer produced by the MCZ (Magnetic applied CZochralki) method may be used as the semiconductor substrate, and it may be an n-type wafer containing n-type impurities. The concentration of the n-type impurities contained in the semiconductor substrate is appropriately selected depending on the withstand voltage of the semiconductor device to be produced. For example, in a semiconductor device with a withstand voltage of 1200V, the concentration of the n-type impurities is adjusted so that the resistivity of the n-type drift layer 9 constituting the semiconductor substrate is about 40 to 120 Ω·cm. In the process of preparing the semiconductor substrate, the entire semiconductor substrate becomes the n-type drift layer 9, and p-type or n-type impurity ions are implanted from the first main surface side or the second main surface side of such a semiconductor substrate, and then diffused into the semiconductor substrate by heat treatment or the like to form a p-type or n-type semiconductor layer, and the semiconductor element 100 is produced.

[0034] 2, a region that becomes the termination region 24 is provided around the cell region 23. The following mainly describes a manufacturing method for the configuration of the cell region 23 of the semiconductor element 100, but the termination region 24 of the semiconductor element 100 may be manufactured by a known manufacturing method. For example, when forming an FLR having a p-type termination well layer 22 as a voltage-resistance holding structure in the termination region 24, it may be formed by implanting p-type impurity ions before processing the cell region 23 of the semiconductor element 100, or it may be formed by implanting p-type impurity ions at the same time as implanting p-type impurity ions into the cell region 23 of the semiconductor element 100.

[0035] Next, an n-type impurity such as phosphorus (P) is injected from the first main surface side of the semiconductor substrate to form an n-type carrier accumulation layer 6. Also, a p-type impurity such as boron (B) is injected from the first main surface side of the semiconductor substrate to form a p-type base layer 5. The n-type carrier accumulation layer 6 and the p-type base layer 5 are formed by injecting impurity ions into the semiconductor substrate and then diffusing the impurity ions by heat treatment. The n-type impurity and the p-type impurity are selectively formed on the first main surface side of the semiconductor substrate because they are ion-injected after a mask process is performed on the first main surface of the semiconductor substrate. The n-type carrier accumulation layer 6 and the p-type base layer 5 are formed in the cell region 23 and connected to the p-type termination well layer 22 in the termination region 24. The mask process refers to a process of applying a resist onto the semiconductor substrate, forming an opening in a predetermined region of the resist using photolithography, and forming a mask on the semiconductor substrate in order to perform ion implantation or etching on a predetermined region of the semiconductor substrate through the opening.

[0036] Next, an n-type impurity is selectively injected into the first main surface side of the p-type base layer 5 in the cell region 23 by mask processing to form the n+ type source layer 4. The n-type impurity to be injected may be, for example, arsenic (As) or phosphorus (P).

[0037] Next, trenches 7 are formed so as to penetrate the p-type base layer 5 and the carrier accumulation layer 6 from the first main surface side of the semiconductor substrate and reach the n- type drift layer 9. In the cell region 23, the side walls of the trenches 7 penetrating the n+ type source layer 4 form part of the n+ type source layer 4. The trenches 7 can be formed by depositing an oxide film such as SiO2 on the semiconductor substrate, then forming openings in the oxide film by mask processing in the portions where the trenches 7 will be formed, and etching the semiconductor substrate using the oxide film with the openings formed therein as a mask.

[0038] Next, the semiconductor substrate is heated in an atmosphere containing oxygen, for example, to form a gate insulating film 8 on the inner wall of the trench 7 and on the first main surface of the semiconductor substrate. The gate insulating film 8 formed on the first main surface of the semiconductor substrate is removed in a later process.

[0039] Next, within the trench 7 having the gate insulating film 8 formed on the inner wall thereof, polysilicon doped with n-type or p-type impurities is deposited by CVD (chemical vapor deposition) or the like.

[0040] Next, a mask having an opening in the two-stage dummy active trench D / A portion is formed by mask processing, and the polysilicon in the two-stage dummy active trench D / A is etched to a desired depth to form the lower stage active portion 14.

[0041] Next, the semiconductor substrate is heated in an atmosphere containing oxygen, for example, to form a gate insulating film 8 on the inner walls of the two-stage dummy active trench D / A and on the upper part of the lower active portion 14, and then polysilicon doped with n-type or p-type impurities is deposited by CVD or the like to form the upper dummy portion 13.

[0042] Next, an interlayer insulating film 2 is formed on the active trench A and the two-stage dummy active trench D / A in the cell region 23, and then the gate insulating film formed on the first main surface of the semiconductor substrate is removed. The interlayer insulating film 2 may be, for example, SiO2. Then, contact holes are formed in the deposited interlayer insulating film 2 by mask processing. The contact holes are formed on the n+ type source layer 4 and the p+ type contact layer 3.

[0043] Next, the emitter electrode 1 on the first main surface of the semiconductor substrate and the interlayer insulating film 2 may be formed by depositing an aluminum silicon alloy (Al-Si alloy) by PVD such as sputtering or vapor deposition. Also, a nickel alloy (Ni alloy) may be further formed on the formed aluminum silicon alloy by electroless plating or electrolytic plating to form the emitter electrode 1. When the emitter electrode 1 is formed by plating, a thick metal film can be easily formed as the emitter electrode 1, so that the heat capacity of the emitter electrode 1 can be increased and the heat resistance can be improved. Note that, when a nickel alloy is further formed by plating after forming the emitter electrode 1 made of an aluminum silicon alloy by PVD, the plating process for forming the nickel alloy may be performed after processing the second main surface side of the semiconductor substrate.

[0044] Next, the second main surface side of the semiconductor substrate is ground to thin the semiconductor substrate to a predetermined designed thickness. The thickness of the semiconductor substrate after grinding may be, for example, 80 μm to 200 μm.

[0045] Next, n-type impurities are implanted from the second main surface side of the semiconductor substrate to form an n-type buffer layer 10. Furthermore, p-type impurities are implanted from the second main surface side of the semiconductor substrate to form a p-type collector layer 11. The n-type buffer layer 10 may be formed by implanting, for example, phosphorus (P) ions. Alternatively, it may be formed by implanting protons (H+). Alternatively, it may be formed by implanting both protons and phosphorus. Protons can be implanted to a deep position from the second main surface of the semiconductor substrate with a relatively low acceleration energy. Also, by changing the acceleration energy, the depth to which the protons are implanted can be changed relatively easily. Therefore, when forming the n-type buffer layer 10 with protons, if the protons are implanted multiple times while changing the acceleration energy, an n-type buffer layer 10 that is wider in the thickness direction of the semiconductor substrate than that formed with phosphorus can be formed. Also, phosphorus can have a higher activation rate as an n-type impurity compared to protons, so that by forming the n-type buffer layer 10 with phosphorus, punch-through of the depletion layer can be more reliably suppressed even in a thin semiconductor substrate. In order to further thin the semiconductor substrate, it is preferable to form the n-type buffer layer 10 by implanting both protons and phosphorus, and in this case, the protons are implanted deeper from the second main surface than the phosphorus.

[0046] The p-type collector layer 11 may be formed by, for example, implanting boron (B). After ion implantation from the second main surface side of the semiconductor substrate, the second main surface is irradiated with a laser for laser annealing, whereby the implanted boron is activated to form the p-type collector layer 11. At this time, phosphorus for the n-type buffer layer 10 implanted at a position relatively shallow from the second main surface of the semiconductor substrate is also activated at the same time. On the other hand, since protons are activated at a relatively low annealing temperature of 380°C to 420°C, care must be taken not to raise the temperature of the entire semiconductor substrate to a temperature higher than 380°C to 420°C after the protons are implanted, except for the step for activating the protons. Since laser annealing can raise the temperature only near the second main surface of the semiconductor substrate, it can be used to activate n-type impurities or p-type impurities even after the protons are implanted.

[0047] Next, a collector electrode 12 is formed on the second main surface of the semiconductor substrate. The collector electrode 12 may be formed by depositing an aluminum silicon alloy (Ai-Si alloy) or titanium (Ti) by PVD such as sputtering or vapor deposition, or may be formed by laminating a plurality of metals such as an aluminum silicon alloy, titanium, nickel, or gold. Furthermore, the collector electrode 12 may be formed by forming a further metal film by electroless plating or electrolytic plating on a metal film formed by PVD.

[0048] The above-mentioned steps are used to manufacture the semiconductor element 100. Since a plurality of semiconductor elements 100 are manufactured in a matrix on a single n-type wafer, the semiconductor elements 100 are completed by cutting the wafer into individual semiconductor elements 100 by laser dicing or blade dicing.

[0049] (operation) The inventors of the present application have found that in order to suppress the dependency of the recovery dV / dt of the freewheeling diode on the collector current of the semiconductor element, it is effective to increase the value (Cgc / Cge) obtained by dividing the gate electrode-collector electrode capacitance (Cgc) of the semiconductor element by the gate electrode-emitter electrode capacitance (Cge). More specifically, by increasing the Cgc of the semiconductor element, the increase in the recovery dV / dt at low current can be suppressed. Furthermore, by decreasing the Cge of the semiconductor element, the recovery dV / dt at high current (at rated current) can be increased. By increasing the value of Cgc / Cge, the switching time can be shortened and the turn-on loss can be reduced. The semiconductor element according to the first embodiment is manufactured based on this finding.

[0050] First, a brief description will be given of the locations where Cgc and Cge occur in the active trench A. The location where Cgc occurs is the region where the active trench A contacts the p-type base layer 5 connected to the emitter electrode 1. The location where Cge occurs is the region where the active trench A contacts the n-type drift layer 9 and the n-type carrier accumulation layer 6.

[0051] In other words, in order to increase only Cgc without increasing Cge, it is sufficient to increase only the area of ​​active trench A that contacts n-type drift layer 9 without increasing the area of ​​active trench A that contacts p-type base layer 5 connected to emitter electrode 1.

[0052] Next, the case of the two-stage dummy active trench D / A will be described. The upper dummy portion 13, which is a region of the two-stage dummy active trench D / A that contacts the p-type base layer 5, is connected to the emitter electrode 1, so Cge is not generated. The lower active portion 14, which is a region that contacts the n-type drift layer 9, is connected to the gate electrode 15, so Cgc is generated. For example, making the longitudinal length of the lower active portion 14 longer than the longitudinal length of the upper dummy portion 13 contributes to increasing Cgc.

[0053] In the first embodiment, since the two-stage dummy active trench D / A is adopted, Cgc can be increased compared to a semiconductor element without the two-stage dummy active trench D / A. Therefore, the Cgc / Cge ratio can be increased. Therefore, it is possible to suppress the recovery dV / dt of the freewheeling diode from depending on the collector current of the semiconductor element.

[0054] (Variation 1) In the first embodiment, the two-stage dummy active trench D / A is formed in the cell region 23, but the two-stage dummy active trench D / A may be formed outside the cell region 23. FIG. 3 is a cross-sectional view of a semiconductor element according to a modified example. The two-stage dummy active trench D / A shown in FIG. 3 may be formed outside the cell region 23. FIG. 4 is a plan view showing an example of the arrangement of the two-stage dummy active trench D / A. FIG. 4 shows that the two-stage dummy active trench D / A is formed in the termination region 24 and the outer peripheral region 25. The termination region 24 is a region that surrounds the cell region 23 in a plan view. The outer peripheral region 25 is a region that surrounds the termination region 24. The two-stage dummy active trench D / A may be formed in the gate pad region in the cell region 23. The two-stage dummy active trench D / A in FIG. 4 is rectangular, but it may be formed in a stripe shape of a straight line pattern, a mesh shape of a crossing pattern, or an island shape of a dot pattern.

[0055] A unique effect of this modified example is that since the two-stage dummy active trenches D / A are not arranged in the cell region 23, the density of the active trenches A in the cell region 23 can be increased to increase the channel density, thereby improving the current carrying capacity.

[0056] (Variation 2) As is clear from the explanation so far, in order to increase Cgc, it is effective to increase the depth of trench 7 and increase the area of ​​active trench A and two-stage dummy active trench D / A that contacts n-type drift layer 9.

[0057] 5 is a cross-sectional view of a semiconductor device according to Modification 2. The length La of the lower active section 14 in the trench depth direction is longer than the length Ld of the upper dummy section 13 in the same direction. In other words, La>Ld. Furthermore, according to one example, the longitudinal length La of the lower active section 14 is greater than the lateral width Wa of the lower active section 14, thereby realizing La>Wa.

[0058] By making the length La of the lower active portion 14 longer than the length Ld of the upper dummy portion 13, it is possible to increase Cgc generated particularly in the lower active portion 14. Further, by making the length La of the lower active portion 14 longer than the lateral width Wa of the lower active portion 14, Cgc can be efficiently increased further. This is because the bottom surface of the trench 7 has one surface in contact with the drift layer 9, while the side walls of the trench 7 have two surfaces in contact with the drift layer 9. Therefore, the increase in the area of the side walls efficiently increases Cgc. That is, increasing the aspect ratio of the lower active portion 14 can efficiently increase Cgc.

[0059] By increasing the length of the lower active portion 14, the position of the lower end of the lower active portion 14 can be separated from the n-type carrier accumulation layer 6 where electric field concentration is likely to occur or the p-type base layer 5 where punch-through is likely to occur. Thereby, the effect as a field plate for holding breakdown voltage can be enhanced.

[0060] According to another example, as shown in FIG. 6, the length La of the lower active portion 14 may be shorter than the length Lb of the upper dummy portion. In this case, La < Ld. By shortening the length La of the lower active portion 14, Cgc generated in the lower active portion 14 decreases, but the etching time for forming the trench 7 can be shortened, and the process cost can be reduced.

[0061] (Modification Example 3) In order to increase the Cgc / Cge ratio, it is also effective to reduce Cge. As is clear from the description so far, in order to reduce Cge, it is effective to reduce the area of the active trench A in contact with the p-type base layer 5.

[0062] 7 is a cross-sectional view of a semiconductor device according to Modification 3. The longitudinal length La of the lower active section of this semiconductor device is greater than the thickness Lp of the p-type base layer 5. In other words, La>Lp. By reducing the thickness Lp of the p-type base layer 5, it is possible to reduce Cge generated in the active trench A. Furthermore, by increasing the length La of the lower active section 14, it is possible to increase Cgc generated in the lower active section 14. Therefore, it is possible to further increase the Cgc / Cge ratio.

[0063] (Variation 4) 8 and 9 are cross-sectional views of a semiconductor device according to Modification 4. The upper end of the lower active section 14 is located in the base layer 5. In the example of Fig. 8, the upper end position of the lower active section 14 and the lower end position of the base layer 5 are at the same height. In the example of Fig. 9, the upper end position of the lower active section 14 is higher than the lower end position of the base layer 5.

[0064] 1, when the upper end position of the lower active section 14 is lower than the lower end position of the p-type base layer 5, a region is formed above the lower active section 14 where the lower active section 14 does not contact the n-type drift layer 9 or the n-type carrier accumulation layer 6, and Cgc is not generated in that region. In contrast, as shown in FIGS. 8 and 9, by preventing the formation of a region above the lower active section 14 where the lower active section 14 does not contact the n-type drift layer 9 or the n-type carrier accumulation layer 6, Cgc can be increased.

[0065] (Variation 5) 1, the upper end of the lower active section 14 is located below the lower end of the p-type base layer 5, but the upper end of the lower active section 14 may be located even lower. For example, the upper end of the lower active section 14 may be located lower than the concentration peak position of the n-type carrier accumulation layer 6. According to another example, as shown in FIG. 10, the upper end of the lower active section 14 may be located below the lower end of the n-type carrier accumulation layer 6.

[0066] When the device is turned on, holes injected from the back surface change the potential of the p-type base layer 5, causing a displacement current flowing from the p-type base layer 5 to the lower active unit 14 to oscillate the gate potential, deteriorating the controllability of dV / dt. This phenomenon is particularly noticeable when the p-type base layer 5 is floating and when the lower active unit 14 is close to the p-type base layer 5. Therefore, as described above, by separating the lower active unit 14 from the p-type base layer 5, adverse effects such as gate oscillation can be suppressed.

[0067] Regarding the semiconductor element and the semiconductor device according to the following embodiments, differences from the first embodiment will be mainly described.

[0068] Embodiment 2 In the semiconductor device according to the second embodiment, the material of the upper dummy part of the two-stage dummy active D / A is changed from polysilicon to another material. FIG. 11 is a cross-sectional view of the semiconductor device according to the second embodiment. This semiconductor device includes an oxide 16 as the upper dummy part. According to one example, the oxide 16 can be made of the same material as the interlayer insulating film 2. A trench including the oxide 16 and the lower active part 14 is called a two-stage oxide active trench O / A.

[0069] Fig. 12 is a cross-sectional view of a semiconductor device according to another example. In the example of Fig. 12, a metal 17 is provided as an upper-stage dummy portion. This metal 17 is made of the same material as the emitter electrode 1, and can be formed as a part of the emitter electrode 1. A trench provided with the metal 17 and the lower-stage active portion 14 is called a two-stage metal active trench M / A.

[0070] (Method of manufacturing two-stage oxide active trench O / A) First, similarly to the first embodiment, the polysilicon in the two-stage active trench is etched to a desired depth by mask processing to form the lower stage active section 14. Next, an interlayer insulating film is deposited on the active trench A and the lower stage active section 14. In this manner, the oxide 16 of the two-stage oxide film active trench O / A is formed.

[0071] (Manufacturing method for two-stage metal active trench M / A) The manufacturing method is the same as that of the two-stage oxide active trench O / A up to the formation of the lower stage active section 14. To form the two-stage metal active trench M / A, the deposition amount of the interlayer insulating film is reduced, and metal is embedded thereon to form the metal 17.

[0072] The manufacturing process of the two-stage oxide active trench O / A or the two-stage metal active trench M / A can omit the following steps required in the manufacturing process of the two-stage dummy active trench D / A. A process of forming a gate insulating film 8 on the inner walls of the two-stage dummy active trench D / A and on the upper part of the lower stage active section 14. A process of depositing polysilicon doped with n-type or p-type impurities by CVD or the like to form the upper dummy portion 13.

[0073] (Variation 1) 13 is a cross-sectional view of a semiconductor device according to Modification 1. The metal 17, which is the upper dummy portion, is in contact with the base layer 5. In other words, there is no gate insulating film between the metal 17 and the base layer 5. According to another example, the gate insulating film between the upper dummy portion 13 and the p-type base layer 5 in FIG. 1 may be eliminated, and they may be in contact with each other.

[0074] In this manner, the p-type base layer 5 may be electrically connected to the emitter electrode 1 via the upper dummy portion 13 or the metal 17. The p-type base layer 5 may also be in ohmic contact or Schottky contact with the upper dummy portion 13 or the metal 17. This allows holes to be discharged from the p-type base layer 5 to the emitter electrode 1 via the upper dummy portion 13 or the metal 17 at the time of turn-off, thereby reducing the number of holes below the source layer 4 that may cause latch-up breakdown. This improves the latch-up breakdown resistance.

[0075] Embodiment 3 In this embodiment, a reduction in the coupling capacitance Cge occurring between adjacent active trenches A and the upper dummy portion 13 will be described. First, the active trench A and the upper dummy portion 13 will be briefly described. The inventors have found that in the case of a trench arrangement in which the active trench A and the upper dummy portion 13 of the two-stage dummy active trench D / A are adjacent to each other as shown in FIG. 1, the upper dummy portion 13, which is the emitter potential, is arranged adjacent to the active trench A, which is the gate potential, and therefore Cge occurs as a coupling capacitance between the active trench A and the upper dummy portion 13. Note that this phenomenon has a small effect in a region in which the upper dummy portion 13 faces the p-type base layer 5 electrically connected to the emitter electrode 1, but has a large effect particularly when the upper dummy portion 13 faces the n-type drift layer 9 and the n-type carrier accumulation layer 6. The semiconductor device according to the third embodiment is manufactured based on this knowledge.

[0076] 14 is a cross-sectional view of a semiconductor device according to a third embodiment. In this example, a first structure in which two or more active trenches A are arranged side by side and a second structure in which two or more two-stage dummy active trenches D / A are arranged side by side are alternately provided. By bundling and arranging the active trenches A together and bundling and arranging the two-stage dummy active trenches D / A together, the density at which the active trenches A and the two-stage dummy active trenches D / A are adjacent to each other is reduced compared to the case in which one active trench A and one two-stage dummy active trench D / A are alternately provided.

[0077] This makes it possible to reduce the coupling capacitance Cge between the active trench A and the two-stage dummy active trench D / A while maintaining Cgc. As a more preferred example, a first structure in which three or more active trenches A are arranged and a second structure in which three or more two-stage dummy active trenches D / A are arranged can be provided alternately. In this way, an active trench A that is not adjacent to a two-stage dummy active trench D / A is formed, and therefore Cge in particular can be reduced.

[0078] 15 is a cross-sectional view of a semiconductor device according to another example. In this example, the number of two-stage dummy active trenches D / A is greater than the number of active trenches A. The greater the number of two-stage dummy active trenches D / A, the higher the Cge generation rate becomes, and the greater the Cge reduction effect due to the continuous arrangement described above becomes.

[0079] (Variation 1) 16 is a cross-sectional view of a semiconductor element according to Modification 1. This semiconductor element includes a dummy trench D. The dummy trench D is electrically connected to the emitter electrode 1. The gate capacitance can be adjusted by changing the ratio of the dummy trench D to the entire trench. However, a coupling capacitance Cge occurs between the dummy trench D and the lower active section 14.

[0080] (Variation 2) 17 is a cross-sectional view of a semiconductor device according to Modification 2. This semiconductor device includes a first structure in which one or more active trenches are arranged, a second structure in which two or more two-stage dummy active trenches D / A are arranged, and a third structure in which one or more dummy trenches are arranged. The second structure is sandwiched between two third structures.

[0081] By arranging the two-stage dummy active trenches D / A continuously in this manner, it is possible to reduce Cge generated between the lower active section 14 and the dummy trench D. Therefore, it is possible to increase the Cgc / Cge ratio. However, Cge is generated between the dummy trench D and the lower active section 14 as a coupling capacitance.

[0082] (Variation 3) 18 is a cross-sectional view of a semiconductor device according to Modification 3. This semiconductor device includes a first structure in which one or more active trenches A are arranged, a second structure in which one or more two-stage dummy active trenches D / A are arranged, and a third structure in which one or more dummy trenches are arranged. The second structure is sandwiched between the first structure and the third structure.

[0083] By continuously arranging the active trench A and the two-stage dummy active trench D / A and continuously arranging the dummy trenches D, it is possible to reduce Cge generated between the lower stage active section 14 and the dummy trench D and Cge generated between the active trench A and the dummy trench D. This makes it possible to further increase the Cgc / Cge ratio.

[0084] (Variation 4) 19 is a cross-sectional view of a semiconductor device according to Modification 4. The upper dummy portion 13f is not connected to the emitter electrode 1 and is at a floating potential. A trench having the upper dummy portion 13 and the lower active portion 14 is called a two-stage floating active trench F / A.

[0085] By providing the upper dummy portion 13f at a floating potential, it is possible to reduce Cge generated between the active trench A and the upper dummy portion 13 of the two-stage dummy active trench D / A. Therefore, it is possible to further increase the Cgc / Cge ratio.

[0086] (Variation 5) Fig. 20 is a cross-sectional view of a semiconductor device according to Modification 5. This semiconductor device has, as a two-stage dummy active trench, a first trench in which the upper stage dummy portion 13 is connected to the emitter electrode 1, and a second trench in which the upper stage dummy portion 13f is at a floating potential. The two-stage dummy active trench D / A in Fig. 20 is the first trench, and the two-stage floating active trench F / A is the second trench. The second trench is sandwiched between the first trench and the active trench A.

[0087] 21 shows a semiconductor device in which the two-stage dummy active trench D / A in FIG. 20 is replaced with a dummy trench D. In this case, the two-stage floating active trench F / A is sandwiched between the dummy trench D and the active trench A.

[0088] 20, it is possible to reduce Cge generated between the active trench A and the upper dummy portion 13 of the two-stage dummy active trench D / A. According to the configuration of FIG. 21, it is possible to reduce Cge generated between the active trench A and the dummy trench D. Therefore, in either configuration, it is possible to further increase the Cgc / Cge ratio.

[0089] (Variation 6) Fig. 22 is a cross-sectional view of a semiconductor device according to Modification 6. In this semiconductor device, the distance between a first structure in which two or more two-stage dummy active trenches D / A are arranged and a second structure in which two or more active trenches A are arranged is greater than the distance between two two-stage dummy active trenches D / A and is greater than the distance between two active trenches A. Fig. 22 shows that the interval Lpad / a between the active trench A and the two-stage dummy active trench D / A is greater than the interval Lpa between the active trench A and another active trench A and is greater than the interval Lpd / a between the two-stage dummy active trench D / A and another two-stage dummy active trench D / A. In other words, Lpad / a>Lpa, Lpd / a.

[0090] In this way, by increasing the distance between the active trench A and the two-stage dummy active trench D / A, the coupling capacitance Cge generated in the upper dummy portion 13 between the active trench A and the two-stage dummy active trench D / A is reduced. Therefore, the Cgc / Cge ratio can be further increased.

[0091] (Variation 7) 23 is a cross-sectional view of a semiconductor element according to Modification 7. This semiconductor element includes a first structure in which two or more active trenches A are arranged side by side, a second structure adjacent to the first structure in which two or more two-stage dummy active trenches D / A are arranged side by side, and a dummy trench D adjacent to the second structure. The distance between the second structure and the dummy trench D is greater than the distance between the two active trenches A, the distance between the first structure and the second structure, or the distance between the two two-stage dummy active trenches D / A.

[0092] 23 shows that the interval Lpd / ad between the two-stage dummy active trench D / A and the dummy trench D is larger than the interval Lpa between the active trench A and another active trench A, and the interval Lpd / a between the two-stage dummy active trench D / A and another two-stage dummy active trench D / A. In other words, Lpd / ad>Lpa, Lpd / a.

[0093] In this way, by increasing the distance between the two-stage dummy active trench D / A and the dummy trench D, it becomes possible to reduce Cge, which is the coupling capacitance generated between the lower active part 14 of the two-stage dummy active trench D / A and the dummy trench D. Therefore, it is possible to further increase the Cgc / Cge ratio.

[0094] Embodiment 4 24A is a cross-sectional view of a semiconductor device according to a fourth embodiment. Two or more two-stage dummy active trenches D / A are provided adjacent to each other. A portion of the base layer 5 adjacent to the active trench A is connected to the emitter electrode 1. On the other hand, a portion of the base layer 5 sandwiched between the two two-stage dummy active trenches D / A is not connected to the emitter electrode 1. A portion of the base layer 5 sandwiched between the two two-stage dummy active trenches D / A can be set to a floating potential or electrically connected to the emitter electrode 1 in another cross section via a high-resistance resistor.

[0095] 24A can be replaced with a dummy trench D. In that case, a portion of the base layer 5 sandwiched between the two dummy trenches D or a portion sandwiched between the dummy trench D and the two-stage dummy active trench D / A is not connected to the emitter electrode 1 and can be set to a floating potential or can be electrically connected to the emitter electrode 1 via a high-resistance resistor in another cross section.

[0096] 25 is a cross-sectional view of a semiconductor element according to another example. A portion of the base layer 5 adjacent to the two active trenches A is connected to the emitter electrode 1. On the other hand, a portion of the base layer 5 adjacent to the two-stage dummy active trench D / A is not connected to the emitter electrode 1. Therefore, a portion of the base layer 5 sandwiched between the two-stage dummy active trenches D / A and a portion adjacent to both the active trench A and the two-stage dummy active trench D / A are not connected to the emitter electrode 1. A portion of the base layer 5 that is not connected to the emitter electrode 1 can be set to a floating potential or electrically connected to the emitter electrode 1 via a high-resistance resistor in another cross section.

[0097] These configurations can reduce the proportion of the p-type base layer 5 connected to the emitter electrode 1 from which holes are discharged. When holes are less likely to be discharged to the emitter electrode 1, the amount of holes stored in the drift layer 9 increases, and the on-voltage at which conductivity modulation is promoted can be reduced. Furthermore, the displacement current from the floating p-type base layer 5 flows into the upper dummy portion 13 that is not connected to the gate electrode 15, and is discharged to the emitter electrode 1. This can suppress the commonly-concerned phenomenon of a displacement current flowing from the floating p-type base layer 5 to the gate electrode via the active trench, causing the gate potential to oscillate. (Variation 1) 24B is a cross-sectional view of a semiconductor device according to Modification 1. In the base layer 5, a portion sandwiched between two two-stage dummy active trenches D / A is connected to the emitter electrode 1. (Variation 2) 24C is a cross-sectional view of a semiconductor device according to Modification 2. The base layer 5 is divided into a plurality of base portions by providing a plurality of two-stage dummy active trenches D / A. The plurality of base portions include a base portion 5a connected to the emitter electrode 1 and a base portion 5b not connected to the emitter electrode 1. (Variation 3) 24D is a cross-sectional view of a semiconductor element according to Modification 3. This semiconductor element includes at least two dummy trenches D. A portion of the base layer 5 sandwiched between the two dummy trenches D is not connected to the emitter electrode 1, and a portion of the base layer 5 sandwiched between the two two-stage dummy active trenches D / A is connected to the emitter electrode 1. In the modified example 1-3, at least a part of the base layer 5 sandwiched between two two-stage dummy active trenches D / A is connected to the emitter electrode 1. At the time of turn-off, an inversion layer is formed around the lower active part 14 of the two-stage dummy active trench D / A, which functions as a hole discharge path. By connecting the p-type base layer 5 sandwiched between the two-stage dummy active trenches D / A to the emitter electrode 1, holes flowing along the lower active part 14 can be discharged and turn-off loss can be reduced. By partially floating the p-type base layer 5, carriers can be accumulated and the on-voltage can be reduced, while the grounded p-type base layer 5 discharges carriers and the turn-off loss can be reduced. Furthermore, since the effect of the hole discharge path is high at the location where the two-stage dummy active trenches D / A are present, the p-type base layer 5 between the dummy trenches D can be floated and carriers can be accumulated to reduce the on-voltage, while the p-type base layer 5 between the two-stage dummy active trenches D / A can be grounded to reduce the turn-off loss.

[0098] Embodiment 5. 26 is a cross-sectional view of a semiconductor device according to a fifth embodiment. This semiconductor device has a two-stage active trench A / A and a two-stage dummy trench D / D. The two-stage active trench A / A is an active portion divided into upper and lower two portions via an intermediate insulating film 30A. The two-stage dummy trench D / D is a dummy trench divided into upper and lower two portions via an intermediate insulating film 30A. The intermediate insulating film 30A is, for example, an oxide film, similar to the insulating film separating the upper dummy portion 13 and the lower active portion 14 of the two-stage dummy active trench D / A.

[0099] 27 is a cross-sectional view of a semiconductor device according to another example. The active portion of the two-stage active trench A / A is covered with a first insulating film 30a above the intermediate insulating film 30A, and the active portion is covered with a second insulating film 30b below the intermediate insulating film 30A. The first insulating film 30a is thicker than the second insulating film 30b.

[0100] By making the first insulating film 30a thicker than the second insulating film 30b, Cge generated in the upper active portion 18 of the two-stage active trench A / A becomes smaller, and Cgc is generated in the lower active portion 14. Therefore, the Cgc / Cge ratio can be further increased.

[0101] (Variation 1) 28 is a cross-sectional view of a semiconductor element according to Modification 1. This semiconductor element includes a first insulating film 30a that covers a portion of the active section above the intermediate insulating film 30A, and a second insulating film 30b that covers a portion of the active section below the intermediate insulating film 30A. The sidewall and bottom portions of the second insulating film 30b are thicker than the first insulating film 30a. Furthermore, this semiconductor element includes a third insulating film 31a that covers the upper dummy section 13. The sidewall and bottom portions of the insulating film that covers the lower active section 14 are thicker than the third insulating film 31a.

[0102] Thus, in the two-stage active trench A / A and the two-stage dummy active trench D / A, the thickness of the gate insulating film 8 formed on the sidewalls of the trench 7 and on the bottom of the trench 7 in the lower active section 14 is thicker than the gate oxide film covering the upper active section 18 or the upper dummy section 13.

[0103] In another example, the gate insulating film 8 on the sidewall of trench 7 in the lower active unit 14 may be made the same as or thinner than the thickness of the gate insulating film 8 in the upper active unit 18 to increase Cgc, and the gate insulating film 8 at the bottom and bottom corner parts of trench 7 in the lower active unit 14 may be made thinner than the gate insulating film 8 in the upper active unit 18 to suppress degradation of gate characteristics when an electric field is concentrated at the bottom of the trench.

[0104] By increasing the thickness of the gate insulating film 8 formed on the trench sidewalls and bottom of the lower active portion 14 of the two-stage active trench A / A, it is possible to suppress degradation of gate characteristics due to hot carrier injection into the lower active portion 14 caused by dynamic avalanche, which occurs when the electric field concentrates at the trench bottom at turn-off.

[0105] (Variation 2) 29 is a cross-sectional view of a semiconductor element according to Modification 2. This semiconductor element has a three-stage trench. Inside the trench of the semiconductor substrate, the three-stage trench has a first dummy portion 161 connected to the emitter electrode at the top stage, an active portion 14 connected to the gate electrode at the middle stage, and a second dummy portion 19 connected to the emitter electrode at the bottom stage. The first dummy portion 161, the active portion 14, and the second dummy portion 19 are insulated by, for example, polysilicon inside the trench 7.

[0106] By forming the lower stage of the three-stage trench as the second dummy stage 19 at a dummy potential, hot carriers due to dynamic avalanche are injected into the second dummy stage 19 that is not electrically connected to the gate electrode 15, rather than into the active stage 14. This makes it possible to suppress deterioration of the gate characteristics. Furthermore, since the active stage 14 is provided, the same effects as those of the first embodiment can be achieved.

[0107] Embodiment 6 Double gate drive has been proposed as a method for achieving both a reduction in on-resistance and a reduction in switching loss. Double gate drive is a technology that shortens the switching time of an IGBT and reduces switching loss by dividing the gate drive system into two systems and changing the drive timing of the two gates. Specifically, one system of gates is turned off before turning off to close the channel, thereby reducing the carriers in the drift layer before blocking. Therefore, it is possible to achieve both a reduction in on-resistance and a reduction in switching loss. In this embodiment, a semiconductor element for double gate drive is proposed.

[0108] 30 is a cross-sectional view of a semiconductor element according to embodiment 6. The gate electrode has a first gate electrode 15 and a second gate electrode 20 of a different system from the first gate electrode 15. An active section 29 is connected to the first gate electrode 15, and a lower active section 142 is connected to the second gate electrode 20.

[0109] Fig. 33 is a diagram showing a configuration example of a three-phase inverter circuit. This inverter circuit includes p-side semiconductor elements T1, T3, and T5, and n-side semiconductor elements T2, T4, and T6. According to one example, the semiconductor element in Fig. 30 can be provided as any one of the p-side semiconductor elements T1, T3, and T5 and the n-side semiconductor elements T2, T4, and T6.

[0110] According to one example, when the semiconductor element is transitioned from the on state to the off state, a voltage equal to or lower than the threshold voltage (off) is applied to the second gate electrode 20, and then a voltage equal to or lower than the threshold voltage is applied to the first gate electrode 15. This makes it possible to reduce Cgc by the amount of Cgc of the lower active section 142 before turn-off, so that the Cgc at the time of turn-off when a voltage equal to or lower than the threshold voltage is applied to the gate electrode 15 is only the Cgc parasitic to the active trench A. This shortens the switching time, thereby reducing turn-off loss.

[0111] In addition, by simultaneously applying (turning on) a voltage equal to or higher than the threshold voltage to the first gate electrode 15 and the second gate electrode 20 at the time of turning on, switching can be performed without reducing Cgc at the time of turning on, thereby achieving the same object and effect as described in the first embodiment.

[0112] (Variation 1) 31 is a cross-sectional view of a semiconductor element according to Modification 1. The gate electrodes include a first gate electrode 15 and a second gate electrode 20 that is separate from the first gate electrode 15. The active trench A includes a first active trench A1 and a second active trench A2. The active portion of the first active trench A1 is connected to the first gate electrode 15, and the active portion of the second active trench A2 and the lower active portion 142 are connected to the second gate electrode 20.

[0113] Fig. 32 is a cross-sectional view of a semiconductor element according to another example. A portion of the active part of the active trench A above the intermediate insulating film is connected to the first gate electrode 15, and a portion of the active part below the intermediate insulating film is connected to the second gate electrode 20. As for the active part of the active trench A2, both the portion above the intermediate insulating film and the portion below the intermediate insulating film are connected to the second gate electrode 20. According to the configuration of Fig. 32, the functions of the channel forming portion of the upper active part and the Cgc portion of the lower active part 14 can be separated, and each can be switched at an optimal timing.

[0114] By turning off the second gate electrode 20 before turning off the semiconductor element, Cgc of the lower active section 142 can be reduced. Furthermore, by connecting some of the active trenches A to the second gate electrode 20, the active trench A2 connected to the second gate electrode or the lower active section 142 can close the channel of the active section connected to the first gate electrode before turning off. This can reduce carriers in the drift layer 9, thereby reducing turn-off loss.

[0115] (Variation 2) In the sixth embodiment, the operation of the second gate electrode 20 at the time of turning on is not particularly limited, but only at the time of turning on with a low current, a voltage equal to or higher than the threshold voltage may be applied (turned on) to the second gate electrode 20. According to one example, only when the current value becomes 20% or less of the rated current, the second gate electrode 20 may be turned on at the time of turning on.

[0116] 33 shows first semiconductor elements T1, T3, and T5 whose collectors are connected to the high potential side of a power supply, and second semiconductor elements T2, T4, and T6 whose emitters are connected to the low potential side of a power supply and whose collectors are connected to the emitters of the first semiconductor elements T1, T3, and T5. The second semiconductor elements T2, T4, and T6 may be semiconductor elements shown in any one of FIGS. 30-32. According to an example, any one of the second semiconductor elements T2, T4, and T6 is controlled by a gate drive circuit 40 shown in FIGS. 31 and 32. The gate drive circuit 40 applies gate voltages to the first gate electrode 15 and the second gate electrode 20 in separate systems. The gate drive circuit applies a voltage equal to or greater than the threshold to the first gate electrode 15 when the collector current of the first semiconductor element is greater than a predetermined value, but does not apply a voltage equal to or greater than the threshold to the second gate electrode 20, and applies a voltage equal to or greater than the threshold to the first gate electrode 15 and the second gate electrode 20 when the collector current of the first semiconductor element is smaller than a predetermined value. The "predetermined value" of the collector current is a value at low current, and at low current, the recovery dV / dt of the diode is greater than the recovery dV / dt at rated current. This is shown in FIG. 34, for example. Since it is necessary to increase Cgc to reduce the recovery dV / dt at low current, a voltage equal to or greater than the threshold is applied to the first gate electrode 15 and the second gate electrode 20, and since dV / dt is originally small at rated current, it is not necessary to increase Cgc, and a voltage equal to or greater than the threshold is applied to the first gate electrode 15 while a voltage equal to or greater than the threshold is not applied to the second gate electrode 20.

[0117] By controlling in this way, when turning on at a low current, the second gate electrode 20 is turned on, so Cgc is increased and dV / dt at the low current can be reduced. Since the second gate electrode 20 is not turned on at the rated current, Cgc is reduced, the switching time is shortened, and dV / dt can be increased. As a result, the current dependency of dV / dt can be reduced.

[0118] Embodiment 7 35 is a cross-sectional view of a semiconductor device according to a seventh embodiment. This semiconductor device is a reverse conducting IGBT (RC-IGBT) having the above-mentioned technical features. This semiconductor device includes an IGBT region having a p-type collector layer 11 on the left side, and a diode region having an n-type cathode layer 21 on the right side. According to one example, a plurality of two-stage dummy active trenches D / As are provided, and more of them are provided in the diode region than in the IGBT region.

[0119] By making the ratio of the two-stage dummy active trench D / A arranged in the IGBT region smaller than the two-stage dummy active trench D / A arranged in the diode region, it is possible to increase the active trench A density in the IGBT region and increase the channel density, thereby improving the current carrying capacity.

[0120] (Variation 1) Fig. 36 is a cross-sectional view of a semiconductor element according to Modification 1. The semiconductor element in Fig. 36 has an IGBT region and a diode region to configure an RC-IGBT. A plurality of two-stage dummy active trenches D / A are provided in the diode region. A plurality of two-stage active dummy trenches A / D are provided in the IGBT region. Inside the trench of the semiconductor substrate, the two-stage active dummy trench A / D has an upper stage active portion 18 connected to the gate electrode in the upper stage, and a lower stage dummy portion 39 not connected to the gate electrode and covered with a gate insulating film 8 which is an insulating film in the lower stage.

[0121] Dynamic avalanche at turn-off causes hot carrier injection into the gate oxide film at the bottom of the trench in the IGBT region, degrading gate characteristics. By configuring the trench in the IGBT region as a two-stage active dummy trench A / D, the lower stage becomes a dummy, so gate characteristics do not deteriorate even if hot carriers are injected by dynamic avalanche. Furthermore, Cgc, which is used to reduce turn-on loss, is increased by the two-stage dummy active trench D / A provided in the diode region. This makes it possible to both suppress degradation of gate characteristics due to dynamic avalanche and reduce turn-on loss.

[0122] Embodiment 8 Fig. 37 is a cross-sectional view of a semiconductor device according to an eighth embodiment. Two or more two-stage dummy active trenches D / A are provided side by side, and the distance between the two two-stage dummy active trenches D / A is smaller than the distance between the active trench and the trench adjacent to the active trench. Although the two-stage dummy active trench D / A is illustrated in Fig. 37 as the "trench adjacent to the active trench", the "trench adjacent to the active trench" may be either an active trench or a dummy trench.

[0123] In this way, in the semiconductor device according to the eighth embodiment, when viewed at the same cell pitch, the density of the two-stage dummy active trenches D / A is high, and therefore the surface area of ​​the lower active parts 14 of the two-stage dummy active trenches D / A facing the drift layer 9 increases. As a result, Cgc can be increased.

[0124] (Variation 1) FIG. 38 is a cross-sectional view of a semiconductor element of a semiconductor element according to Modification 1. The width of the two-stage dummy active trench D / A is smaller than the width of the active trench A. According to another example, the width of the two-stage dummy active trench D / A is smaller than the width of the dummy trench. According to one example, as is clear from FIG. 38, the pitch between adjacent two-stage dummy active trenches D / A is shorter than the pitch between the active trench A and the two-stage dummy active trench D / A. In this way, by reducing the width of the two-stage dummy active trench D / A, the density of the two-stage dummy active trench D / A can be increased when viewed at the same cell pitch. Therefore, the surface area of ​​the two-stage dummy active trench D / A is increased, and Cgc can be increased.

[0125] (Variation 2) Fig. 39-41 are diagrams showing a semiconductor device according to Modification 2. Fig. 39 is a cross-sectional view, and Fig. 40 is a cross-sectional view taken along line zz in Fig. 39. The two-stage dummy active trench D / A has a branched shape in plan view. Fig. 40 shows that the two-stage dummy active trench D / A is branched into three parts in plan view.

[0126] FIG. 41 is a plan view of a two-stage dummy active trench D / A according to another example. FIG. 41 corresponds to a cross-sectional view taken along the line zz in FIG. 39. In the example of FIG. 41, the two-stage dummy active trench D / A has a portion that is substantially constant in width and formed in a ring shape in a plan view. The drift layer 9 is located at a position surrounded by the ring-shaped portion of the two-stage dummy active trench D / A. In other words, the two-stage dummy active trench D / A has a substantially constant width overall, but has a branched portion formed by narrowing a portion. According to one example, the narrowed portion can be provided in the center of the two-stage dummy active trench D / A.

[0127] According to the configuration described with reference to Figures 39-41, by branching a part of the two-stage dummy active trench D / A, the surface area of ​​the two-stage dummy active trench D / A can be increased. Therefore, Cgc can be increased.

[0128] (Variation 3) Fig. 42 is a diagram showing a semiconductor device according to Modification 3. The two-stage dummy active trench D / A includes a main body 14A and protruding parts 14B protruding in a direction perpendicular to the longitudinal direction of the main body 14A in a plan view. Fig. 42 shows that a plurality of protruding parts 14B are provided on the left and right sides of the main body 14A.

[0129] 43 is a plan view of a two-stage dummy active trench D / A according to another example. The two-stage dummy active trench D / A has a main body portion 14A and a recessed portion 14C recessed in a direction perpendicular to the longitudinal direction of the main body portion 14A in a plan view.

[0130] In this way, by providing the protruding portion 14B or the recessed portion 14C, the surface area of ​​the two-stage dummy active trench D / A can be increased compared to the case where either one of them is not provided, and therefore Cgc can be increased.

[0131] According to one example, in order to increase the surface area of ​​the two-stage dummy active trench D / A, the protrusion 14B or the recess 14C can be miniaturized. For example, as shown in FIG. 42, the width W1 of the protrusion 14B can be made smaller than the width W2 of the main body 14A in a plan view. Also, as shown in FIG. 43, the width W1 of the recess 14C can be made smaller than the width W2 of the main body 14A in a plan view. Furthermore, the interval between the multiple protrusions 14B can be made smaller than the distance between the two-stage dummy active trench D / A and the trench adjacent to the two-stage dummy active trench D / A. Similarly, the interval between the multiple recesses 14C can be made smaller than the distance between the two-stage dummy active trench D / A and the trench adjacent to the two-stage dummy active trench D / A.

[0132] (Variation 4) 44 is a diagram showing a semiconductor device according to Modification 4. The two-stage dummy active trench D / A has a plurality of bent portions 14D in plan view. According to one example, the two-stage dummy active trench D / A has a plurality of bent portions 14D in plan view and is provided parallel to the active trench A as a whole. In this way, by providing a plurality of bent portions 14D, the surface area of ​​the two-stage dummy active trench D / A increases. Therefore, Cgc can be increased.

[0133] The features described in the above embodiments can be combined. Furthermore, the techniques described in the above embodiments can be applied to a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). Furthermore, the semiconductor substrate can be formed of a wide band gap semiconductor. The wide band gap semiconductor is, for example, silicon carbide, a gallium nitride-based material, or diamond. [Explanation of symbols]

[0134] 13 upper dummy section, 14 lower active section, A active trench, D / A two-stage dummy active trench

Claims

1. A semiconductor substrate; an emitter electrode formed on the semiconductor substrate; a gate electrode formed on the semiconductor substrate; a drift layer of a first conductivity type formed in the semiconductor substrate; a first conductivity type source layer formed on an upper surface side of the semiconductor substrate; a second conductivity type base layer formed on an upper surface side of the semiconductor substrate; a collector electrode formed under the semiconductor substrate; a gate insulating film provided along the trench of the semiconductor substrate; an active trench having an active portion provided in contact with the gate insulating film and connected to the gate electrode; The active section is divided into upper and lower two sections via an intermediate insulating film, a first insulating film covering a portion of the active section above the intermediate insulating film; a second insulating film covering a portion of the active section below the intermediate insulating film; The second insulating film has a sidewall portion and a bottom portion that are thicker than the first insulating film; a two-stage dummy active trench having an upper stage dummy portion not connected to the gate electrode in an upper stage and a lower stage active portion connected to the gate electrode and covered with an insulating film in a lower stage inside the trench of the semiconductor substrate; a third insulating film provided in contact with the gate insulating film and covering the upper dummy portion; a sidewall portion and a bottom portion of the insulating film covering the lower active portion are thicker than the third insulating film.

2. 2. The semiconductor device according to claim 1, further comprising an active trench having a gate insulating film provided along the trench in the semiconductor substrate, and an active portion provided in contact with the gate insulating film and connected to the gate electrode.

3. 3. The semiconductor device according to claim 2, wherein the two-stage dummy active trench and the active trench are formed in a cell region, which is a region in which the base layer is formed in a plan view.

4. the active trench is formed in a cell region, which is a region in which the base layer is formed in a plan view; 3. The semiconductor device according to claim 2, wherein the two-stage dummy active trench is formed in a termination region that surrounds the cell region in a planar view, a peripheral region that surrounds the termination region, or a gate pad region.

5. 5. The semiconductor device according to claim 2, wherein the length in the longitudinal direction of the lower active section is longer than the length in the longitudinal direction of the upper dummy section.

6. 6. The semiconductor device according to claim 2, wherein a length of the lower active section in a longitudinal direction is greater than a thickness of the base layer.

7. 7. The semiconductor device according to claim 2, wherein an upper end of the lower active section is located within the base layer.

8. The semiconductor device according to any one of claims 2 and 4 to 6, further comprising a first conductivity type carrier accumulation layer between the base layer and the drift layer, the first conductivity type carrier accumulation layer having a lower impurity concentration of the first conductivity type than the source layer and a higher impurity concentration of the first conductivity type than the drift layer.

9. The semiconductor device of claim 8 , wherein an upper end of the lower active part is located below a lower end of the carrier accumulation layer.

10. 10. The semiconductor device according to claim 2, wherein the upper dummy portion is connected to the emitter electrode.

11. 10. The semiconductor device according to claim 2, wherein the upper dummy portion is made of an oxide or a metal.

12. 10. The semiconductor device according to claim 2, wherein the upper dummy portion is in contact with the base layer.

13. 3. The semiconductor device according to claim 2, wherein a first structure in which two or more of the active trenches are arranged side by side and a second structure in which two or more of the two-stage dummy active trenches are arranged side by side are provided alternately.

14. 3. The semiconductor device according to claim 2, wherein a first structure in which three or more of the active trenches are arranged and a second structure in which three or more of the two-stage dummy active trenches are arranged are alternately provided.

15. 15. The semiconductor device according to claim 13, wherein the number of the two-stage dummy active trenches is greater than the number of the active trenches.

16. 3. The semiconductor device according to claim 2, further comprising a dummy trench.

17. a first structure in which one or more of the active trenches are arranged, a second structure in which two or more of the two-stage dummy active trenches are arranged, and a third structure in which one or more of the dummy trenches are arranged, The semiconductor device of claim 16 , wherein the second structure is sandwiched between two of the third structures.

18. a first structure in which one or more of the active trenches are arranged, a second structure in which one or more of the two-stage dummy active trenches are arranged, and a third structure in which one or more of the dummy trenches are arranged, The semiconductor device of claim 16 , wherein the second structure is sandwiched between the first structure and the third structure.

19. 20. The semiconductor device according to claim 2, wherein the upper dummy portion is set to a floating potential.

20. the two-stage dummy active trench includes a first trench in which the upper stage dummy portion is connected to the emitter electrode, and a second trench in which the upper stage dummy portion is at a floating potential; The semiconductor device of claim 2 , wherein the second trench is sandwiched between the first trench and the active trench.

21. Equipped with a dummy trench, the upper dummy section is at a floating potential; The semiconductor device according to claim 2 , wherein the two-stage dummy active trench is sandwiched between the dummy trench and the active trench.

22. 3. The semiconductor device according to claim 2, wherein the distance between a first structure in which two or more of the two-stage dummy active trenches are arranged and a second structure in which two or more of the active trenches are arranged is greater than the distance between two of the two-stage dummy active trenches and greater than the distance between two of the active trenches.

23. a first structure in which two or more of the active trenches are arranged; a second structure adjacent to the first structure and including two or more of the two-stage dummy active trenches arranged side by side; a dummy trench adjacent to the second structure; 3. The semiconductor device of claim 2, wherein the distance between the second structure and the dummy trench is greater than the distance between two of the active trenches, the distance between the first structure and the second structure, or the distance between two of the two-stage dummy active trenches.

24. a portion of the base layer adjacent to the active trench is connected to the emitter electrode; 3. The semiconductor device according to claim 2, wherein a portion of the base layer sandwiched between two of the two-stage dummy active trenches is not connected to the emitter electrode.

25. At least one dummy trench is provided; 3. The semiconductor device according to claim 2, wherein a portion of the base layer sandwiched between two of the dummy trenches or a portion sandwiched between the dummy trench and the two-stage dummy active trench is not connected to an emitter electrode.

26. a portion of the base layer adjacent to the two active trenches is connected to the emitter electrode; 3. The semiconductor device according to claim 2, wherein a portion of the base layer adjacent to the two-stage dummy active trench is not connected to the emitter electrode.

27. the gate electrode includes a first gate electrode and a second gate electrode of a different system from the first gate electrode, 3. The semiconductor device of claim 2, wherein the active section is connected to the first gate electrode, and the lower active section is connected to the second gate electrode.

28. the gate electrode includes a first gate electrode and a second gate electrode of a different system from the first gate electrode; the active trench includes a first active trench and a second active trench; the active portion of the first active trench is connected to the first gate electrode; The semiconductor device of claim 2 , wherein the active portion of the second active trench and the lower active portion are connected to the second gate electrode.

29. The active section is divided into upper and lower two sections via an intermediate insulating film, the gate electrode includes a first gate electrode and a second gate electrode of a different system from the first gate electrode, a portion of the active portion above the intermediate insulating film is connected to the first gate electrode; 3. The semiconductor device according to claim 2, wherein the portion of the active portion below the intermediate insulating film is connected to the second gate electrode.

30. A semiconductor device according to any one of claims 1 to 29, comprising a MOSFET.

31. The semiconductor device according to any one of claims 1 to 30, wherein the semiconductor substrate is formed of a wide band gap semiconductor.

32. 32. The semiconductor device according to claim 31, wherein the wide band gap semiconductor is silicon carbide, a gallium nitride based material or diamond.

33. 3. The semiconductor device according to claim 2, wherein two or more of the two-stage dummy active trenches are provided side by side, and the distance between the two two-stage dummy active trenches is smaller than the distance between the active trench and a trench adjacent to the active trench.

34. The semiconductor device of claim 33 , wherein the width of the two-stage dummy active trench is smaller than the width of the active trench.

35. Equipped with a dummy trench, The semiconductor device of claim 33 , wherein the width of the two-stage dummy active trench is smaller than the width of the dummy trench.

36. The semiconductor device according to any one of claims 2, 4-29, and 33-35, characterized in that the two-stage dummy active trench has a branched shape in a plan view.

37. The semiconductor device according to any one of claims 2, 4-29 and 33-35, characterized in that the two-stage dummy active trench has a substantially constant width and a portion formed in a ring shape in a plan view.

38. The semiconductor element described in any one of claims 2, 4-29, and 33-35, characterized in that the two-stage dummy active trench has a main body portion and a protruding portion protruding in a direction perpendicular to the longitudinal direction of the main body portion in a planar view, or a recessed portion recessed in a direction perpendicular to the longitudinal direction of the main body portion in a planar view.

39. 40. The semiconductor element according to claim 38, wherein a width of the protrusion or depression is smaller than a width of the main body in a plan view.

40. 40. The semiconductor device according to claim 39, wherein, in a plan view, a plurality of the protrusions are formed, and the interval between the protrusions is smaller than the distance between the two-stage dummy active trench and a trench adjacent to the two-stage dummy active trench.

41. 40. The semiconductor element according to claim 39, wherein, in a plan view, a plurality of the recesses are formed, and the interval between the recesses is smaller than the distance between the two-stage dummy active trench and a trench adjacent to the two-stage dummy active trench.

42. The semiconductor device according to any one of claims 2, 4-29 and 33-41, wherein the two-stage dummy active trench has a plurality of bent portions in a plan view.

43. 43. The semiconductor device according to claim 2, wherein a portion of the base layer sandwiched between the two two-stage dummy active trenches is connected to the emitter electrode.

44. 2. The semiconductor device according to claim 1, wherein the base layer is divided into a plurality of base portions by providing a plurality of the two-stage dummy active trenches, and the plurality of base portions include a portion connected to the emitter electrode and a portion not connected to the emitter electrode.

45. Two dummy trenches are provided, a portion of the base layer sandwiched between the two dummy trenches is not connected to the emitter electrode, 2 . The semiconductor device according to claim 1 , wherein a portion of the base layer sandwiched between the two two-stage dummy active trenches is connected to the emitter electrode.

46. The RC-IGBT is configured by having an IGBT region and a diode region, A plurality of the two-stage dummy active trenches are provided in the diode region; The semiconductor element according to any one of claims 2 and 4 to 29, characterized in that a plurality of two-stage active dummy trenches are provided in the IGBT region inside the trench of the semiconductor substrate, the upper stage having an upper stage active portion connected to the gate electrode, and a lower stage dummy portion not connected to the gate electrode and covered with an insulating film.

47. 7. The semiconductor device according to claim 2, wherein an upper end of the lower active section is located below a lower end of the base layer.

48. The semiconductor device according to claim 8 , wherein a longitudinal length of the lower active section in the carrier accumulation layer is shorter than a longitudinal length of the lower active section in the drift layer.

49. A first semiconductor element having a collector connected to a high potential side of a power supply; A second semiconductor element having the same structure as the semiconductor element according to any one of claims 27 to 29, the second semiconductor element having an emitter connected to the low potential side of a power supply and a collector connected to the emitter of the first semiconductor element; a gate drive circuit for applying gate voltages to the first gate electrode and the second gate electrode in separate systems; The gate drive circuit includes: when a collector current of the first semiconductor element is greater than a predetermined value, a voltage equal to or greater than a threshold is applied to the first gate electrode while a voltage equal to or greater than the threshold is not applied to the second gate electrode; a first gate electrode and a second gate electrode are applied with a voltage equal to or higher than a threshold voltage when a collector current of the first semiconductor element is smaller than a predetermined value.

Images