Controller and Memory Systems

Abstract

To provide a controller capable of achieving downsizing and faster speed, and a memory system.SOLUTION: A controller comprises first and second PCIe MAC layer circuits connected to a physical layer interface circuit on the basis of lane reversal. The controller comprises a signal processing circuit including a first terminal which receives some signals of a first auxiliary signal line for transmitting a Sideband signal of a first port and a second terminal which receives some signals of a second auxiliary signal line for transmitting a Sideband signal of a second port. The controller can switch wiring of some signals of the first auxiliary signal line and wiring of some signals of the second auxiliary signal line for each of the first terminal and the second terminal of the signal processing circuit on the basis of the lane reversal. The controller also switches wiring of some other signals of the first auxiliary signal line and wiring of some other signals of the second auxiliary signal line between the physical layer interface circuit, the first PCIe MAC layer circuit, and the second PCIe MAC layer circuit.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] SUMMARY OF THE DISCLOSURE The present invention relates to a controller and a memory system. [Background technology]

[0002] In recent years, solid state drives (SSDs) have been developed as memory systems equipped with non-volatile memories such as NAND flash memories. As the data capacity stored in memory systems such as SSDs increases, the number of non-volatile memory packages installed in SSDs is also increasing. This has led to a demand for smaller and faster memory systems. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Pat. No. 10,817,443 [Patent Document 2] U.S. Pat. No. 10,467,111 [Patent Document 3] JP 2012-22463 A Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a controller and a memory system that can be made smaller and faster. [Means for solving the problem]

[0005] The controller of the embodiment includes: The host is reachable,A physical layer interface circuit corresponding to a dual port of a first port and a second port conforming to the PCIe standard, the first port including a first number of lanes to which a first order is assigned, and the second port including a second number of lanes to which a second order is assigned, the first number of lanes and the second number of lanes being connected to the physical layer interface circuit via wiring arranged in an order in which a part of the first order and a part of the second order are swapped based on lane reversal conforming to the PCIe standard. A controller is provided corresponding to each of the first port and the second port, and includes first and second PCIe MAC (Media Access Control) layer circuits that connect to the physical layer interface circuit based on the lane reversal. The controller comprises: A first terminal and a second terminal, said first number of lanes of Different from the first signal line Transmitted via the first auxiliary signal line Sideband signal of the first port and the second terminal is configured to receive a signal from said second number of lanes of Different from the second signal line Transmitted via the second auxiliary signal line Sideband signal of the second port configured to receive a signal from a portion of the controller includes a switching circuit capable of switching wiring of the part of signals on the first auxiliary signal line and wiring of the part of signals on the second auxiliary signal line to the first terminal and the second terminal of the signal processing circuit, respectively, based on the lane reversal, and capable of switching wiring of the other part of signals on the first auxiliary signal line and wiring of the other part of signals on the second auxiliary signal line between the physical layer interface circuit and the first and second PCIe MAC layer circuits. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 illustrates an example of a configuration of a storage device according to an embodiment. [Diagram 2] FIG. 1 is a perspective view showing an example of the appearance of a storage apparatus. [Diagram 3] FIG. 1 is a cross-sectional view showing an example of a storage apparatus. [Figure 4]FIG. 13 shows an example of lane numbers when a controller is mounted on the back side of a board. [Diagram 5] FIG. 2 is a diagram showing an example of the internal configuration of a controller of the storage apparatus. [Figure 6] A diagram showing an example of using lane reversal with Dual Port. [Figure 7] A diagram showing an example of using lane reversal on a single port. [Figure 8] FIG. 13 is a diagram showing an example of the configuration of a controller of a storage apparatus according to a modified example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, an embodiment will be described with reference to the drawings.

[0008] 1 is a diagram showing an example of a configuration of a storage device 1 according to an embodiment. In this embodiment, it is assumed that the storage device 1, which is a memory system, is realized as an SSD (Solid State Drive).

[0009] 1, the storage device 1 includes a controller 10, a buffer memory 20, and a storage 30. The storage device 1 can be connected to a host 2 via an interface conforming to the PCI-Express™ (also referred to as PCIe™) standard, for example.

[0010] The storage device 1 is an enterprise SSD. The storage device 1 is an example of a memory system having a configuration in which a storage 30 and a controller 10 are mounted on a printed circuit board 12 (see FIG. 2). The storage device 1 has a connector unit 14 (see FIG. 2) with wiring provided on the printed circuit board 12 as a terminal, and can function as a removable SSD that can be attached to a connector (also called a card connector) in the host 2.

[0011] The host 2 may be, for example, a storage system, an information processing device such as a server or a personal computer, a mobile phone, a digital camera, an imaging device, a mobile terminal such as a tablet computer or a smartphone, a game device, or an in-vehicle terminal such as a car navigation system.

[0012] The buffer memory 20 is, for example, a dynamic random access memory (DRAM). The buffer memory 20 functions as a working memory for the controller 10. The buffer memory 20 may be an SRAM. The buffer memory 20 may be built into the controller 10.

[0013] The storage 30 is, for example, a NAND type flash memory. The storage 30 includes at least one semiconductor memory chip. The storage 30 may be another semiconductor memory. Examples include MRAM (Magnetoresistive RAM), FeRAM (Ferroelectric RAM), PRAM (Phase Change RAM), and RRAM (Resistance RAM).

[0014] The controller 10 is a chip component that integrates functional units such as a CPU (Central Processing Unit) that serves as the core of a computer, a memory that stores firmware that operates the CPU, and an I / O circuit. The controller 10 is configured as, for example, a SoC (System On a Chip).

[0015] The controller 10 receives commands (for example, a write command or a read command) from the host 2. In response to the received command, the controller 10 executes a write process of data transferred from the host 2 to the storage 30 and a read process of data requested by the host 2 from the storage 30 while using the buffer memory 20 as a temporary storage area for data. In other words, the controller 10 controls the storage 30 based on the command from the host 2.

[0016] Fig. 2 is a perspective view showing an example of the appearance of the storage device 1, and Fig. 3 is a cross-sectional view showing an example of the storage device 1. Note that Fig. 3 shows a part of the AA cross section in Fig. 2. As shown in Figs. 2 and 3, the storage device 1 includes a box-shaped housing 11.

[0017] The storage device 1 also includes a printed circuit board (hereinafter, simply referred to as board) 12 having a substantially rectangular shape. The board 12 may have a single-layer structure, or may have a multi-layer structure formed by layering synthetic resins such as epoxy resin. Wiring patterns of various shapes are formed on the surface of each layer. For example, a layer on which signal lines for transmitting and receiving signals are arranged, a layer on which ground wiring that serves as a reference potential for the controller 10 and storage 30 is arranged, a layer on which wiring that serves as a power supply potential for the controller 10 and storage 30 is arranged, etc. may be formed.

[0018] A connector section 14 is provided at an end 12a on one of the short sides of the substrate 12. The substrate 12 has a front surface (an example of a first surface) 12b and a back surface (an example of a second surface) 12c opposite to the front surface 12b. The connector section 14 has a plurality of terminals provided on the front surface 12b of the substrate 12 and a plurality of terminals provided on the back surface 12c. A part of a wiring pattern (not shown) formed on the substrate 12 is electrically connected to each terminal of the connector section 14. Each terminal of the connector section 14 is formed by wiring formed on the substrate 12. That is, the connector section 14 is formed as an edge connector. The connector section 14 is directly connected to a connector (not shown) on a circuit board of the host 2 or connected via a cable. In this way, the storage device 1 is electrically connected to the host 2.

[0019] 3, the board 12 and the controller 10 are provided inside a housing 11. Although not shown in FIG 3, a buffer memory 20 and a storage 30 are also provided inside the housing 11.

[0020] As shown in FIG. 3, the controller 10 is mounted on a back surface 12c of the substrate 12, which is the surface opposite to the surface 12b of the substrate 12 on which a plurality of terminals are provided.

[0021] By providing the board 12, controller 10, buffer memory 20 and storage 30 inside the housing 11 in this manner, each of these parts and other circuit components mounted on the board 12 can be protected from structural damage, electrical shorts, static electricity, etc.

[0022] Here, the reason why the storage device 1 mounts the controller 10 on the rear surface 12c of the substrate 12 will be explained.

[0023] Previously, there was the U.2 standard, which defined connection specifications that comply with the PCIe standard used by SSDs, etc. According to this U.2 standard, there was a margin in the height limit inside the storage device's housing, so it was possible to mount a controller on the surface (first side) of the printed circuit board.

[0024] In addition, in order to achieve high-speed transfer speeds of several GHz for the PCIe interface, the U.2 standard requires that the PCIe interface terminals (pins) of an SoC in which multiple components (systems) required for control, including the CPU, are integrated onto a single chip are arranged in a pattern (parallel pattern) that prevents pattern intersections.

[0025] Meanwhile, in recent years, a new standard called the Enterprise and Data Center SSD Form Factor (EDSFF) has been established. According to this EDSFF standard, in order to miniaturize storage devices, the internal height limit of the storage device housing is stricter than that of the U.2 standard.

[0026] Therefore, in the storage device 1 of this embodiment, even in the EDSFF standard, the problem of height restrictions is avoided by mounting the controller 10, etc. on the rear surface 12c of the substrate 12, which has a larger margin of error in terms of height restrictions. By mounting the controller 10, etc. on the rear surface 12c of the substrate 12, it is expected that the heat dissipation efficiency will be improved, which is also advantageous for cooling.

[0027] Here, FIG. 4 is a diagram showing an example of lane numbers when the controller 10 is mounted on the back surface 12c of the board 12. The diagram shown in FIG. 4 shows a comparison between an example assuming that the controller 10 is arranged on the back surface 12c of the board 12 in the EDSFF standard and an example in which the controller 10 is arranged on the front surface 12b of the board 12 in the U.2 standard. In FIG. 4, the number after the L in each of the lanes L0 to L4 indicates the lane number in the PCIe interface standard. Each of the lanes L0 to L4 includes multiple signal lines, but these are omitted in FIG. 4. As shown in FIG. 4, when the controller 10, whose terminals are arranged in a parallel pattern (here, in lane order) suitable for the U.2 standard of the PCIe interface, is mounted on the back surface 12c of the board 12, the lane numbers of the signal lines between the connector unit 14 and the controller 10 are inverted.

[0028] On the other hand, the signal lines of the PCIe interface support lane reversal, which is a lane order swapping function compliant with the PCIe standard. Therefore, the wiring of the signal lines of the PCIe interface can function as a lane reversal pattern when the controller 10 is mounted on the rear surface 12c of the board 12. Lane reversal allows logical inversion of the order of lane numbers of the signal lines, thereby increasing the flexibility of the board layout and reducing the number of signal lines that need to cross each other in the wiring of the printed circuit board.

[0029] Therefore, the storage device 1 of this embodiment connects the connector unit 14 and the controller 10 using lane reversal that complies with the PCIe standard.

[0030] Here, Fig. 5 is a diagram showing an example of the internal configuration of the controller 10 of the storage device 1. As shown in Fig. 5, the storage device 1 is a device compatible with Dual Port of the PCIe standard (hereinafter referred to as a Dual Port device). That is, the storage device 1 can be connected to the host 2 via two ports. The storage device 1 can be accessed from the host 2 via two ports, each of which has four lanes. In Fig. 5, the host 2 has a host port 21A which is a first port and a host port 21B which is a second port. Here, PA-L0 to PA-L3 and PB-L0 to PB-L3 respectively indicate one lane of the transmission path provided in each port.

[0031] 5, the connector unit 14 of the storage device 1 and the host port 21A and the host port 21B of the host 2 are connected with the order of some lanes swapped in accordance with lane reversal of the PCIe standard. Specifically, as shown in FIG 5, PA-L2 of the host port 21A is connected to lane 4 of the connector unit 14, PA-L3 of the host port 21A is connected to lane 5 of the connector unit 14, PB-L0 of the host port 21B is connected to lane 2 of the connector unit 14, and PB-L1 of the host port 21B is connected to lane 3 of the connector unit 14.

[0032] 5, the controller 10 includes a physical layer interface circuit 15 realized as a standard physical layer (PHY) of the PCIe standard, a first PCIe MAC (Media Access Control) layer circuit MAC16A corresponding to the host port 21A, and a second PCIe MAC layer circuit MAC16B corresponding to the host port 21B. A huddle 17 is a CPU peripheral logic circuit provided in the controller 10.

[0033] The physical layer interface circuit 15 connects to the lanes of the connector unit 14 via multiple signal lines using lane reversal compliant with the PCIe standard. The multiple signal lines transmit signals compliant with the PCIe standard. Here, each lane has one differential pair for transmission and reception for performing bidirectional communication. In the PCIe standard, a transmission differential signal TX and a reception differential signal RX are assigned to one of multiple terminals of each lane. Bidirectional communication can be performed by using the transmission differential signal TX and the reception differential signal RX.

[0034] The MAC 16A and the MAC 16B are provided for each of the host ports 21A and 21B. The MAC 16A and the MAC 16B are connected to the physical layer interface circuit 15 using lane reversal conforming to the PCIe standard, and control access to the storage 30.

[0035] The controller 10 also has an auxiliary signal line that is provided separately from the signal line and transmits a sideband signal. More specifically, the controller 10 has a signal processing circuit that includes a first terminal that receives a part of a signal of a first auxiliary signal line (auxiliary signal line) that transmits a sideband signal of the host port 21A, and a second terminal that receives a part of a signal of a second auxiliary signal line (auxiliary signal line) that transmits a sideband signal of the host port 21B. The sideband signal of the host port 21A is different from a first signal line (signal line) corresponding to a first number of lanes to which a first order is assigned in the host port 21A. The sideband signal of the host port 21B is different from a second signal line (signal line) corresponding to a second number of lanes to which a second order is assigned in the host port 21B.

[0036] In addition, the controller 10 includes a switching circuit that allows the auxiliary signal lines to support lane reversal between the physical layer interface circuit 15 and the MAC 16A and MAC 16B. The switching circuit will be described below.

[0037] In a dual port device, when lane reversal is used with the dual port, the following problems occur. Here, FIG. 6 is a diagram showing an example of using lane reversal with the dual port. As shown in FIG. 6, when lane reversal is used with the dual port, the host port 21A and the host port 21B are connected inversely to the MAC16A and the MAC16B of the controller 10, respectively. As a result, the following problems occur. (1) The signal PERST#, which is a sideband signal, is switched between the host port 21A and the host port 21B. (2) The signal Refclk, which is a sideband signal, is switched between the host port 21A and the host port 21B. (3) A PIPE (PHY Interface for the PCI Express Architecture) clock switch circuit 18, which detects loss of the signal Refclk, receives the signal Refclk of the opposite port.

[0038] An example of using lane reversal in a single port will be described with reference to Fig. 7. When lane reversal is used in a single port, lane reversal in one PCIe MAC (Media Access Control) layer is used as shown in Fig. 7. Also, there is one signal PERST# and one signal Refclk, which are sideband signals. Therefore, even if lane reversal is used, the host port 21A, which is a single port, and the controller 10 can be connected without any problem.

[0039] 5, the storage device 1 according to this embodiment, which is a dual port device, is provided with a switching circuit including switch circuits S1 to S3 that switch sideband signals between the host port 21A and the host port 21B. This allows the storage device 1 to use lane reversal in the dual port. This will be described in detail below.

[0040] The switching circuit can switch wiring of some signals on the first auxiliary signal line and wiring of some signals on the second auxiliary signal line for each of the first terminal and the second terminal of the signal processing circuit based on lane reversal. In addition, the switching circuit can switch wiring of other signals on the first auxiliary signal line and wiring of other signals on the second auxiliary signal line between physical layer interface circuit 15 and MAC16A and MAC16B.

[0041] 5, the signal PERST#, which is a PCIe sideband signal, is a negative logic reset signal sent from the host 2. The signal PERST# can be used by the host 2 to reset a bus used for communication conforming to the PCIe standard. The signal PERST# can be used by the host 2 to reinitialize the storage device 1 when an error occurs, for example.

[0042] 5, the signal Refclk, which is a PCIe sideband signal, is a reference differential clock signal sent from the host 2. The reference differential clock signal is made up of two differential signals to form a differential clock. By receiving the differential clock from the connected host 2, the storage device 1 can easily synchronize signals transmitted between the storage device 1 and the connected host 2.

[0043] The switch circuit S1 included in the switching circuit functions as a first circuit that switches detection of an interrupt of a signal PERST#, which is a sideband signal, between the host port 21A and the host port 21B. The switch circuit S1 includes a multiplexer 51, a multiplexer 52, and a signal PERST# switching unit 53.

[0044] The multiplexer 51 includes one input terminal to which the signal PERST#A is input, the other input terminal to which the signal PERST#B is input, a control terminal connected to a signal PERST# switching unit 53 of the huddle 17, and an output terminal connected to a terminal to which the signal PERST#A of the huddle 17 is input. The multiplexer 51 outputs either the input signal PERST#A or the signal PERST#B in response to a signal from the signal PERST# switching unit 53 input to the control terminal.

[0045] The multiplexer 52 includes one input terminal to which the signal PERST#B is input, the other input terminal to which the signal PERST#A is input, a control terminal connected to a signal PERST# switching unit 53 of the huddle 17, and an output terminal connected to a terminal to which the signal PERST#B of the huddle 17 is input. The multiplexer 52 outputs either the input signal PERST#A or the signal PERST#B in response to a signal from the signal PERST# switching unit 53 input to the control terminal.

[0046] The signal PERST# switching unit 53 is one of the modules provided in the huddle 17. The signal PERST# switching unit 53 determines which reset signal (signal PERST#A or signal PERST#B) to select under the control of a CPU that operates according to firmware. Then, the signal PERST# switching unit 53 outputs a signal indicating the result of the determination to the multiplexer 51 and the multiplexer 52.

[0047] That is, the switch circuit S1 switches the output signals from the multiplexer 51 and the multiplexer 52 in response to a switching signal from the signal PERST# switching unit 53. This allows the detection of the interruption of the signal PERST# to be correctly switched between the host port 21A and the host port 21B.

[0048] A switch circuit S2 included in the switching circuit functions as a second circuit that switches between the signal RefclkA / signal RefclkB in the physical layer interface circuit 15. The switch circuit S2 in the physical layer interface circuit 15 is controlled by a CPU that operates according to firmware.

[0049] The physical layer interface circuit 15 has physical layers (PHY0 to PHY7) corresponding to the multiple lanes PA-L0 to PA-L3 of the host port 21A and the multiple lanes PB-L0 to PB-L3 of the host port 21B.

[0050] The physical layer interface circuit 15 receives a signal RefclkA from the host port 21A via the connector unit 14, and receives a signal RefclkB from the host port 21B via the connector unit 14. The switch circuit S2 switches between the signal RefclkA / signal RefclkB in the physical layer interface circuit 15 under the control of a CPU that operates according to firmware.

[0051] More specifically, the physical layer interface circuit 15 turns on the switch provided in the physical layer PHY2 among the switches provided in the physical layers PHY2, PHY3, PHY6, and PHY7 constituting the switch circuit S2. As a result, the signal PCLK2 corresponding to the signal RefclkA is output from the physical layer PHY2 to the PIPE clock switch circuit 18-2. Also, the physical layer interface circuit 15 turns on the switch provided in the physical layer PHY0 among the switches provided in the physical layers PHY0, PHY1, PHY4, and PHY5 constituting the switch circuit S2. As a result, the signal PCLK0 corresponding to the signal RefclkB is output from the physical layer PHY0 to the PIPE clock switch circuit 18-1.

[0052] The two switch circuits S3 included in the switching circuit function as a third circuit that switches the Refclk loss detection signals output from the corresponding Refclk Loss dets 19 between the host port 21A and the host port 21B. The switch circuit S3 includes a multiplexer 61, a multiplexer 62, and a detection signal switching unit 63.

[0053] The Refclk Loss det 19 monitors the clock cycles of the signals RefclkA and RefclkB. If the Refclk Loss det 19 detects that the signals RefclkA and RefclkB have deviated from a certain frequency range, it outputs a Refclk loss detection signal.

[0054] The multiplexer 61 has one input terminal to which the Refclk loss detection signal of signal RefclkB is input, the other input terminal to which the Refclk loss detection signal of signal RefclkA is input, a control terminal connected to the detection signal switching unit 63, and an output terminal connected to the control terminal of the PIPE clock switch circuit 18. The multiplexer 61 outputs either the Refclk loss detection signal of the input signal RefclkB or the Refclk loss detection signal of the signal RefclkA in response to the signal from the detection signal switching unit 63 input to the control terminal.

[0055] The multiplexer 62 has one input terminal to which the Refclk loss detection signal of signal RefclkA is input, the other input terminal to which the Refclk loss detection signal of signal RefclkB is input, a control terminal connected to the detection signal switching unit 63, and an output terminal connected to the control terminal of the PIPE clock switch circuit 18. The multiplexer 62 outputs either the Refclk loss detection signal of signal RefclkB or the Refclk loss detection signal of signal RefclkA according to the signal from the detection signal switching unit 63 input to the control terminal.

[0056] The detection signal switching unit 63, under the control of the CPU operating according to firmware, determines whether to select the Refclk loss detection signal of the signal RefclkB or the Refclk loss detection signal of the signal RefclkA. Then, the detection signal switching unit 63 outputs a signal designating the determined loss detection signal to the multiplexers 61 and 62, thereby selecting the signal on the same side as that switched by the signal PERST# switching unit 53.

[0057] The PIPE clock switch circuit 18-1 has one input terminal to which a signal OSC, which is a synchronization signal output from an oscillator, is input, the other input terminal (second terminal) to which PCLK0 from the physical layer interface circuit 15 is input, a control terminal connected to the multiplexer 61, and an output terminal connected to the MAC16B.

[0058] The PIPE clock switch circuit 18-1 outputs to the MAC 16B a signal to be input to either one of the input terminals or the other input terminal in response to the loss detection signal input from the multiplexer 61 to the control terminal.

[0059] The PIPE clock switch circuit 18-2 has one input terminal to which a signal OSC, which is a synchronization signal output from an oscillator, is input, the other input terminal (first terminal) to which PCLK2 from the physical layer interface circuit 15 is input, a control terminal connected to the multiplexer 62, and an output terminal connected to the MAC16A.

[0060] The PIPE clock switch circuit 18-2 outputs to the MAC 16A a signal to be input to either one of the input terminals or the other input terminal in response to the loss detection signal input from the multiplexer 62 to the control terminal.

[0061] That is, the switch circuit S3 switches the output signals from the multiplexer 61 and the multiplexer 62 in response to a switching signal from the detection signal switching unit 63. This allows the Refclk loss detection signal to be correctly switched between the host port 21A and the host port 21B.

[0062] Thus, according to this embodiment, the storage device 1, which is a dual port device, uses lane reversal conforming to the PCIe standard, making it possible to mount at least the controller 10 on the back surface of the board 12. With this configuration, according to this embodiment, it is possible to alleviate height restrictions and improve heat dissipation efficiency without sacrificing the transmission characteristics on the board 12.

[0063] (Modification) Fig. 8 is a diagram showing a configuration example of the controller 10 of the storage device 1 according to the modified example. As shown in Fig. 8, the storage device 1 may be provided with a bifurcation switch circuit S4 that switches the path from the physical layer interface circuit 15 to MAC16A and MAC16B. The bifurcation switch circuit S4 is a line-compatible circuit that constitutes a switching circuit.

[0064] The bifurcation switch circuit S4 is provided with many switches using multiplexers, and correctly branches each lane connected to the physical layer interface circuit 15 to MAC16A / MAC16B. The multiple multiplexers execute switching of the path from the physical layer interface circuit 15 to MAC16A and MAC16B based on lane reversal under the control of a CPU that operates according to firmware. Specifically, the bifurcation switch circuit S4 operates as follows based on lane reversal.

[0065] The bifurcation switch circuit S4 branches the lane PB-L3 of the host port 21B connected to the physical layer PHY0 of the physical layer interface circuit 15 to PB-L3 of the MAC16B. The bifurcation switch circuit S4 branches the lane PB-L2 of the host port 21B connected to the physical layer PHY1 of the physical layer interface circuit 15 to PB-L2 of the MAC16B. The bifurcation switch circuit S4 branches the lane PA-L3 of the host port 21A connected to the physical layer PHY2 of the physical layer interface circuit 15 to PA-L3 of the MAC16A. The bifurcation switch circuit S4 branches the lane PA-L2 of the host port 21A connected to the physical layer PHY3 of the physical layer interface circuit 15 to PA-L2 of the MAC16A.

[0066] Also, the bifurcation switch circuit S4 branches the lane PB-L1 of the host port 21B connected to the physical layer PHY4 of the physical layer interface circuit 15 to PB-L1 of the MAC16B. The bifurcation switch circuit S4 branches the lane PB-L0 of the host port 21B connected to the physical layer PHY5 of the physical layer interface circuit 15 to PB-L0 of the MAC16B. The bifurcation switch circuit S4 branches the lane PA-L1 connected to the physical layer PHY6 of the physical layer interface circuit 15 to PA-L1 of the host port 21A of the MAC16A. The bifurcation switch circuit S4 branches the lane PA-L0 of the host port 21A connected to the physical layer PHY7 of the physical layer interface circuit 15 to PA-L0 of the MAC16A.

[0067] As described above, by using the bifurcation switch circuit S4 to correctly branch each lane connected to the physical layer interface circuit 15 to MAC16A / MAC16B, the lane numbers of the signal lines between the connector unit 14 and the controller 10 are prevented from being inverted even when the controller 10 is mounted on the back surface 12c of the substrate 12.

[0068] However, this type of modification requires a large number of switches, which may complicate the wiring within the SoC. However, by designing the wiring while taking into account timing convergence in the implementation, the timing of each signal can be properly synchronized.

[0069] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0070] 1. Memory System 2 Host 10 Controller 12 Substrate 14 Connector part 15 Physical layer interface circuit 16A,16B MAC layer 21A Host Port 21B Host Port 30 Storage S1 Switching circuit, first circuit S2 Switching circuit, second circuit S3 Switching circuit, 3rd circuit S4 Switching circuit

Claims

1. A physical layer interface circuit connectable to a host and corresponding to a dual port having a first port and a second port conforming to the PCIe standard, the first port including a first number of lanes to which a first order is assigned, and the second port including a second number of lanes to which a second order is assigned, the first number of lanes and the second number of lanes being connected to the physical layer interface circuit via wiring arranged in an order in which a portion of the first order and a portion of the second order are swapped based on lane reversal conforming to the PCIe standard, a first PCIe MAC (Media Access Control) layer circuit provided for each of the first and second ports and connected to the physical layer interface circuit based on the lane reversal; a signal processing circuit including a first terminal and a second terminal, the first terminal configured to receive a part of a sideband signal of the first port transferred via a first auxiliary signal line different from a first signal line of the first number of lanes, and the second terminal configured to receive a part of a sideband signal of the second port transferred via a second auxiliary signal line different from a second signal line of the second number of lanes; a switching circuit capable of switching wiring of the part of signals on the first auxiliary signal line and wiring of the part of signals on the second auxiliary signal line to the first terminal and the second terminal of the signal processing circuit, respectively, based on the lane reversal, and capable of switching wiring of the other part of signals on the first auxiliary signal line and wiring of the other part of signals on the second auxiliary signal line between the physical layer interface circuit and the first and second PCIe MAC layer circuits; A controller comprising:

2. the switching circuit includes a circuit capable of switching between wiring of the part of signals of the first auxiliary signal line and wiring of the part of signals of the second auxiliary signal line, the part of the signal on the first auxiliary signal line and the part of the signal on the second auxiliary signal line are reset signals serving as the sideband signals used by the host to reset a bus used for communication conforming to the PCIe standard; The controller of claim 1 .

3. the switching circuit includes a circuit capable of switching between wiring of another part of signals of the first auxiliary signal line and wiring of another part of signals of the second auxiliary signal line; another part of the signal on the first auxiliary signal line and another part of the signal on the second auxiliary signal line are reference differential clock signals as the sideband signal transmitted from the host.

3. The controller according to claim 1 or 2.

4. a physical layer interface circuit corresponding to a dual port having a first port and a second port conforming to a PCIe standard, the first port including a first number of lanes to which a first order is assigned, the second port including a second number of lanes to which a second order is assigned, the first number of lanes and the second number of lanes being connected to the physical layer interface circuit via wiring arranged in an order in which a part of the first order and a part of the second order are swapped based on lane reversal conforming to the PCIe standard; a first PCIe MAC (Media Access Control) layer circuit provided for each of the first and second ports and connected to the physical layer interface circuit based on the lane reversal; a signal processing circuit including a first terminal and a second terminal, the first terminal configured to receive a part of a sideband signal of the first port transferred via a first auxiliary signal line different from a first signal line of the first number of lanes, and the second terminal configured to receive a part of a sideband signal of the second port transferred via a second auxiliary signal line different from a second signal line of the second number of lanes; a switching circuit that switches paths to the first and second PCIe MAC layer circuits for the first and second number of lanes connected to the physical layer interface circuit based on the lane reversal; A controller comprising:

5. A substrate; a connector portion provided on the board and corresponding to a dual port having a first port and a second port; a semiconductor memory chip mounted on the substrate; the controller according to claim 1 , which is mounted on a second surface of the board opposite to the connector portion and controls an operation of the semiconductor memory chip; A memory system comprising:

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