Hybrid digital and analog signal generation system and method - Patents.com

Abstract

The analog signal source comprises two or more digital-to-analog converters (DACs) combined to generate one or more frequency components, the analog signal source comprising a first path for generating a substantially low frequency signal, the first path comprising a first of the DACs, and a second path for generating a substantially high frequency signal, the second path comprising a second of the DACs.

Description

[Technical field]

[0001] (CROSS REFERENCE TO RELATED APPLICATIONS) This application claims priority to U.S. Provisional Patent Application No. 63 / 016,747, entitled "ADVANCED ANALOG-TO-DIGITAL CONVERSION SYSTEMS AND METHODS," filed April 28, 2020, to Fortney, U.S. Provisional Patent Application No. 63 / 034,052, entitled "ADVANCED DIGITAL-TO-ANALOG SIGNAL GENERATION SYSTEMS AND METHODS," filed June 3, 2020, to Fortney, and U.S. Provisional Patent Application No. 63 / 057,745, entitled "SYNCHRONOUS SOURCE MEASURE SYSTEMS AND METHODS," filed July 28, 2020, to Fortney, each of which is incorporated herein by reference in its entirety.

[0002] This disclosure relates to voltage and current analog source generation, including by hybrid alternating current (AC) and direct current (DC) systems and methods. More generally, it relates to electronics, analytical instrumentation, software, and infrastructure for signal supply and signal measurement. This disclosure also relates to systems for measuring signals for material and device characterization and other applications under difficult experimental conditions that can cause high levels of noise and interference. In these contexts, it relates to digital-to-analog conversion (and vice versa). [Background technology]

[0003] Materials and device property measurements (e.g., electronic transport properties such as hole, mobility, and carrier concentration) are often very sensitive to noise, interference, and stray signals. For example, superconducting properties are typically measured at extremely low temperatures (e.g., below 4 K) necessary to observe those properties without excessive noise. These measurements may also require very high magnetic field strengths (e.g., above 5 T), which can complicate the experimental setup. Dealing with noise, interference, and stray signals under these compromising conditions is critical to obtain reliable and accurate data.

[0004] Any noise or irregularities introduced via the input or source signal can appear in the sample and throughout the measurement system. Because of this, input or source signal problems are widespread. They degrade the measurement itself. They can also adversely affect and be made worse by any electronics and instruments they traverse. The best way to deal with this is to generate a source signal that introduces as little noise or ambiguity as possible.

[0005] Techniques such as dithering, subranging, pulse width modulation, least significant bit / most significant bit (LSB / MSB) dual digital-to-analog converter (DAC) architectures can all improve resolution and reliability. Combining stable components with low drift references, temperature controlled elements, chopper amplifier methods, sigma-delta blocks, successive approximation register analog-to-digital converter (ADC) techniques, etc. can improve accuracy.

[0006] While these techniques are useful, they may be inadequate for extremely sensitive material measurements performed under compromising conditions. In particular, they have limited flexibility in dealing with noise, glitches, and other ambiguities introduced into the measurement system via the source signal. Material measurement systems are often dynamic. They periodically require reconfiguration and reconfiguration steps to accommodate a variety of different types of measurements. Their source signal generators need to have built-in flexibility. Current systems often apply source processing (e.g., signal gain) uniformly to different mismatched sides of the source. Many cannot treat DC and AC source components differently and independently. This creates problems and limits flexibility, as the DC and AC components are often very different in scale and range.

[0007] Thus, there is a critical need for new and improved solutions for providing robust, high quality, low noise source or output signals to which signal processing and gain may be applied in a flexible manner. There is a need for a system that will do this for source signals constructed from DC and AC components that differ substantially in range. Summary of the Invention [Means for solving the problem]

[0008] The analog signal source comprises two or more digital-to-analog converters (DACs) that are combined to generate one or more frequency components. The analog signal source comprises a first path for generating a substantially low frequency signal, the first path comprising a first of the DACs. The analog signal source comprises a second path for generating a substantially high frequency signal, the second path comprising a second of the DACs. The analog signal source also comprises a data processor for processing the input signal and providing a processed input signal to the first and second paths. The analog signal source comprises a combining circuit configured to combine outputs of the first and second paths into a source signal. The analog signal source comprises a feedback portion configured to sense the source signal. The analog signal source comprises a servo loop configured to use the sensed source signal and adjust as necessary to maintain the source signal substantially in line with the input signal.

[0009] In some embodiments, the data processor providing the processed input signal to the first and second paths includes at least one of feeding a DC input to the first path, feeding a low frequency input to at least one of the first path and the second path, and feeding a high frequency input to at least one of the first path and the second path. The servo loop maintaining the source signal substantially matching the input signal may include at least one of removing DC errors, removing low frequency errors, and maintaining high frequency signal integrity. The bandwidth of the feedback section may be substantially higher than the bandwidth of the first path. The feedback section sensing the source signal may include comparing the input signal to the output signal. The data processor processing the input signal may include at least one of removing high frequency signals that are higher than the bandwidth of the first path but within the bandwidth of the feedback section, and removing high frequency signals that are higher than the bandwidth of the feedback section and higher than the bandwidth of the first path.

[0010] The first path may be configured for direct current (DC). The feedback section may comprise at least one analog-to-digital converter (ADC). The data processor may comprise an ADC feedback, and the data processor processing the input signal may include comparing the input signal to a source signal and removing high frequency signals from the input signal that are higher than the bandwidth of the first path but within the bandwidth of the feedback section. The second path may be configured to accommodate at least one of more than one frequency and a composite waveform characterized by multiple frequency components. The first path may comprise an integrator. The first path may comprise a first gain configured to range to the first path prior to being combined with the second path. The second path may comprise a second gain configured to range to the second path prior to being combined with the first path. The first and second gains may be configured to operate independently of each other. The feedback section may comprise a signal from outside the signal source. The first path may include at least one of a dithering function, a subranging function, and pulse width modulation in series with an output of the second path. The second path may be configured to at least one of vary a DC offset of the low frequency signal faster than a low frequency response time of the servo loop and vary a DC offset of the low frequency transient information faster than a low frequency response time of the servo loop.

[0011] All devices in the signal source may share the same clock. At least one of the first and second paths and the feedback section may comprise at least one of a phase shift and a group delay. The signal source may comprise a third path for generating a substantially high frequency signal, and the combination circuit may be configured to combine the outputs of the first, second and third paths into a source signal. The outputs of the first path, the second path and the feedback section may be accessible to a user via a data processor. The source signal may be fed to at least one of a voltage source, a current source, a power supply, a source-measurement unit, a temperature controller, a measurement system and a radio frequency (RF) source. The signal source may be configured to provide an additional source signal independent of the source signal provided by the combination circuit. The source signal may control the source-measurement unit. The first path may be configured to add a small AC signal to at least one of a large DC signal and a low frequency ramp signal to generate a first path output. The second path may be configured to receive a high frequency signal, and the first path may be configured to receive frequency information regarding the high frequency signal. The first path may comprise filtering. The second path may comprise filtering. The signal source may comprise a third path comprising filtering. The filtering may be implemented in at least one of the first, second and third paths after the two or more DACs. The first path may be configured to generate a harmonic signal. The second path may be configured to generate a harmonic signal. The signal source may comprise a third path configured to generate a harmonic signal.

[0012] The signal source may be used in conjunction with at least one of a voltage source, a current source, a power supply, a source-measurement unit, a temperature controller, a material parameter measurement system, and a radio frequency (RF) source. The combining circuit may be configured to combine the outputs of the first and second paths into more than one source signal. The signal source may be configured to operate as a controller for the source-measurement unit. The combining circuit may be configured to combine the outputs of the first and second paths into at least one harmonic signal.

[0013] Aspects of the disclosure also include a method of providing a signal, the method including providing an input signal to a data processor and processing the input signal via the data processor. The method also includes transmitting the processed input signal to a first and second path via the data processor, the first and second paths each including two or more DACs for generating two or more frequency components. The method also includes generating a first path output of a substantially low frequency signal via the first path, generating a second path output of a substantially high frequency signal via the second path, combining the first and second path outputs into a source signal via a combinational circuit, and sensing the source signal via a feedback section. The method further includes providing the sensed source signal to a servo loop via the feedback section, and maintaining the source signal substantially in line with the input signal via the servo loop using the sensed source signal. The present invention provides, for example, the following: (Item 1) 1. An analog signal source, comprising: two or more digital-to-analog converters (DACs) that combine to generate one or more frequency components; a first path for generating a substantially low frequency signal, the first path comprising a first of the DACs; a second path for generating a substantially high frequency signal, the second path comprising a second of the DACs; and a data processor for processing an input signal and providing said processed input signal to said first and second paths; a combining circuit configured to combine outputs of the first and second paths into the source signal; a feedback portion configured to sense the source signal; a servo loop configured to use the sensed source signal and adjust it as necessary to maintain the source signal substantially in line with the input signal; 1. An analog signal source comprising: (Item 2) Providing the processed input signal to the first and second paths comprises: feeding a DC input to the first path; feeding a low frequency input to at least one of the first path and the second path; feeding a high frequency input to at least one of the first path and the second path; Item 1. The signal source according to item 1, comprising at least one of: (Item 3) Maintaining the source signal to substantially match the input signal may include Removing DC errors; Removing low frequency errors; and Maintaining the integrity of the high frequency signal. 3. The signal source according to any one of items 1 and 2, comprising at least one of: (Item 4) 4. The signal source of any one of claims 1-3, wherein the bandwidth of the feedback portion is substantially higher than the bandwidth of the first path. (Item 5) 5. The signal source of any one of claims 1-4, wherein sensing the source signal includes comparing the input signal to the output signal. (Item 6) The processing of the input signal by the data processor comprises: Removing high frequency signals that are higher than a bandwidth of the first path but within a bandwidth of the feedback section; removing high frequency signals that are higher than a bandwidth of the feedback section and higher than a bandwidth of the first path; 6. The signal source according to item 5, comprising at least one of: (Item 7) 7. The signal source of any one of claims 1-6, wherein the first path is configured for direct current (DC). (Item 8) 9. The signal source of any one of claims 1-8, wherein the feedback portion comprises at least one analog-to-digital converter (ADC). (Item 9) The data processor includes an ADC feedback, and the processing of the input signal by the data processor includes: comparing the input signal with a source signal; removing high frequency signals from the input signal that are higher than a bandwidth of the first path but within a bandwidth of the feedback section; 8. The signal source according to item 7, comprising: (Item 10) The second pathway is More than one frequency, A complex waveform characterized by multiple frequency components 10. The signal source of any one of items 1-9, configured to adapt at least one of: (Item 11) 11. The signal source of any one of claims 1-10, wherein the first path comprises an integrator. (Item 12) the first path comprises a first gain configured to range to the first path prior to being combined with the second path; the second path comprises a second gain configured to range the second path prior to being combined with the first path; the first and second gains being configured to operate independently of each other; 12. A signal source according to any one of items 1-11. (Item 13) Item 13. The signal source of any one of items 1-12, wherein the feedback portion comprises a signal from outside the signal source. (Item 14) 14. The signal source of any one of claims 1-13, wherein the first path comprises at least one of a dithering function, a sub-ranging function, and pulse width modulation in series with the output of the second path. (Item 15) The second pathway is Varying a DC offset of the low frequency signal faster than a low frequency response time of the servo loop; Varying the DC offset of the low frequency transient information faster than the low frequency response time of the servo loop. 15. The signal source of any one of items 1-14, configured to perform at least one of the following: (Item 16) 16. The signal source of any one of claims 1-15, wherein all devices in the signal source share the same clock. (Item 17) 17. The signal source of any one of claims 1-16, wherein at least one of the first and second paths and the feedback section comprises at least one of a phase shift and a group delay. (Item 18) 18. The signal source of any one of claims 1-17, further comprising a third path for generating a substantially high frequency signal, the combining circuit being configured to combine outputs of the first, second and third paths into the source signal. (Item 19) 19. The signal source of any one of claims 1-18, wherein outputs of the first path, second path and feedback section are accessible to a user via the data processor. (Item 20) The signal source of any one of items 1-19, wherein the signal source is used in conjunction with at least one of a voltage source, a current source, a power supply, a source measurement unit, a temperature controller, a material parameter measurement system, and a radio frequency (RF) source. (Item 21) the combining circuit is configured to combine the outputs of the first and second paths into more than one source signal. the signal source is configured to act as a controller for a source-measurement unit; and The combining circuit is configured to combine the outputs of the first and second paths into at least one harmonic signal. 21. The signal source according to any one of items 1-20, wherein the signal source is at least one of: (Item 22) 1. A method of providing a signal, comprising: providing an input signal to a data processor; processing the input signal via the data processor; transmitting the processed input signal through the data processor to first and second paths, the first and second paths comprising two or more digital-to-analog converters (DACs) for generating two or more frequency components; generating a first path output of a substantially low frequency signal via the first path; generating a second path output of a substantially high frequency signal via the second path; combining the first and second path outputs into a source signal via a combining circuit; sensing said source signal via a feedback portion; providing said sensed source signal to a servo loop via said feedback portion; maintaining said source signal substantially in line with said input signal via said servo loop using said sensed source signal; A method comprising: [Brief description of the drawings]

[0014] [Figure 1A] FIG. 1A illustrates a non-hybrid source signal chain 100 that applies the same gain chain to both the AC and DC components.

[0015] [Figure 1B] FIG. 1B shows a 100 mV AC signal superimposed on a 5V DC signal, illustrating the difficulty of configuring gain in signal chain 100 for both signals.

[0016] [Figure 1C] FIG. 1C is an inset of the 100 mV AC signal shown in FIG. 1B.

[0017] [Figure 1D] FIG. 1D shows a 1 mV AC signal superimposed on a 5V DC signal, illustrating the difficulty of configuring gain in signal chain 100 for both signals.

[0018] [Figure 1E] FIG. 1E is an inset of the 1 mV AC signal shown in FIG. 1D.

[0019] [Figure 1F] FIG. 1F shows a 100 μV AC signal superimposed on a 5V DC signal, illustrating the difficulty of configuring gain in signal chain 100 for both signals.

[0020] [Figure 1G] FIG. 1G is an inset of the 100 μV AC signal shown in FIG. 1F.

[0021] [Diagram 2] FIG. 2 illustrates a hybrid system in the form of an exemplary source signal chain 200.

[0022] [Diagram 3] FIG. 3 illustrates another example source signal chain 300 in which AC circuits are prevented from affecting the accuracy of DC circuits.

[0023] [Figure 4] FIG. 4 is an example circuit 400 illustrating filter configuration considerations for signal chain 300.

[0024] [Diagram 5] FIG. 5 is a signal flow diagram 500 representing the circuit 400 .

[0025] [Figure 6] FIG. 6 shows a response 600 of the circuit 400 when the transition frequency of the high pass filter 312 is small and the transition frequency of the low pass filter 314 is large.

[0026] [Figure 7] FIG. 7 shows a response 700 of the circuit 400 when the transition frequency of the high pass filter 312 and the transition frequency of the low pass filter 314 are both equal to one.

[0027] [Figure 8] FIG. 8 shows a response 800 of circuit 400 when the transition frequency of high pass filter 312 is 0.01 and the transition frequency of low pass filter 314 is 100.

[0028] [Figure 9] FIG. 9 shows the response 900 of circuit 400 when the secondary poles of filters 312 and 314 are each displaced 100 times from the primary poles.

[0029] [Figure 10] FIG. 10 shows the response 1000 of the circuit 400 when the low frequency secondary pole is displaced by a factor of 100 and the high frequency secondary pole is omitted.

[0030] [Figure 11] FIG. 11 shows the response 1100 of the circuit 400 when the high frequency secondary pole is displaced by a factor of 100 and the low frequency secondary pole is omitted.

[0031] [Figure 12] FIG. 12 shows the response 1200 of circuit 400 when the secondary poles of both filters 312 and 314 are displaced by a factor of 1×10 −4 .

[0032] [Figure 13] FIG. 13 illustrates an example source signal chain 1300 having a DC feedback loop.

[0033] [Figure 14] FIG. 14 illustrates another example source signal chain 1400 in which the DC feedback is digitized feedback using an ADC.

[0034] [Figure 15] FIG. 15 illustrates one exemplary variation of a digitally synthesized source channel 1500.

[0035] [Figure 16] FIG. 16 illustrates an example variation of a source wave table 1600 that may be used in conjunction with the digital source channel 1500 within the context of this disclosure.

[0036] [Figure 17] FIG. 17 is a waveform 1700 generated by plotting the source wave table 1600 that may be used in conjunction with a digital source channel 1500 within the context of this disclosure.

[0037] [Figure 18A] FIG. 18A shows the stepped waveform from low pass filtering the waveform of FIG. 17A.

[0038] [Figure 18B] FIG. 18B shows a smoothed version of the waveform of FIG. 18A.

[0039] [Figure 18C] FIG. 18C is a generalized DAC transfer function 1850 that may be used in accordance with aspects of the disclosure.

[0040] [Figure 19] FIG. 19 illustrates a source signal chain 1900 between an example head unit 1960 and an example source pod 1950 in accordance with an aspect of the present disclosure.

[0041] [Figure 20] FIG. 20 illustrates an exemplary measurement system that may be used in accordance with aspects of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0042] Detailed Description Hybrid Supply

[0043] Overview

[0044] This disclosure addresses the problem of improving source signal quality using a methodology called "hybrid feed." Hybrid feeds generate high quality analog source signals from both AC and DC components. It adjusts the gain paths for AC and DC differently to take advantage of the different advantages of AC and DC feed electronics. The source signals have extremely low levels of noise and glitching. They have flexibility and range that exceeds traditional single range feeds. Variations of this disclosure include hybrid feeds that use DACs, generally referred to herein as "hybrid DAC systems." These solutions are particularly useful for applications that require low noise signals with a high degree of repeatability and reliability. U.S. Provisional Patent Application No. 63 / 057,745 discusses material measurement applications of hybrid feeds in more detail.

[0045] A hybrid DAC system may include, among other components, DACs, ADCs, filtering elements, combining means (e.g., summation elements and integrators), feedback elements, etc. A hybrid DAC may include a software-implemented processor or processing means, which may also include analog and / or digital hardware. The processing algorithms can precisely control the operation and result in a highly accurate output signal.

[0046] Hybrid DAC systems offer flexibility in configuring source signals for different requirements. They may control several properties through fine-tuning of components, gain, and other variables and / or selection of specific components. Configurable properties include resolution, quantization, update rate, offset error, gain error, differential nonlinearity error, integral nonlinearity error, calibration error, output noise, dynamic range, output bandwidth, source impedance, output drive capability, switching noise, phase error, drift versus time and temperature, etc. These and other concepts are explored below.

[0047] Exemplary converter systems that may be used within the context of this disclosure include any suitable DAC or ADC. A specific example includes a DAC that uses an ADC (e.g., a Linear Technology 24-bit LTC2400) as a feedback element in a digitally corrected loop to achieve 20-bit performance. In this variation, the DC DAC may be a slave to the ADC feedback. A comparator may determine the difference between the intended output and the actual output of the system. A corrected code may be generated and presented to the DAC, for example. This may correct for drift and nonlinearity of the DAC to a desired accuracy. The ADC may set the accuracy in some variations. It may digitally sense the feedback by placing the ADC at the load. These and many other methods for using DACs (e.g., LSB / MSB subranging, pulse width modulation (PWM), and fast integration) are within the scope of this disclosure.

[0048] Comparison with non-hybrid supply

[0049] For comparison, FIG. 1A illustrates a non-hybrid source signal chain 100 that applies the same gain chain to both the AC and DC components. In this specification, when describing signal feeds, the words "chain" and "path" will be used synonymously. Use of the chain 100 is typically limited to situations where the AC 102 and DC 104 inputs are generally within the same or similar ranges. Here, the small AC signal relative to the DC signal has only a few bits of resolution. In this narrow set of situations, both the AC and DC signals can be amplified together. However, such a single gain chain has no flexibility. The only parameter in the chain 100 with any variability is the gain of the variable amplifier 120, which is applied to both the AC and DC components simultaneously. Also, since all of the components carry both signal types, this topology precludes independent configuration of the AC and DC portions of the source signal.

[0050] In the chain 100, element 106 sums the AC 102 and DC 104 signals together before applying any gain. DAC 108 converts the combined AD / DC signal to analog. It then provides the combined signal to a variable amplifier 120. The gain of the amplifier 120 may be selected by a user. It may also be ranged automatically and / or according to feedback from an "analog output" signal at the sample 110 (e.g., via a feedback loop (not shown)). From the variable amplifier 120, the combined signal is sent to the sample 110 via a second amplifier 112.

[0051] As used herein, the term "sample" will be used synonymously with the phrase "device under test (DUT)." It should be understood that either the DUT or the "sample" can be a sample of a device or a material. Often, in the context of materials measurements disclosed herein, a device (e.g., a transistor) is created for the express purpose of testing a material (e.g., a semiconductor material) in the created device.

[0052] 1B-1G show the effect of a small AC signal superimposed on a larger DC signal. They show that although the AC signal is below the noise floor in these cases, it may be detectable (e.g., with a lock-in amplifier). The user can set the amplitude of the AC signal with a higher resolution (e.g., 16 bits as opposed to 2 or 3).

[0053] Figures 1B and 1C show the highest AC amplitude of the three cases, a 100 mV AC sine wave 140 superimposed on a 5 V DC offset 130. Figure 1B shows several cycles of the wave 140 as measured by a digital multimeter. Figure 1B is a blowup of some of those cycles.

[0054] 1B and 1C, it is easy to see that the wave 140 is barely visible when superimposed at a scale appropriate for viewing the DC signal 130. However, a large gain suitable for configuring the small AC signal 140 would also magnify errors and noise in the larger DC signal 130. At the same time, a smaller gain more appropriate for the large DC signal 130 would not properly amplify the AC signal 140. Thus, configuring a single gain chain (e.g., 100) to simultaneously accommodate both the DC 130 and AC 140 signals would be difficult and error-prone.

[0055] 1D and 1E further illustrate the point with an AC signal 150 with an even smaller amplitude of 1 mV. The AC signal 150 is superimposed on a 5V DC offset 130. As shown in most detail by inset 1E, the amplitude of the wave 150 is imperceptible when viewed at the appropriate scale with respect to the DC offset 130. FIGS. 1F and 1G produce the same point with an even smaller 100 μV signal, which is a typical source amplitude in material characterization experiments. As shown in inset 1G, the 100 μV amplitude of the wave 160 is buried within and dominated by the DC offset 130 and the noise of the instrumentation (oscilloscope). In the present situation, which is typical for material applications, ranging into a single gain chain 100 to compose both signals is impractical or impossible in practice due to the resolution of practical converters.

[0056] Hybrid Source Variation

[0057] The following variations contrast the features and operation of an exemplary hybrid signal generation system / source with that of the non-hybrid chain 100. The hybrid system separates the low and high frequency generation paths, allowing separate and independent configuration of each over a range of frequencies. The separate configurations simultaneously generate high quality AC signals and very accurate high resolution DC signals. Combining the separately configured signals provides an analog output signal with a superior range of frequencies and reliability over that achieved using a single path (e.g., chain 100).

[0058] 2 illustrates a relatively simple hybrid system in the form of an exemplary source signal chain 200. Chain 200 dedicates separate DACs 206 and 208 and amplifiers 220a and 220b to separately constructing AC and DC paths. The separate constructing paths are labeled in FIG. 2 as "AC / High Frequency Path" and "DC / Low Frequency Path," respectively. Element 210 sums the outputs of both paths and sends them to amplifier 212. After amplification, the analog output signal is routed to sample 110.

[0059] More specifically, the chain 200 feeds an AC input 202 to an "AC / high frequency path", which first converts the signal using a DAC 206 and then amplifies it using a variable gain 220a. Separately, a DC input 204 is fed to a "DC / low frequency path", which converts the signal using a DAC 208 and then amplifies it using a variable gain 220b. Both paths are summed at 210 and then provided to the sample 110 via an amplifier 212. The variable gains 220a and 220b may be set by range and other settings, or by user preferences, protocols, or may be preset. Separate ranging is particularly important with respect to hybrid generation techniques. High frequency AC generation containing separate ranging allows the hybrid DAC to generate a small AC signal that rides on a large DC output (see, for example, Figures 1B-1G).

[0060] 3 illustrates another example source signal chain 300 in which the AC and DC configurations are separate and parallel. Chain 300 prevents the AC path ("AC / high frequency path") from affecting the accuracy of the DC path ("DC / low frequency path") by including AC input 302 in the configuration of DC contributions to the analog output signal. Chain 300 can achieve reasonable accuracy while using less circuitry (i.e., fewer components than more complex variations) than many hybrid systems.

[0061] More specifically, as shown in Figure 3, the chain 300 sends the sum of the AC 302 and DC 304 inputs at 306 to a DAC 308 in the DC / low frequency path. It routes the AC 302 input in parallel to a DAC 310 in the AC / high frequency path. The chain 300 then amplifies both the AC signal and the composite DC / AC signal by variable amplifiers (220a and 220b, respectively). The gains 220a and 220b for the DC and AC circuits can be different and configured respectively. They may be set in the same manner as described above for the gains 220a and 220b in the context of Figure 2.

[0062] The AC component signal is then high-pass filtered to remove low frequency components (312). The DC component signal is low-pass filtered to remove high frequency components (314). The filtered AC and DC signals are then summed at 316. The summed signal is amplified at 318 and sent to the sampler 110.

[0063] Chain 300 allows for parallel configuration of AC DAC 310 and DC DAC 308 and their associated path components, while facilitating separate ranging capabilities in each path (e.g., to address the ranging issues shown in FIGS. 1B-1G). This removes DC errors from the AC generation path and vice versa via filters 312 and 314. Specifically, high-pass filter / AC 312 removes DC / low frequencies from the AC / high frequency path. In other words, DC errors that may be generated by AC DAC 310 and amplifier 220a are rejected by filter 312 so that they do not affect the DC output performance in the analog output signal. Low-pass filter / DC 314 similarly removes AC errors from the DC / low frequency path.

[0064] The addition of AC (high frequency) to DC / low frequency path at 306 of the chain 300 allows separate AC and DC paths to be constructed and then combined at the output.

[0065] However, the frequency limitations of the AC / high frequency and DC / low frequency paths of the chain 300 may affect the overall performance. Variability and / or drift in the crossover frequencies of the filters 312 and 314 may cause frequency errors due to initial component tolerances, temperature drift, and drift over time. These effects may cause the bandwidth of the AC and DC paths to be substantially different from the filter transition frequencies that provide a flat frequency response in the sample 110. The output may be significantly degraded when the parasitic or inherent frequency performance of the paths approaches the transition frequencies of the filters 312 and 314.

[0066] Selecting the filters 312 and 314 (primary) poles and their secondary characteristics can produce a relatively flat output spectrum from DC to high frequencies. Filters 312 and 314, and more specifically, their respective transition frequencies and poles, should be selected with these considerations in mind.

[0067] Figures 4-12 are helpful in exploring these filter considerations. Figure 4 shows an example circuit 400 illustrating the filter considerations for chain 300. High frequency signals traverse upper path 402. Low frequencies traverse lower path 404. The high and low frequency signals are combined by a series of RC circuits 406. Note that circuits other than RC circuits 406 may also provide the recombination. Element 408 is an AC signal source. Figure 5 is a signal flow diagram 500 representing circuit 400. For simplicity of presentation, the values ​​in Figure 5 are normalized.

[0068] 6-12 explore the effect that the transition frequencies of the high-pass filter 312 and the low-pass filter 314 in 400 have on changing the frequency response of the circuit. They show how a flat frequency response in the system 300 cannot be achieved for some practical values ​​of these frequencies. In particular, different variations 600-1200 based on different transition frequencies of the filters 312 and 314 exhibit dramatically different frequency performance. They show how changes in the filters 312 and 314 can tune the frequency performance of the chain 300.

[0069] 6 shows an extreme frequency response 600 of circuit 400 where ω1 and ω2 are very far away from the normalized frequency and there is no perceptible dip in the frequency response. In variation 600, the transition frequency ω1 of high pass filter 312 is small (1×10 in relative units). -18 ), the transition frequency ω2 of the low pass filter 314 is large (1×10 18 ). These conditions effectively remove filters 312 and 314 from circuit 400. They set a low enough transition for high pass filter 312, so that it passes essentially all frequencies. They also set a high enough transition for low pass filter 314, so that it also passes substantially all frequencies. As shown in FIG. 6, the response 600 of circuit 400 under these conditions does not vary with frequency.

[0070] 7 shows another extreme case 700. In 700, the transition frequency of the high pass filter 312 and the transition frequency of the low pass filter 314 are both equal to 1. In this configuration, the second order and first order filter poles of both filters 312 and 314 are matched. The arrangement is often called a buffered twin-tee filter. The overall response is a "dip" 702 at 1 Hz.

[0071] 8 and 9 show an intermediate case. FIG. 8 shows the response 800 of the circuit 400 when the transition frequency ω1 of the high-pass filter 312 is 0.01 and the transition frequency ω2 of the low-pass filter 314 is 100. In this configuration, the secondary poles of each of the two filters 312 and 314 are displaced 10 times from their primary poles. This changes the narrow notch 702 of 700 into a wider "valley" 802 that extends over two decades in frequency. The depth is about 1% of the maximum value. FIG. 9 symmetrically shows the response 900 when the secondary poles of the filters 312 and 314 are displaced 100 times from their primary poles. This occurs when the transition frequency ω1 of the filter 312 is 0.1 and that of the filter 314 is 10. As shown in FIG. 9, the response 800 exhibits a valley 902 that is about 10% deep and about 4 decades wide in frequency. In each case in Figures 7-9, the frequency response is symmetric about 1 Hz.

[0072] 10 and 11 show the case where the response is offset from the 1 Hz center. Specifically, FIG. 10 shows the response of circuit 400 when the low frequency secondary pole is displaced by a factor of 100 and the high frequency secondary pole is essentially omitted. This is because the transition frequency ω of filter 312 is shifted by a factor of 1×10 -18 and occurs when the transition frequency ω1 of filter 312 is 0.01 and the ω2 of filter 314 is 100. The response 1000 exhibits a valley 1002 centered at 10 Hz and is approximately 1% deep. The width of the valley 1002 spans approximately two decades in frequency. FIG. 11 shows the response 1100 of circuit 400 when the high frequency secondary pole is displaced by a factor of 100 and the low frequency secondary pole is omitted. This occurs when the transition frequency ω1 of filter 312 is 0.01 and the ω2 of filter 314 is 1×10 -18 The response 1100 exhibits a valley 1102 centered at 0.1 Hz, with a depth of about 1% and a width of about 2 decades in frequency.

[0073] The variation in circuit 400 represented by 600-1100 shows that the secondary poles of filters 312 and 314 can be substantially displaced to minimize valleys at the crossovers. For example, the secondary poles can be displaced by 1×10 -4 10 times (corresponding to the transition frequency ω1 of filter 312 of 0.0001 and the transition frequency ω2 of filter 314 of 10,000) results in a depth of 1×10 -4 and width 1×10 8 In applications where the dual path approach involves a negative feedback loop (e.g., chopper stabilized operational amplifiers), the valley 1202 may be of little importance and a deviation of 10x or 100x, etc. may be sufficient. In an alternative, the valley 1202 may be eliminated using a second order transfer function that is more complex than the single pole assumed in 600-1200.

[0074] 13 illustrates another example hybrid DAC source signal chain 1300 with a DC feedback loop. The DC feedback loop can correct errors in the analog output signal. It can keep the AC and DC paths separate while allowing for a flat response from high frequency down to DC.

[0075] In the chain 1300, the AC and DC inputs 1302 and 1304, respectively, are summed (1306) and sent to a DC constituent path via a DAC 1308. The AC input 1302 is fed to the AC constituent path via a DAC 1310. The AC constituent path then passes through a variable amplifier 220a, which is then summed (1312) with the signal from the DC constituent path after it has been amplified by 220b. The gains 220a and 220b may be set as discussed above in the context of Figures 9 and 10. The sum 1312 is then fed to the sample 130 via an amplifier 1314.

[0076] DC feedback is accomplished as follows: The DC component path from the DAC 1308 is summed 1316 with the DC input signal after DAC 1308 processing and then sent to variable amplifier 220c via 1318. The gain 220c may be set as discussed above with respect to 220a and 220b. The DC component signal is then summed with the AC component signal at 1312. This feedback loop essentially treats the AC path as a disturbance to the DC path, allowing for a flat frequency output to the sample 130.

[0077] In chain 1300, the AC / high frequency path and the DC / low frequency path are separate, allowing for component configuration and separate path ranging. The DC / low frequency path of 1300 can be configured for DC (e.g., via DAC 1308 and / or gain 220b). In particular, DAC 1308 can be configured with low DC offset. In addition, output summation element 1312 can be selected to reduce DC errors in the output to amplifier 1314 and the final analog output to sample 110. Also, feedback elements (i.e., amplifier 220 and summation 1316) can be selected with low DC offset and low drift with temperature and time.

[0078] These adjustments can eliminate the nonlinear aspects of the frequency response shown in Figures 7-11. The feedback path in 1300 can eliminate the valley 1201 in the response 1200 (Figure 12). The feedback path can also compensate for negative effects on DC performance caused by other parts of the chain 1300. For example, it can compensate for DC offset errors such as those emanating from components such as amplifier 1314, AC path DAC 1310, and amplifier 220a, among other components. Combining AC and DC paths with a feedback path where the AC path is a disturbance to the DC path (see summation of AC and DC signals in 1306 sent to the DC path) can allow for a nearly seamless transition between ranging and other variations in the measurement system. In addition, this can introduce a feedback line that responds only to low frequencies (e.g., DC configuration).

[0079] The DC / low frequency path components are generally configured less for bandwidth performance compared to components designed for AC. This encompasses most of the components in the DC / low frequency "servo loop" 1330, which refers to the DC DAC and feedback mechanism (i.e., the loop 1330 encompassed by elements 1304, 1306, 1308, 1316, 1318, 220b, 1312, 1314, 220c, and 1316 in the chain 1300). This typically means that the DC / low frequency servo loop 1330 can only respond effectively to frequencies up to a defined frequency limit. Above that upper limit, spurious offsets, lags, errors, and other problems can appear. Below this, the DC / low frequency path can handle signals with relatively few problems. The chain 1300 sends all frequencies to the DC / low frequency path via 1306, which sums together the AC 1302 and DC 1304 inputs. The feedback path can subtract the output frequency from the DC / low frequency path after the DAC 1308. The DC / low frequency servo loop 1330 can adjust the analog output signal until the feedback path and the DC DAC 1308 output are equal. Changes in the analog output can be continuously compensated for to form the DC / low frequency output.

[0080] In the chain 1300, the servo loop 1330 may have a limited bandwidth. The loop 1330 will not affect frequencies outside of its bandwidth. In this case, the bandwidth of the feedback path and the DC / low frequency DAC 1308 output response may need to be significantly higher than that of the servo loop 1330. The feedback signal and the DC / low frequency DAC can be designed to filter out high frequencies before being sent to the rest of the DC / low frequency path. This can prevent the servo loop 1330 from filtering out small amounts of high frequency signals that may cause errors. The frequencies fed into the AC / high frequency path can be summed directly to the output after the servo loop 1330 at 1312. Frequencies higher than the bandwidth of the feedback path are not fed back to the input through the feedback path and are not affected by the servo loop 1330.

[0081] The DC and low frequency performance of the chain 1300 can be defined by the DC / low frequency DAC 1308, the feedback loop subtraction element 1316, the feedback gain element 220c, along with DC parasitic errors. These DC regulated errors can include thermoelectric errors, low frequency crosstalk, loop parasitic capacitance, among others. Proper layout of the circuit board (e.g., printed circuit board (PCB)) on which 1300 is mounted can reduce such DC parasitic errors.

[0082] Improved DC / low frequency performance of the chain 1300 can be achieved for low frequency signals generated by either the AC / high frequency DAC 1310 or the DC / low frequency DAC 1308. The signals can be summed at 1306 to the input of the servo loop 1330 and fed back through a feedback path. This can allow the servo loop 1330 to configure these signals. This maintains the AC / high frequency performance characteristics, since frequencies generated above the frequency response of the servo loop 1330 are not affected.

[0083] There are advantages to generating low frequency signals in either the AC and DC paths. Frequencies above the bandwidth of the servo loop 1330 must be fed through the AC / high frequency path, but low frequency signals can be fed through either path (or both at the same time). Generating all frequencies in the AC / high frequency path can be advantageous, especially for signals with consistent amplitude. In this case, AC gain performance can be held constant across the bandwidth of the system. Ranging in this mode can also allow small amplitude AC signals to be generated in either path. This allows the generation of small AC signals superimposed on a DC (or low frequency AC) offset. The technique can generate accurate high resolution ramps where signals with very small AC frequencies ride on the ramp.

[0084] Separate ranging of AC and low frequency signals, as in chain 1300, can be useful in other scenarios. For example, separate ranging can help generate source signals for harmonic measurements with dual frequencies. Accurately generating signals with harmonic frequencies can greatly improve the accuracy, reliability, and repeatability of material characterization measurements.

[0085] It may also be advantageous to generate a low frequency signal via the DC / Low Frequency path in the chain 1300. Because the feedback path of the servo loop 1300 dominates its performance characteristics, the DC / Low Frequency path can generate a very fine resolution signal without ranging. Doing so in combination with the loop 1300 integration can generate an accurate high resolution signal. Ranging can provide additional improvement in resolution or noise, potentially at the expense of range change error. The architecture of the chain 1300 also facilitates increased resolution of the DC / Low Frequency path. The chain 1300 uses, in part, an integrator 1318 for this purpose. Variations include other methods such as dithering DACs, pulse width modulation, etc.

[0086] 14 shows another example source signal chain 1400. In 1400, the DC feedback is digitized using an ADC. This brings the feedback configuration to the hybrid technique described above. This introduces less DC inaccuracy and enhances the DC DAC resolution. This takes advantage of the fact that ADCs are typically more accurate than DACs, resulting in better control.

[0087] The AC / high frequency path in chain 1400 is the same as in chain 1300 of FIG. 13. The DC / low frequency path of chain 1400 differs from that of chain 1300 primarily by including ADC 1402 in the DC feedback as part of its servo loop 1430. However, there are some other subtle differences. Specifically, DC feedback from sample 110 is fed to ADC 1402 via variable amplifier 720c, where it is converted to an analog signal. That signal is then summed 1404 with DC, the combined DC input / AC input signal from 1306. The combined signal is then fed to amplifier 720b via DAC 1308, 1406, and then summed with the AC constituent signal at 1312. The gains 720a, 720b, and 720c can all be set as described above with respect to FIG. 13.

[0088] The ADC 1402 feedback in the chain 1400 can provide better accuracy and resolution because the best implementation of a low frequency ADC can have better performance than a DAC. The feedback path in 1400 is also combined in the digital domain (i.e., with 1404). This can reduce errors from analog combination. Digitizing the feedback can allow for the generation of composite waveforms that would be extremely difficult to generate using analog feedback. Digital feedback can also enhance the resolution of the DC DAC 1308. This allows for the use of a lower quality, cheaper DAC 1308 since the accuracy is determined by the ADC feedback path. The accuracy of the DC DAC 1308 does not affect the accuracy of the analog output signal. The integrator 1406 in the DC / low frequency path also enhances the resolution of the path. Since the resolution and accuracy are primarily achieved through the feedback path, averaging a high bit ADC 1402 with good linearity and noise can easily increase the overall resolution to well below the noise specification of the system.

[0089] The improved accuracy of the chain 1400 also allows for the feeding of analog output signals back from remote locations. The feedback path in the chain 1400 can eliminate many of the errors and offsets that occur in the cabling and interconnections.

[0090] Chains 1300 and 1400 can improve the transient response. A fast changing DC signal can be processed in the digital domain. A sudden change in the DC signal can be sent to the AC / high frequency path. Because the AC / high frequency path can change its output quickly, large spikes in the DC signal can be expected. The signal can be processed to cause large fast transients in the AC path. Once the DC signal reaches its new level, the servo loop 1330 / 1430 can servo the DC signal again. This technique allows for fast changes, fast settling times, and preserves the full resolution of the DC integrator and accuracy of the DC loop.

[0091] Chains 200, 300, 1300, and 1400 are all shown with two generation paths, DC / low frequency and AC / high frequency. However, it should be understood that more than two generation paths are possible and may be advantageous. Three or more generation paths may handle, for example, increased signaling bandwidth. They may add more DACs to the signal processing and improve accuracy. Generating very high frequencies and combining the outputs may provide a high quality output with a wide bandwidth.

[0092] Digital Source Compositing

[0093] Variations of the disclosed system can use direct digital synthesis to generate the source signal. Direct digital signals provide more consistency and control over the source signal. Digital signals also tend to have less interference and noise. These problems ultimately result in noise or ambiguity in the output signal, so using direct digital synthesis can improve measurement accuracy and repeatability. Although a specific example is described below, it should be understood that any suitable mechanism for providing a digital source signal can be used in conjunction with any of the variations described herein.

[0094] 15 illustrates one exemplary variation of a digitally synthesized source channel 1500. The digitally synthesized source channel 1500 may provide the analog signal inputs 102, 202, 302, 1302, and 1402 described above. The source processing 1502 shown in FIG. 15 may include any of the signal chains disclosed herein, including chains 200, 300, 1300, and 1400.

[0095] The sources may be derived primarily from a waveform table 1502. Table 1502 may be an algorithm (software or firmware) that generates waveforms based on inputs 1504. The inputs 1504 may instruct table 1502 to select a particular waveform to deliver. The inputs 1504 may select, among other things, the frequency, phase shift, and lag. Each of the inputs 1504 is not necessarily used in all variations. They may be stored locally, entered directly by a user, generated by other software, and / or according to a measurement or diagnostic protocol.

[0096] Reference signals 1506 may also be input to the table 1502. The references 1506 include source references from lock-in amplifiers (e.g., source lock-in references from channels 1-3) and phase-locked loop (PLL) references. The references 1506 may be selected by a mux 1508 and sent to a multiplexer (mux) 1510 where they are combined with the waveform settings 1504 and additional references 1516. The references 1506 may be selected by a user, other software, and / or according to a measurement or diagnostic protocol. They are then sent to the table 1502 for selection of a specific waveform to output as the source signal. The output waveforms from the table 1502 may then be further processed (1502) by any signal processing methods described herein and provided to the source pod 104. The channel 1500 may also use a lock-in reference with an optional phase shift 1504 rather than being selected directly via the input 1504. In this case, the frequency and phase of the source can be determined by a lock-in reference signal (e.g., reference 1512). An optional phase shift 1504 can set the phase relationship with reference 1512. The external phase relationship can be configured to be different for each channel.

[0097] Figures 16 and 17 show an example variation of a source wave table 1600 that may be provided by element 1502 of digital source 1500. Waveform 1700 of Figure 17 is generated by plotting the data in table 1600. Figure 17 plots a single period of waveform 1700 in relative units.

[0098] In one variation, the source signal supply algorithm can iteratively increment through a table 1600 that represents one or more periods of the waveform. The table 1600 provides waveform amplitude (output) versus time (position), both in normalized units. Using normalized units is not a requirement. It is convenient to scale either the voltage or the time dependence of the waveform based on the input 1304. In this way, the table 1600 determines the shape of the waveform 1700. The rate at which the algorithm cycles through the table 1600, called the phase increment (element 1504, FIG. 15), determines the frequency of the waveform 1700.

[0099] The "position" in table 1600 need not change by integer numbers. In some variations, for example, a higher resolution phase accumulator (element 1504, FIG. 15) can be used to track the phase of waveform 1700. Phase accumulator 1504 can increment by a non-integer amount and convert this phase to a position in table 1600.

[0100] The waveform 1700 of FIG. 17 can be smoothed and / or made continuous, either by the table itself 1502 or at the source processing 1510 using a low pass filter. For low pass smoothing, w Discrete output values ​​with non-zero widths in can replace the values ​​in the table of FIG. 16. Note that table 1600 can vary substantially in length and complexity. In some variations, it can have thousands (e.g., 4,000 or more) entries. This produces a "stepped" output waveform 1802, as shown in FIG. 18A. Applying an analog low pass filter to 1802 (e.g., the AC DAC output) produces a smooth waveform 1804, shown in FIG. 18B. The AC waveform 1804 can be combined with a DC offset setting (not shown) and fed into a closed loop DC supply system in source processing 1510. This can be part of the hybrid supply variations discussed above in the context of FIGS. 2-14.

[0101] Transfer Function

[0102] 18C shows a generalized form of an example transfer function 1850 that may be used in conjunction with the chain 1400 of the present disclosure. The intent of the analysis performed by 1850 and the associated transfer function is to demonstrate the flat frequency response of the system of 1400. FIG. 18 reduces the circuit to more general signal elements for analysis of the transfer function.

[0103] The transfer function 1850 has an output V out It controls the source that governs it, i.e., AC (V2) or DC (V1).

[0104] Generalized Hybrid DAC Transfer Function V out 1852 is given by: [ka]

[0105] It can be assumed that the inner loop is faster than the outer loop. The gain k establishes the transition frequency. Below this frequency, V1(s) dominates. Above this frequency, V1(s)+ dominates. If A1V1(s)=A2V2(s), the outer loop becomes transparent, leaving the transfer function of the inner loop. In the case of a voltage source, G(s) is the open loop transfer function of the opamp and H(s) is unity. In the case of a current source, G(s) is the open loop transfer function of the opamp and H(s) is the sense resistor and amplifier.

[0106] In either case, the gain A1 should exceed A2, i.e. the DC range should be equal to or greater than the AC range. For the current source, the sense resistor is selected for the higher range.

[0107] Measurement System Integration

[0108] Measurement system overview

[0109] 19 shows an example source 1900 configuration with a "source pod" 1950 configuration. The source configuration 1900 connects to and controls the source pod 1950 by a "head" or control unit 1960. While FIG. 19 shows a system 1900 with a particular hybrid DAC, it should be understood that the system 1900 may accommodate any such system disclosed herein. In particular, the system 1900 may accommodate the chains 100, 200, 300, 1300, and 1400.

[0110] The sample source signal (i.e., the signal sent by chain 1900 to sample 110) is a combination of an AC signal (the "AC component signal") and a DC signal (the "DC component signal"). These signals are combined to generate the sample source signal via a variable gain 220 that can be dynamically ranged to avoid glitching in the signal. The DC component signal is generated based on DC feedback from the combination of the AC and DC component signals.

[0111] More specifically, the AC configuration DAC 1914 provides the AC configuration source signal to an amplifier 1916 at a source pot 1950 where it is combined with the DC configuration source signal by 1918 and provided to the amplifier 220 where it is ranged and then onto the sample 110. The waveform shape, amplitude, frequency, and phase of the source provided to the AC configuration DAC 1914 may be preprogrammed, selected by a user, and / or selected from among options by the head 1960 according to user preferences and / or protocols (e.g., measurement or diagnostic). The output of 1918 is also provided to the DC configuration ADC 1926 of the head 102 as DC feedback via an amplifier 1924. The DC feedback signal is then sent to the DC configuration DAC 1930 via an offset 1928 and then routed to 1918 via an amplifier 1932.

[0112] 19, the range of the ranged amplifier 220, along with other settings, can be selected via a "range and other settings" signal transmitted via range and other settings element 1922 of head 102. The range and other settings may be preprogrammed, selected by the user, and / or selected from among options by head 1960 according to user preferences and / or protocols (e.g., measurement or diagnostic).

[0113] The source pod 1950 may further include digital (non-analog) circuitry capable of performing various functions including analysis, communication of data, command information, power regulation, timing, and communication with external devices. In a variation, the source pod 1950 has the ability to deactivate this non-analog circuitry while providing its source signal or performing measurements. Doing so reduces the amount of interference and noise in the signal or measurement. For the same reason, the digital signals in the source pod 1950 may be isolated from the measurement pod 1950 and head 102.

[0114] Other variations of the system 1900 include any suitable number of heads 1960, source pods, and measurement pods 1950. For example, FIG. 20 shows another exemplary variation 2000 in which the head unit 1960 may have six channels that may support three measurement type pods 1950a and three source type pods 1950b. In this variation, the head 1960 is also shown connected to an optional computer 2002 and three exemplary sampled or devices under test (DUTs) 110. Again, this configuration is merely exemplary. There is no requirement for an equal number of measurement pods 1950a and source pods 1950b. One source 1950a may, for example, provide excitation signals for all three DUTs 110.

[0115] Balanced current supply

[0116] 19, the source pod 1950 may further include a balanced current supply (BCS) capability 1932. The BCS 1932 is described in more detail in U.S. Patent No. 6,501,255 (the '255 patent) to Pomeroy, entitled "DIFFERENTIAL CURRENT SOURCE WITH ACTIVE COMMON MODE REDUCTION," filed October 4, 2001, which is incorporated herein by reference in its entirety.

[0117] Simply put, source systems (e.g., 1900) can be vulnerable to current spikes and / or inconsistent loads that cause asymmetries between inputs / outputs. These spikes can harm components of those systems. There is a need for current balancing in the materials measurement context, where both floating and grounded loads can be addressed without substantially modifying or rewiring the circuitry. The BCS1932 addresses this need.

[0118] As discussed in the '255 patent, the BCS1932 drives the load with two modified Howland current sources that are out of phase with each other. In the context of the system 1900, the BCS1932 uses a sense resistor to measure a source current associated with a source signal ("sample source signal" in FIG. 19) transmitted from the source pod 1950 to the sample. This then varies the resistance range of the sense resistor according to the magnitude of the measured source current. The BCS1932 can also balance the load by modifying the resistance of one (or both) of the source and measurement pods 1950 based on the source signal measurement. For example, when the measured source current exceeds a certain threshold, the BCS1932 can increase or decrease the resistance of one or both pods 1950 to reduce the current until it falls below the threshold. The threshold current can represent, for example, a current above which damage would occur to one or more of the components of the system 1900.

[0119] Variations including system 1900 and others may employ chains 100, 200, 300, 1300, and 1400 for additional purposes other than those described above. For example, chains 100, 200, 300, 1300, and 1400 may be employed in conjunction with or as part of a current or voltage source (e.g., to regulate a voltage or current output). They may be employed in temperature controllers, other parameter controllers, power supplies, or source measurement units (e.g., devices that measure the output of a current or voltage source). They may, for example, operate as controllers in conjunction with or for source measurement units. They may be employed in other measurement systems (e.g., systems that measure material parameters, i.e., current / voltage (IV) characteristics, resistivity, superconducting transport, applied current, voltage, current, transconductance, breakdown / leakage, etc.). The chains 100, 200, 300, 1300, and 1400 may also be incorporated into devices that transmit, receive, and / or provide radio frequency (RF) energy and / or communications and / or other communications.

[0120] Although chains 200, 300, 1300, and 1400 are discussed above as providing only a single analog output, it should be understood that they may provide multiple analog outputs. For example, sum 316 of chain 300 may be modified such that it generates two or more combinations of signals from the AC / high frequency path and the DC / low frequency path. Similar modifications can be made to 210 and 1312. As discussed above, they can generate one or more harmonic signals.

[0121] Although various inventive aspects, concepts, and features of the present invention may be described and illustrated herein as embodied in combination in exemplary embodiments, these various aspects, concepts, and features may be used in many alternative embodiments, either individually or in various combinations and subcombinations thereof. Unless expressly excluded herein, all such combinations and subcombinations are intended to be within the scope of the present invention. Still further, various alternative embodiments of various aspects, concepts, and features of the present invention may be described herein, such as alternative materials, structures, configurations, methods, circuits, devices and components, software, hardware, control logic, form, compatibility, and function, but such descriptions are not intended to be a complete or exhaustive list of available alternative embodiments, whether currently known or later developed. Those skilled in the art may readily adopt one or more of the inventive aspects, concepts, or features into additional embodiments and uses within the scope of the present invention, even if such embodiments are not expressly disclosed herein.

[0122] In addition, although some features, concepts, or aspects of the invention may be described herein as being preferred arrangements or methods, such description is not intended to imply that such features are required or necessary unless expressly so described. Still further, exemplary or representative values ​​and ranges may be included to aid in understanding the present disclosure, however, such values ​​and ranges are not intended to be construed in a limiting sense, and are intended to be critical values ​​or ranges only if so expressly described. Still further, exemplary or representative values ​​and ranges may be included to aid in understanding the present disclosure, however, such values ​​and ranges are not intended to be construed in a limiting sense, and are intended to be critical values ​​or ranges only if so expressly described. Parameters identified as "approximately" or "about" a specified value are intended to include both the specified value and values ​​within 10% of the specified value, unless expressly described otherwise. Furthermore, it is to be understood that the drawings accompanying this application may, but need not be, to scale and thus may be understood as teaching various ratios and proportions apparent in the drawings. Also, while various aspects, features, and concepts may be expressly identified herein as being inventive or forming part of the invention, such identification is not intended to be exclusive; rather, there are inventive aspects, concepts, and features that are fully described herein without being expressly identified as such or as part of a specific invention, and the invention may instead be set forth in the appended claims. The description of an exemplary method or process is not limited to the inclusion of every step as required in all cases, nor should the order in which the steps are presented be construed as required or necessary unless expressly so recited.

Claims

1. 1. An analog signal source, comprising: two or more digital-to-analog converters (DACs) combined to generate one or more frequency components, the two or more DACs comprising a first DAC and a second DAC; a first path generating a low frequency signal and outputting the low frequency signal as an output of the first path, the first path comprising the first DAC; a second path, the second path generating a high frequency signal and outputting the high frequency signal as an output of the second path, the second path comprising the second DAC; a data processor for processing an input signal and providing a direct current (DC) component of the input signal to the first path and an alternating current (AC) component of the input signal to the second path; a combining circuit configured to combine the outputs of the first and second paths into a source signal; a feedback portion configured to sense the source signal; the first DAC, the data processor, the combinational circuit, and the feedback portion form a servo loop, the servo loop using the sensed source signal; the servo loop removing DC errors; said servo loop removing low frequency errors; an analog signal source configured to reduce a difference between the source signal and the input signal by at least one of:

2. 2. The analog signal source of claim 1, wherein the bandwidth of the feedback portion is higher than the bandwidth of the first path.

3. 2. The analog signal source of claim 1, wherein sensing the source signal comprises comparing the input signal to an output signal of the analog signal source.

4. The processing of the input signal by the data processor comprises: Removing high frequency signals that are higher than a bandwidth of the first path but within a bandwidth of the feedback section; removing high frequency signals that are higher than a bandwidth of the feedback portion and higher than a bandwidth of the first path; 4. The analog signal source of claim 3, comprising at least one of:

5. The analog signal source of claim 1 , wherein the feedback portion comprises at least one analog-to-digital converter (ADC).

6. The data processor includes an ADC feedback, and the processing of the input signal by the data processor includes: comparing the input signal to the source signal; removing high frequency signals from the input signal that are higher than a bandwidth of the first path but within a bandwidth of the feedback section; 2. The analog signal source of claim 1, comprising:

7. The analog signal source of claim 1 , wherein the first path comprises an integrator.

8. 2. The analog signal source of claim 1, wherein the first path comprises at least one of a dithering function, a sub-ranging function, and a pulse width modulation function in series with the output of the second path.

9. The second pathway includes: Varying a DC offset of the low frequency signal faster than a low frequency response time of the servo loop; Varying the DC offset of the low frequency transient information faster than the low frequency response time of the servo loop; The analog signal source of claim 1 , configured to do at least one of the following:

10. 2. The analog signal source of claim 1, wherein the analog signal source has a single clock.

11. 2. The analog signal source of claim 1, wherein at least one of the first and second paths and the feedback section comprises at least one of a phase shift and a group delay.

12. 2. The analog signal source of claim 1, further comprising a third path for generating a high frequency signal, the combining circuit being configured to combine outputs of the first, second and third paths into the source signal.

13. An analog signal source as described in claim 1, wherein the data processor is connected to a computer, and the data processor provides waveform shapes, amplitudes, frequencies, and phases of the outputs of the first path, second path, and feedback section to the computer for selection by a user via the data processor.

14. 10. The analog signal source of claim 1, wherein the analog signal source is used in conjunction with at least one of a voltage source, a current source, a power supply, a source measurement unit, a temperature controller, a material parameter measurement system, and a radio frequency (RF) source.

15. The analog signal source configured to act as a controller for a source measurement unit; or 2. The analog signal source of claim 1, wherein the high frequency signal is a harmonic of the low frequency signal.

16. 1. A method of providing a signal, comprising: providing an input signal to a data processor; processing the input signal via the data processor; transmitting a direct current (DC) component of the input signal to a first path and an alternating current (AC) component of the input signal to a second path via the data processor, the first and second paths comprising two or more digital-to-analog converters (DACs) for generating two or more frequency components; generating a first path output of a low frequency signal via the first path; generating a second path output of a high frequency signal via the second path; combining the first and second path outputs into a source signal via a combining circuit; sensing said source signal via a feedback portion; providing the sensed source signal to a servo loop via the feedback section, the first DAC, the data processor, the combinational circuit, and the feedback section constituting the servo loop; using the sensed source signal; the servo loop removing DC errors; said servo loop removing low frequency errors; reducing the difference between the source signal and the input signal via the servo loop by at least one of A method comprising:

Images