Super beta triode transistor and its manufacturing method

Abstract

The present invention provides a super β triode transistor and a method for fabricating the same, which includes: providing a substrate, forming an isolation buried layer of a first conductivity type and a doping layer of the first conductivity type based on the substrate, forming a base region of a second conductivity type in the doping layer, forming a doping island of the second conductivity type having a doping concentration greater than that of the base region on the periphery of the base region, forming a collector region of the first conductivity type in the doping layer spaced apart from the base region, and forming an emitter region of the first conductivity type in the base region. The super β triode transistor of the present invention can effectively reduce the vertical electric field in the base region, reduce the lateral leakage current of the device, and better achieve a balance between preventing punch-through in the base region and improving the current amplification factor.

Description

[Technical field]

[0001] The present invention relates to the field of semiconductor device design and manufacturing, and more particularly to a super-β triode transistor and a method for fabricating the same.

[0002] This application claims priority based on a Chinese patent application filed with the China Patent Office on July 28, 2021, bearing application number 202110858844.X and entitled "Super β triode transistor and its manufacturing method", the entire contents of which are incorporated herein by reference. [Background technology]

[0003] A triode transistor has two N-type regions surrounding a P-type region. One N-type region is the collector, the other N-type region is the emitter, and the P-type region is the base. Depending on the voltage biasing scheme of the triode transistor, the triode transistor will have different operating modes. When the emitter-base junction is reverse biased and the collector-base junction is reverse biased, the triode transistor operates in the off mode. When the emitter-base junction is forward biased and the collector-base junction is reverse biased, the triode transistor operates in the active mode. When the emitter-base junction is forward biased and the collector-base junction is forward biased, the triode transistor operates in the saturation mode. When the triode transistor is used as an amplifier, the active mode is used, and when the triode transistor is used as a switching device, the off mode and the saturation mode are used. One of the parameters of a triode transistor is the common emitter current gain, commonly called β or HFE. When in active mode, the common emitter current gain is the ratio of the collector current to the base current. Summary of the Invention [Problem to be solved by the invention]

[0004] In the conventional triode transistor, in order to reduce the base recombination, ensure sufficient base transport coefficient, and improve the common emitter current gain, a shallower base region and a lower base doping concentration are generally pursued, but this brings the risk of larger punch-through in the base region of the triode transistor. In addition, the uniform distribution of the base region concentration in the lateral direction (the width direction of the conductive channel) will lead to the generation of leakage current in the non-working base region of the lateral NPN, and the conventional triode transistor also has the disadvantages of lower emitter junction injection efficiency, larger leakage current, smaller current gain, etc.

[0005] In view of the above-mentioned shortcomings of the prior art, the present invention aims to provide a super β triode transistor and a manufacturing method thereof, to solve the problem of the higher risk of punch-through in the base region of the triode transistor structure in the prior art. [Means for solving the problem]

[0006] In order to achieve the above and other related objects, the present invention provides a method for manufacturing a super β triode transistor, including: providing a substrate; forming an isolated buried layer of a first conductivity type and a doped layer of a first conductivity type based on the substrate, the isolated buried layer being located at a bottom of the doped layer; forming a base region of a second conductivity type in the doped layer; forming a doped island of a second conductivity type having a doping concentration greater than a doping concentration of the base region on an outer periphery of the base region; forming a collector region of a first conductivity type in the doped layer spaced apart from the base region; and forming an emitter region of a first conductivity type in the base region.

[0007] Optionally, the doping concentration of the base region is in the range of 5e17cm -3 ~8e17cm -3and the doping concentration of the doping islands is in the range of 5e18cm -3 That's all.

[0008] Optionally, the doping concentration of the collector region is greater than the doping concentration of the doping layer and the doping concentration of the isolation buried layer is greater than the doping concentration of the doping layer.

[0009] Optionally, the junction depth of the base region implant is less than or equal to the junction depth of the doping island implant.

[0010] Optionally, the manufacturing method further includes forming a contact region of a second conductivity type in the base region and forming a contact region of a first conductivity type in the collector region, wherein a doping concentration of the contact region of the second conductivity type is greater than a doping concentration of the doping island and a doping concentration of the contact region of the first conductivity type is greater than a doping concentration of the collector region.

[0011] Optionally, a bottom of the collector region is connected to at least a portion of the isolation buried layer and a bottom of the doping island is connected to at least a portion of the isolation buried layer.

[0012] Optionally, forming an isolated buried layer of a first conductivity type and a doped layer of a first conductivity type in the substrate, the isolated buried layer being located at the bottom of the doped layer, includes forming an isolated buried layer inside the substrate by an ion implantation process and forming a doped layer on a surface layer of the substrate by an ion implantation process, or includes forming an isolated buried layer on a surface layer of the substrate by an ion implantation process and forming a doped layer on the substrate by an epitaxial process.

[0013] The present invention further provides a super β triode transistor including: a substrate having an isolated buried layer of a first conductivity type formed therein; a doped layer of a first conductivity type formed on a surface layer of the substrate or on the substrate, the isolated buried layer being a doped layer of the first conductivity type located at a bottom of the doped layer; a base region of a second conductivity type formed in the doped layer; a doped island of a second conductivity type formed on an outer periphery of the base region and having a doping concentration higher than that of the base region; a collector region of a first conductivity type formed in the doped layer and spaced apart from the base region; and an emitter region of a first conductivity type formed in the base region.

[0014] Optionally, the doping concentration of the base region is in the range of 5e17cm -3 ~8e17cm -3 and the doping concentration of the doping islands is in the range of 5e18cm -3 That's all.

[0015] Optionally, the doping concentration of the isolation buried layer is in the range of 1e17cm -3 ~3e17cm -3 and the doping concentration of the doped layer is in the range of 1e16cm -3 ~4e16cm -3 and the doping concentration of the collector region is in the range of 1e17cm -3 ~5e17cm -3 and the doping concentration of the emitter region is in the range of 1e17cm -3 ~5e17cm -3 It is.

[0016] Optionally, a contact region of a second conductivity type is further formed in the base region, the doping concentration of the contact region of the second conductivity type being greater than the doping concentration of the doping island, and a contact region of a first conductivity type is further formed in the collector region, the doping concentration of the contact region of the first conductivity type being greater than the doping concentration of the collector region.

[0017] Optionally, a bottom of the collector region is connected to at least a portion of the isolation buried layer and a bottom of the doping island is connected to at least a portion of the isolation buried layer.

[0018] Optionally, the doping concentration of the collector region is greater than the doping concentration of the doping layer and the doping concentration of the isolation buried layer is greater than the doping concentration of the doping layer.

[0019] Optionally, the junction depth of the base region implant is less than or equal to the junction depth of the doping island implant.

[0020] Optionally, the base region is formed at an upper surface of the doped layer, and a surrounding cover structure consisting of the doped island and the isolating buried layer surrounds the base region. Effect of the Invention

[0021] As described above, the super β triode transistor and the manufacturing method thereof of the present invention have the following beneficial effects.

[0022] In the present invention, a high concentration of ions is implanted in the periphery of the base region to form a doping island having a doping concentration greater than that of the base region, and a concentration gradient is formed between the doping island and the base region. On the one hand, the doping island can assist the lateral depletion at the bottom and assist the quick pinch-off at the bottom of the base region to prevent punch-through in the base region, while still reducing the recombination in the base region and improving the common emitter current gain; on the other hand, the presence of the doping island allows the non-operating base region to have a higher P-type concentration, which can greatly reduce the lateral leakage current of the NPN, thereby generating a higher current gain for the device.

[0023] The super β triode transistor of the present invention can effectively reduce the vertical electric field in the base region, reduce the lateral leakage current of the device, and achieve a better balance between preventing punch-through in the base region and improving the current amplification factor. [Brief description of the drawings]

[0024] [Figure 1] 1A to 1C are schematic diagrams showing steps in a method for manufacturing a super β triode transistor according to an embodiment of the present invention; [Diagram 2] 1A to 1C are schematic diagrams showing steps in a method for manufacturing a super β triode transistor according to an embodiment of the present invention; [Diagram 3] 1A to 1C are schematic diagrams showing steps in a method for manufacturing a super β triode transistor according to an embodiment of the present invention; [Figure 4] 1A to 1C are schematic diagrams showing steps in a method for manufacturing a super β triode transistor according to an embodiment of the present invention; [Diagram 5] 1A to 1C are schematic diagrams showing steps in a method for manufacturing a super β triode transistor according to an embodiment of the present invention; [Figure 6] 1A to 1C are schematic diagrams showing steps in a method for manufacturing a super β triode transistor according to an embodiment of the present invention; [Figure 7] FIG. 1 is a schematic diagram illustrating a configuration of a super β triode transistor according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] Hereinafter, the embodiments of the present invention will be described with reference to specific examples, and those skilled in the art will be able to understand other advantages and effects of the present invention from the contents disclosed in the present specification. The present invention can be implemented or applied by further different specific embodiments, and various modifications or changes can be made to each detail of the specification based on different viewpoints and applications without departing from the spirit of the present invention.

[0026] In describing the embodiments of the present invention in detail, for convenience of description, the cross-sectional views showing the device structure are not enlarged according to the general ratio, and the illustrated schematic diagrams are merely illustrative and do not limit the scope of protection of the present invention herein, and in actual fabrication, the three-dimensional spatial dimensions of length, width and depth should be included.

[0027] For ease of explanation, spatial relationship terms such as "below," "below," "lower than," "below," "above," "on" and the like are used herein to describe the relationship of one element or feature to another element or feature depicted in the figures. It should be understood that these spatial relationship terms are intended to include other orientations than those shown in the figures of a device in use or operation. It should be noted that when a layer is referred to as being "between" two layers, that layer may be the only layer located between the two layers, or there may be one or more intervening layers between the two layers.

[0028] In the context of the present invention, a structure in which a first feature is described is located "on" a second feature may include embodiments in which the first and second features are formed such that they are in direct contact, or may include embodiments in which another feature is formed between the first and second features, where the first and second features may not be in direct contact.

[0029] For illustrative purposes, the drawings provided by this embodiment are only for schematic illustration of the basic idea of ​​the present invention, and only the parts relevant to the present invention are shown in the drawings, not the number, shape, and dimensions of the parts in actual implementation, and the form, number, and proportion of each part in actual implementation may be changed arbitrarily, and the layout form of the parts may also be more complex.

[0030] Conventional triode transistors generally pursue shallower base regions and lower base region doping concentrations to reduce base region recombination, ensure sufficient base region transport coefficient, and improve common-emitter current gain, but this brings about the risk of larger punch-through in the base region of triode transistors. In addition, the uniform distribution of base region concentration in the lateral direction (the width direction of the conductive channel) will result in the generation of leakage current in the non-working base region of the lateral NPN, and conventional triode transistors also suffer from lower emitter junction injection efficiency, larger leakage current, smaller current gain, and other disadvantages. In the present invention, a high concentration of ions is implanted into the outer periphery of the base region 104 to form a doping island 105 having a doping concentration greater than that of the base region 104, and a concentration gradient is formed between the doping island 105 and the base region 104. On the one hand, the doping island 105 can assist the lateral depletion at the bottom and assist the quick pinch-off at the bottom of the base region to prevent punch-through in the base region, while still reducing the recombination in the base region and improving the common emitter current gain; on the other hand, the presence of the doping island 105 makes the non-operating base region have a higher P-type concentration, which can greatly reduce the lateral leakage current of the NPN, thereby generating a higher current gain for the device.

[0031] To solve the above problems, as shown in FIGS. 1 to 7, the present embodiment provides a method for fabricating a super β triode transistor, which includes the following steps.

[0032] As shown in FIG. 1, first, in step 1), a substrate 101 is provided, and a first conductive type isolation buried layer 102 is formed in the substrate 101 .

[0033] As an example, the substrate may be a semiconductor substrate such as a Si substrate, a Ge substrate, a SiGe substrate, an SOI (silicon on insulator), or a GOI (germanium on insulator). In other embodiments, the semiconductor substrate may be a substrate including other elemental or compound semiconductors such as GaAs, InP, or SiC, or may be a stacked structure such as Si / SiGe, or may be other epitaxial structures such as SGOI (silicon germanium on insulator). In this embodiment, the substrate is a Si substrate.

[0034] For example, a first conductive type isolation buried layer 102 can be formed in the substrate by an ion implantation process and an annealing process. In this embodiment, the doping concentration of the isolation buried layer 102 is in the range of 1e17 cm -3 ~3e17cm -3 It is.

[0035] As shown in FIG. 2, in step 2), a first conductive type doped layer 103 is formed on the substrate 101, and the isolation buried layer 102 is located at the bottom of the doped layer.

[0036] As an example, a first conductive type doped layer 103 can be formed on the substrate 101 by a vapor phase epitaxial process, and preferably, the material of the doped layer 103 is selected to be the same material as that of the substrate 101, and in this embodiment, the material of the doped layer 103 is Si.

[0037] The doping concentration of the doped layer 103 is in the range of 1e16 cm -3 ~4e16cm -3 In one embodiment, the doping concentration of the doping layer 103 is 2e16 cm -3 By adjusting the doping concentration of the doping layer 103, the turn-on resistance and breakdown voltage of the device can be effectively adjusted to meet the performance requirements of different devices.

[0038] In another embodiment, the isolated buried layer 102 may be first formed inside the substrate by an ion implantation process, and then a doped layer 103 may be formed on the surface of the substrate by an ion implantation process, and the depth position of the isolated buried layer 102 may be controlled so that the isolated buried layer 102 is located at the bottom of the doped layer 103.

[0039] As shown in FIG. 3, subsequently, in step 3), a base region 104 of a second conductivity type is formed in the doping layer 103 .

[0040] For example, a second conductive type base region 104 can be formed in the doping layer 103 through a photolithography process, an ion implantation process, and an annealing process, and the doping concentration of the base region 104 can be in the range of 5e17 cm -3 ~8e17cm -3 In one specific embodiment, the doping concentration of the base region 104 is 6e17 cm -3 The doping concentration of the base region 104 in this embodiment is lower, that is, the doping concentration of the base region 104 is further reduced and is lower than the doping concentration of the conventional base region, so that the recombination in the base region 104 can be effectively reduced, and the transport coefficient of the base region 104 can be ensured to be sufficient, while still reducing the risk of punch-through in the base region, and further shielding the leakage current of the non-operating base region in the lateral direction, and thus the balance between the three can be better achieved.

[0041] 4, in step 4), a doped island 105 of a second conductivity type having a doping concentration greater than that of the base region 104 is formed around the periphery of the base region 104. The bottom of the doped island 105 is connected to at least a portion of the isolation buried layer 102.

[0042] In this embodiment, the junction depth of the implantation of the base region 104 is equal to or less than the junction depth of the implantation of the doping island 105. The base region 104 is formed on the upper surface of the doping layer 103. A surrounding cover structure consisting of the doping island 105 and the isolated buried layer 102 surrounds the base region 104.

[0043] For example, a doping island 105 of a second conductivity type having a doping concentration greater than that of the base region 104 can be formed around the periphery of the base region 104 by a photolithography process, an ion implantation process, and an annealing process. In this embodiment, the doping concentration of the doping island 105 is in the range of 5e18 cm3. -3 or more, for example 8e18cm -3 ~9e18cm -3 In the present invention, by implanting a high concentration of ions at the periphery of the base region 104 to form a doping island 105, and forming a concentration gradient between the high concentration of the doping island 105 and the low concentration of the base region 104, on the one hand, the doping island 105 can assist the lateral depletion at the bottom and the quick pinch-off at the bottom of the base region 104 to prevent the punch-through of the base region 104, while still reducing the recombination in the base region and improving the common emitter current gain; on the other hand, the presence of the doping island 105 makes the non-operating base region 104 have a higher P-type concentration, which can greatly reduce the lateral leakage current of the NPN, thereby generating a higher current gain for the device.

[0044] As shown in FIG. 5, subsequently, in step 5), a collector region 106 of a first conductivity type spaced apart from the base region 104 is formed in the doping layer 103 .

[0045] For example, a first conductivity type collector region 106 can be formed in the doping layer 103 by a photolithography process, an ion implantation process, and an annealing process, the collector region 106 being spaced apart from the base region 104, and the bottom of the collector region 106 being connected to at least a part of the isolation buried layer 102. As an example, the doping concentration of the collector region 106 is in the range of 1e17 cm -3 ~5e17cm -3 In one specific embodiment, the doping concentration of the collector region 106 is 3e17 cm -3 It is.

[0046] As shown in FIG. 6, subsequently, in step 6), a contact region 107 of a second conductivity type having a doping concentration greater than the doping concentration of the doping island 105 is formed in the base region 104 to reduce the contact resistance of the base region 104.

[0047] Finally, in step 7), a first conductive type emitter region 108 is formed in the base region 104, as shown in FIG.

[0048] For example, a first conductivity type emitter region 108 can be formed in the base region 104 by a photolithography process, an ion implantation process, and an annealing process, and the doping concentration of the emitter region 108 can be in the range of 1e17 cm. -3 ~5e17cm -3 In one specific embodiment, the doping concentration of the emitter region 108 is 5e17 cm -3The method further includes forming a contact region 109 of a first conductivity type in the collector region 106, the contact region 109 having a doping concentration greater than that of the collector region 106. As an example, the emitter region 108 of the first conductivity type and the contact region 109 of the first conductivity type may be formed in the same doping step. That is, the emitter region 108 of the first conductivity type and the contact region 109 of the first conductivity type may be formed simultaneously by a single photolithography process, an ion implantation process, and an annealing process. This can reduce process costs and improve process efficiency. In another embodiment, the collector region 106, the base region 104, and the emitter region 108 are all extended to the surface of the substrate, and the extension method includes, but is not limited to, implanting a contact region, extending a doped region, and providing a through hole.

[0049] In this embodiment, the first conductivity type is N-type conductivity and the second conductivity type is P-type conductivity. Of course, in other embodiments, the first conductivity type may be P-type conductivity and the second conductivity type may be N-type conductivity.

[0050] 7, the present embodiment further provides a super β triode transistor, which includes a substrate 101 having a first conductive type isolation buried layer 102 formed therein, a doped layer 103 of a first conductive type formed on a surface of or on the substrate 101, the isolation buried layer 102 being located at the bottom of the doped layer 103, a base region 104 of a second conductive type formed in the doped layer 103, a doped island 105 of a second conductive type formed around the periphery of the base region 104 and having a doping concentration higher than that of the base region 104, a collector region 106 of a first conductive type formed in the doped layer 103 and spaced apart from the base region 104, and an emitter region 108 of a first conductive type formed in the base region 104.

[0051] As an example, the substrate 101 may be a semiconductor substrate such as a Si substrate, a Ge substrate, a SiGe substrate, an SOI (silicon on insulator), or a GOI (germanium on insulator). In other embodiments, the semiconductor substrate may be a substrate including other elemental or compound semiconductors such as GaAs, InP, or SiC, or may be a stacked structure such as Si / SiGe, or may be other epitaxial structures such as SGOI (silicon germanium on insulator). In this embodiment, the substrate is a Si substrate.

[0052] As an example, the doping concentration of the doped layer 103 is in the range of 1e16 cm -3 ~4e16cm -3 In one embodiment, the doping concentration of the doping layer 103 is 2e16 cm -3 By adjusting the doping concentration of the doping layer 103, the turn-on resistance and breakdown voltage of the device can be effectively adjusted to meet different device performance requirements.

[0053] As an example, the doping concentration of the base region 104 ranges from 5e17 cm -3 ~8e17cm -3 In one specific embodiment, the doping concentration of the base region 104 is 6e17 cm -3 The doping concentration of the base region 104 in this embodiment is lower, that is, the doping concentration of the base region 104 is further reduced and is lower than the doping concentration of the conventional base region, so that the recombination in the base region 104 can be effectively reduced, and the transport coefficient of the base region 104 can be ensured to be sufficient, while still reducing the risk of punch-through in the base region, and further shielding the leakage current of the non-operating base region in the lateral direction, and thus the balance between the three can be better achieved.

[0054] In this embodiment, the doping concentration of the doping islands 105 is in the range of 5e18cm -3 or more, for example 8e18cm -3~9e18cm -3 In the present invention, by implanting a high concentration of ions at the periphery of the base region 104 to form a doping island 105, and forming a concentration gradient between the high concentration of the doping island 105 and the low concentration of the base region 104, on the one hand, the doping island 105 can assist the lateral depletion at the bottom and the quick pinch-off at the bottom of the base region 104 to prevent the punch-through of the base region 104, while still reducing the recombination in the base region and improving the common emitter current gain; on the other hand, the presence of the doping island 105 makes the non-operating base region 104 have a higher P-type concentration, which can greatly reduce the lateral leakage current of the NPN, thereby generating a higher current gain for the device.

[0055] In this embodiment, the junction depth of the implantation of the base region 104 is equal to or less than the junction depth of the implantation of the doping island 105. The base region 104 is formed on the upper surface of the doping layer 103, and a surrounding cover structure consisting of the doping island 105 and the isolated buried layer 102 surrounds the base region 104.

[0056] As an example, the doping concentration of the isolation buried layer 102 is in the range of 1e17 cm -3 ~3e17cm -3 The doping concentration of the collector region 106 is in the range of 1e17 cm -3 ~5e17cm -3 In one specific embodiment, the doping concentration of the collector region 106 is 3e17 cm -3 The doping concentration of the emitter region 108 is in the range of 1e17 cm -3 ~5e17cm -3 In one specific embodiment, the doping concentration of the emitter region 108 is 5e17 cm -3 It is.

[0057] In this embodiment, a contact region 107 of a second conductivity type is further formed in the base region 104, the contact region 107 having a doping concentration greater than that of the doping island 105. A contact region 109 of a first conductivity type is further formed in the collector region 106, the contact region 109 having a doping concentration greater than that of the collector region 106.

[0058] In this embodiment, the bottom of the collector region 106 is connected to at least a portion of the isolated buried layer 102 , and the bottom of the doping island 105 is connected to at least a portion of the isolated buried layer 102 .

[0059] In this embodiment, the first conductivity type is N-type conductivity and the second conductivity type is P-type conductivity. Of course, in other embodiments, the first conductivity type may be P-type conductivity and the second conductivity type may be N-type conductivity.

[0060] As described above, the super β triode transistor and the manufacturing method thereof of the present invention have the following beneficial effects.

[0061] In the present invention, a high concentration of ions is implanted into the outer periphery of the base region 104 to form a doping island 105 having a doping concentration greater than that of the base region 104, and a concentration gradient is formed between the doping island 105 and the base region 104. On the one hand, the doping island 105 can assist the lateral depletion at the bottom and assist the quick pinch-off at the bottom of the base region to prevent punch-through in the base region, while still reducing the recombination in the base region and improving the common emitter current gain; on the other hand, the presence of the doping island 105 makes the non-operating base region have a higher P-type concentration, which can greatly reduce the lateral leakage current of the NPN, thereby generating a higher current gain for the device.

[0062] The super β triode transistor of the present invention can effectively reduce the vertical electric field in the base region 104, reduce the lateral leakage current of the device, and achieve a better balance between preventing punch-through in the base region 104 and improving the current amplification factor.

[0063] Therefore, the present invention effectively overcomes various shortcomings of the prior art and has high industrial applicability.

[0064] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Those skilled in the art may modify or change the above embodiments without violating the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical ideas disclosed in the present invention are still included in the scope of the claims of the present invention. [Explanation of symbols]

[0065] 101 substrate, 102 isolation buried layer, 103 doped layer, 104 base region, 105 doped island, 106 collector region, 107 contact region of second conductivity type, 108 emitter region, 109 contact region of first conductivity type.

Claims

1. providing a substrate; forming an isolated buried layer of a first conductivity type and a doped layer of a first conductivity type based on the substrate, the isolated buried layer being located at a bottom of the doped layer; forming a base region of a second conductivity type in the doped layer; forming a doped island of a second conductivity type around an outer periphery of the base region, the doped island having a doping concentration greater than a doping concentration of the base region; forming a collector region of a first conductivity type in the doping layer spaced apart from the base region; forming an emitter region of a first conductivity type in the base region; A bottom of the collector region is connected to at least a portion of the isolation buried layer, and a bottom of the doping island is connected to at least a portion of the isolation buried layer. A method for manufacturing a super β triode transistor.

2. The doping concentration of the base region ranges from 5e17 cm －３ ~8e17cm －３ and the doping concentration range of the doping islands is 5e18 cm －３ That's all.

2. The method for manufacturing a super β triode transistor according to claim 1.

3. The doping concentration of the collector region is greater than the doping concentration of the doping layer, and the doping concentration of the isolation buried layer is greater than the doping concentration of the doping layer.

2. The method for manufacturing a super β triode transistor according to claim 1.

4. The junction depth of the base region implant is less than or equal to the junction depth of the doping island implant.

2. The method for manufacturing a super β triode transistor according to claim 1.

5. forming a contact region of a second conductivity type in the base region and a contact region of a first conductivity type in the collector region; The doping concentration of the contact region of the second conductivity type is greater than the doping concentration of the doping island, and the doping concentration of the contact region of the first conductivity type is greater than the doping concentration of the collector region.

2. The method for manufacturing a super β triode transistor according to claim 1.

6. forming an isolation buried layer of a first conductivity type and a doped layer of a first conductivity type based on the substrate, the isolation buried layer being located at a bottom of the doped layer; forming the isolation buried layer within the substrate by an ion implantation process; forming the doping layer on a surface of the substrate by an ion implantation process; Or, forming the isolation buried layer on a surface layer of the substrate by an ion implantation process; forming the doped layer on the substrate by an epitaxial process.

2. The method for manufacturing a super β triode transistor according to claim 1.

7. a substrate having a first conductivity type isolation buried layer formed therein; a doped layer of a first conductivity type formed on a surface layer of the substrate or on the substrate, the isolation buried layer being located at a bottom of the doped layer; a base region of a second conductivity type formed in the doped layer; a doping island of a second conductivity type formed on an outer periphery of the base region and having a doping concentration greater than a doping concentration of the base region; a collector region of a first conductivity type formed in the doping layer and spaced apart from the base region; an emitter region of a first conductivity type formed in the base region, A bottom of the collector region is connected to at least a portion of the isolation buried layer, and a bottom of the doping island is connected to at least a portion of the isolation buried layer. A super-β triode transistor characterized by:

8. The doping concentration of the base region ranges from 5e17 cm －３ ~8e17cm －３ and the doping concentration range of the doping islands is 5e18 cm －３ That's all.

8. The super-β triode transistor of claim 7.

9. The doping concentration of the isolation buried layer is in the range of 1e17 cm －３ ~3e17cm －３ and the doping concentration of the doped layer is in the range of 1e16 cm －３ ~4e16cm －３ and the doping concentration of the collector region is in the range of 1e17 cm －３ ~5e17cm －３ and the doping concentration of the emitter region is in the range of 1e17 cm －３ ~5e17cm －３ is 8. The super-β triode transistor of claim 7.

10. a contact region of a second conductivity type is further formed in the base region, the doping concentration of the contact region of the second conductivity type being greater than the doping concentration of the doping island; A contact region of a first conductivity type is further formed in the collector region, the doping concentration of the contact region of the first conductivity type being greater than the doping concentration of the collector region.

8. The super-β triode transistor of claim 7.

11. The doping concentration of the collector region is greater than the doping concentration of the doping layer, and the doping concentration of the isolation buried layer is greater than the doping concentration of the doping layer.

8. The super-β triode transistor of claim 7.

12. The junction depth of the base region implant is less than or equal to the junction depth of the doping island implant.

8. The super-β triode transistor of claim 7.

13. The base region is formed on an upper surface of the doping layer, and a surrounding cover structure consisting of the doping island and the isolation buried layer surrounds the base region.

8. The super-β triode transistor of claim 7.

14. A substrate having a first conductivity type isolation buried layer formed therein; a doped layer of a first conductivity type formed on a surface layer of the substrate or on the substrate, the isolation buried layer being located at a bottom of the doped layer; a base region of a second conductivity type formed in the doped layer; a doping island of a second conductivity type formed on an outer periphery of the base region and having a doping concentration greater than a doping concentration of the base region; a collector region of a first conductivity type formed in the doping layer and spaced apart from the base region; an emitter region of a first conductivity type formed in the base region; The base region is formed on an upper surface of the doping layer, and a surrounding cover structure consisting of the doping island and the isolation buried layer surrounds the base region. A super-β triode transistor characterized by:

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