Semiconductor mounting structure

Abstract

To provide a semiconductor mounting structure that can suppress cracks occurring in solder and effectively dissipate heat generated by a heated semiconductor.SOLUTION: It has a DRAM package 12, a SoC substrate 16 on which the DRAM package 12 is mounted, and a main substrate 18 on which the SoC substrate 16 is mounted, the SoC substrate 16 has a silicon chip 14 mounted on the side facing the main substrate 18, and the main substrate 18 has an aperture 28 at least at the position where the silicon chip 14 on the SoC substrate 16 faces.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor package structure, and more particularly to a semiconductor package structure including a plurality of semiconductor components and a plurality of substrates. [Background technology]

[0002] Patent Document 1 discloses a mounting structure in which a composite wiring board consisting of a first wiring board and a second wiring board is mounted on a third wiring board such as a motherboard. The first wiring board has an opening for accommodating an electronic component, and the second wiring board has the electronic component mounted on its lower surface. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2016-66699 A Summary of the Invention

[0004] One embodiment of the technology disclosed herein provides a semiconductor mounting structure that can effectively dissipate heat from heated semiconductor components, thereby suppressing warping of the substrate and suppressing cracks in the solder. [Means for solving the problem]

[0005] (1) A semiconductor mounting structure comprising: a first semiconductor component; a first substrate on which the first semiconductor component is mounted; and a second substrate on which the first substrate is mounted, the first substrate having a second semiconductor component mounted on a surface thereof facing the second substrate, the second substrate having an opening at least at a position on the first substrate where the second semiconductor component faces.

[0006] (2) A semiconductor mounting structure according to (1), wherein the first semiconductor component is a semiconductor package in which a first semiconductor element is resin-sealed, and the second semiconductor component is a second semiconductor element having external terminals formed on the mounting surface of the second semiconductor component.

[0007] (3) A semiconductor mounting structure according to (1) or (2), in which the first semiconductor component is mounted on the first substrate at the periphery of the mounting surface of the first semiconductor component, and the second semiconductor component is mounted on the first substrate with the mounting surface of the second semiconductor component facing the first substrate, and the mounting locations of the first semiconductor component and the second semiconductor component are formed in positions that do not overlap in the longitudinal direction of the first substrate.

[0008] (4) A semiconductor mounting structure according to any one of (1) to (3), in which the longitudinal width of the first semiconductor component is greater than the longitudinal width of the second semiconductor component, and the solder pattern of the first substrate on which the first semiconductor component is mounted is formed outside the outline of the second semiconductor component.

[0009] (5) A semiconductor mounting structure according to any one of (1) to (4), wherein the opening in the second substrate is larger than the outer shape of the second semiconductor component.

[0010] (6) A semiconductor mounting structure according to any one of (1) to (5), in which the first substrate includes a thermal deformation suppression member having the same material properties and dimensions as the second semiconductor component on the surface opposite to the surface on which the second semiconductor component is mounted.

[0011] (7) The semiconductor mounting structure of (6), wherein the thermal deformation suppression member is positioned so as to overlap the second semiconductor component via the first substrate.

[0012] (8) A semiconductor mounting structure according to any one of (1) to (7), in which a thermally conductive member is connected to the second semiconductor component.

[0013] (9) A semiconductor mounting structure according to (8), wherein the thermal conduction member has a first thermal conductor connected to the second semiconductor component, and a second thermal conductor having one end connected to the first thermal conductor through an opening and the other end arranged outside the second substrate, and the first thermal conductor is softer than the second thermal conductor.

[0014] (10) The semiconductor mounting structure of (9), wherein the other end of the second thermal conductor is connected to a housing arranged outside the second substrate.

[0015] (11) A semiconductor mounting structure according to (9) or (10), wherein the second substrate has a notch communicating with the opening, and the second thermal conductor is disposed along the notch.

[0016] (12) A semiconductor mounting structure according to any one of (1) to (11), wherein a third thermal conductor is connected to the first semiconductor component.

[0017] (13) The semiconductor mounting structure according to (12), wherein the third thermal conductor is connected to the housing.

[0018] (14) A semiconductor mounting structure according to any one of (1) to (13), in which the first substrate has a first solder pattern on both sides of which the solder patterns match.

[0019] (15) The semiconductor mounting structure of (14), wherein the second substrate has at least one second solder pattern.

[0020] (16) A semiconductor mounting structure as described in (15), in which the second solder pattern is provided in multiple locations around the opening of the second substrate.

[0021] (17) A semiconductor mounting structure according to (15) or (16), wherein the area of ​​the second solder pattern is larger than the area of ​​the individual solders forming the first solder pattern.

[0022] (18) A semiconductor mounting structure according to any one of (1) to (17), wherein the first semiconductor component is a semiconductor memory.

[0023] (19) A semiconductor packaging structure according to any one of (1) to (18), wherein the first substrate is a system-on-chip substrate. [Brief description of the drawings]

[0024] [Figure 1] FIG. 1 is a cross-sectional view of a main portion of a semiconductor mounting structure according to a first embodiment. [Diagram 2] FIG. 2 is a cross-sectional view of the mounting structure shown in FIG. 1 attached to a housing. [Diagram 3]FIG. 3A is a bottom view of the SoC substrate, and FIG. 3B is a top view of the SoC substrate. [Figure 4] FIG. 4 is a top view of the main board shown in FIG. [Diagram 5] FIG. 5 is a cross-sectional view of a main part of a mounting structure according to the second embodiment. [Figure 6] FIG. 6 is a top view of the main board employed in the mounting structure shown in FIG. [Figure 7] FIG. 7 is a cross-sectional view showing a mounting structure of the third embodiment. [Figure 8] FIG. 8 is a top view of the main board employed in the mounting structure shown in FIG. [Figure 9] FIG. 9A is a bottom view of the SoC substrate employed in the mounting structure of the fourth embodiment, and FIG. 9B is a top view of the SoC substrate. [Figure 10] FIG. 10 is a cross-sectional view of a main part of a mounting structure according to the fifth embodiment. [Figure 11] FIG. 11 is a cross-sectional view of the mounting structure shown in FIG. 10 attached to a housing. [Figure 12] In FIG. 12, 12A is an explanatory diagram showing the occurrence of warpage in the SoC substrate, and 12B is an explanatory diagram showing the suppression of warpage in the SoC substrate. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0026] In this specification, the first semiconductor component of the present invention is exemplified by a semiconductor package in which a first semiconductor element is resin-sealed.The semiconductor package is exemplified by a DRAM package in which a DRAM (Dynamic Random Access Memory) as the first semiconductor element is resin-sealed.The second semiconductor component of the present invention is exemplified by a second semiconductor element in which external terminals are formed on the mounting surface of the second semiconductor component.The second semiconductor element is exemplified by a silicon chip such as a CPU (Central Processing Unit) or a GPU (Graphics Processing Unit).

[0027] The first semiconductor element is not limited to a DRAM, and may be a semiconductor memory such as a RAM (Random Access Memory) or a ROM (Read Only Memory). The second semiconductor element is not limited to a silicon chip, and may be another second semiconductor element. Hereinafter, a semiconductor mounting structure according to an embodiment including a DRAM package and a silicon chip will be described.

[0028] Fig. 1 is a cross-sectional view of a main part showing the configuration of a semiconductor mounting structure (hereinafter, abbreviated as "mounting structure") 10 according to a first embodiment. Fig. 2 is a cross-sectional view showing a configuration example when the mounting structure 10 shown in Fig. 1 is attached to a housing 100.

[0029] As shown in FIG. 1 and FIG. 2, the mounting structure 10 includes a DRAM package 12 and a semiconductor device on which the DRAM package 12 is mounted. system The DRAM package 12 includes an on-chip substrate (hereinafter referred to as an "SoC (System on a chip) substrate") 16 and a main substrate 18 on which the SoC substrate 16 is mounted. The SoC substrate 16 has a silicon chip 14 mounted on a surface thereof facing the main substrate 18. Here, the SoC substrate 16 corresponds to the first substrate of the present invention, and the main substrate 18 corresponds to the second substrate of the present invention. For ease of explanation, the upper surfaces of the DRAM package 12, the SoC substrate 16, and the main substrate 18 in FIGS. 1 and 2 will be referred to as the upper surfaces, and the lower surfaces thereof will be referred to as the lower surfaces.

[0030] The DRAM package 12 and the SoC substrate 16 are electrically connected to each other through a solder 20 at a plurality of pads (not shown in FIGS. 1 and 2) provided on the lower surface 12B of the DRAM package 12 and the upper surface 16A of the SoC substrate 16. Similarly, the SoC substrate 16 and the main substrate 18 are electrically connected to each other through a solder 22 at a plurality of pads (not shown in FIGS. 1 and 2) provided on the lower surface 16B of the SoC substrate 16 and the upper surface 18A of the main substrate 18. According to the mounting structure 10 configured in this manner, the DRAM package 12, the SoC substrate 16, and the main substrate 18 are configured to have a three-layer structure in which the DRAM package 12, the SoC substrate 16, and the main substrate 18 are stacked in the vertical direction in FIGS. 1 and 2. The DRAM package 12, the SoC substrate 16, and the main substrate 18 are exemplified as being configured to have a rectangular shape having a longitudinal direction (the direction of the arrow A in FIGS. 1 and 3) in a plan view.

[0031] 3A shows a bottom surface 16B of the SoC substrate 16, and FIG. 3B shows a top surface 16A of the SoC substrate 16. In FIG.

[0032] As shown in 3A of Fig. 3, a rectangular silicon chip 14 is mounted in the center of the lower surface 16B of the SoC substrate 16. That is, the upper surface, which is the mounting surface of the silicon chip 14, is mounted facing the SoC substrate 16. The SoC substrate 16 is mounted on the main substrate 18 (see Fig. 1) so that the silicon chip 14 faces the main substrate 18. In addition, a plurality of pads 24 are provided in a grid pattern on the lower surface 16B of the SoC substrate 16 so as to surround the silicon chip 14 on all four sides. The silicon chip 14 becomes a heat source when the mounting structure 10 is driven.

[0033] 3B, a plurality of pads 26 are provided in a grid pattern over the entire area of ​​the top surface 16A of the SoC substrate 16. Pads (not shown) of the DRAM package 12 are electrically connected to these pads 26 via solder 20 (see FIG. 1). As a result, the bottom surface 12B, which is the mounting surface of the DRAM package 12, is mounted on the top surface 16A of the SoC substrate 16. Note that the DRAM package 12, like the silicon chip 14, becomes a heat source when the mounting structure 10 is operated.

[0034] In FIG. 4, an upper surface 18A of the main board 18 is shown.

[0035] 4, the main substrate 18 has an opening 28 at a position facing the silicon chip 14 of the SoC substrate 16 (see FIG. 1). The opening 28 corresponds to the opening of the present invention, and is formed at a position facing the silicon chip 14 when the SoC substrate 16 is mounted on the main substrate 18. As a result, the silicon chip 14 is exposed to the outside through the opening 28 in the mounting structure 10. The opening 28 functions as an opening for dissipating heat generated in the silicon chip 14 to the outside of the mounting structure 10.

[0036] 1 and 2 show only one opening 28, but the present invention is not limited to this, and a plurality of openings 28 may be formed in the main substrate 18. However, in order to effectively realize the above-mentioned heat dissipation, it is sufficient that the opening 28 is provided at least in a position facing the silicon chip 14 of the SoC substrate 16. Also, it is preferable that the opening 28 is larger than the outer shape of the silicon chip 14 when viewed from the side of the DRAM package 12. This can enhance the heat dissipation effect of the silicon chip 14, and also facilitates the work of attaching a thermally conductive member (TIM material 42) to the silicon chip 14, which will be described later.

[0037] 4, a plurality of pads 30 are provided in a grid pattern on the upper surface 18A of the main substrate 18 so as to surround the opening 28 on all four sides, and these pads 30 are respectively connected to pads 24 (see 3A in FIG. 3) of the SoC substrate 16 via solder 22 (see FIG. 1). In this way, the SoC substrate 16 is mounted on the main substrate 18. The above is the configuration of the mounting structure 10 of the first embodiment.

[0038] According to the mounting structure 10 of the first embodiment, the main substrate 18 has an opening 28 at least at a position where the silicon chip 14 of the SoC substrate 16 faces, and therefore the heat of the silicon chip 14 is dissipated to the outside of the mounting structure 10 through the opening 28. This makes it possible to suppress warping of the DRAM package 12, the SoC substrate 16, and the main substrate 18 caused by the heat of the silicon chip 14, and also makes it possible to suppress cracks occurring in the solders 20, 22.

[0039] [Comparison with Comparative Examples (Other Configuration Examples)] Meanwhile, there is another configuration example for stacking main substrate 18, SoC substrate 16, and DRAM package 12 and mounting (connecting) them by soldering, as follows. That is, there is a configuration in which SoC substrate 16 is mounted on main substrate 18, an intermediate substrate is mounted on SoC substrate 16, and DRAM package 12 is mounted on the intermediate substrate. In this configuration example, main substrate 18, SoC substrate 16, intermediate substrate, and DRAM package 12 are stacked vertically to form a four-layer structure. Also, SoC substrate 16 is mounted on upper surface 16A of SoC substrate 16 so that silicon chip 14 faces the intermediate substrate.

[0040] The main board 18, the SoC board 16, and the intermediate board are, for example, boards formed by laminating prepreg sheets and copper foils. In contrast, the DRAM package 12 and the silicon chip 14 are, for example, semiconductor components formed by laminating silicon sheets and resin sheets. in be.

[0041] Since the substrate and the semiconductor components are made of materials with different linear expansion coefficients, when the ambient temperature rises due to heat generation from the semiconductor components, the substrate or the semiconductor components will warp or swell due to the difference in the dimensions of expansion, which causes a problem that a load is locally applied to some of the solder, causing cracks in the solder.

[0042] Therefore, in the mounting structure 10 of the first embodiment, the SoC substrate 16 is mounted on the main substrate 18 so that the silicon chip 14 faces the main substrate 18, and the DRAM package 12 is directly mounted on the SoC substrate 16, thereby eliminating the intermediate substrate. With this configuration, it is possible to eliminate the factors of warping or undulation caused by the intermediate substrate, and therefore it is possible to suppress warping or undulation occurring in the substrate or semiconductor components. As a result, with the mounting structure 10 of the first embodiment, it is possible to suppress cracks occurring in the solder, thereby solving the above problem.

[0043] 2, the mounting structure 10 is attached to the housing 100 via these heat dissipation structures 40, 50. An example of the heat dissipation structures 40, 50 will be described below.

[0044] 2, the heat dissipation structure 40 includes a TIM (Thermal Interface Material) 42 attached to the silicon chip 14, and a metal member 44 having one end 44A connected to the TIM material 42 via the opening 28 and the other end 44B disposed outside the main substrate 18. Here, the TIM material 42 and the metal member 44 correspond to the heat conductive member of the present invention. The TIM material 42 corresponds to the first thermal conductor of the present invention, and the metal member 44 corresponds to the second thermal conductor of the present invention. In the embodiment, a strip-shaped sheet metal is used as the metal member 44, but the present invention is not limited thereto, and the metal member 44 may have another shape, such as a disk shape.

[0045] According to the heat dissipation structure 40 shown in FIG. 2, heat generated in the silicon chip 14 by the operation of the mounting structure 10 is transferred to the TIM material 42, then transferred from the TIM material 42 to the metal member 44, and dissipated to the outside from the outer surface of the metal member 44. As a result, according to the mounting structure 10 having the heat dissipation structure 40, the heat generated in the silicon chip 14 can be effectively dissipated to the outside. Therefore, the warping of the DRAM package 12, the SoC substrate 16, and the main substrate 18 caused by the heat of the silicon chip 14 can be further suppressed, and the cracks generated in the solders 22 and 20 can be further suppressed. In addition, the transfer of heat from the silicon chip 14 from the SoC substrate 16 to the DRAM package 12 and from the SoC substrate 16 to the main substrate 18 can be suppressed, respectively, and therefore the DRAM package 12 and the main substrate 18 can be protected from the heat of the silicon chip 14.

[0046] As another example of the heat dissipation structure 40, one end 44A of the metal member 44 and the silicon chip 14 may be directly connected, but by interposing the TIM material 42 between the end 44A of the metal member 44 and the silicon chip 14, there is an advantage that the heat of the silicon chip 14 can be effectively dissipated. Also, it is preferable to use a material softer than the metal member 44 as the TIM material 42, for example, an elastic body having shock absorbing properties and adhesiveness. This prevents the metal member 44 from being displaced when an impact occurs. Silicon chip The load on the metal member 44 can be reduced. Silicon chip Even if a relative positional misalignment occurs between the substrate 14 and the TIM material 42, the TIM material 42 can absorb the positional misalignment by elastically deforming. In this case, it is preferable to use a gel-like material in which thermally conductive particles such as metal powder are added to a resin such as silicone as the TIM material 42.

[0047] Moreover, in the heat dissipation structure 40, it is preferable that the other end 44B of the metal member 44 is connected to the housing 100 arranged outside the main board 18. As a result, the heat generated in the silicon chip 14 is transferred to the housing 100 via the TIM material 42 and the metal member 44, and is also dissipated from the housing 100 to the outside air. This allows the heat generated in the silicon chip 14 to be dissipated more effectively. The housing 100 is preferably made of a metal with high thermal conductivity, and one example is made of aluminum.

[0048] Next, a description will be given of the heat dissipation structure 50 shown in Fig. 2. This heat dissipation structure 50 has a TIM material 52 attached to the DRAM package 12. The TIM material 52 corresponds to the third thermal conductor of the present invention.

[0049] According to the heat dissipation structure 50, heat generated in the DRAM package 12 by the operation of the mounting structure 10 is transferred to the TIM material 52 and dissipated to the outside from the TIM material 52. As a result, the mounting structure 10 can effectively dissipate the heat generated in the DRAM package 12. Therefore, it is possible to prevent the heat from the DRAM package 12 from being transferred to the SoC substrate 16, the silicon chip 14, and the main substrate 18, so that the SoC substrate 16, the silicon chip 14, and the main substrate 18 can be protected from the heat of the DRAM package 12.

[0050] In the heat dissipation structure 50, it is preferable to connect the upper surface 52A of the TIM material 52 to the housing 100. As a result, the heat generated in the DRAM package 12 is transferred to the housing 100 via the TIM material 52, and is also dissipated from the housing 100 to the outside air. As a result, the heat generated in the DRAM package 12 can be dissipated more effectively. In this example, since the TIM material 52 and the housing 100 are arranged in close proximity to each other, the TIM material 52 is directly connected to the housing 100. However, in the case where the TIM material 52 and the housing 100 are arranged at a distance from each other, the TIM material 52 and the housing 100 may be connected to each other via a metal member, as in the heat dissipation structure 40. As in the TIM material 42, it is preferable to use a gel-like material in which thermally conductive particles such as metal powder are added to a resin such as silicon.

[0051] Thus, the mounting structure 10 of the first embodiment has a heat dissipation structure 40 for dissipating heat from the silicon chip 14, which is a heat source, and a heat dissipation structure 50 for dissipating heat from the DRAM package 12, which is also a heat source, so that the heat generated in the mounting structure 10 can be effectively dissipated.

[0052] The mounting structure 10 described above has two heat dissipation structures 40, 50, but it is sufficient that at least the heat dissipation structure 40 is included among the two heat dissipation structures 40, 50. This makes it possible to effectively dissipate heat from the silicon chip 14 arranged in a space where heat dissipation is difficult (the narrow space surrounded by the SoC substrate 16 and the main substrate 18). However, by including the heat dissipation structure 50, heat generated in the DRAM package 12 can also be effectively dissipated.

[0053] Other Embodiments Other embodiments will be described below.

[0054] Fig. 5 is a cross-sectional view of a main part of a mounting structure 60 according to a second embodiment. Fig. 6 is a top view showing an upper surface 62A of a main board 62 employed in the mounting structure 60. In describing the mounting structure 60 shown in Figs. 5 and 6, members that are the same as or similar to those in the mounting structure 10 shown in Figs. 1 to 4 are denoted by the same reference numerals.

[0055] The difference between the configuration of the mounting structure 60 and the mounting structure 10 is that the main board 18 of the mounting structure 10 has only the opening 28, whereas the main board 62 of the mounting structure 60 has the opening 28 and a notch 64 communicating with the opening 28. In addition, the metal member 44 is disposed along the notch 64.

[0056] As in the mounting structure 60, by arranging the metal member 44 along the cutout portion 64 of the main board 62, it is possible to reduce the thickness in the vertical direction of the mounting structure 60 including the metal member 44. In other words, it is possible to make the mounting structure 60 including the metal member 44 more compact.

[0057] Fig. 7 is a cross-sectional view of a main part of a mounting structure 70 according to a third embodiment. Fig. 8 is a top view showing an upper surface 72A of a main board 72 used in the mounting structure 70. In describing the mounting structure 70 shown in Figs. 7 and 8, members that are the same as or similar to those in the mounting structure 10 shown in Figs. 1 to 4 are denoted by the same reference numerals.

[0058] The difference between the configuration of the mounting structure 70 and the mounting structure 10 is that the main board 18 of the mounting structure 10 has only a plurality of pads 30, whereas the main board 72 of the mounting structure 70 has a plurality of pads 30 and four solder patterns 74 for heat dissipation. These solder patterns 74 are thermally connected to some of the plurality of pads 30. The solder pattern 74 corresponds to the second solder pattern of the present invention.

[0059] The solder patterns 74 are formed, for example, in a rectangular shape, and the TIM material 76 shown in Fig. 7 is attached to these solder patterns 74. One end 78A of a metal member 78 is attached to this TIM material 76, and the other end 78B of the metal member 78 is disposed outside the main board 72. The other end 78B is connected to the housing 100. Note that, although Fig. 8 illustrates an example of the main board 72 having four solder patterns 74 surrounding the rectangular opening 28, it is sufficient that at least one solder pattern 74 is provided.

[0060] As in the mounting structure 70, by providing the solder pattern 74 on the main board 72, the heat transferred from the silicon chip 14 to the main board 72 can be effectively dissipated. Furthermore, by connecting the solder pattern 74 to the metal member 78 via the TIM material 76, the heat can be dissipated even more effectively. Furthermore, by connecting the other end 78B of the metal member 78 to the housing 100, the heat can be dissipated even more effectively. Note that, like the TIM material 42, the TIM material 76 is preferably a gel-like material in which thermally conductive particles such as metal powder are added to a resin such as silicone. Furthermore, although not shown in FIG. 7, it is preferable to provide the heat dissipation structure 40 shown in FIG. 2.

[0061] Fig. 9A shows a bottom surface 82B of an SoC substrate 82 employed in a mounting structure 80 of the fourth embodiment, and Fig. 9B shows a top surface 82A of the SoC substrate 82. In describing the mounting structure 80 shown in Fig. 9, members that are the same as or similar to those in the mounting structure 10 shown in Figs. 1 to 4 will be described with the same reference numerals.

[0062] The differences in configuration between the mounting structure 80 and the mounting structure 10 will be described. The SoC substrate 16 of the mounting structure 10 has a configuration in which the multiple pads 24 arranged on the lower surface 16B and the multiple pads 26 arranged on the upper surface 16A are not arranged on the same axis in the vertical direction. In contrast, the SoC substrate 82 of the mounting structure 80 has a configuration in which the multiple pads 84 arranged on the lower surface 82B and the multiple pads 86 arranged on the upper surface 82A are arranged on the same axis in the vertical direction. Note that, for convenience of explanation, in FIG. 9, solders 22 and 20 are shown overlapping the pads 84 and 86, respectively.

[0063] As in the mounting structure 80, by arranging a plurality of pads 84 and a plurality of pads 86 of the SoC substrate 82 on the same axis in the vertical direction, the load on the solders 20, 22 can be reduced.

[0064] Moreover, according to the mounting structure 80, the peripheral portion of the mounting surface (lower surface 12B of the DRAM package 12) of the DRAM package 12 shown by the two-dot chain line in Fig. 9B is mounted on the SoC substrate 82. The silicon chip 14 shown in Fig. 9A is mounted with its mounting surface (upper surface of the silicon chip 14) facing the SoC substrate 82. The mounting locations of the DRAM package 12 and the silicon chip 14 are formed at positions that do not overlap in the longitudinal direction of the SoC substrate 82, as shown by the arrow A.

[0065] In this case, according to the mounting structure 80, the width W1 in the longitudinal direction of the DRAM package 12 is equal to the width W2 in the longitudinal direction of the silicon chip 14. Towards width W29B, and the solder pattern of the SoC substrate 82 on which the DRAM package 12 is mounted is formed outside the outline of the silicon chip 14. Here, the above-mentioned solder pattern refers to the arrangement pattern of a plurality of solders 20 shown in 9B of FIG. 9. Also, the SoC substrate 82 has a solder pattern showing the arrangement pattern of a plurality of solders 22 shown in 9A of FIG. That is, the SoC substrate 82 has a first solder pattern of the present invention in which the solder patterns match on both sides (upper surface 82A and lower surface 82B) of the SoC substrate 82.

[0066] The SoC board 82 is mounted on the main board 72 shown in FIG. 8. The main board 72 has, for example, at least one solder pattern 74 (four in FIG. 8). The solder pattern 74 corresponds to the second solder pattern of the present invention. A plurality of solder patterns 74 are provided around the opening 28 of the main board 72. The solder pattern 74 is formed, for example, in a rectangular shape, and its area is larger than the area of ​​each of the solders 22 forming the first solder pattern. For example, the area of ​​the solder pattern 74 is preferably larger than the area of ​​a solder pattern P (see FIG. 8) of three pieces (3×3) of solder 22 in length and width.

[0067] Fig. 10 is a cross-sectional view of a main part of a mounting structure 90 according to a fifth embodiment. Fig. 11 is a cross-sectional view showing a configuration example in which the mounting structure 90 is attached to a housing 100 via heat dissipation structures 40 and 50. In explaining the mounting structure 90 shown in Figs. 10 and 11, the mounting structures 10, 60, and 61 shown in Figs. 1 to 9 will be described. 7 Components that are the same as or similar to 0 and 80 will be described using the same reference numerals.

[0068] The difference in configuration between mounting structure 90 and mounting structures 10, 60, 70, and 80 is that SoC substrate 16 of mounting structures 10, 60, 70, and 80 has only silicon chip 14 with electrical performance, whereas SoC substrate 82 of mounting structure 90 has silicon chip 14 and silicon chip 92 that is quasi-rectangular in shape with respect to silicon chip 14. Silicon chip 92 is disposed on upper surface 82A of SoC substrate 82. Silicon chip 92 corresponds to the thermal deformation suppressing member of the present invention.

[0069] The silicon chip 92 has the same material properties (linear expansion coefficient, Young's modulus, Poisson's ratio) and dimensions as the silicon chip 14, but does not need to have electrical performance. The linear expansion coefficient is preferably within ±10% of the difference from the silicon chip 14, the Young's modulus is preferably within ±10%, and the Poisson's ratio is preferably within ±20%. The length of one side, which is one element of the dimensions, is preferably within ±10% of the difference from the silicon chip 14. The thickness, which is one element of the dimensions, is preferably thinner than the thickness of the solder 20 by, for example, 0.05 mm or more so as not to contact the DRAM package 12. The silicon chip 92 is mounted on the SoC substrate 82 in the same manner as the silicon chip 14. For example, when the silicon chip 14 is mounted by applying an adhesive, the silicon chip 92 is also mounted on the SoC substrate 82 by applying an adhesive.

[0070] Moreover, it is preferable that the silicon chip 92 is disposed at a position overlapping the silicon chip 14 when the silicon chip 92 is viewed from the side of the DRAM package 12. This makes it possible to effectively suppress warping of the SoC substrate 82 caused by the heat of the silicon chip 14.

[0071] The warping of the SoC substrate 82 caused by the heat of the silicon chip 14 will be described below with reference to 13A and 13B in FIG.

[0072] When mounting structure 90 is heated to a high temperature and a silicon chip 14 with electrical properties is mounted on underside 82B of SoC substrate 82, by its nature, silicon chip 14 is unlikely to stretch, while SoC substrate 82, which is a resin substrate, is likely to stretch, so that SoC substrate 82 as a whole will warp so that upper surface 82A is convex (lower surface 82B is concave) as shown by arrow B in 13A.

[0073] Therefore, when a silicon chip 92, which is pseudo silicon, is mounted on the upper surface 82A of the SoC substrate 82, the linear expansion coefficients of the upper surface 82A and the lower surface 82B of the SoC substrate 82 are aligned as shown in 13B, so that the SoC substrate 82 is less likely to warp. This makes it possible to suppress damage (cracks) to the solders 20, 22 caused by the warping of the SoC substrate 82.

[0074] In the above mounting structure 90, it is preferable to employ a main board 62 having the cutout portion 64 shown in FIG. 6, and it is also preferable to employ a main board 72 having a solder pattern 74 shown in FIGS.

[0075] 〔others〕 Although not shown in the figure, in another embodiment, when the DRAM package 12 and the silicon chip 14 are viewed from above and below, Silicon chip It is preferable to roughly match the positions, number and shape of the silicon sheets 14. This can reduce the load on the solders 20, 22 when the atmospheric temperature changes.

[0076] 1, the distance a between the end of the opening 28 and the end of the silicon chip 14 in the horizontal direction is preferably 1 mm or more from the viewpoint of easily attaching, for example, the TIM material 42 (see FIG. 2) to the silicon chip 14. The distance b between the end of the opening 28 and the outer circumferential surface of the solder 22 is preferably 0.5 mm or more from the viewpoint of effectively arranging the pads 30 on the main substrate 18.

[0077] Although the mounting structure according to the embodiment has been described above, the present invention may be further improved or modified without departing from the gist of the present invention. [Explanation of symbols]

[0078] 10 Implementation structure 12 DRAM Package 12B Bottom 14 Silicon chip 16 SoC Board 16A Top 16B Bottom 18 Main Board 18A top 20 Solder 22 Solder 24 Pads 26 Pad 28 Opening 30 Pads 40 Heat dissipation structure 42 TIM material 44 Metallic parts 44A One end 44B other end 50 Heat dissipation structure 52 TIM material 52A Top 60 Mounting Structure 62 Main Board 62A Top 64 Notch 70 Mounting structure 72 Main Board 72A Top 74 Solder Pattern 76 TIM material 78 Metallic parts 78A One end 78B Other end 80 Mounting Structure 82 SoC Board 82A Top 82B Bottom 84 Pad 86 Pad 90 Mounting Structure 92 Silicon Chip

Claims

1. A first semiconductor component; a first substrate on which the first semiconductor component is mounted; a second substrate on which the first substrate is mounted; Equipped with a second semiconductor component is mounted on a surface of the first substrate facing the second substrate; the second substrate has an opening at least at a position where the second semiconductor component of the first substrate faces; a width in a longitudinal direction of the first semiconductor component is larger than a width in a longitudinal direction of the second semiconductor component, and a solder pattern of the first substrate on which the first semiconductor component is mounted is formed outside an outer shape of the second semiconductor component; Semiconductor packaging structure.

2. A first semiconductor component; a first substrate on which the first semiconductor component is mounted; a second substrate on which the first substrate is mounted; Equipped with a second semiconductor component is mounted on a surface of the first substrate facing the second substrate; the second substrate has an opening at least at a position where the second semiconductor component of the first substrate faces; The first substrate includes a thermal deformation suppressing member having the same material properties and dimensions as the second semiconductor component on a surface opposite to the surface on which the second semiconductor component is mounted. Semiconductor packaging structure.

3. the thermal deformation suppressing member is disposed at a position overlapping the second semiconductor component via the first substrate; The semiconductor mounting structure of claim 2 .

4. A first semiconductor component; a first substrate on which the first semiconductor component is mounted; a second substrate on which the first substrate is mounted; Equipped with a second semiconductor component is mounted on a surface of the first substrate facing the second substrate; the second substrate has an opening at least at a position where the second semiconductor component of the first substrate faces; a thermal conductive member is connected to the second semiconductor component; the thermal conductive member is connected to the second semiconductor component from the outside of the second substrate through the opening. Semiconductor packaging structure.

5. The heat conductive member is a first thermal conductor connected to the second semiconductor component; a second thermal conductor having one end connected to the first thermal conductor through the opening and the other end disposed outside the second substrate; having The first thermal conductor is softer than the second thermal conductor. The semiconductor mounting structure of claim 4 .

6. The other end of the second thermal conductor is connected to a housing arranged on the outside of the second substrate. The semiconductor mounting structure of claim 5 .

7. the second substrate has a notch communicating with the opening, The second thermal conductor is disposed along the notch. The semiconductor mounting structure according to claim 5 or 6.

8. The first substrate has a first solder pattern on both sides of the first substrate, the first solder pattern being coincident with the solder pattern on both sides of the first substrate. The semiconductor mounting structure according to claim 1 .

9. the second substrate has at least one second solder pattern; The semiconductor mounting structure of claim 8.

10. The second solder pattern is provided in a plurality around the opening of the second substrate. The semiconductor mounting structure of claim 9.

11. The area of ​​the second solder pattern is larger than the area of ​​the individual solders forming the first solder pattern. The semiconductor mounting structure according to claim 9 or 10.

12. The first semiconductor component is a semiconductor package in which a first semiconductor element is resin-encapsulated, and the second semiconductor component is a second semiconductor element having an external terminal formed on a mounting surface of the second semiconductor component. The semiconductor mounting structure according to any one of claims 1 to 11.

13. The opening of the second substrate is larger than an outer shape of the second semiconductor component. The semiconductor mounting structure according to any one of claims 1 to 12.

14. A third thermal conductor is connected to the first semiconductor component. The semiconductor mounting structure according to any one of claims 1 to 13.

15. The third thermal conductor is connected to a housing. The semiconductor mounting structure of claim 14.

16. The first semiconductor component is a semiconductor memory. The semiconductor mounting structure according to any one of claims 1 to 15.

17. The first substrate is a system-on-chip substrate. The semiconductor mounting structure according to any one of claims 1 to 16.

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