Semiconductor Device

Abstract

To provide a semiconductor device including an amplification circuit that amplifies a high-frequency signal, capable of having stable NF characteristics without depending on an external terminal.SOLUTION: In a semiconductor device, an LNA circuit 120 includes an input terminal Rx_in to which a high-frequency signal is input, an output terminal Rx_out that outputs a signal obtained by amplifying the high-frequency signal, a first power source terminal VSS, a first transistor Q1, a second transistor Q2, a second power source terminal Vcc, and a first resistor element R501. A gate terminal and a drain terminal of the first transistor are connected through the first resistor element. In a low-frequency region lower than the frequency band of the high-frequency signal, the impedance of the first resistor element is lower than the impedance of the parasitic capacitance between the gate terminal and the drain terminal of the first transistor, and the impedance of the first resistor element is lower than the impedance of the parasitic capacitance between the gate terminal and the source terminal of the first transistor.SELECTED DRAWING: Figure 5B

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] 2. Description of the Related Art Semiconductor devices equipped with an amplifier circuit such as an LNA (Low Noise Amplifier) ​​that amplifies a high-frequency signal input from an antenna terminal or the like are widely used.

[0003] Patent Document 1 discloses a configuration in which a current mirror circuit is used in an amplifier circuit for wireless communication to supply an appropriate bias signal to the amplifier circuit.

[0004] An LNA is an amplifier circuit that amplifies an input signal and outputs it as an output signal to a downstream circuit. Important characteristics of an LNA include the NF (Noise Figure) characteristic, which indicates the ratio of the SNR (Signal to Noise Ratio) of the input signal to the output signal, and the K-factor, which indicates the margin for oscillation. To achieve the desired NF characteristic, it is necessary to pass an appropriate bias current through the LNA. However, since the bias current is affected by temperature variations, manufacturing variations, etc., in conventional semiconductor devices, the bias current is controlled using an external terminal.

[0005] The lower the NF characteristic value, the lower the noise component contained in the output signal, which is desirable as a circuit characteristic. The lower the K value, the more unstable the circuit operation and the higher the possibility of the circuit oscillating, while the higher the K value, the more stable the circuit operation, which is desirable as a circuit characteristic. It is generally believed that a K value of over 1.0 indicates that oscillation will not occur regardless of the matching circuit. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] U.S. Pat. No. 10,158,327 Summary of the Invention [Problem to be solved by the invention]

[0007] However, such external terminals are an obstacle to reducing the mounting area. Therefore, the present disclosure provides a semiconductor device including an amplifier circuit that amplifies a high-frequency signal, which is capable of obtaining stable NF characteristics without relying on external terminals. [Means for solving the problem]

[0008] A semiconductor device according to the present disclosure includes an input terminal to which a high frequency signal is input, an output terminal to which a signal obtained by amplifying the high frequency signal is output, a first power supply terminal, a first transistor, a second transistor, a second power supply terminal, and a first resistive element, wherein a gate terminal of the first transistor is connected to the input terminal, a source terminal of the first transistor is connected to the first power supply terminal, a drain terminal of the first transistor is DC-connected to the second power supply terminal, and a drain terminal of the first transistor is connected to the output terminal, and the gate terminal and drain terminal of the first transistor are connected to the first resistor element. a first power supply terminal connected to the first power supply terminal, a gate terminal and a drain terminal of the second transistor connected to the first power supply terminal, a first node and a gate terminal of the first transistor connected in a DC manner, and in a low frequency region lower than a frequency band of the high frequency signal, an impedance of the first resistance element is lower than an impedance of a parasitic capacitance between the gate terminal and the drain terminal of the first transistor, and an impedance of the first resistance element is lower than an impedance of a parasitic capacitance between the gate terminal and the source terminal of the first transistor. Effect of the Invention

[0009] According to the present disclosure, in a semiconductor device including an amplifier circuit that amplifies a high-frequency signal, stable NF characteristics can be obtained regardless of an external terminal. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a diagram showing an example of a block diagram of a semiconductor device according to an embodiment. [Diagram 2] FIG. 2 is a diagram for explaining the relationship between the NF characteristics and Vgs of a FET. [Diagram 3] FIG. 3 is a diagram for explaining the influence of manufacturing variations in FETs. [Figure 4] FIG. 4 is a diagram showing an example of a circuit configuration of an LNA circuit to which a current mirror circuit is applied. [Figure 5A] FIG. 5A is a diagram (1) showing an example of a circuit configuration of an LNA circuit according to the first embodiment. [Figure 5B] FIG. 5B is a diagram (2) showing an example of the circuit configuration of the LNA circuit according to the first embodiment. [Figure 6] FIG. 6 is a diagram showing an example of a circuit of a FET amplifier A to which no resistive element is added. [Figure 7] FIG. 7 is a diagram showing an equivalent circuit of the FET amplifier A to which no resistive element is added. [Figure 8] FIG. 8 is a diagram illustrating an example of the frequency characteristics of the K value of a FET amplifier. [Figure 9] FIG. 9 is a diagram showing an example of a circuit of a FET amplifier B to which a resistive element is added. [Figure 10] FIG. 10 is a diagram (1) showing an equivalent circuit of a FET amplifier B to which a resistive element is added. [Figure 11] FIG. 11 is a diagram (2) showing an equivalent circuit of FET amplifier B with a resistive element added. [Figure 12] FIG. 12 is a diagram showing an example of a simulation result of the NF characteristic of the LNA circuit according to the first embodiment. [Figure 13] FIG. 13 is a diagram showing an example of a simulation result of the K value of the LNA circuit according to the first embodiment. [Figure 14] FIG. 14 is a diagram illustrating an example of a circuit configuration of an LNA circuit according to the second embodiment. [Figure 15] FIG. 15 is a diagram showing an example of a block diagram of a conventional semiconductor device. [Figure 16] FIG. 16 is a diagram showing an example of a circuit configuration of a conventional LNA circuit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] First, an overview of the embodiment of the present disclosure will be described.

[0012] <Overview of the embodiment of the present disclosure> (1) A semiconductor device according to an embodiment of the present disclosure includes an input terminal to which a high frequency signal is input, an output terminal to which a signal obtained by amplifying the high frequency signal is output, a first power supply terminal, a first transistor, a second transistor, a second power supply terminal, and a first resistive element, wherein a gate terminal of the first transistor is connected to the input terminal, a source terminal of the first transistor is connected to the first power supply terminal, a drain terminal of the first transistor is connected in a DC manner to the second power supply terminal, and a drain terminal of the first transistor is connected to the output terminal, and the gate terminal and the drain terminal of the first transistor are connected to the front end of the first transistor. the second transistor is connected via the first resistive element, the source terminal of the second transistor is connected to the first power supply terminal, the gate terminal and the drain terminal of the second transistor are shorted at a first node, the first node and the gate terminal of the first transistor are DC-connected, and in a low-frequency region lower than a frequency band of the high-frequency signal, the impedance of the first resistive element is lower than the impedance of a parasitic capacitance between the gate terminal and the drain terminal of the first transistor, and the impedance of the first resistive element is lower than the impedance of a parasitic capacitance between the gate terminal and the source terminal of the first transistor.

[0013] With the above configuration, a semiconductor device including an amplifier circuit for amplifying a high-frequency signal can obtain stable NF characteristics without depending on an external terminal. For example, according to the semiconductor device of the present disclosure, the second current flowing through the first transistor can be determined without depending on an external terminal by the ratio of the gate width of the first transistor to the gate width of the second transistor and the resistance value of the first resistor. Furthermore, the semiconductor device according to this embodiment can suppress the fluctuation of the current value of the second current even if the threshold voltage Vth of the transistor fluctuates due to, for example, manufacturing variations, etc., so that a stable NF (Noise Figure) characteristic can be obtained. Furthermore, the semiconductor device according to this embodiment can improve the stability (K value) against oscillation of the amplifier circuit because negative feedback is applied by the first resistor element.

[0014] (2) In the frequency band of the high frequency signal, the impedance of the first resistive element is lower than the impedance of a parasitic capacitance between the gate terminal and the drain terminal of the first transistor.

[0015] (3) Preferably, the semiconductor device further includes a second resistive element connected between a source terminal of the second transistor and the first power supply terminal.

[0016] In the semiconductor device, for example, due to restrictions on the minimum layout of the FET, the ratio of the gate width of the first transistor to the gate width of the second transistor may become smaller than the ratio of the second current to the first current. In such a case, the semiconductor device can maintain the function of the current mirror circuit by utilizing the resistance value of the second resistive element.

[0017] (4) Preferably, in the semiconductor device, the first transistor and the second transistor are formed on the same semiconductor substrate. By configuring the semiconductor device as an MMIC (Monolithic Microwave Integrated Circuit), in which each circuit is formed on the same semiconductor substrate, the mounting area can be reduced.

[0018] <Details of the embodiment of the present disclosure> DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a semiconductor device according to the present disclosure will be described below with reference to the drawings. In the following description, the same or corresponding elements are denoted by the same reference numerals, and description thereof may be omitted.

[0019] <Configuration of a conventional semiconductor device> Before describing the configuration of the semiconductor device 100 according to the present disclosure, an overview of the configuration of a conventional semiconductor device will be described.

[0020] 15 is a diagram showing an example of a block diagram of a conventional semiconductor device. The semiconductor device 1 is used as a front-end circuit in a wireless communication device, and includes, for example, a SW (Switch) circuit 10, an LNA (Low Noise Amplifier) ​​circuit 20, and a PA (Power Amplifier) ​​circuit 30.

[0021] The SW circuit 10 is a switch that selectively connects the RF_in / out terminal of the semiconductor device 1 to the LNA circuit 20 or the PA circuit 30 depending on the voltage levels of control voltages Vc1 and Vc2 output from a control unit or the like of the wireless communication device.

[0022] The LNA circuit 20 is an amplifier circuit that amplifies a received signal input to an input terminal Rx_in 102 and outputs the amplified signal to a subsequent circuit from an output terminal Rx_out terminal 103. In the example of Fig. 15, external terminals Vbias_1 and Vbias_2 are provided so that the bias current flowing through the LNA circuit 20 can be changed from the outside.

[0023] The PA circuit 30 is an amplifier circuit that amplifies a transmission signal input from a previous circuit to a Tx_in terminal 104, which is an input terminal, and outputs the amplified signal to the SW circuit 10. In the example of Fig. 15, external terminals PA_bias1 and PA_bias2 are provided so that a bias current flowing through the PA circuit 30 can be adjusted from the outside.

[0024] The Vcc terminal is connected to the SW circuit 10, the LNA circuit 20, the PA circuit 30, etc., and supplies power supply voltage to each circuit. The Vss terminal is connected to the SW circuit 10, the LNA circuit 20, the PA circuit 30, etc., and connects each circuit to a ground potential (circuit ground).

[0025] (Conventional LNA circuit configuration) An example of the circuit configuration of a conventional LNA circuit is shown in Fig. 16. The LNA circuit 20 shown in Fig. 16 has a two-stage configuration including an amplifier circuit configured with a transistor Tr1 and an amplifier circuit configured with a transistor Tr2.

[0026] The transistors Tr1 and Tr2 are, for example, FETs such as GaAs (gallium arsenide) FETs or GaN (gallium nitride) FETs. The source terminals of the transistors Tr1 and Tr2 are connected to Vss, a power supply terminal of the ground potential, via inductor elements L1 and L2, respectively. The drain terminals of the transistors Tr1 and Tr2 are connected to Vcc, a power supply terminal for applying a drain voltage, via high-frequency choke coils RFC1 and RFC2, respectively. The gate terminals of the transistors Tr1 and Tr2 are connected to Vbias_1 and Vbias_2, external terminals for applying a gate voltage, via high-frequency choke coils RFC2 and RFC4, respectively.

[0027] The matching circuits M1 to M4 are matching circuits that match the input impedance or output impedance of each amplifier circuit, and are composed of passive elements such as delay lines, inductors, etc. With the above configuration, the transistors Tr1 and Tr2 each constitute a source-grounded FET amplifier that amplifies the input power input to the gate terminal and outputs it from the drain terminal.

[0028] In the LNA circuit 20 shown in Fig. 16, the gate bias voltages of the transistors Tr1 and Tr2 are applied from the outside using the external terminals Vbias_1 and Vbias_2. However, in order to reduce the mounting area, it is desirable to control the bias currents of the transistors Tr1 and Tr2 by, for example, a self-bias function in the MMIC, without using external terminals. However, in conventional technology, it has been difficult to obtain stable NF characteristics against temperature changes and manufacturing variations by the self-bias function in the MMIC without using external terminals.

[0029] Therefore, this disclosure discloses an LNA circuit that can obtain stable NF characteristics by using a self-bias function within the MMIC without relying on an external terminal, and a semiconductor device that includes the LNA circuit.

[0030] <Configuration of Semiconductor Device> 1 is a diagram showing an example of a block diagram of a semiconductor device according to an embodiment. A semiconductor device 100 according to an embodiment of the present disclosure is, for example, an MMIC used as a front-end circuit in a wireless communication device in the microwave band (6 GHz to 90 GHz) or the like. The semiconductor device 100 has, for example, a SW circuit 110, an LNA circuit 120, and a PA circuit 130. However, the configuration of the semiconductor device 100 shown in FIG. 1 is only an example. For example, the semiconductor device 100 may have the SW circuit 110 and the LNA circuit 120, or may have only the LNA circuit 120.

[0031] The SW circuit 110 selectively connects the RF_in / out terminal 101 of the semiconductor device 100 to the LNA circuit 120 or the PA circuit 130 according to the logic of control voltages Vc1 and Vc2 output from a control unit or the like of the wireless communication device. In the example of Fig. 1, the SW circuit 110 connects the RF_in / out terminal 101 to an input terminal Rx_in102 of the LNA circuit 120. In this case, the RF_in / out terminal 101 functions as an input terminal for inputting a received signal.

[0032] The LNA circuit 120 is an amplifier circuit that amplifies a received signal input to an input terminal Rx_in 102 of the LNA circuit 120 and outputs the amplified signal to a downstream circuit from an Rx_out terminal (output terminal) 103. As shown in FIG. 1, the semiconductor device 100 according to an embodiment of the present disclosure does not have the external terminals Vbias_1 and Vbias_2 provided in the conventional semiconductor device 1 described in FIG.

[0033] The PA circuit 130 is an amplifier circuit that amplifies a transmission signal input to the Tx_in terminal 104 from a previous circuit and outputs the amplified signal to the SW circuit 110. It is known that the maximum power that the PA circuit 130 can output and electrical characteristics such as distortion change depending on the bias current flowing through the PA circuit 130. The semiconductor device 100 according to an embodiment of the present disclosure is also provided with external terminals PA_bias1 and PA_bias2 so that the bias current flowing through the PA circuit 130 can be adjusted from the outside, as shown in FIG.

[0034] The Vcc terminal 105 is a power supply terminal (second power supply terminal) connected to the SW circuit 10, the LNA circuit 20, the PA circuit 30, etc., and supplies power supply voltages to each circuit. The Vss terminal 106 is a power supply terminal (first power supply terminal) connected to the SW circuit 10, the LNA circuit 20, the PA circuit 30, etc., and connects each circuit to a ground potential (circuit ground).

[0035] (NF characteristics of LNA circuit) Important characteristics of the LNA circuit 120 include the NF characteristic, which indicates the amount of noise generated in the LNA circuit 120, and the K factor, which indicates the margin for oscillation of the LNA circuit 120. Of these, it is known that the NF characteristic changes depending on the bias current flowing through the FET that constitutes the LNA circuit 120.

[0036] FIG. 2 is a diagram for explaining the relationship between the NF characteristic and Vgs of a FET. In the graph shown in FIG. 2, the horizontal axis indicates Vgs, which is the source-gate voltage of a FET in a source-grounded FET amplifier. The vertical axis indicates Ids, which is the current flowing between the drain and source of the FET, and the value of the NF characteristic. As shown by the solid line 201 in FIG. 2, the value of Ids of the FET increases in current value approximately in proportion to the value of Vgs when the value of Vgs exceeds the threshold voltage Vth of the FET. On the other hand, as shown by the dashed line 202 in FIG. 2, the value of the NF characteristic of the FET decreases with an increase in Ids toward the point where the value of Vgs exceeds Vth, and the value of the NF characteristic increases with an increase in Ids when the value of Vgs exceeds Vgs_opt. This is thought to be because, as a general FET characteristic, the high-frequency operation of the FET improves as Vgs increases, but when the Vgs value becomes large enough (=Vgs_opt), the high-frequency operation of the FET saturates, and the increase in noise such as the gate noise coefficient and drain noise coefficient becomes dominant.

[0037] Since the NF characteristic of the LNA circuit 120 has a large effect on the receiving sensitivity of the wireless communication device, it is required to design the LNA circuit 120 so that the value of the NF characteristic is as low as possible. Specifically, in FIG. 2, it is important to set the gate voltage of the FET to Vgs_opt so that the bias current Ids_opt that minimizes the NF value flows. However, the threshold voltage Vth of the FET varies due to, for example, manufacturing variations and temperature dependency.

[0038] FIG. 3 is a diagram for explaining the influence of manufacturing variations of FETs. In FIG. 3, similarly to FIG. 2, the horizontal axis indicates Vgs, and the vertical axis indicates Ids and NF characteristics. As shown in FIG. 3, when the threshold voltage Vth varies due to manufacturing variations of the FET, the gate voltage Vgs_opt for setting the drain current of the FET to Ids_opt at which the value of the NF characteristics is minimum varies. Therefore, if the gate voltage Vgs is simply set to a constant value, the NF characteristics will vary as shown in FIG. 3 due to the variations in the threshold voltage Vth of the FET. Therefore, it is desirable that the LNA circuit 120 has a function of maintaining the value of the drain current Ids at Ids_opt even if the threshold voltage Vth of the FET varies.

[0039] Patent Document 1 describes an LNA circuit to which a current mirror circuit is applied in order to suppress fluctuations in drain current Ids caused by manufacturing variations in FETs.

[0040] (LNA circuit using a current mirror circuit) Fig. 4 is a diagram showing an example of the circuit configuration of an LNA circuit to which a current mirror circuit is applied. In the LNA circuit 400 shown in Fig. 4, a transistor Tr1 constitutes a source-grounded FET amplifier, which amplifies a signal input from an input terminal 401 and outputs it from an output terminal 402. A transistor Tr2 is a FET that constitutes a current mirror circuit with the transistor Tr1, and the gate terminal and drain terminal are connected in a DC manner to the gate terminal of the transistor Tr1 via a high-frequency choke coil RFC.

[0041] In FIG. 4, a drain current Ids2 that is the same as the reference current Iref input from the Iref terminal 412 flows through the transistor Tr2 as shown in equation (1). Ids2=Iref (1)

[0042] Also, in transistor Tr1, a drain current Ids1 proportional to the drain current Ids2 of transistor Tr2 flows according to the ratio of the gate width of transistor Tr1 to the gate width of transistor Tr2. This relationship is represented by the following equation (2), for example, when the gate width of transistor Tr1 is Wg_tr1 and the gate width of transistor Tr2 is Wg_tr2. Wg_tr1 / Wg_tr2 = Ids1 / Ids2 ···(2)

[0043] From the above equations (1) and (2), it can be understood that by supplying the reference current Iref to the Iref terminal 412, the drain current Ids1 of transistor Tr1 can be set to Ids_opt that satisfies the following equation (3) and has the minimum value of the NF characteristic. Ids_opt = (Wg_tr1 / Wg_tr2) × Iref ···(3)

[0044] Note that (Wg_tr1 / Wg_tr2) in equation (3) is assumed to increase and decrease in the same direction according to manufacturing variations for both the numerator and the denominator, and this term is assumed to be constant regardless of manufacturing variations. Therefore, if the value of the reference current Iref can be maintained constant, the value of the drain current Ids of transistor Tr1 can be maintained at Ids_opt.

[0045] However, in this method, the Iref terminal 412 remains as an external terminal in the semiconductor device 100. Also, an internal circuit increases to generate the reference current Iref inside the semiconductor device 100. Therefore, the semiconductor device 100 according to the present disclosure has an LNA circuit as shown below in order to obtain stable NF characteristics without relying on external terminals.

[0046] [First Embodiment] <Configuration of LNA Circuit> 5A is a diagram (1) showing an example of a circuit configuration of an LNA circuit according to the first embodiment. The LNA circuit 120 shown in FIG. 5A has a first transistor Q1 that constitutes a source-grounded FET amplifier, and a second transistor Q2 that constitutes a current mirror circuit with the first transistor Q1.

[0047] The first transistor Q1 is, for example, a GaAs FET or a GaN FET with a gate length of about 60 nm to 600 nm and a gate width of about 30 μm to 300 μm. However, the first transistor Q1 may be a FET with a different configuration from the above. The gate terminal of the first transistor Q1 is connected to an input terminal such as Rx_in102. In the example of FIG. 5A and FIG. 5B, the gate terminal of the first transistor Q1 is connected to an input terminal such as Rx_in102 or an RF_in / out terminal 101 via a matching circuit M501 and a capacitive element C501. Thus, in the present disclosure, being connected is not limited to being physically connected, but includes being electrically connected via, for example, other elements, circuits, etc.

[0048] The source terminal of the first transistor Q1 is connected to a Vss terminal (first power supply terminal) which is a ground potential (circuit ground) via an inductor element L501. The drain terminal of the first transistor Q1 is connected to an output terminal such as an Rx_out terminal 103 via, for example, a matching circuit M502 and a capacitive element C502. The drain terminal of the first transistor Q1 is connected in a DC manner to a Vcc terminal (second power supply terminal) 105 which supplies a power supply voltage via a high-frequency choke coil RFC501. Furthermore, the gate terminal and drain terminal of the first transistor Q1 are connected via a first resistor element R501.

[0049] The second transistor Q2 is, for example, a FET formed on the same semiconductor substrate as the first transistor Q1 and having the same gate length as the first transistor Q1, but is not limited to this. The source terminal of the second transistor Q2 is connected to, for example, the Vss terminal (first power supply terminal). The gate terminal and drain terminal of the second transistor Q2 are shorted and are DC-connected to the gate terminal of the first transistor Q1 via the high-frequency choke coil RFC502.

[0050] The capacitive elements C501 and C502 are DC-cutting capacitors, and may be included in, for example, the matching circuit M501 or the matching circuit M502. The matching circuit M501 is a matching circuit that matches the input impedance of the FET amplifier configured with the first transistor Q1 to the impedance of an input terminal such as Rx_in102, looking from the input terminal side to the first transistor Q1 side. The matching circuit M502 is a matching circuit that matches the output impedance of the FET amplifier configured with the first transistor Q1 to the impedance of an output terminal such as Rx_out terminal 103, looking from the first transistor Q1 side to the output terminal side. The matching circuits M501 and M502 are configured with passive elements such as delay lines and inductor elements. The inductor element L501 is a line element or the like for setting the gain of the first transistor Q1 in design.

[0051] In the LNA circuit 120 shown in FIG. 5A, the current Ir1 flowing through the first resistive element R501 is expressed by the following equation (4), where the voltage of the gate terminal of the first transistor Q1 is Vg, the voltage of the Vcc terminal 105 is Vcc, and the resistance value of the first resistive element R501 is R1. Ir1 = (Vcc - Vg) / R1 (4)

[0052] As shown in equation (5), a drain current Id1 flows through the second transistor Q2, which is the same as the current Ir1 flowing through the first resistor element R501. Id1 = Ir1 (5)

[0053] A drain current Id2 proportional to the drain current Id1 of the second transistor Q2 flows through the first transistor Q1 in accordance with the ratio of the gate width of the first transistor Q1 to the gate width of the second transistor Q2. This relationship is expressed by the following equation (6), for example, where the gate width of the first transistor Q1 is Wg_Q1 and the gate width of the second transistor Q2 is Wg_Q2. Wg_Q1 / Wg_Q2=Id2 / Id1 (6)

[0054] From the above equations (5) and (6), it can be seen that the current Ir1 that satisfies the following equation (7) can set the drain current Id2 of the first transistor Q to Ids_opt. Ids_opt=(Wg_Q1 / Wg_Q2)×Ir1 ···(7)

[0055] Furthermore, by setting the resistance value R1 of the first resistor element so that current flows through the first resistor element R501 based on the equations (4) and (7), the following equation (8) is obtained. Ids_opt=(Wg_Q1 / Wg_Q2)×(Vcc-Vg) / R1 ···(8)

[0056] According to formula (4), the value of the current Ir1 flowing through the first resistor element R501 is affected by the manufacturing variation of the first resistor element R501, but the manufacturing variation is small at ±5% by using a thin-film metal resistor element, so the effect on the current Ir1 is small. Also, the value of the current Ir1 is affected by the manufacturing variation of the first transistor Q1, but the effect of the variation in the threshold voltage Vth on the value of (Vcc-Vg) is small at ±4% when Vcc=4V and Vg=±0.15V, so the effect on the current Ir1 is small.

[0057] As shown in the formula (8), the LNA circuit 120 according to the first embodiment can change the value of the drain current Id2 of the first transistor Q1 by the resistance value R1 of the first resistor element R501. Therefore, by designing the first resistor element R501 to have a resistance value that makes the NF characteristic of the amplifier circuit formed by the first transistor Q1 Ids_opt (or a predetermined value or less), it is possible to realize a NF characteristic suitable for the LNA circuit. Furthermore, the LNA circuit 120 according to the first embodiment can realize a miniaturization of the semiconductor device 100, since it does not require external terminals such as the Iref terminal 412 in FIG. 4 or Vbias_1 and Vbias_2 in FIG. 16.

[0058] In the low power consumption semiconductor device 100, for example, if the gate width of the first transistor Q1 is Wg1 and the gate width of the second transistor Q2 is Wg2, the gate width Wg1 of the first transistor Q1 may be set to a value close to the minimum rule. In such a case, due to the restrictions of the minimum layout rule of the FET, the formula (7) may become as shown in the formula (9). Ids_opt>(Wg_Q1 / Wg_Q2)×Ir1 ···(9)

[0059] In such a case, for example, as shown in FIG. 5B, by adding a second resistor element R502, the first transistor Q1 and the second transistor Q2 can maintain the function as a current mirror circuit.

[0060] Fig. 5B is a diagram showing an example of the circuit configuration of the LNA circuit according to the first embodiment. In addition to the configuration of the LNA circuit 120 described in Fig. 5A, the LNA circuit shown in Fig. 5B has a second resistor element R502 between the source terminal of the second transistor Q2 and the VSS terminal. This second resistor element R502 adjusts the total source resistance value Rs of the FET, Rs = (intrinsic Rs + parasitic Rs), so as to satisfy the formula (10). This makes it possible to more stably maintain the function of the first transistor Q1 and the second transistor Q2 as a current mirror circuit. (R2+Rs_Q2) / (Rs_Q1)=Id2 / Id1 ···(10) Here, R2 denotes the resistance value of the second resistor element 502, Rs_Q2 denotes the source resistance value inherent in the second transistor Q2, and Rs_Q1 denotes the source resistance value inherent in the first transistor Q1.

[0061] In this way, according to the LNA circuit 120 of the first embodiment and the semiconductor device 100 equipped with the LNA circuit 120, it becomes possible to stably set the Ids of the LNA circuit 120 to Ids_opt at which the value of the NF characteristic is minimized, without relying on an external terminal.

[0062] Furthermore, in the LNA circuit 120 according to the first embodiment and the semiconductor device 100 including the LNA circuit 120, the first resistor element R501 serves as a negative feedback resistor, which also provides the effect of improving the K value, which indicates the margin of oscillation.

[0063] (Improvement effect of K value) Here, the effect of improving the K value by the first resistor element R501 functioning as a feedback resistor in the LNA circuit 120 according to the first embodiment as shown in FIGS. 5A and 5B will be described.

[0064] Fig. 6 is a diagram showing an example of a circuit of a FET amplifier A to which no resistive element is added. The FET amplifier A600 shown in Fig. 6 is a source-grounded FET amplifier in which the source terminal of the FET is grounded to VSS, which is the ground potential, and the signal input from Port1 is amplified and output from Port2. Only elements related to the input and output signals are shown in the diagram.

[0065] Fig. 7 is a diagram showing an equivalent circuit of the FET amplifier A with no resistance element added. As shown in Fig. 7, the equivalent circuit of the FET amplifier A600 shown in Fig. 6 can be represented by a parasitic capacitance Cgd between the gate terminal and drain terminal of the transistor Tr1, a parasitic capacitance Cgs between the gate terminal and source terminal of the transistor Tr1, and a current source having a mutual conductance Gm.

[0066] Fig. 8 is a diagram showing an example of the frequency characteristics of the K value of a FET amplifier. In the graph shown in Fig. 8, the horizontal axis indicates frequency, and the vertical axis indicates the K value, which is an index of the stability of the FET amplifier. The K value is calculated by the following formula (11).

[0067]

number

[0068] As mentioned above, the lower the K value, the more unstable the system is and the more likely it is to oscillate, while the higher the K value, the more stable it is. Also, a K value of over 1.0 indicates that the system will not oscillate regardless of the matching circuit.

[0069] In Fig. 8, the solid line graph shows the frequency characteristics of the K value of the FET amplifier A600 to which no resistive element is added, as shown in Fig. 6 and Fig. 7. For example, in Fig. 7, when the feedback from Port2 to Port1 is feedback by Cgd, the impedance of Cgd becomes high in the low frequency range, and the potential between Port2 and Port1 increases, resulting in positive feedback, so the K value decreases as the frequency decreases, and the FET amplifier A becomes unstable.

[0070] Fig. 9 is a diagram showing an example of a circuit of the FET amplifier B to which a resistive element is added. The FET amplifier B900 shown in Fig. 9 has a configuration in which a resistive element Rf1 is connected between the gate terminal and the drain terminal of the transistor Tr1 included in the FET amplifier A600 shown in Fig. 6.

[0071] FIG. 10 is a diagram showing an equivalent circuit of the FET amplifier B to which a resistive element is added. As shown in FIG. 10, the equivalent circuit of the FET amplifier B900 shown in FIG. 9 can be expressed by a parasitic capacitance Cgd between the gate terminal and drain terminal of the transistor Tr1, a parasitic capacitance Cgs between the gate terminal and source terminal of the transistor Tr1, a current source having a mutual conductance Gm, and a resistive element Rf1. In addition, by adding Rf1, in the low frequency region where the formulas (A) and (B) in FIG. 10 are satisfied, the impedance value due to the parasitic capacitances Cgd and Cgs of the transistor Tr1 becomes relatively low compared to the value of the resistive element Rf1 and can be ignored. In this case, the equivalent circuit of the FET amplifier B900 becomes as shown in FIG. 11.

[0072] Fig. 11 is a diagram showing an equivalent circuit in the low frequency region of FET amplifier B to which a resistive element is added. This diagram shows an equivalent circuit of FET amplifier B900 in the low frequency region (for example, 1 GHz or less). In the equivalent circuit shown in Fig. 11, resistive element Rf1 configures negative feedback of FET amplifier B900. At this time, in the FET amplifier B900, the impedance values ​​of Cgs and Cgd in the low frequency region are relatively negligible compared to the value of resistive element Rf1, so that feedback from Port2 to Port1 does not become positive feedback.

[0073] In Fig. 8, the dashed line graph indicates the frequency characteristics of the K value of FET amplifier B900 to which a resistive element has been added, as shown in Fig. 9. As described above, in the FET amplifier B900 to which a resistive element has been added, the feedback from Port2 to Port1 does not become positive in the low frequency range, so there is no possibility of oscillation due to the gain of Gm, and the K value is around 1.0.

[0074] For example, when Cgs=100 fF, the right hand side of equation (b) in FIG. 10 is 3 kΩ at a frequency of 1 GHz. Therefore, when the resistance value of the resistive element Rf1 is sufficiently small, such as 3 kΩ, the FET amplifier B is completely stable in the low frequency range. On the other hand, even if the resistance value of the resistive element Rf1 is not sufficiently small compared to 3 kΩ, the K value is higher than when the resistive element Rf1 is not present, and the stability of the FET amplifier B900 is improved. In this way, the stability of the FET amplifier B900 with the addition of the resistive element Rf1 is improved in the low frequency range.

[0075] In the FET amplifier B900 with the added resistive element Rf1, in the frequency band for amplifying high frequency signals (for example, 28 GHz), Rf1>>1 / (jωCgs) holds, so that the change in characteristics due to the resistive element Rf1 is negligible.

[0076] <Simulation results> Next, the results of a simulation of the LNA circuit 120 according to the first embodiment will be shown. Here, in the LNA circuit 120 as shown in Fig. 5B, the gate length of the transistor Q1 was set to about 150 nm, the gate width was set to 50 µm, and the resistance value of the first resistor element R501 was set to 4.3 kΩ. The simulation was also performed with the gate length of the second transistor Q2 set to about 150 nm, the gate width to 30 µm, and the value of the second resistor element R502 set to 2 Ω.

[0077] (NF characteristics) FIG. 12 shows a simulation result of the NF characteristic of the LNA circuit according to the first embodiment. In FIG. 12, the horizontal axis represents the variation of the threshold voltage Vth of the FET, that is, the manufacturing variation, and the vertical axis represents the minimum value of the NF characteristic. A first solid line 1201 represents the variation of the minimum value of the NF characteristic corresponding to the variation of the threshold voltage Vth at Ta=25° C. of the LNA circuit 120 according to the first embodiment. A second solid line 1202 represents the variation of the minimum value of the NF characteristic corresponding to the variation of the threshold voltage Vth at Ta=105° C. of the LNA circuit 120 according to the first embodiment. A third dotted line 1203 represents the variation of the minimum value of the NF characteristic corresponding to the variation of the threshold voltage Vth at Ta=25° C. when the LNA circuit is configured as the FET amplifier A without the addition of a resistive element as shown in FIG. 6 and a fixed Vg voltage is applied. The fourth dotted line 1204 indicates the change in the minimum value of the NF characteristics corresponding to the change in threshold voltage Vth at Ta=105° C. when, for example, the LNA circuit is configured as an FET amplifier A with no added resistive element as shown in FIG. 6 and a fixed Vg voltage is applied.

[0078] 12, it can be seen that the LNA circuit 120 according to the first embodiment suppresses the change in the minimum value of the NF characteristics even when the threshold voltage Vth varies, compared to an LNA circuit to which a fixed Vg voltage is applied. It can also be seen that the LNA circuit 120 according to the first embodiment suppresses the change in the minimum value of the NF characteristics even when the temperature varies, compared to an LNA circuit to which a fixed Vg voltage is applied.

[0079] (K value) FIG. 13 is a diagram showing a simulation result of the K value of the LNA circuit according to the first embodiment. Here, the frequency characteristic of the K value was simulated under the severe condition of Ta=-40°C where the circuit operation becomes most unstable. In FIG. 13, the horizontal axis indicates frequency, and the vertical axis indicates the K value. Also, a first line 1301 indicates the frequency characteristic of the K value of the LNA circuit 120 according to the first embodiment at Ta=-40°C. A second line 1302 indicates the frequency characteristic of the K value at Ta=-40°C when the LNA circuit is configured as an FET amplifier A without an added resistive element as shown in FIG. 6, for example, and a fixed Vg voltage is applied.

[0080] Looking at the second line 1302, it can be seen that the LNA circuit to which a fixed Vg voltage is applied has a K value below 0.5 in the frequency range of 10 MHz to 1 GHz, making it unstable. On the other hand, looking at the first line 1301, the LNA circuit 120 according to the first embodiment maintains a K value above 1.0 in the low frequency range of 1 GHz or less. Moreover, the LNA circuit 120 according to the first embodiment has a K value of 0.5 or more at all frequencies shown in FIG.

[0081] [Second embodiment] In the first embodiment, an example has been described in which the LNA circuit 120 included in the semiconductor device 100 is configured with a single-stage FET amplifier. However, the LNA circuit 120 may be configured with a two-stage FET amplifier, for example, as shown in FIG. 14.

[0082] Fig. 14 is a diagram showing an example of a circuit configuration of an LNA circuit according to the second embodiment. In the example of Fig. 14, a second-stage FET amplifier is added to the rear stage of the LNA circuit 120 according to the first embodiment described in Fig. 5B. As a result, the drain of the first transistor Q1 is connected to an output terminal such as the Rx_out terminal 103 via a matching circuit M502, a capacitive element C502, and a second FET amplifier 1501.

[0083] The second FET amplifier 1501 may be the same as the LNA circuit 20 according to the first embodiment shown in Fig. 5B, for example. In the example of Fig. 14, the second FET amplifier 1501 has a third transistor Q3 and a fourth transistor Q4 that configures a current mirror circuit with the third transistor Q3. Similarly to the LNA circuit 20 according to the first embodiment, the second FET amplifier 1501 also has resistor elements R1401 and R1402, an inductor element L1401, high-frequency choke coils RFC1401 and RFC1402, a capacitor element C1401, and the like.

[0084] However, the configuration of the LNA circuit 120 according to the second embodiment shown in Fig. 14 is just an example. For example, the matching circuit M1401 may be integrated with the matching circuit M502 to form one matching circuit. In addition, since the NF characteristics of the receiving circuit are dominated by the NF characteristics of the first-stage LNA circuit, the second FET amplifier 1501 may be a FET amplifier of another type that does not require an external terminal.

[0085] The semiconductor device 100 according to the present disclosure shown in FIG. 1 has, for example, an LNA circuit 120 according to a first embodiment as shown in FIGS. 5A and 5B, or an LNA circuit 120 according to a second embodiment as shown in FIG. 14. Therefore, according to each embodiment of the present disclosure, in the semiconductor device 100 including an amplifier circuit for amplifying a high-frequency signal, stable characteristics can be obtained without depending on an external terminal. Note that the semiconductor device according to the present disclosure is not limited to the configuration of the semiconductor device 100 shown in FIG. 1, and may be a semiconductor device of various configurations including, for example, the LNA circuit 120 according to the first embodiment as shown in FIGS. 5A and 5B, or the LNA circuit 120 according to the second embodiment as shown in FIG. 14.

[0086] Although the embodiments of the present disclosure have been described above, the present disclosure is not limited to the above embodiments. Various changes, modifications, substitutions, additions, deletions, and combinations are possible within the scope of the claims. These naturally fall within the technical scope of the present disclosure. [Explanation of symbols]

[0087] 1, 100 Semiconductor device 101 RF_in / out terminal (an example of an input terminal) 102 Rx_in (an example of an input terminal) 103 Rx_out terminal 104 Tx_in terminal 105 Vcc terminal (second power supply terminal) 106 Vss terminal (first power supply terminal) 10, 110 Switch circuit 20, 120 LNA circuit 30, 130 PA circuit 201 Solid Line 400 LNA circuit 401 Input terminal 402 Output terminal 412 Iref terminal 600 FET Amplifier A 1201 First solid line 1202 Second solid line 1203 Third dotted line 1204 Fourth dotted line 1301 First Line 1302 Second Line C501, C502, C1401 Capacitive elements Cgd, Cgs internal capacity Gm transconductance L501, L1401 inductor elements M1, M2, M3, M4 matching circuit M501, M502, M1401, M1402 matching circuit Q1 First transistor Q2 Second transistor Q3 Third transistor Q4 Fourth transistor R501 First resistor element R502 Second resistor element R1401 Third resistor element R1402 4th resistor element Rf1 Resistor element RFC1, RFC2, RFC3, RFC4 Choke Coils RFC501, RFC502, RFC1401, RFC1402 Choke Coils Tr1, Tr2 transistors

Claims

1. an input terminal to which a high frequency signal is input; an output terminal for outputting a signal obtained by amplifying the high frequency signal; A first power supply terminal; A first transistor; A second transistor; and A second power supply terminal; A first resistive element; A first coil; A second coil; Equipped with a gate terminal of the first transistor is connected to the input terminal; a source terminal of the first transistor is connected to the first power supply terminal; a drain terminal of the first transistor is connected to the second power supply terminal via the first coil; Also, the drain terminal of the first transistor is further connected to the output terminal; a gate terminal and a drain terminal of the first transistor are connected to each other via the first resistance element; a source terminal of the second transistor is connected to the first power supply terminal; the gate terminal and the drain terminal of the second transistor are connected together at a first node; the first node and a gate terminal of the first transistor are connected to each other via the second coil; In a low frequency region lower than the frequency band of the high frequency signal, an impedance of the first resistive element is lower than an impedance of a parasitic capacitance between the gate terminal and the drain terminal of the first transistor; The impedance of the first resistive element is lower than the impedance of a parasitic capacitance between the gate terminal and the source terminal of the first transistor. Semiconductor device.

2. In the frequency band of the high frequency signal, The impedance of the first resistive element is lower than the impedance of a parasitic capacitance between the gate terminal and the drain terminal of the first transistor. The semiconductor device according to claim 1 .

3. 3. The semiconductor device according to claim 1, further comprising a second resistive element connected between a source terminal of said second transistor and said first power supply terminal.

4. The semiconductor device according to claim 1 , wherein the first transistor and the second transistor are formed on a same semiconductor substrate.

5. The semiconductor device described in claim 4, wherein the first transistor has a gate length that is the same as the gate length of the second transistor.

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