Semiconductor Device

Abstract

To provide a semiconductor device capable of increasing reliability while reducing inductance.SOLUTION: A semiconductor device 11 includes a circuit pattern 17, a semiconductor chip, a first electrode plate 31, and a second electrode plate 32. The first electrode plate 31 includes a first part 41a, a second part 42a, and a third part 43. The second electrode plate 32 includes a fourth part 44a, a fifth part 45a, and a sixth part 46. The second part 42a and the fifth part 45a are placed with a space in a first direction. The third part 43 and the sixth part 46 are placed in parallel, with a space in a second direction. The third part 43 includes a projection region projecting to the side of the fifth part 45a with respect to the second end part 62a in the first direction.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] A semiconductor module in which two electrode plates are arranged in parallel is known (see, for example, Patent Document 1). The semiconductor module disclosed in Patent Document 1 includes a positive electrode pad, a first electrode plate electrically connected to the positive electrode pad and having a flat plate portion, a negative electrode pad, and a second electrode plate electrically connected to the negative electrode pad and having a flat plate portion. According to Patent Document 1, the first electrode plate and the second electrode plate are arranged as parallel flat plates. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2020 / 035931 Summary of the Invention [Problem to be solved by the invention]

[0004] According to Patent Document 1, the electrode plate is formed by bending a single plate-shaped member. The bent part of the electrode plate is attached to an electrode pad on a circuit board. At this time, the two parallel plates are attached close to each other to reduce inductance.

[0005] Here, if two electrode plates are brought closer to each other, the gap between the electrode plates becomes too small, and there is a risk that the electrode plates will come into contact with each other and cause a short circuit. Such a semiconductor device cannot improve the reliability. In particular, when forming an electrode plate by bending a plate-shaped member, there is a high risk that the inclined parts will come into contact because of low bending accuracy. In addition, ultrasonic bonding may be used to attach the electrode plate. In this case, the direction of vibration during ultrasonic bonding is perpendicular to the thickness direction of the electrode plate, so the electrode plate is likely to be inclined and deformed. This further increases the risk that the electrode plates will come into contact with each other and cause a short circuit.

[0006] Therefore, an object of the present invention is to provide a semiconductor device that can improve reliability while reducing inductance. [Means for solving the problem]

[0007] A semiconductor device according to the present disclosure includes a circuit pattern including a first circuit plate and a second circuit plate spaced apart from the first circuit plate in a first direction, a semiconductor chip arranged on the circuit pattern and electrically connected to the circuit pattern, a first electrode plate electrically connected to the first circuit plate, and a second electrode plate electrically connected to the second circuit plate. The first electrode plate includes a first portion joined to the first circuit plate, a second portion arranged continuous with a first end portion on one side of the first portion in the first direction and extending in a second direction which is a thickness direction of the circuit pattern, and a third portion arranged continuous with a second end portion on one side of the second portion in the second direction and spaced apart from the first portion in the second direction. The second electrode plate includes a fourth portion joined to the second circuit plate, a fifth portion arranged to be connected to a third end portion on one side of the fourth portion in the first direction and extending in the second direction, and a sixth portion arranged to be connected to a fourth end portion on one side of the fifth portion in the second direction and spaced apart from the fourth portion in the second direction. The second portion and the fifth portion are spaced apart in the first direction. The third portion and the sixth portion are spaced apart in the second direction and arranged in parallel. The third portion includes a protruding region that protrudes toward the fifth portion in the first direction beyond the second end portion. Effect of the Invention

[0008] According to the semiconductor device, the inductance can be reduced and the reliability can be improved. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a schematic plan view of a semiconductor device according to a first embodiment. [Diagram 2] FIG. 2 is a schematic side view of the semiconductor device shown in FIG. 1 in which the frame is omitted. [Diagram 3] FIG. 3 is a schematic plan view of the semiconductor device shown in FIG. 1 in which the second electrode plate is not shown. [Figure 4] FIG. 4 is a schematic plan view of the semiconductor device shown in FIG. 1 in which the first electrode plate, the second electrode plate, and the third electrode plate are not shown. [Diagram 5] 5 is a schematic perspective view showing, in an enlarged manner, a part of a first electrode plate and a part of a second electrode plate included in the semiconductor device shown in FIG. [Figure 6] FIG. 6 is a schematic plan view of the second electrode plate. [Figure 7] FIG. 7 is a schematic side view of the second electrode plate. [Figure 8] FIG. 8 is a schematic side view of the second electrode plate. [Figure 9] FIG. 9 is a schematic plan view of the second electrode plate before being folded. [Figure 10] FIG. 10 is a schematic plan view of the first electrode plate. [Figure 11] FIG. 11 is a schematic side view of the first electrode plate. [Figure 12] FIG. 12 is a schematic side view of the first electrode plate. [Figure 13] FIG. 13 is a schematic plan view of the first electrode plate before being folded. [Figure 14] FIG. 14 is a schematic side view showing a part of the semiconductor device before ultrasonic bonding. [Figure 15]FIG. 15 is a schematic side view showing a part of the semiconductor device after ultrasonic bonding. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] [Description of the embodiments of the present disclosure] First, the embodiments of the present disclosure will be listed and described. The semiconductor device according to the present disclosure includes a circuit pattern including a first circuit plate and a second circuit plate spaced apart from the first circuit plate in a first direction, a semiconductor chip disposed on the circuit pattern and electrically connected to the circuit pattern, a first electrode plate electrically connected to the first circuit plate, and a second electrode plate electrically connected to the second circuit plate. The first electrode plate includes a first portion bonded to the first circuit plate, a second portion arranged to be continuous with a first end portion on one side of the first portion in the first direction and extending in a second direction which is the thickness direction of the circuit pattern, and a third portion arranged to be continuous with a second end portion on one side of the second portion in the second direction and spaced apart from the first portion in the second direction. The second electrode plate includes a fourth portion joined to the second circuit plate, a fifth portion arranged to be connected to a third end portion on one side of the fourth portion in the first direction and extending in the second direction, and a sixth portion arranged to be connected to a fourth end portion on one side of the fifth portion in the second direction and spaced apart from the fourth portion in the second direction. The second portion and the fifth portion are spaced apart in the first direction. The third portion and the sixth portion are spaced apart in the second direction and arranged in parallel. The third portion includes a protruding region that protrudes toward the fifth portion in the first direction beyond the second end portion.

[0011] In a semiconductor device including a first electrode plate and a second electrode plate, the first electrode plate and the second electrode plate are arranged to form parallel plates in the semiconductor device in order to reduce inductance. Here, the first electrode plate and the second electrode plate may be formed by folding a plate-shaped member. In this case, a portion to be joined to the circuit pattern, a portion rising in the thickness direction of the circuit pattern, and a portion arranged in parallel to the circuit pattern in the frame and forming a parallel plate are formed. Here, in order to obtain the effect of reducing inductance more efficiently, it is necessary to secure the area forming the parallel plate as wide as possible and to reduce the interval. Here, if the folded parts are close to each other, the first electrode plate and the second electrode plate may come into contact when being joined to the circuit pattern, and may cause a short circuit. In particular, when joining by ultrasonic bonding, the risk of a short circuit increases due to the direction of ultrasonic vibration. Note that if the parts to be joined are pulled apart in the first direction in order to reduce the risk of a short circuit, the area forming the parallel plate becomes smaller, and the effect of reducing inductance is reduced.

[0012] According to the semiconductor device of the present disclosure, since the third portion includes a protruding region that protrudes toward the fifth portion side from the second end, the region constituting the parallel plate can be secured widely, and the effect of reducing inductance can be increased. In this case, since the third portion includes a protruding region that protrudes toward the fifth portion side from the second end, the risk of the second end coming close to the fifth portion can be reduced. Therefore, the risk of contact with the second electrode plate and shorting in the region including the second end can be reduced. As described above, according to such a semiconductor device, it is possible to improve reliability while reducing inductance.

[0013] In the above semiconductor device, the first electrode plate may be a P-type bus bar, and the second electrode plate may be an N-type bus bar. In such a semiconductor device, the direction of the current flowing through the third portion of the first electrode plate is opposite to the direction of the current flowing through the sixth portion of the second electrode plate, thereby achieving a large reduction in inductance.

[0014] In the above semiconductor device, the first portion and the first circuit plate may be ultrasonically bonded. The fourth portion and the second circuit plate may be ultrasonically bonded. In this manner, the first portion and the first circuit plate and the fourth portion and the second circuit plate can be bonded without using a bonding material. In this case, the thickness direction of the protruding region is perpendicular to the direction of vibration during ultrasonic bonding, so that it is difficult to mechanically deform in the direction of vibration. Therefore, even if the first electrode plate and the second electrode plate are ultrasonically bonded, there is a low risk of them coming into contact with each other and causing a short circuit. This can improve reliability.

[0015] In the semiconductor device, the first electrode plate may be formed by bending a plate-shaped member. This allows the first electrode plate to be manufactured by punching out the plate-shaped material into a predetermined shape and bending it, thereby improving productivity.

[0016] In the semiconductor device, an end face of the protruding region facing the fifth portion in the first direction may correspond to a side face of the first electrode plate. This reduces the risk that the second end portion corresponding to the folded portion will come close to the second electrode plate when the plate-like member is folded to form the first electrode plate. Therefore, even if the folding accuracy is low, the risk of contact and short circuit due to tilt during joining can be reduced.

[0017] In the semiconductor device, the distance between the end face of the protruding region and the fifth portion may be 1 mm or less. This makes it possible to ensure a wide region constituting the parallel plates, thereby further reducing inductance.

[0018] In the semiconductor device, the first portion may be provided as a pair symmetrically spaced apart from one another in a third direction perpendicular to the first direction when viewed in the second direction. This allows current to flow efficiently from the first portion through the second portion to the third portion, thereby further reducing inductance.

[0019] In the semiconductor device, the distance between the protruding region and the fifth portion may be 80% or less of the distance between the third portion and the sixth portion, thereby ensuring a wide region constituting the parallel plates and further reducing inductance.

[0020] [Details of the embodiment of the present disclosure] Next, an embodiment of a semiconductor device according to the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are designated by the same reference characters and their description will not be repeated.

[0021] (Embodiment 1) The configuration of a semiconductor device according to a first embodiment of the present disclosure will be described. FIG. 1 is a schematic plan view of the semiconductor device according to the first embodiment. To facilitate understanding, the sealing resin included in the semiconductor device is omitted in the drawings shown in FIG. 1 and subsequent figures. FIG. 2 is a schematic side view of the semiconductor device shown in FIG. 1, in which a frame body described later is omitted. FIG. 3 is a schematic plan view of the semiconductor device shown in FIG. 1, in which a second electrode plate described later is omitted. FIG. 4 is a schematic plan view of the semiconductor device shown in FIG. 1, in which a first electrode plate, a second electrode plate, and a third electrode plate described later are omitted. FIG. 5 is a schematic perspective view showing an enlarged view of a part of the first electrode plate and a part of the second electrode plate included in the semiconductor device shown in FIG. 1.

[0022] 1, 2, 3, 4, and 5, a semiconductor device 11 in the first embodiment includes a base plate 12, a frame 13, a substrate 14, semiconductor chips 21a, 21b, 21c, 21d, 22a, 22b, 22c, and 22d, wires 23a, 23b, 23c, 23d, 24a, 24b, 24c, 24d, 25a, 25b, 25c, 25d, 26a, 26b, 26c, and 26d, press-fit pins 27a, 27b, 27c, and 27d, a first electrode plate 31, a second electrode plate 32, and a third electrode plate 33. The first electrode plate 31 is a P terminal and is also called a P-type bus bar. The second electrode plate 32 is an N terminal and is also called an N-type bus bar. The third electrode plate 33 is an O terminal and is also called an O-type bus bar. First electrode plate 31, second electrode plate 32, and third electrode plate 33 are each made of a conductive material, such as a copper plate. When semiconductor device 11 is driven, the direction of the current flowing in first electrode plate 31 and the direction of the current flowing in second electrode plate 32 are opposite to each other.

[0023] The base plate 12 is a rectangular plate-like shape when viewed in the thickness direction. In this embodiment, the longitudinal direction of the base plate 12 is the X direction, the lateral direction of the base plate 12 is the Y direction, and the thickness direction of the base plate 12 is the Z direction. In this embodiment, the X direction is the first direction, the Z direction is the second direction, and the Y direction is the third direction. The base plate 12 includes a main surface 12a located on one side in the thickness direction and a main surface 12b located on the other side in the thickness direction. Four through holes 12c, 12d, 12e, and 12f penetrating in the thickness direction are formed in the four corner regions of the base plate 12. That is, the through holes 12c, 12d, 12e, and 12f reach from one main surface 12a of the base plate 12 to the other main surface 12b. The through holes 12c, 12d, 12e, and 12f are used when mounting the semiconductor device 11 at a predetermined location.

[0024] The frame body 13 is disposed on the base plate 12. The frame body 13 is disposed on the base plate 12 so as to surround the substrate 14. The frame body 13 includes a first wall portion 13a and a second wall portion 13b that face each other in the Y direction, and a third wall portion 13c and a fourth wall portion 13d that face each other in the X direction. A space 19 surrounded by the base plate 12 and the frame body 13 is filled with a sealing resin (not shown). As the type of sealing resin, for example, epoxy resin, silicone gel, or urethane resin is selected.

[0025] The substrate 14 is disposed on one main surface 12a of the base plate 12. The substrate 14 includes a metal plate 15, an insulating plate 16, and a circuit pattern 17. The insulating plate 16 is sandwiched between the metal plate 15 and the circuit pattern 17. The substrate 14 has a structure in which the metal plate 15, the insulating plate 16, and the circuit pattern 17 are laminated. The metal plate 15 is bonded to one main surface 12a of the base plate 12. In this manner, the substrate 14 is attached to the base plate 12.

[0026] The circuit pattern 17 includes a first circuit board 18a, a second circuit board 18b, a third circuit board 18c, a fourth circuit board 18d, a fifth circuit board 18e, a sixth circuit board 18f, and a seventh circuit board 18g. The first circuit board 18a, the fourth circuit board 18d, the fifth circuit board 18e, the sixth circuit board 18f, and the seventh circuit board 18g are each in the form of a strip extending in the Y direction. The widths in the X direction of the fourth circuit board 18d, the fifth circuit board 18e, the sixth circuit board 18f, and the seventh circuit board 18g are all equal. The width in the X direction of the first circuit board 18a is wider than the width in the X direction of the fourth circuit board 18d. The third circuit board 18c has a region extending in the form of a strip in the Y direction. In the X direction, the fourth circuit plate 18d, the fifth circuit plate 18e, the first circuit plate 18a, the second circuit plate 18b, the sixth circuit plate 18f, and the seventh circuit plate 18g are arranged in order from the closest to the third wall portion 13c. The second circuit plate 18b is formed as a pair with a gap in the Y direction. The pair of second circuit plates 18b are arranged adjacent to each other in the Y direction in a region of the third circuit plate 18c that is narrow in the Y direction. The fourth circuit plate 18d and the seventh circuit plate 18g each constitute a so-called auxiliary source wiring pattern. The fifth circuit plate 18e and the sixth circuit plate 18f each constitute a so-called gate wiring pattern.

[0027] The semiconductor chips 21a, 21b, 21c, 21d, 22a, 22b, 22c, and 22d are vertical type, that is, semiconductor chips in which current flows in the thickness direction. The semiconductor chips 21a, 21b, 21c, and 21d are arranged on the first circuit board 18a with a gap in the Y direction. The semiconductor chips 22a, 22b, 22c, and 22d are arranged on a belt-like region of the third circuit board 18c with a gap in the Y direction. The semiconductor chips 21a, 21b, 21c, 21d, 22a, 22b, 22c, and 22d are wide band gap semiconductor chips. A wide band gap semiconductor chip is a semiconductor chip having a semiconductor layer made of a material with a band gap larger than that of silicon as an operating layer. The wide band gap semiconductor chip has a semiconductor layer made of, for example, silicon carbide, gallium nitride, or gallium oxide as an operating layer. Such wide band gap semiconductor chips have a high breakdown voltage and can reduce the resistance of the drift layer, thereby reducing the on-resistance. The semiconductor chips 21a, 21b, 21c, 21d, 22a, 22b, 22c, and 22d are, for example, metal-oxide-semiconductor field effect transistors (MOSFETs). The semiconductor chips 21a, 21b, 21c, 21d, 22a, 22b, 22c, and 22d may have a semiconductor layer made of silicon as an operating layer.

[0028] The source pads of the semiconductor chips 21a, 21b, 21c, 21d and the fourth circuit board 18d are connected by wires 23a, 23b, 23c, 23d, respectively. The gate pads of the semiconductor chips 21a, 21b, 21c, 21d and the fifth circuit board 18e are connected by wires 24a, 24b, 24c, 24d, respectively. The source pads of the semiconductor chips 21a, 21b, 21c, 21d and the third circuit board 18c are connected by wires 25a, 25b, 25c, 25d, 26a, 26b, 26c, 26d, respectively. The source pads of the semiconductor chips 22a, 22b, 22c, 22d and the seventh circuit board 18g are connected by wires 23e, 23f, 23g, 23h, respectively. The gate pads of the semiconductor chips 22a, 22b, 22c, and 22d are connected to the sixth circuit board 18f by wires 24e, 24f, 24g, and 24h, respectively. The source pads of the semiconductor chips 22a and 22b are connected to the second circuit board 18b on one side by wires 25e, 25f, 26e, and 26f. The source pads of the semiconductor chips 22c and 22d are connected to the second circuit board 18b on the other side by wires 25g, 25h, 26g, and 26h.

[0029] The press-fit pins 27a, 27b, 27c, and 27d are arranged on the fourth circuit board 18d, the fifth circuit board 18e, the sixth circuit board 18f, and the seventh circuit board 18g so as to extend in the Z direction. One end of the press-fit pin 27a in the Z direction is connected to an end on the second wall portion 13b side on the fourth circuit board 18d. One end of the press-fit pin 27b in the Z direction is connected to an end on the second wall portion 13b side on the fifth circuit board 18e. One end of the press-fit pin 27c in the Z direction is connected to an end on the first wall portion 13a side on the sixth circuit board 18f. One end of the press-fit pin 27d in the Z direction is connected to an end on the first wall portion 13a side on the seventh circuit board 18g. The other end of the press-fit pins 27a, 27b, 27c, and 27d in the Z direction protrudes to the outside of the semiconductor device 11. Electrical connection between the outside of the semiconductor device 11 and the semiconductor chips 21a, 21b, 21c, 21d, 22a, 22b, 22c, and 22d is ensured through the press-fit pins 27a, 27b, 27c, and 27d.

[0030] Next, the configuration of the third electrode plate 33 will be described. The third electrode plate 33, which is an O-terminal, i.e., an O-shaped bus bar, is formed by bending a single plate-shaped member. The third electrode plate 33 includes seventh portions 47a and 47b, an eighth portion 48, and a ninth portion 49.

[0031] The seventh portions 47a and 47b are electrically connected to the circuit pattern 17, and two of them are formed with a gap in the Y direction. The seventh portions 47a and 47b are each formed in a rectangular shape when viewed in the thickness direction (Z direction) of the base plate 12. The seventh portions 47a and 47b are each parallel to the XY plane. The seventh portions 47a and 47b are each bonded to the third circuit board 18c at positions that avoid the semiconductor chips 22a, 22b, 22c, and 22d when viewed in the Z direction. In this embodiment, the seventh portions 47a and 47b are bonded to the third circuit board 18c by ultrasonic bonding.

[0032] The eighth portion 48 is formed so as to be continuous with each of the seventh portions 47a and 47b and rise from the third circuit board 18c. The eighth portion 48 is formed in a rectangular shape when viewed in the X direction. The eighth portion 48 is parallel to the YZ plane.

[0033] The ninth portion 49 is formed by continuing from the eighth portion 48. The ninth portion 49 is parallel to the XY plane. That is, the seventh portions 47a and 47b are parallel to the ninth portion 49. The ninth portion 49 is disposed so as to penetrate the fourth wall portion 13d in the X direction ...

[0034] Next, the configuration of the second electrode plate 32 will be described. The second electrode plate 32, which is an N terminal, i.e., an N-type bus bar, is formed by bending a single plate-like member. Fig. 6 is a schematic plan view of the second electrode plate 32. Figs. 7 and 8 are schematic side views of the second electrode plate 32. Fig. 7 shows the second electrode plate 32 as viewed in the Y direction, and Fig. 8 shows the second electrode plate 32 as viewed in the X direction. Fig. 9 is a schematic plan view of the second electrode plate 32 before being bent.

[0035] 6 to 9, the second electrode plate 32 includes fourth portions 44a, 44b, fifth portions 45a, 45b, and a sixth portion 46. With particular reference to Fig. 9, the second electrode plate 32 is formed by bending the portions indicated by dashed lines 37a, 37b at 90 degrees and bending the portions indicated by dashed lines 38a, 38b at 90 degrees to have the shape shown in Figs.

[0036] The fourth portions 44a and 44b are electrically connected to the circuit pattern 17, and two of them are formed with a gap in the Y direction. Specifically, the fourth portions 44a and 44b are provided as a pair symmetrically with a gap in a third direction (Y direction) perpendicular to the first direction (X direction) when viewed in the second direction (Z direction). The fourth portions 44a and 44b are each formed in a rectangular shape when viewed in the thickness direction (Z direction) of the base plate 12. The fourth portions 44a and 44b are each parallel to the XY plane. The fourth portion 44a is bonded to one of the second circuit boards 18b. The fourth portion 44b is bonded to the other of the second circuit boards 18b. In this embodiment, the fourth portion 44a is bonded to one of the second circuit boards 18b by ultrasonic bonding. The fourth portion 44b is bonded to the other of the second circuit boards 18b by ultrasonic bonding.

[0037] Two fifth portions 45a and 45b are formed with an interval in the Y direction. Each of the fifth portions 45a and 45b is formed in a rectangular shape when viewed in the X direction. The fifth portions 45a and 45b are arranged to be continuous with the third end 63a on one side of the fourth portions 44a and 44b in the first direction (X direction). Specifically, the fifth portion 45a is formed to be continuous with the fourth portion 44a and to rise from one of the second circuit boards 18b. The fifth portion 45b is formed to be continuous with the fourth portion 44b and to rise from the other of the second circuit boards 18b. Each of the fifth portions 45a and 45b is parallel to the YZ plane. The fifth portions 45a and 45b have a shape extending in the second direction.

[0038] The sixth portion 46 is formed by continuing from each of the fifth portions 45a and 45b. Specifically, the sixth portion 46 is connected to a fourth end 64a on one side of the fifth portions 45a and 45b in the second direction (Z direction). The sixth portion 46 is disposed at a distance from the fourth portions 44a and 44b in the second direction. The sixth portion 46 is parallel to the XY plane. That is, the fourth portions 44a and 44b are parallel to the sixth portion 46. The sixth portion 46 is disposed so as to penetrate the third wall portion 13c in the X direction. The sixth portion 46 includes a fourth region 54 continuing from the fifth portions 45a and 45b, a fifth region 55 having a rectangular shape as viewed in the thickness direction (Z direction), and a sixth region 56 formed to protrude from the fifth region 55 in the X direction. The boundaries of the fourth region 54, the fifth region 55, and the sixth region 56 are indicated by dashed lines in FIG. 6. The sixth region 56 has a through hole 35 formed therethrough in the thickness direction. The second electrode plate 32 is disposed such that the fourth region 54, the fifth region 55, and a part of the sixth region 56 are located within the space 19, and the remaining part of the sixth region 56 and the through hole 35 are located outside the semiconductor device 11. The sixth portion 46 of the second electrode plate 32 is mainly a region that constitutes a parallel plate with the first electrode plate 31. The sixth region 56 and the through hole 35 of the sixth portion 46 are used to ensure electrical connection of the second electrode plate 32 to the outside.

[0039] Next, the configuration of the first electrode plate 31 will be described. The first electrode plate 31, which is a P terminal, i.e., a P-type bus bar, is formed by bending a single plate-like member. Fig. 10 is a schematic plan view of the first electrode plate 31. Figs. 11 and 12 are schematic side views of the first electrode plate 31. Fig. 11 shows the first electrode plate 31 as viewed in the Y direction, and Fig. 12 shows the first electrode plate 31 as viewed in the X direction. Fig. 13 is a schematic plan view of the first electrode plate 31 before being bent.

[0040] 10 to 13, first electrode plate 31 includes first portions 41a, 41b, second portions 42a, 42b, and third portion 43. Referring particularly to Fig. 13, first electrode plate 31 is formed by bending portions along dashed lines 39a, 39b at 90 degrees and portions along dashed lines 40a, 40b at 90 degrees to have the shape shown in Figs.

[0041] The first portions 41a and 41b are electrically connected to the circuit pattern 17, and two of them are formed with a gap in the Y direction. Specifically, the first portions 41a and 41b are provided as a pair symmetrically with a gap in a third direction (Y direction) perpendicular to the first direction (X direction) when viewed in the second direction (Z direction). The first portions 41a and 41b are each formed in a rectangular shape when viewed in the thickness direction (Z direction) of the base plate 12. The first portions 41a and 41b are each parallel to the XY plane. The first portions 41a and 41b are each joined to the first circuit board 18a at positions avoiding the semiconductor chips 21a, 21b, 21c, and 21d when viewed in the Z direction. In this embodiment, the first portions 41a and 41b are joined to the first circuit board 18a by ultrasonic bonding. This will be described later.

[0042] The second parts 42a and 42b are formed in pairs with an interval therebetween in the Y direction. The second parts 42a and 42b are each formed in a rectangular shape when viewed in the X direction. The second parts 42a and 42b are arranged so as to be continuous with the first end 61a on one side of the first parts 41a and 41b in the first direction. Specifically, the second parts 42a and 42b are formed so as to be continuous with the first parts 41a and 41b, respectively, and to rise from the third circuit board 18c. The second parts 42a and 42b are each parallel to the YZ plane. The second parts 42a and 42b are shaped to extend in a second direction (Z direction) which is the thickness direction of the circuit pattern 17.

[0043] The third portion 43 is formed by continuing from each of the second portions 42a, 42b. Specifically, the third portion 43 is connected to the second end 62a on one side of the second portions 42a, 42b in the second direction. The third portion 43 is disposed at an interval from the first portions 41a, 41b in the second direction (Z direction). The third portion 43 is parallel to the XY plane. That is, the first portions 41a, 41b and the third portion 43 are parallel to each other. The third portion 43 is disposed so as to penetrate the third wall portion 13c in the X direction. The third portion 43 includes a first region 51 continuing from the second portions 42a, 42b, a second region 52 having a rectangular shape as viewed in the thickness direction (Z direction), and a third region 53 formed to protrude from the second region 52 in the X direction. The boundaries of the first region 51, the second region 52, and the third region 53 are indicated by dashed lines in FIG. 10. The third region 53 has a through hole 34 penetrating in the thickness direction. The first electrode plate 31 is arranged such that the first region 51, the second region 52, and a part of the third region 53 are located in the space 19, and the remaining part of the third region 53 and the through hole 34 are located outside the semiconductor device 11. In addition, in the Z direction, the third portion 43 is arranged closer to the substrate 14 than the sixth portion 46. That is, in the Z direction, the third portion 43 of the first electrode plate 31 is arranged between the substrate 14 and the sixth portion 46 of the second electrode plate 32 with a gap therebetween. The third portion 43 of the first electrode plate 31 mainly constitutes a region that constitutes a parallel plate with the second electrode plate 32. The third region 53 and the through hole 34 of the third portion 43 are used to ensure electrical connection of the first electrode plate 31 to the outside. Further, the third region 53 of the third portion 43 and the sixth region 56 of the sixth portion 46 are disposed with a shift in position in the Y direction. Specifically, the third region 53 is disposed at a position closer to the first wall portion 13a in the Y direction, and the sixth region 56 is disposed at a position closer to the second wall portion 13b in the Y direction.

[0044] Here, the first region 51 included in the third portion 43 is a protruding region that protrudes toward the fifth portions 45a, 45b side from the second end 62a in the X direction, which is the first direction. That is, the first region 51, which is a protruding region, also constitutes a parallel plate between the sixth portion 46 and the first region 51 in a region indicated by a space 29 surrounded by a dashed line in FIG. 2 and the like. An end face 65 of the first region 51, which is a protruding region facing the fifth portions 45a, 45b in the first direction, corresponds to a side surface of the first electrode plate 31. Also, the distance between the first region 51, which is a protruding region, and the fifth portions 45a, 45b, indicated by the distance D1 in FIG. 2, is 80% or less of the distance between the third portion 43 and the sixth portion 46, indicated by the distance D2 in FIG. 2.

[0045] Next, an example of a manufacturing method of the semiconductor device 11 having the above configuration will be briefly described. First, the substrate 14 is bonded onto the base plate 12, and the semiconductor chips 21a, 21b, 21c, 21d, 22a, 22b, 22c, and 22d are bonded to the circuit pattern 17. At this time, for example, the bonding is performed by reflow soldering using solder. Then, for example, the respective members are connected by the wires 23a to 23h, 24a to 24h, 25a to 25h, and 26a to 26h using stitch bonding. In addition, the first electrode plate 31, the second electrode plate 32, and the third electrode plate 33 are formed by punching out a single plate-like member into a predetermined shape and then bending it. Then, the first electrode plate 31, the second electrode plate 32, and the third electrode plate 33 are integrated with the frame body 13 by insert molding. Then, the frame body 13 integrated with the first electrode plate 31, the second electrode plate 32, and the third electrode plate 33 is attached by bonding on the base plate 12.

[0046] Thereafter, the first portions 41a, 41b, the fourth portions 44a, 44b, and the seventh portions 47a, 47b are ultrasonically bonded to the circuit pattern 17. Fig. 14 is a schematic side view showing a portion of the semiconductor device 11 before ultrasonic bonding. Fig. 15 is a schematic side view showing a portion of the semiconductor device 11 after ultrasonic bonding. In Fig. 15, the second portion 42a and the fifth portion 45a are exaggerated and greatly tilted to facilitate understanding.

[0047] 14 and 15, if the bending accuracy is low and the angle between the first portion 41a and the second portion 42a is not 90 degrees, the second portion 42a will be close to each other. However, the second end 62a, which is the bent portion, is located farther from the fifth portion 45a than the first region 51, which is the protruding region, and therefore the risk of contact and short circuit can be reduced. In this manner, the first electrode plate 31 and the second electrode plate 32 are joined by ultrasonic bonding.

[0048] Then, a sealing resin is filled into the space 19. Thereafter, a lid (not shown) is attached to complete the manufacturing of the semiconductor device 11.

[0049] According to such a semiconductor device 11, since the third portion 43 includes the first region 51 which is a protruding region protruding toward the fifth portion 45a side from the second end 62a, the region constituting the parallel plate can be secured widely, and the effect of reducing the inductance can be increased. In this case, since the third portion 43 includes the first region 51 which is a protruding region protruding toward the fifth portion 45a side from the second end 62a, the risk that the second end 62a will come close to the fifth portion 45a can be reduced. Therefore, the risk of contact with the second electrode plate 32 and short circuiting in the region including the second end 62a can be reduced. As described above, according to such a semiconductor device 11, the reliability can be improved while the inductance is reduced.

[0050] In this embodiment, the first electrode plate 31 is a P-type bus bar, and the second electrode plate 32 is an N-type bus bar. In such a semiconductor device 11, the direction of the current flowing through the third portion 43 of the first electrode plate 31 is opposite to the direction of the current flowing through the sixth portion 46 of the second electrode plate 32, thereby achieving a large reduction in inductance.

[0051] In this embodiment, the first portions 41a, 41b and the first circuit board 18a are ultrasonically bonded, and the fourth portions 44a, 44b and the second circuit board 18b are ultrasonically bonded. Therefore, the first portions 41a, 41b and the first circuit board 18a and the fourth portions 44a, 44b and the second circuit board 18b can be bonded without using a bonding material. In this case, the thickness direction of the first region 51, which is the protruding region, is perpendicular to the direction of vibration during ultrasonic bonding, so it is difficult to mechanically deform in the direction of vibration. Therefore, even if the first electrode plate 31 and the second electrode plate 32 are ultrasonically bonded, there is a low risk of them coming into contact with each other and shorting out. This can improve reliability.

[0052] In this embodiment, the first electrode plate 31 is formed by bending a plate-shaped member. Therefore, the first electrode plate 31 can be manufactured by punching out a plate-shaped material into a predetermined shape and bending it, thereby improving productivity.

[0053] In this embodiment, an end surface 65 of the first region 51, which is a protruding region facing the fifth portions 45a, 45b in the first direction, corresponds to a side surface of the first electrode plate 31. This reduces the risk that the second end 62a, which corresponds to the folded portion, will come close to the second electrode plate 32 when the plate-like member is folded to form the first electrode plate 31. Therefore, even if the folding accuracy is low, the risk of contact and short circuit due to tilt at the time of joining can be reduced.

[0054] In this embodiment, the distance between the end face 65 of the first region 51, which is the protruding region, and the fifth portions 45a, 45b is 1 mm or less. This ensures a wide region that constitutes the parallel plates, thereby further reducing the inductance.

[0055] In this embodiment, the first portions 41a, 41b are provided as a pair symmetrically spaced apart from each other in a third direction perpendicular to the first direction when viewed in the second direction, so that a current can efficiently flow from the first portion through the second portion to the third portion, thereby further reducing inductance.

[0056] In this embodiment, the distance between the first region 51, which is the protruding region, and the fifth portions 45a, 45b is 80% or less of the distance between the third portion 43 and the sixth portion 46. This ensures a wide region constituting the parallel plates, thereby further reducing the inductance.

[0057] (Other embodiments) In the above embodiment, the first electrode plate is formed by bending one plate-like member, but the present invention is not limited to this, and the first electrode plate may be formed by joining a plurality of plate-like members, for example, by joining a plate-like member corresponding to the first portion, a plate-like member corresponding to the second portion, and a plate-like member corresponding to the third portion together. The same applies to the second electrode plate and the third electrode plate.

[0058] In the above embodiment, the first electrode plate is joined to the first circuit plate by ultrasonic bonding, but the present invention is not limited to this, and the first electrode plate may be joined to the first circuit plate by a bonding material such as solder or a conductive adhesive. The same applies to the second and third electrode plates.

[0059] In the above embodiment, the semiconductor device is configured to include a first electrode plate which is a P-type bus bar, a second electrode plate which is an N-type bus bar, and a third electrode plate which is an O-type bus bar. However, the present invention is not limited to this, and the semiconductor device may include two electrode plates which do not include a third electrode plate and which form parallel plates.

[0060] It should be understood that the embodiments disclosed herein are illustrative in all respects and are not limiting in any respect. The scope of the present invention is defined by the claims, not the above description, and is intended to include all modifications within the meaning and scope of the claims. [Industrial Applicability]

[0061] The semiconductor device of the present disclosure can be particularly advantageously applied in cases where reduced inductance and improved reliability are required. [Explanation of symbols]

[0062] 11 Semiconductor device 12 Base plate 12a,12b main surface 12c,12d,12e,12f,34,35,36 through hole 13 Frame 13a 1st wall 13b 2nd wall part 13c 3rd wall section 13d Fourth wall 14 Substrate 15 metal plate 16 Insulating plate 17 Circuit Pattern 18a 1st circuit board 18b 2nd circuit board 18c 3rd circuit board 18d 4th circuit board 18e 5th circuit board 18f 6th circuit board 18g 7th circuit board 19 Space 21a, 21b, 21c, 21d, 22a, 22b, 22c, 22d Semiconductor chips 23a, 23b, 23c, 23d, 23e, 23f, 23g, 23h, 24a, 24b, 24c, 24d, 24e, 24f, 24g, 24h, 25a, 25b, 25c, 25d, 25e, 25f, 25g, 25h, 26a, 26b, 26c, 26d, 26e, 26f, 26g, 26h Wire 27a,27b,27c,27d プレスフィットピン 31. 1st electrode plate 32. Second electrode plate 33. The third electrode plate 37a,37b,38a,38b,39a,39b,40a,40b broken line 41a,41b Part 1 42a,42b Part 2 43 Part 3 44a,44b Part 4 45a,45b Part 5 46 Part 6 47a,47b Part 7 48 Part 8 49 Part 9 51 1st area (prominent area) 52 Second Area 53 The third area 54 The 4th Domain 55 The 5th Domain 56 6th Area 57 The 7th Domain 58 The 8th Domain 61a 1st end 62a Second end 63a Third end 64a 4th end 65 End face 66 D1,D2 interval

Claims

1. a circuit pattern including a first circuit board and a second circuit board spaced apart from the first circuit board in a first direction; a semiconductor chip disposed on the circuit pattern and electrically connected to the circuit pattern; a first electrode plate electrically connected to the first circuit plate; a second electrode plate electrically connected to the second circuit plate; The first electrode plate is a first portion joined to the first circuit board; a second portion disposed adjacent to a first end of the first portion in the first direction and extending in a second direction that is a thickness direction of the circuit pattern; a third portion connected to a second end portion on one side of the second portion in the second direction and spaced apart from the first portion in the second direction; The second electrode plate is a fourth portion joined to the second circuit board; a fifth portion disposed adjacent to a third end portion on one side of the fourth portion in the first direction and extending in the second direction; a sixth portion connected to a fourth end portion on one side of the fifth portion in the second direction and spaced apart from the fourth portion in the second direction; the second portion and the fifth portion are spaced apart in the first direction, the third portion and the sixth portion are arranged in parallel to each other and spaced apart from each other in the second direction, The third portion includes a protruding region that protrudes toward the fifth portion further than the second end in the first direction.

2. the first electrode plate is a P-type bus bar, The semiconductor device according to claim 1 , wherein the second electrode plate is an N-type bus bar.

3. the first portion and the first circuit board are ultrasonically bonded; 3. The semiconductor device according to claim 1, wherein the fourth portion and the second circuit board are ultrasonically bonded together.

4. The semiconductor device according to claim 1 , wherein the first electrode plate is formed by bending a plate-like member.

5. 5 . The semiconductor device according to claim 1 , wherein an end face of the protruding region facing the fifth portion in the first direction corresponds to a side face of the first electrode plate.

6. The semiconductor device according to claim 1 , wherein a distance between an end face of the protruding region and the fifth portion is 1 mm or less.

7. 7. The semiconductor device according to claim 1, wherein the first portions are provided as a pair symmetrically spaced apart from each other in a third direction perpendicular to the first direction when viewed in the second direction.

8. 8. The semiconductor device according to claim 1, wherein a distance between said protruding region and said fifth portion is 80% or less of a distance between said third portion and said sixth portion.

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