Control device, image processing device and electronic device

Abstract

To perform processing about power supply control, between processors connected by a communication connector which does not include an interface for power supply control on a specification.SOLUTION: An image processing apparatus includes a CPU 10, an ASIC 20, and a PCIe connector 3. The ASIC 20 transmits a request signal for requesting switching from a low-power consumption mode to a normal-power consumption mode to the CPU 10 by using a first interface which implements HotPlug in the PCIe. In response to receiving the request signal, the CPU 10 transmits an instruction signal for an instruction to switch from the pow-power consumption mode to the normal-power consumption mode to a power supply device 21 by using a second interface which implements HotPlug in the PCIe.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a control device, an image processing device, and an electronic device. [Background technology]

[0002] Patent Document 1 describes that serial communication is performed between a plurality of boards such as a central processing unit (CPU) and an application specific integrated circuit (ASIC), and power supply control is also performed. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2000-105796 A Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to perform processing related to power supply control between processors connected by a communication connector that does not include a standard interface for power supply control. [Means for solving the problem]

[0005] The control device of claim 1 of the present invention has two or more processors including at least a first processor and a second processor, and a communication connector including at least two or more interfaces for exchanging signals between the two or more processors to determine the presence of each other, wherein the first processor transmits a request signal to the second processor using a first interface of the two or more interfaces, requesting a switch from a first power consumption mode to a second power consumption mode having higher power consumption than the first power consumption mode, and upon receiving the request signal, the second processor transmits an instruction signal to the power supply device using the second interface of the two or more interfaces, instructing the power supply device to switch from the first power consumption mode to the second power consumption mode.

[0006] A control device according to claim 2 of the present invention, in the configuration described in claim 1, is configured such that information relating to the target to which power is to be supplied is input to the first processor, and the second processor transmits an instruction signal to the power supply device in accordance with the information input to the first processor.

[0007] A control device according to claim 3 of the present invention, in the configuration described in claim 1 or 2, receives information regarding the target to which power is to be supplied to the first processor via an OR circuit and without passing through the OR circuit, and the first processor includes information regarding the difference between the information input via the OR circuit and the information input without passing through the OR circuit in the request signal and transmits it to the second processor.

[0008] A control device according to a fourth aspect of the present invention has the configuration according to any one of the first to third aspects, wherein the communication connector complies with the PCIe (Peripheral Component Interconnect-Express) standard.

[0009] A control device according to claim 5 of the present invention has a configuration as defined in any one of claims 1 to 4, in which at least two or more interfaces for transmitting and receiving signals between the two or more processors to determine their presence are interfaces for realizing HotPlug.

[0010] The control device of claim 6 of the present invention, in the configuration described in any one of claims 1 to 5, has a board including a CPU (Central Processing Unit) which is the first processor and a board including an ASIC (Application Specific Integrated Circuit) which is the second processor, which are connected by the communication connector.

[0011] An image processing device according to a seventh aspect of the present invention includes the control device according to any one of the first to sixth aspects.

[0012] An electronic device according to an eighth aspect of the present invention includes the control device according to any one of the first to sixth aspects. Effect of the Invention

[0013] According to the control device of claim 1, processing related to power supply control is performed between the first processor and the second processor connected by a communication connector that does not include a power supply control interface according to its standard.

[0014] According to the control device of claim 2, an instruction signal is transmitted to the power supply control device according to the result of a comparison between information regarding the target to which power is supplied that is input to the first processor in the first power consumption mode and information regarding the target to which power is supplied that is input to the first processor when switching from the first power consumption mode to the second power consumption mode.

[0015] According to the control device of claim 3 of the present invention, information regarding the difference between the information input via the OR circuit and the information input without passing through the OR circuit is included in a request signal and transmitted to the second processor.

[0016] According to the control device of claim 4 of the present invention, the communication connector is realized according to the PCIe standard.

[0017] According to the control device of claim 5 of the present invention, at least two or more interfaces for transmitting and receiving signals for determining the presence of each other between two or more processors are realized by an interface for realizing HotPlug.

[0018] According to the control device of the sixth aspect of the present invention, a board including a CPU as a first processor and a board including an ASIC as a second processor are connected by a communication connector.

[0019] According to the image processing device of claim 7, processing related to power supply control is performed between the first processor and the second processor connected by a communication connector that does not include a power supply control interface according to its standard.

[0020] According to the electronic device of claim 8, processing related to power supply control is performed between the first processor and the second processor connected by a communication connector that does not include a power supply control interface according to its standard. [Brief description of the drawings]

[0021] [Figure 1] FIG. 1 is a diagram illustrating an example of the configuration of an image processing device 1000 according to an embodiment of the present invention. [Diagram 2] 4 is a diagram illustrating an example of a pin assignment in a PCIe connector used in the present embodiment. FIG. [Diagram 3] 4 is a flowchart illustrating an operation of the control device 100 according to the present embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0022] FIG. 1 is a diagram illustrating the configuration of an image processing device 1000 according to an embodiment of the present invention. The image processing device 1000 is a device called a multifunction device that has multiple functions related to image processing such as printing and copying. The image processing device 1000 includes a control device 100, an image reading device 200, an image forming device 300, and various devices 400. The control device 100 is a device that controls the operation of the image processing device 1000. The image reading device 200 is a device that reads an image from a medium such as paper. The image forming device 300 is a device that forms an image on a medium such as paper. The various devices 400 are, for example, a user interface device, a sensor device, etc.

[0023] The control device 100 is an example of a control device according to the present invention. The control device 100 includes a CPU (Central Processing Unit) board 1, an engine control board 2, and a PCIe connector 3 that connects these boards 1 and 2.

[0024] The CPU board 1 includes a CPU 10 which is an example of a second processor according to the present invention, a power supply device 11 which supplies power to the CPU board 1, and a power supply control device 12 which performs processing related to power supply control in the image processing device 1000.

[0025] The engine control board 2 includes an ASIC (Application Specific Integrated Circuit) 20 which is an example of a first processor according to the present invention, a power supply device 21 which supplies power to the engine control board 2, and an OR circuit 22.

[0026] The PCIe (Peripheral Component Interconnect-Express) connector 3 is a communication connector conforming to PCIe, which is a serial transfer type communication interface standard for high speed data communication. In the image processing device 1000, in order to realize a certain level or higher of high processing performance, a CPU 10 that mainly performs central control and an ASIC 20 that mainly performs image processing are separately implemented, and the CPU 10 and the ASIC 20 are connected by the PCIe connector 3.

[0027] In the image processing device 1000 configured as described above, in order to switch from a first power consumption mode, for example, a low power consumption mode or a power saving mode, to a second power consumption mode, for example, a normal power consumption mode or a standby mode, which consumes more power than the first power consumption mode, it is necessary to exchange signals related to power control between the CPU 10 and the ASIC 20.

[0028] However, the PCIe communication interface standard does not include such an interface for power supply control. Therefore, in this embodiment, in the PCIe communication interface standard, two or more interfaces that transmit and receive signals for determining the presence of two or more processors are used to exchange signals related to the above-mentioned power supply control between the CPU 10 and the ASIC 20.

[0029] More specifically, the PCIe communication interface standard provides two interfaces called HotPlug for transmitting signals between two boards to determine whether the other board exists. In this embodiment, the interfaces called HotPlug are used to transmit signals related to power supply control between the CPU 10 and the ASIC 20.

[0030] 2 is a diagram for explaining an example of pin assignment in the PCIe connector 3 used in this embodiment. PCIe employs a transfer method in which two lines are grouped together to make communication bidirectional. These two-line grouped bidirectional communication paths are called lanes. FIG. 2 illustrates an example of pin assignment when the number of lanes is one.

[0031] As shown in Fig. 2, the pin with the pin no. "A1" and the pin name "PRSNT#1" is the first pin corresponding to HotPlug. In this embodiment, the interface corresponding to this pin is an interface for transmitting an instruction signal from the CPU 10 to the engine control board 2 to instruct it to switch from the first power consumption mode to the second power consumption mode. This interface is an example of the second interface in the present invention. In Fig. 1, the signal line a1 means that it is the signal line of the interface corresponding to this pin.

[0032] In FIG. 2, the pin with the pin no. "B17" and the pin name "PRSNT#2" is the second pin corresponding to HotPlug. In this embodiment, the interface corresponding to this pin is an interface for transmitting a request signal from the ASIC 20 to the CPU 10 requesting that the CPU 10 switch from the first power consumption mode to the second power consumption mode. This interface is an example of the first interface in the present invention. In FIG. 1, the signal line a2 means that it is the signal line of the interface corresponding to this pin.

[0033] That is, the ASIC 20 transmits a request signal requesting switching from the first power consumption mode to the second power consumption mode to the CPU 10 using the first interface. Upon receiving this request signal, the CPU 10 transmits an instruction signal instructing the power supply device 21 to switch from the first power consumption mode to the second power consumption mode using the second interface via the power supply control device 12. Note that the examples of pin assignments other than those described above are conventionally compliant with PCIe, and therefore detailed explanations will be omitted.

[0034] Returning to the explanation of FIG. 1, the OR circuit 22 will be explained. One input terminal of the OR circuit 22 is connected to the image reading device 200. When the image reading device 200 requests switching from the first power consumption mode to the second power consumption mode due to a reason attributable to the image reading device 200 itself, the image reading device 200 inputs, for example, a signal with a signal value of "1" to the OR circuit 22. At this time, the image reading device 200 also inputs the signal with a signal value of "1" directly to the ASIC 20 without going through the OR circuit 22.

[0035] The other input terminal of the OR circuit 22 is connected to the image forming apparatus 300. When the image forming apparatus 300 requests switching from the first power consumption mode to the second power consumption mode due to a reason attributable to the image forming apparatus 300 itself, the image forming apparatus 300 inputs a signal having a signal value of "1" to the OR circuit 22. At this time, the image forming apparatus 300 also inputs the signal having a signal value of "1" directly to the ASIC 20 without passing through the OR circuit 22.

[0036] An output terminal of the OR circuit 22 is connected to the ASIC 20. When a signal having a signal value of “1” is input from the image reading device 200 and / or the image forming device 300, the OR circuit 22 inputs the signal having a signal value of “1” to the ASIC 20.

[0037] The ASIC 20 holds in an internal memory a signal value directly input from the image reading device 200, a signal value directly input from the image forming device 300, and a signal value input from the output terminal of the OR circuit 22, and transmits a request signal including these signal values ​​to the CPU 10 using the first interface. The CPU 10 determines the reason for switching from the first power consumption mode to the second power consumption mode based on the combination of these signal values. Specifically, when the combination is a signal value "1" input from the image reading device 200 and a signal value "1" input from the output terminal of the OR circuit 22, the CPU 10 determines that switching from the first power consumption mode to the second power consumption mode is requested due to a reason caused by the image reading device 200. On the other hand, when the combination is a signal value "1" input from the image forming device 300 and a signal value "1" input from the output terminal of the OR circuit 22, the CPU 10 determines that switching from the first power consumption mode to the second power consumption mode is requested due to a reason caused by the image forming device 300.

[0038] As a result, when the CPU 10 determines that a request to switch from the first power consumption mode to the second power consumption mode has been made due to a reason attributable to the image reading device 200, for example, the CPU 10 can instruct only the image reading device 200 to switch from the first power consumption mode to the second power consumption mode. Also, when the CPU 10 determines that a request to switch from the first power consumption mode to the second power consumption mode has been made due to a reason attributable to the image forming device 300, for example, the CPU 10 can instruct only the image forming device 300 to switch from the first power consumption mode to the second power consumption mode.

[0039] In this way, information on the power supply targets is input to the ASIC 20 from a plurality of power supply targets via the OR circuit 22 and without via the OR circuit 22. The ASIC 20 then transmits a request signal including information on the difference between the information input via the OR circuit 22 and the information input without via the OR circuit 22 to the CPU 10. The CPU 10 transmits an instruction signal corresponding to the information on the difference to the power supply device 21. As a result, power is supplied only to power supply targets that require power.

[0040] 3 is a flowchart illustrating the operation of the control device 100 according to this embodiment. The image processing device 1000 operates in the second power consumption mode, for example, after the image processing device 1000 is powered on (step S11). At this time, power is supplied to the CPU board 1, the engine control board 2, the image reading device 200, the image forming device 300, and the various devices 400.

[0041] If a timeout occurs without any event occurring while operating in the second power consumption mode, the CPU 10 determines to switch to the first power consumption mode (step S12: YES), and instructs the power supply control device 12 to switch to the first power consumption mode (step S13). As a result, under the control of the power supply control device 12, the power supply to the engine control board 2, the image reading device 200, the image forming device 300, and the various devices 400 is reduced or stopped while the power supply to the CPU board 1 is maintained.

[0042] The CPU 10 judges whether or not a switch from the first power consumption mode to the second power consumption mode has been requested by the CPU board 1 (step S14). Here, a switch from the first power consumption mode to the second power consumption mode is requested by the CPU board 1 when, for example, a user interface device as a device is operated, or when, for example, a sensor device as a device detects a phenomenon that is a reason for switching to a power consumption mode.

[0043] When it is determined that the CPU board 1 has requested a switch from the first power consumption mode to the second power consumption mode (step S14: YES), the CPU 10 transmits an instruction signal to the power supply control device 12 to instruct the power supply control device 12 to switch from the first power consumption mode to the second power consumption mode (step S15). This instruction signal is transmitted from the power supply control device 12 to the power supply device 11, and is also transmitted to the power supply device 21 using the above-mentioned second interface. As a result, the image processing device 1000 is switched to the second power consumption mode (step S16), and operates with power supplied to all of the CPU board 1, the engine control board 2, the image reading device 200, the image forming device 300, and the various devices 400 (step S11).

[0044] When it is not determined that the CPU board 1 has requested to switch from the first power consumption mode to the second power consumption mode (step S14: NO), the ASIC 20 determines whether or not the image reading device 200 or the image forming device 300 has requested to switch from the first power consumption mode to the second power consumption mode (step S17). When the ASIC 20 determines, based on the input from the OR circuit 22, that the image reading device 200 or the image forming device 300 has requested to switch from the first power consumption mode to the second power consumption mode (step S17: YES), it transmits a request signal requesting to switch from the first power consumption mode to the second power consumption mode to the CPU 10 using the above-mentioned first interface (step S18).

[0045] At this time, the ASIC 20 transmits to the CPU 10 a request signal including the signal value directly input from the image reading device 200, the signal value directly input from the image forming device 300, and the signal value input from the output terminal of the OR circuit 22.

[0046] When the CPU 10 receives this request signal, it transmits an instruction signal to the power supply control device 12 to instruct it to switch from the first power consumption mode to the second power consumption mode (step S15). This instruction signal is transmitted from the power supply control device 12 to the power supply device 11, and is also transmitted to the power supply device 21 using the above-mentioned second interface. At this time, the CPU 10 judges the reason for switching from the first power consumption mode to the second power consumption mode based on the combination of the above signal values, and transmits an instruction signal according to the reason to the power supply control device 12. As a result, under the control of the power supply control device 12, power is supplied only to the power supply target that requires power (step S16). For example, if the reason for switching from the first power consumption mode to the second power consumption mode is due to a request from the image reading device 200, power is supplied to the CPU board 1, the engine control board 2, the image reading device 200, and various devices 400, while the power supply to the image forming device 300 is reduced or stopped.

[0047] According to the present embodiment described above, a request for power supply control from the engine control board 2 to the CPU board 1 and an instruction for power supply control from the CPU board 1 to the engine control board 2 are realized using an existing PCIe connector. In other words, between processors connected by a communication connector that does not include a power supply control interface in its specifications, a process for power supply control is performed using a communication connector that includes at least two or more interfaces for transmitting and receiving signals for determining the presence of each other between two or more processors.

[0048] The above-described embodiment is merely an example of the implementation of the present invention, and may be modified as follows. Furthermore, the above-described embodiment and each of the modifications shown below may be implemented in combination as necessary.

[0049] For example, the second processor exemplified by the CPU 10 in the embodiment and the first processor exemplified by the ASIC 20 may be other processors such as a GPU (Graphics Processing Unit) or an FPGA (Field-Programmable Gate Array).

[0050] Instead of PCIe exemplified in the embodiment, another interface standard having at least two or more interfaces for transmitting and receiving signals between two or more processors to determine the presence of each other may be used. Furthermore, the at least two or more interfaces for transmitting and receiving signals between two or more processors to determine the presence of each other may be interfaces other than the interface for realizing HotPlug exemplified in the embodiment.

[0051] The control device according to the present invention is not limited to the image processing device exemplified in the embodiment, but can be implemented in electronic devices in general.

[0052] In the above-described embodiment, the programs executed by the CPU 10 or the ASIC 20 may be downloaded to the control device via a communication line such as the Internet. Furthermore, these programs may be provided in a state recorded on a computer-readable recording medium such as a magnetic recording medium (such as a magnetic tape or a magnetic disk), an optical recording medium (such as an optical disk), a magneto-optical recording medium, or a semiconductor memory. [Explanation of symbols]

[0053] Reference Signs List 1: CPU board, 2: engine control board, 3: PCIe connector, 10: CPU, 11: power supply device, 12: power supply control device, 20: ASIC, 21: power supply device, 22: OR circuit, 100: control device, 200: image reading device, 300: image forming device, 1000: image processing device.

Claims

1. two or more processors including at least a first processor and a second processor; a communication connector including at least two interfaces for transmitting and receiving signals between the two or more processors for determining the presence of each other; having The first processor, transmitting a request signal to the second processor, using a first interface of the two or more interfaces, to request switching from a first power consumption mode to a second power consumption mode having a higher power consumption than the first power consumption mode; The second processor, The control device, upon receiving the request signal, transmits an instruction signal to the power supply device, instructing the power supply device to switch from the first power consumption mode to the second power consumption mode, using a second interface among the two or more interfaces.

2. The first processor includes: Information about the electricity supply target is entered, The control device according to claim 1 , wherein the second processor transmits to the power supply device an instruction signal corresponding to the information input to the first processor.

3. information relating to a target to which power is to be supplied is input to the first processor via an OR circuit and without via the OR circuit; 3. The control device according to claim 1, wherein the first processor includes information regarding a difference between the information input via the OR circuit and the information input without passing through the OR circuit in the request signal and transmits the request signal to the second processor.

4. 4. The control device according to claim 1, wherein the communication connector complies with the PCIe (Peripheral Component Interconnect-Express) standard.

5. At least two or more interfaces for transmitting and receiving signals for determining the presence of each other between the two or more processors, 5. The control device according to claim 1, which is an interface for implementing HotPlug.

6. a substrate including a CPU (Central Processing Unit) that is the first processor; a substrate including an ASIC (Application Specific Integrated Circuit) which is the second processor; 6. The control device according to claim 1, wherein the communication connector is connected to the control device.

7. An image processing device comprising the control device according to any one of claims 1 to 6.

8. An electronic device comprising the control device according to any one of claims 1 to 6.

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