Semiconductor Device

Abstract

To obtain semiconductor devices that can reduce the inductance value of wires.SOLUTION: A MMIC2 has DC pads 3a-3c. A plurality of MIM capacitors 5a-5c are mounted on the bias substrate 4. A plurality of pads 6a-6c are provided on the bias substrate 4 and are connected to the top ground electrodes of the plurality of MIM capacitors 5a-5c, respectively. Wires 7a-7c connect DC pads 3a-3c to any of the plurality of pads 6a-6c. The plurality of pads 6a-6c are disposed between the DC pads 3a-3c and the plurality of MIM capacitors 5a-5c in plan view and extend parallel to the rows of the plurality of MIM capacitors 5a-5c arranged side by side.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] Microwave or millimeter wave band MMICs (Monolithic Microwave Integrated Circuits) are used (see, for example, Patent Document 1). In a semiconductor device in which an MMIC is mounted in a package, an MIM capacitor is placed near the DC pad of the MMIC, and the two are connected by a wire. This MIM capacitor shorts out unnecessary low frequency signals, preventing leakage of RF signals into the oscillation or bias circuit side of the amplifier MMIC circuit. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 63-244761 Summary of the Invention [Problem to be solved by the invention]

[0004] The size of the MIM capacitor is, for example, about three times larger than the size of the DC pad. Therefore, when multiple DC pads, especially three or more, are placed close to each other, and three or more MIM capacitors are connected to them by wires and placed side by side, the wires become slanted. This results in a longer wire and a larger inductance value. The low-frequency signal is reflected back to the circuit side by the inductance component of the wire, making it impossible to short out, which can cause oscillation.

[0005] Increasing the number of wires can reduce the total inductance value by paralleling the inductance, but there is a limit to how much inductance can be reduced because the number of wires is limited by the size of the MIM capacitor.

[0006] The present disclosure has been made to solve the above-mentioned problems, and has an object to obtain a semiconductor device capable of reducing the inductance value of wires. [Means for solving the problem]

[0007] The semiconductor device according to the present disclosure comprises an MMIC having a DC pad, a bias substrate, a plurality of MIM capacitors mounted on the bias substrate, a plurality of pads provided on the bias substrate and connected to upper electrodes of the plurality of MIM capacitors, respectively, and a wire connecting the DC pad to any one of the plurality of pads, wherein the plurality of pads are arranged between the DC pad and the plurality of MIM capacitors in a planar view and extend parallel to the row of the plurality of MIM capacitors arranged side by side. Effect of the Invention

[0008] In the present disclosure, multiple pads are arranged between the DC pads and the MIM capacitors in a plan view, and extend parallel to the row of horizontally arranged MIM capacitors. This increases the degree of freedom of the bonding position of the wires to the pads, allowing the wires to be shorter. The number of wires is also independent of the size of the MIM capacitor. This allows the inductance value of the wires to be reduced. [Brief description of the drawings]

[0009] [Figure 1] 1 is a plan view showing a semiconductor device according to a first embodiment. [Diagram 2] FIG. 2 is a plan view showing a bias substrate according to the first embodiment. [Diagram 3] FIG. 3 is a cross-sectional view taken along line I-II of FIG. [Figure 4] FIG. 1 is a diagram showing a semiconductor device according to a first comparative example. [Diagram 5] FIG. 11 is a diagram showing a semiconductor device according to a second comparative example. [Figure 6] FIG. 11 is a plan view showing an example of a wire length of a semiconductor device according to Comparative Example 2. [Figure 7] 2 is a plan view showing an example of a wire length of the semiconductor device according to the first embodiment. FIG. [Figure 8] 10 is a plan view showing a modified example of the bias substrate according to the first embodiment. FIG. [Figure 9] FIG. 11 is a plan view showing a bias substrate according to the second embodiment. [Figure 10] FIG. 11 is a plan view showing a modified example of the bias substrate according to the second embodiment. [Figure 11] FIG. 11 is a plan view showing a bias substrate according to the third embodiment. [Figure 12] FIG. 11 is a plan view showing a semiconductor device according to a fourth embodiment. [Figure 13] FIG. 11 is a plan view showing a bias substrate according to the fourth embodiment. [Figure 14] FIG. 13 is a plan view showing dimensions of a bias substrate according to the fourth embodiment. [Figure 15] FIG. 13 is a plan view showing a semiconductor device according to a fifth embodiment. [Figure 16] FIG. 13 is a diagram showing an equivalent circuit of a semiconductor device according to a fifth embodiment. [Figure 17] FIG. 13 is a diagram showing capacitance values ​​that can be achieved by combining wire connection methods. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] A semiconductor device according to an embodiment will be described with reference to the drawings. The same or corresponding components are denoted by the same reference numerals, and repeated description may be omitted.

[0011] Embodiment 1 1 is a plan view showing a semiconductor device according to a first embodiment. An MMIC 2 is provided in a package 1. The MMIC 2 is a microwave or millimeter wave amplifier MMIC circuit, and has three DC pads 3a to 3c arranged in a row on its upper surface. A bias substrate 4 is provided adjacent to the MMIC 2 in the package 1. The material of the bias substrate 4 is a substrate material generally used for high frequency circuits, such as GaAs, GaN, SiC, ceramics, etc.

[0012] Three MIM capacitors 5a to 5c are mounted on a bias substrate 4. The MIM capacitors 5a to 5c are arranged in a row in a plan view. Three pads 6a to 6c are provided on the bias substrate 4. The pads 6a to 6c are connected to the upper electrodes of the MIM capacitors 5a to 5c by air bridges or the like (not shown), respectively. The pads 6a to 6c are arranged between the DC pads 3a to 3c and the MIM capacitors 5a to 5c in a plan view, and extend parallel to the row of the horizontally arranged MIM capacitors 5a to 5c.

[0013] Wires 7a to 7c connect the DC pads 3a to 3c to the pads 6a to 6c, respectively. However, it is not necessary to connect wires to all the pads, and it is sufficient that at least one wire connects any one of the DC pads 3a to 3c to any one of the pads 6a to 6c.

[0014] The upper electrodes of MIM capacitors 5a to 5c are each wire-connected to lead connection portion 8 of package 1. However, if there is a concern that direct wire bonding to the upper electrodes of the MIM capacitors may cause damage, another pad connected to the upper electrodes may be provided on the side of the MIM capacitor opposite MMIC 2, and this pad may be wire-connected to lead connection portion 8.

[0015] FIG. 2 is a plan view showing the bias substrate according to the first embodiment. Each of the pads 6a to 6c extends to a position facing the three MIM capacitors 5a to 5c. Specifically, the pad 6a extends from the upper electrode of the MIM capacitor 5a toward the MMIC 2, and then extends from a position facing the MIM capacitor 5a to a position facing at least a part of the MIM capacitor 5c. The pad 6c extends from the upper electrode of the MIM capacitor 5c toward the MMIC 2, and then extends from a position facing the MIM capacitor 5c to a position facing at least a part of the MIM capacitor 5a. The pad 6b extends from the upper electrode of the MIM capacitor 5b toward the MMIC 2, and then branches from a position facing the MIM capacitor 5b to a position facing at least a part of the MIM capacitor 5a and a position facing at least a part of the MIM capacitor 5c. Therefore, the pads 6a to 6c have a length equivalent to the length of the three MIM capacitors 5a to 5c.

[0016] FIG. 3 is a cross-sectional view taken along line I-II in FIG. 2. The MIM capacitor 5c has a base electrode 9, an insulating film 10, and an upper electrode 11, which are stacked in this order from the bottom. The capacitance value of the MIM capacitor 5c is determined by the relative dielectric constant and thickness of the insulating film 10, and the area of ​​the MIM capacitor 5c. A ground pad 12 is provided on the bias substrate 4 and is connected to the base electrode 9 of the MIM capacitor 5c. The ground pad 12 is pulled out to the side opposite the MMIC 2 with respect to the MIM capacitor 5c in a plan view. A plurality of via holes 13 pass through the bias substrate 4 and are connected to the base electrode 9 of the MIM capacitor 5c. The base electrode 9 of the MIM capacitor 5c is connected to GND through the via holes 13. The structures of the MIM capacitors 5a and 5b are similar.

[0017] However, if the MIM capacitors 5a to 5c are each previously connected to GND through the via holes 13, it becomes difficult to connect the MIM capacitors 5a to 5c in series. Therefore, if it is necessary to connect the MIM capacitors 5a to 5c in series, it is not always necessary to form the via holes 13. If there are no via holes 13, the ground pads 12 connected to the base electrodes 9 of the MIM capacitors 5a to 5c are connected to GND through wires. It is also possible to omit the ground pads 12 and connect to GND using only the base electrodes 9 that have the same shape as the ground pads 12.

[0018] 2, the pulled-out ground pad 12 has a shape close to a square. However, if it is desired to connect ground pad 12 to GND with multiple wires, ground pad 12 may be rectangular along the sides of MIM capacitors 5a to 5c, or the area of ​​the pad may be increased.

[0019] Next, the effects of this embodiment will be described in comparison with Comparative Examples 1 and 2. In Comparative Examples 1 and 2, the bias substrate 4 and pads 6a to 6c are not used, and the MIM capacitors 5a to 5c are directly wire-connected to the DC pads 3a to 3c. Fig. 4 is a diagram showing a semiconductor device according to Comparative Example 1. The MIM capacitors 5a to 5c are arranged in a line. The wire 7c connecting the right-most DC pad 3c and the MIM capacitor 5c is the longest.

[0020] 5 is a diagram showing a semiconductor device according to Comparative Example 2. Only the central MIM capacitor 5b is placed far from the MMIC 2, and the left and right MIM capacitors 5a and 5c are placed side by side near the MMIC 2. The length of the wire 7b connecting the central DC pad 3b and the MIM capacitor 5b is more than twice the length of the left and right wires 7a and 7c.

[0021] In this way, in Comparative Examples 1 and 2, some of the wires are long, so that low-frequency signals cannot be effectively shorted, and the risk of oscillation increases. In contrast, in this embodiment, multiple pads 6a-6c are arranged between the DC pads 3a-3c and the MIM capacitors 5a-5c in a plan view, and extend parallel to the row of the MIM capacitors 5a-5c arranged side by side. This increases the degree of freedom in the bonding positions of the wires 7a-7c relative to the pads 6a-6c, and the wires 7a-7c can be shortened. The number of wires 7a-7c also does not depend on the size of the MIM capacitors 5a-5c. Therefore, the inductance value of the wires 7a-7c can be reduced.

[0022] If the inductance of wires 7a to 7c is Lw and the resistance is R, then the cutoff frequency fc of wires 7a to 7c is fc = R / (2 x π x Lw). As Lw increases, fc decreases, and the low-frequency band that passes becomes narrower. Therefore, if an attempt is made to short out a low-frequency signal and Lw becomes large, the region close to DC can be shorted, but the low-frequency region away from DC will be reflected to the MMIC 2 side, increasing the risk of oscillation. Because the inductance functions as a low-pass filter, frequencies above fc will be reflected and not pass.

[0023] 6 is a plan view showing an example of the wire length of the semiconductor device according to Comparative Example 2. Three DC pads 3a-3c and three MIM capacitors 5a-5c of the MMIC 2 are directly wire-connected, respectively. The size of the DC pads 3a-3c is 150 um×100 um. The size of the MIM capacitors 5a-5c is 300 um×300 um. The dimension from the DC pads 3a-3c to the end of the MMIC 2 is 50 um. The distance between the MMIC 2 and the MIM capacitors 5a-5c is 50 um. The wires 7a-7c are placed at the centers of the DC pads 3a-3c and the MIM capacitors 5a-5c. In this case, the length of the wires 7a and 7c connecting the left and right DC pads 3a, 3c and the MIM capacitors 5a, 5c is 300 um, ignoring the height of the loop shape of the wire. If the distance between the MIM capacitors 5a to 5c is 100 um, the length of the wire 7b connecting the central DC pad 3b and the MIM capacitor 5b is 700 um.

[0024] 7 is a plan view showing an example of the wire length of the semiconductor device according to the first embodiment. The width of the pads 6a to 6c is 50 um. The spacing between the pads 6a to 6c is 10 um. The length of the wire 7a of the left DC pad 3a is 195 um. The length of the wire 7b of the central DC pad 3b is 255 um. The length of the wire 7c of the right DC pad 3c is 315 um. Therefore, the length of the wires 7a to 7c in the first embodiment is less than half the length of the central wire 7b of comparative example 2, which is 700 um.

[0025] Table 1 shows the relationship between the wire length and the corresponding inductance value L and cutoff frequency fc. Here, the relationship between the wire length and the inductance value was estimated using 1nH / mm estimated by electromagnetic field analysis. The wire diameter in the calculation was set to 30um.

[0026] [Table 1]

[0027] In the case of the wire length of 700 um in the comparative example 2, the inductance value L is 0.70 nH and the cutoff frequency fc is 22.7 MHz. Therefore, frequencies above 22.7 MHz are reflected. On the other hand, in the case of the wire length of 315 um in the embodiment 1, the inductance value L is 0.315 nH and the cutoff frequency fc is 50.6 MHz. Therefore, it is possible to short out to a higher frequency of 50.6 MHz, and the risk of oscillation is greatly reduced. Note that the height of the wire was ignored in this estimation, but if the height direction is taken into account, the wire length will be about 1.5 times the above length, and the cutoff frequency fc shown in Table 1 will actually shift to the lower side.

[0028] In Comparative Examples 1 and 2, the number of wires is limited depending on the area of ​​the MIM capacitor, so the maximum number of wires is small. For example, in the case of a 300 um x 300 um MIM capacitor, the upper limit of the number of wires is considered to be three even if there are no restrictions on the peripheral circuit. In contrast, in this embodiment, the longitudinal length of the pads 6a to 6c connected to the upper electrodes of the MIM capacitors 5a to 5c is about three times the length of one side of the MIM capacitors 5a to 5c. Therefore, the inductance value of the wires can be reduced by increasing the number of wires.

[0029] 8 is a plan view showing a modified example of the bias substrate according to the first embodiment. The number of wires can be increased by increasing the size of the DC pad 3b of the MMIC 2. For example, if five wires can be inserted, the inductance value of the wire can be reduced to 1 / 5 of that of a single wire. Therefore, five wires are connected to the central pad 6b, and two wires are connected to the left pad 6c.

[0030] The optimum capacitance value of the MIM capacitor varies depending on the frequency band used by the amplifier MMIC, bias conditions, the circuit configuration of the MMIC, the circuit configuration around the MMIC, and the like. Therefore, in the past, in order to select and mount MIM capacitors with different capacitance values ​​according to the conditions, all types were prepared in the required quantity before the start of assembly. However, chip capacitors have almost no difference in appearance even if they have different capacitances, and it may be difficult to distinguish them, so if there are many types of MIM capacitors, work errors may be induced. In addition, since it is not possible to standardize MIM capacitors, the number of types increases, and the number of types used per type decreases, which may restrict cost reduction. Even if MIM capacitors with the same capacitance value can be used, if a MIM capacitor is provided for each DC pad of the MMIC, the number of parts to be die-bonded increases. For example, in Comparative Examples 1 and 2, three MIM capacitors 5a to 5c are each die-bonded to the package 1. The throughput decreases due to the increase in the time required for die-bonding. On the other hand, in this embodiment, one bias substrate 4 provided with three MIM capacitors 5a to 5c is die-bonded to the package 1. Therefore, the number of components to be die-bonded is smaller in this embodiment, and the throughput is improved.

[0031] Furthermore, the pads 6a to 6c are arranged in three rows, and it is desirable that the pad width be the minimum dimension that allows wires to be inserted. It is also desirable that the pad spacing be the minimum spacing possible in the process. By minimizing the pad width and pad spacing, it is possible to shorten the length of the wires 7a to 7c that connect the DC pads 3a to 3c and the pads 6a to 6c. Note that the pad width may be determined by the required current capacity.

[0032] When it is desired to increase the capacitance value of the MIM capacitor, i.e., the area of ​​the MIM capacitor, and there is a restriction on the size of the bias substrate 4, the number of MIM capacitors may be two or less. In addition, although the capacitance values ​​of the three MIM capacitors are set to the same in this embodiment, when many MIM capacitors are used, the capacitance value may be changed every three capacitors.

[0033] Embodiment 2 FIG. 9 is a plan view showing a bias substrate according to the second embodiment. The MIM capacitor 5d is provided on the right side of the row of the MIM capacitors 5a to 5c. The MIM capacitors 5a to 5d are arranged in a row. A pad 6d is further provided on the bias substrate 4. The pad 6d is connected to the upper electrode of the MIM capacitor 5d, extends toward the MMIC 2 in a plan view, and then wraps around between the DC pads 3a to 3c and the pads 6a to 6c. The pad 6d extends parallel to the row of the horizontally arranged MIM capacitors 5a to 5d, and extends to a position facing the MIM capacitors 5a to 5d. Therefore, the pad 6d has a length equivalent to the length of the four MIM capacitors 5a to 5d. The other configurations are the same as those of the first embodiment.

[0034] 10 is a plan view showing a modified example of the bias substrate according to the second embodiment. An MIM capacitor 5e is further provided on the left side of the row of MIM capacitors 5a to 5d. The MIM capacitors 5a to 5e are arranged in a row. A pad 6e is further provided on the bias substrate 4. The pad 6e is connected to the upper electrode of the MIM capacitor 5e, extends toward the MMIC 2 in a plan view, and then wraps around between the DC pads 3a to 3c and the pads 6a to 6d. The pad 6e extends parallel to the row of the horizontally arranged MIM capacitors 5a to 5e, and extends to a position facing the MIM capacitors 5a to 5e. Therefore, the pad 6e has a length equivalent to the length of the five MIM capacitors 5a to 5e.

[0035] 9, one MIM capacitor is added to the right side of the row of MIM capacitors in the first embodiment, and in FIG. 10, one MIM capacitor is added to each side of the row. Therefore, the bias substrate 4 becomes longer in the horizontal direction. However, the pads 6d, 6e connected to the added MIM capacitor also extend parallel to the row of the horizontally arranged MIM capacitors 5a to 5c. Therefore, even if four or five DC pads of the MMIC 2 are arranged closely to each other, the wires can be shortened as in the first embodiment.

[0036] In addition, the wires connected to pad 6b closest to MIM capacitors 5a to 5c are long. If the inductance value of the wires is not acceptable, the size of the DC pads connected to pad 6b can be increased to increase the number of wires, as in the case of FIG.

[0037] Embodiment 3 11 is a plan view showing a bias substrate according to the third embodiment. Six MIM capacitors 5a to 5f are mounted on a bias substrate 4 in two rows. The MIM capacitors 5d to 5f are disposed farther from the MMIC 2 than the MIM capacitors 5a to 5c, and are disposed parallel to the row of the MIM capacitors 5a to 5c. The pads 6d to 6f are connected to the upper electrodes of the MIM capacitors 5d to 5f, respectively, and extend from both sides toward the MMIC 2 in a plan view before wrapping around between the DC pads 3a to 3c and the pads 6a to 6c. Each of the pads 6d to 6f extends parallel to the row of the horizontally arranged MIM capacitors 5a to 5c, and extends to a position facing the MIM capacitors 5a to 5c.

[0038] The structure of this embodiment is effective when the longitudinal dimension of the MMIC 2 is short and there are many pads arranged closely together. Depending on the size of the MMIC 2 and the positional relationship of the pads, it may be possible to use two bias substrates 4 of the first embodiment arranged side by side.

[0039] Embodiment 4 FIG. 12 is a plan view showing a semiconductor device according to a fourth embodiment. FIG. 13 is a plan view showing a bias substrate according to the fourth embodiment. The pads 6a to 6d have an uneven planar shape. The pads 6b and 6c adjacent to each other are arranged so that the convex portion of one of the pads fits into the concave portion of the other pad. The pads 6a and 6d adjacent to each other are arranged so that the convex portion of one of the pads fits into the concave portion of the other pad. This makes it possible to shorten the distance between the end of the bias substrate 4 on the MMIC 2 side and the MIM capacitors 5a to 5d. This makes it possible to shorten the wire length and effectively short out low-frequency signals.

[0040] FIG. 14 is a plan view showing the dimensions of the bias substrate according to the fourth embodiment. The length of the wire connected to the left pad 6a is 195 um. The length of the wire connected to the center pad 6b is 215 um. The length of the wire connected to the right pad 6c is 275 um, which is 40 um shorter than the length of 315 um in the case of FIG. 7. According to Table 1, when the wire length is 315 um, the inductance value L is 0.315 nH and the cutoff frequency fc is 50.6 MHz. On the other hand, when the wire length is 275 um, the inductance value L is 0.275 nH and the cutoff frequency fc is 57.9 MHz. Therefore, it can be seen that this embodiment allows short-circuiting up to a higher frequency, and the risk of oscillation is further reduced.

[0041] Embodiment 5. 15 is a plan view showing a semiconductor device according to a fifth embodiment. In this embodiment, MIM capacitors 5a to 5c have different capacitances. If the capacitance values ​​of MIM capacitors 5a to 5c are C1, C2, and C3, respectively, then by selecting a wire connection method, the capacitance can be digitally selected between the maximum capacitance C1+C2+C3 and the minimum capacitance C1×C2×C3 / (C1×C2+C2×C3+C1×C3). Since the capacitance value can be selectively determined using the same component, the number and types of components can be reduced.

[0042] 15, DC pad 3 is wire-connected to pads 6a and 6c. The top electrode of MIM capacitor 5b is wire-connected to ground pad 12 of MIM capacitor 5c. Ground pads 12 of MIM capacitors 5a and 5b are wire-connected to GND. The top electrode of MIM capacitor 5a and pad 6c are wire-connected to lead connection portion 8.

[0043] 16 is a diagram showing an equivalent circuit of a semiconductor device according to a fifth embodiment. Capacitors C2 and C3 connected in series are connected to GND in parallel with capacitance C1. This is the case where the capacitance value is set to C1+C2×C3 / (C2+C3). Note that in this embodiment, it is assumed that MIM capacitors are connected in series for use, and the via hole 13 connecting the base electrode 9 and GND mentioned in the first embodiment is not provided.

[0044] Also, it is desirable to set C1:C2:C3=4:2:1. For example, C1, C2, and C3 are 200pF, 100pF, and 50pF, respectively. FIG. 17 is a diagram showing capacitance values ​​that can be realized by combinations of wire connection methods. By selecting the wire connection method, the capacitance can be digitally selected between the maximum capacitance C1+C2+C3 and the minimum capacitance C1×C2×C3 / (C1×C2+C2×C3+C1×C3). The capacitance value in the wire connection method of FIGS. 15 and 16 is calculated to be about 233.33pF from C1+C2×C3 / (C2+C3). The order of C1, C2, and C3 may be reversed.

[0045] If fine adjustment of the capacitance values ​​is required, for example, the capacitance values ​​are set to C1:C2:C3 = 3:1.5:1. If a large dynamic range is desired even if the capacitance value interval becomes coarse, the capacitance values ​​are set to C1:C2:C3 = 6:3:1, for example.

[0046] In addition, when using MMICs with different performance or when changing bias conditions, it may be necessary to change the capacitance value. In the conventional technology, different parts had to be used, but in this embodiment, which allows the selection of the capacitance value, the same parts can be used, thereby reducing costs.

[0047] Although the preferred embodiments have been described above in detail, the present disclosure is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the claims. Various aspects of the present disclosure are described below as appendices. (Appendix 1) an MMIC having a DC pad; A bias substrate; A plurality of MIM capacitors mounted on the bias substrate; a plurality of pads provided on the bias substrate and connected to upper electrodes of the plurality of MIM capacitors, respectively; a wire connecting the DC pad to any one of the plurality of pads; The semiconductor device is characterized in that the multiple pads are arranged between the DC pad and the multiple MIM capacitors in a planar view and extend parallel to the row of the multiple MIM capacitors arranged side by side. (Appendix 2) the plurality of MIM capacitors include first to third MIM capacitors arranged in a row; the plurality of pads include first to third pads respectively connected to upper electrodes of the first to third MIM capacitors; 2. The semiconductor device according to claim 1, wherein the first to third pads extend to positions facing the first to third MIM capacitors, respectively. (Appendix 3) the first pad extends from a position facing the first MIM capacitor to a position facing a third MIM capacitor; the third pad extends from a position facing the third MIM capacitor to a position facing the first MIM capacitor; The semiconductor device described in Appendix 2, characterized in that the second pad branches off from a position opposite the second MIM capacitor and extends to a position opposite the first MIM capacitor and a position opposite a third MIM capacitor. (Appendix 4) the plurality of MIM capacitors further includes a fourth MIM capacitor arranged in a row with the first to third MIM capacitors; the plurality of pads further includes a fourth pad connected to a top electrode of the fourth MIM capacitor; 4. The semiconductor device according to claim 2, wherein the fourth pad extends to a position facing the first to fourth MIM capacitors. (Appendix 5) the plurality of MIM capacitors include fourth to sixth MIM capacitors arranged in parallel with the rows of the first to third MIM capacitors; the plurality of pads include fourth to sixth pads that are connected to upper electrodes of the fourth to sixth MIM capacitors, respectively, and are disposed between the DC pad and the first to third pads in a plan view; 4. The semiconductor device according to claim 2, wherein the fourth to sixth pads extend to positions facing the first to third MIM capacitors, respectively. (Appendix 6) The semiconductor device described in any one of appendix 1 to 5, characterized in that the multiple pads have two adjacent pads with uneven shapes, and are arranged so that the convex portion of one pad fits into the concave portion of the other pad. (Appendix 7) 7. The semiconductor device according to claim 1, wherein the MIM capacitors have different capacitances from one another. (Appendix 8) 4. The semiconductor device according to claim 2, wherein the capacitances of the first to third MIM capacitors are C1, C2, and C3, respectively, and C1:C2:C3=4:2:1. (Appendix 9) 9. The semiconductor device according to any one of claims 1 to 8, further comprising a plurality of ground pads provided on the bias substrate and connected to the base electrodes of the plurality of MIM capacitors, respectively. (Appendix 10) 9. The semiconductor device according to any one of claims 1 to 8, further comprising a plurality of via holes penetrating the bias substrate and connected to the base electrodes of the plurality of MIM capacitors, respectively. [Explanation of symbols]

[0048] 2 MMIC, 3, 3a to 3c DC pads, 4 bias substrate, 5a to 5f MIM capacitors, 6a to 6f pads, 7a to 7c wires, 9 base electrode, 11 top electrode, 12 ground pad, 13 via hole

Claims

1. an MMIC having a DC pad; A bias substrate; a plurality of MIM capacitors mounted on the bias substrate; a plurality of pads provided on the bias substrate and connected to upper electrodes of the plurality of MIM capacitors, respectively; a wire connecting the DC pad to any one of the plurality of pads; The semiconductor device according to the present invention is characterized in that the pads are arranged between the DC pad and the MIM capacitors in a plan view, and extend parallel to a row of the MIM capacitors arranged side by side.

2. The plurality of MIM capacitors include first to third MIM capacitors arranged in a row, the plurality of pads include first to third pads respectively connected to upper electrodes of the first to third MIM capacitors; 2. The semiconductor device according to claim 1, wherein the first to third pads extend to positions facing the first to third MIM capacitors, respectively.

3. the first pad extends from a position facing the first MIM capacitor to a position facing a third MIM capacitor; the third pad extends from a position facing the third MIM capacitor to a position facing the first MIM capacitor; 3. The semiconductor device according to claim 2, wherein the second pad branches from a position facing the second MIM capacitor and extends to a position facing the first MIM capacitor and a position facing a third MIM capacitor.

4. the plurality of MIM capacitors further includes a fourth MIM capacitor arranged in a row with the first to third MIM capacitors; the plurality of pads further includes a fourth pad connected to a top electrode of the fourth MIM capacitor; 4. The semiconductor device according to claim 2, wherein the fourth pad extends to a position facing the first to fourth MIM capacitors.

5. the plurality of MIM capacitors include fourth to sixth MIM capacitors arranged in parallel with the rows of the first to third MIM capacitors; the plurality of pads include fourth to sixth pads that are connected to upper electrodes of the fourth to sixth MIM capacitors, respectively, and are disposed between the DC pad and the first to third pads in a plan view; 4. The semiconductor device according to claim 2, wherein the fourth to sixth pads extend to positions facing the first to third MIM capacitors, respectively.

6. The semiconductor device according to any one of claims 1 to 3, characterized in that the plurality of pads include two adjacent pads having a concave-convex shape, and are arranged so that the convex portion of one pad is fitted into the concave portion of the other pad.

7. 4. The semiconductor device according to claim 1, wherein the plurality of MIM capacitors have different capacitances.

8. 4. The semiconductor device according to claim 2, wherein the capacitances of the first to third MIM capacitors are C1, C2, and C3, respectively, and C1:C2:C3=4:2:

1.

9. 4. The semiconductor device according to claim 1, further comprising a plurality of ground pads provided on the bias substrate and connected to the base electrodes of the plurality of MIM capacitors, respectively.

10. 4. The semiconductor device according to claim 1, further comprising a plurality of via holes which penetrate the bias substrate and are connected to the base electrodes of the plurality of MIM capacitors, respectively.

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