Method for using a sacrificial conductive stack to prevent corrosion - Patents.com

Abstract

To provide a method of manufacturing an integrated circuit (IC) chip in which a copper metallization layer is protected by a conductive stack in order to prevent corrosion.SOLUTION: A method of manufacturing a wafer 100 containing an IC chip, includes opening a windows 108 on a first front surface of an IC chip via a passivation overcoat 106 in order to expose a copper metallization layer 102. The window includes: a side wall; and a bottom part adjacent to the copper metallization layer. The method also includes steps of: depositing a barrier conductive stack 112 on the passivation overcoat and the exposed portions of the copper metallization layer; and depositing a sacrificial conductive stack 118 on the barrier conductive stack. The sacrificial conductive stack has a thickness of 50Å to 500Å. In addition, the method includes steps of polishing the first front surface of a semiconductor chip in order to remove the sacrificial conductive stack and the barrier conductive stack from the front surface of the passivation overcoat.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] This application relates generally to preventing corrosion of copper interconnects, and more particularly to a method of using a sacrificial conductive stack to prevent corrosion. [Background technology]

[0002] Currently, even when semiconductor wafer fabrication is complete, the formation of a packaged integrated circuit (IC) chip may require multiple steps and may be performed in multiple locations. Due to the potential steps involved and potential delays that may be experienced, any copper connections that may be exposed to the atmosphere must be protected to prevent corrosion. For at least some IC chips that remain part of the wafer, probing of the wafer with copper connections must be performed while corrosion prevention methods are performed. Currently used processes for corrosion prevention and / or probing are costly for interconnect methods that use under-bump metallurgy or plated copper interconnects. Improvements are needed. Summary of the Invention

[0003] The described embodiment provides a method of using a sacrificial conductive stack to prevent corrosion of copper connections on an IC chip. This method can also be used to enable probing of the chip, including thermal stress of data written to memory, while protecting the integrity of the copper connections. After a window is opened in the copper connections, a barrier conductive stack is formed on the surface of the chip that overlaps the window. A sacrificial conductive stack is formed on top of the barrier conductive stack and kept as thin as possible. These portions of the barrier conductive stack, as well as the sacrificial conductive stack on top of the protective overcoat, are removed by chemical mechanical polishing. In this state, the wafer containing the IC chip with the copper connections can be shipped, probed, or thermally stressed without damaging the copper connections. Before forming the interconnect or under bump metal, the sacrificial conductive stack is substantially removed from the window to expose the barrier conductive stack.

[0004] In one aspect, an embodiment of a method utilizing a sacrificial conductive layer to prevent corrosion of copper metallization in an integrated circuit chip is described, the method including opening a window on a first surface of the IC chip through a passivation overcoat to expose a copper metallization layer, the window having sidewalls and a bottom adjacent to the copper metallization layer, depositing a barrier conductive stack on the passivation overcoat and the exposed portion of the copper metallization layer, depositing a sacrificial conductive stack having a thickness of 50 Å to 500 Å on the barrier conductive stack, and polishing the first surface of the semiconductor chip to remove the sacrificial conductive stack and the barrier conductive stack from the surface of the passivation overcoat.

[0005] In another aspect, one embodiment of a method for forming an interconnect over a copper metallization layer is described, the method including receiving a semiconductor chip including a window through a protective overcoat to a copper metallization layer, the window having a barrier conductive stack adjacent to the copper metallization layer and the protective overcoat and a sacrificial conductive stack adjacent to the barrier conductive stack, and performing an etching process to remove the sacrificial conductive stack.

[0006] In yet another aspect, an embodiment of an integrated circuit (IC) chip is described that includes a copper metallization layer, a passivation overcoat overlying the copper metallization layer, a window through the passivation overcoat exposing the copper metallization layer, the window having sidewalls and a bottom adjacent the copper metallization layer, a barrier conductive stack lining the sidewalls and bottom of the window and in contact with the copper metallization layer, and a further metallization layer coupled to the copper metallization layer through the barrier conductive layer. [Brief description of the drawings]

[0007] [Figure 1]1 illustrates an example of a wafer in which a copper metallization layer is protected by a sacrificial conductive stack to prevent corrosion, according to one embodiment.

[0008] [Figure 2A] 1 illustrates a portion of an IC chip having some type of interconnect or under-bump metallization formed in accordance with one embodiment. [Figure 2B] 1 illustrates a portion of an IC chip having some type of interconnect or under-bump metallization formed in accordance with one embodiment. [Figure 2C] 1 illustrates a portion of an IC chip having some type of interconnect or under-bump metallization formed in accordance with one embodiment. [Figure 2D] 1 illustrates a portion of an IC chip having some type of interconnect or under-bump metallization formed in accordance with one embodiment. [Figure 2E] 1 illustrates a portion of an IC chip having some type of interconnect or under-bump metallization formed in accordance with one embodiment. [Figure 2F] 1 illustrates a portion of an IC chip having some type of interconnect or under-bump metallization formed in accordance with one embodiment. [Figure 2G] 1 illustrates a portion of an IC chip having some type of interconnect or under-bump metallization formed in accordance with one embodiment.

[0009] [Diagram 3] 1 illustrates a method for forming a sacrificial conductive stack to prevent corrosion, according to one embodiment.

[0010] [Figure 4] 1 illustrates a method of forming an interconnect on a copper metallization layer according to one embodiment.

[0011] [Diagram 5]1 shows a wafer in which a copper metallization layer for receiving wire bonds is protected from corrosion according to the prior art.

[0012] [Figure 6] 1 shows a wafer in which a copper metallization layer has been protected from corrosion in accordance with the prior art, the wafer being sent to a bump shop for the formation of a bump array. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] In the drawings, like reference numbers refer to like elements. In this description, the term "couple" means either an indirect or direct electrical connection, unless limited to "communicatively coupled," which may include a wireless connection. Thus, when a first device couples to a second device, the connection may be through a direct electrical connection or through an indirect electrical connection via other devices and connections.

[0014] As semiconductor chips and their packaging continue to evolve, numerous methods of interconnecting multiple chips to shorten the interconnects have evolved. It is not uncommon for the formation of packaged chips to occur at multiple locations. For example, a wafer containing several to thousands of chips may be manufactured at a first location. In some cases, the manufacturing may include writing unique information to non-volatile memory on the chips, which requires probing each chip to determine if the information was stored correctly, thermal stressing the wafer, and a second probing of the chips to determine which chips have failed under the stress. The wafer may then be shipped to a second location where the chips may be separated and bonded to lead frames or bump arrays or other forms of connectors may be formed.

[0015] Metallization layers in a manufacturing facility (fab) can be either copper or aluminum. Copper metallization layers in a manufacturing facility are generally formed using a damascene process that etches trenches in a dielectric layer and fills the trenches with copper. In contrast, metallization layers formed after a protective overcoat is provided on the chip, such as under-bump metallization or interconnect layers, are generally formed by depositing a layer of aluminum and then patterning and etching the aluminum, or by patterning a photoresist layer on the top layer of the chip and plating copper on the surfaces exposed by the photoresist. Deposition of bump metal generally consists of depositing a barrier layer followed by copper plating. This application refers to fab metallization as opposed to bump shop metallization to distinguish between these two different metallization processes and the time at which they occur. This reference to bump shop metallization is not intended to be limiting to under-bump metallization, but serves merely as an example.

[0016] If the final fab metallization layer is copper, it may be subject to corrosive effects such as heat and humidity in the time before the bump shop metallization is formed. Currently, chips may spend several weeks between completion of the chip itself and any further packaging required, and may be shipped to other facilities, often overseas, so the copper must be protected from possible corrosion. FIG. 5 shows a prior art wafer 500 in which the final fab metallization layer is copper. The wafer 500 includes a substrate 502 on which various devices (not specifically shown), such as transistors, resistors, capacitors, etc., are formed. An interlevel dielectric (ILD) 504 is formed over the substrate, and metallization layers are formed to connect the devices on the chip to each other. The metallization layers shown include metal N-1 506A, metal N 506B, and copper metallization layer 508. Although three metallization layers are shown in this figure, the number of metallization layers may be less than three or more, depending on the design of the chip. Although the described approach specifies copper in the final metallization layer 508, the other metallization layers can be either aluminum or copper. Vias 505 provide connections between the different interconnect layers.

[0017] A moisture impermeable protective overcoat 510 is formed over the copper metallization layer 508 and the ILD 504 for protection. In the illustrated embodiment, the protective overcoat 510 has two layers: an oxide layer 510A, which may be silicon oxide, forms a layer directly over the copper metallization layer 508, and a layer 510B, which may be either a nitride or oxynitride, is formed over the oxide layer 510A. A window 512 is opened in the protective overcoat 510 to contact the copper metallization layer 508. A tri-layer liner is formed within the window 512 to protect the copper metallization layer 508 from oxidation and to allow any necessary probing to be performed on the wafer 500. A layer of tantalum nitride (TaN) 514 is provided as a barrier layer, followed by a layer of nickel (Ni) 516. These two layers provide the necessary barrier, but there is no surface that is corrosion resistant and can be probed. The final layer provided is palladium (Pd) 518, which may be used for probing and will not corrode at the temperatures to which the chip will be exposed. The palladium layer 518 is typically about 1500 Å thick. While the embodiment shown in FIG. 5 works well for chips that receive wire bonding, this configuration will not work with other types of interconnects, such as bump arrays or other interconnect techniques. A problem with using this embodiment with additional metallization is that the additional metallization will not adhere to the palladium and will peel off.

[0018] FIG. 6 shows a schematic diagram of a wafer 600 with copper connections protected against corrosion and that can be used to form a bump array. In this figure, all elements below the copper metallization layer 508 are the same as in FIG. 5, but the solutions used for corrosion resistance and the capabilities probed are different. Again, a protective overcoat, a first protective overcoat 602 in this example, is formed on top of the copper metallization layer 508 and ILD 504, and a window (not specifically shown) is formed through the protective overcoat 602 to expose the copper metallization layer 508. A thin layer of tantalum nitride 604 is deposited over the protective overcoat 602 and the exposed surface of the copper metallization layer 508. The tantalum nitride 604 is followed by a layer of aluminum 606 that forms a cap over the copper metallization layer 508. The aluminum 606 is covered with photoresist that is patterned and the unnecessary portions of the aluminum 606 and TaN 604 are removed to form an aluminum cap 607. Because the aluminum cap 607 is soft and deformed, the aluminum cap 607 is covered by a second protective overcoat 608, again including an oxide layer 608A and an oxynitride 608B. The second protective overcoat 608 is then patterned and etched to open a second window 610 to expose the aluminum cap 607.

[0019] The aluminum cap 607 works well to protect the copper metallization layer 508 from corrosion and to allow probing if necessary. When the wafer containing the aluminum cap 607 is received at the bump shop, the wafer may be cleaned, typically with a short sputter etch process, and the bump array may be formed according to known techniques. The entire process is known and understood. However, the need for two masks to implement the aluminum cap makes this process expensive to utilize.

[0020] Applicant has determined that the protective process used for wire bonding applications is not applicable to such applications forming bump arrays, but can be adapted for use with bump arrays and other connectors by thinning the final corrosion resistant layer to a point where the wafer cleaning process utilized in the bump shop can completely or substantially remove this layer, i.e., the outer layer of the protective metal layer becomes a sacrificial layer, rather than becoming a permanent part of the circuit being fabricated.

[0021] For clarity, applicants note that for purposes of this application, reference to a sacrificial layer or sacrificial conductive stack is intended to cover both one or more conductive layers that are fully sacrificial, i.e., completely removed during processing, and one or more conductive layers that are substantially removed but may leave residues or tags of material in locations that are difficult to remove. This latter situation may arise, for example, when a sputter etch process is utilized to remove the conductive stack from a recess, such as an opening in a metallization layer. Because of the directionality of the etch process, the etch may successfully remove a portion of the sacrificial conductive stack at the bottom of the opening, but leave a portion of the conductive stack proximate the sidewalls and / or corners of the opening. These residues, if present, do not interfere with the creation of bumps or other connectors. In contrast, when a wet etch process is utilized to remove the sacrificial conductive stack, the etch process may generally completely remove the sacrificial conductive stack.

[0022] FIG. 1 illustrates an example of a wafer 100 including an IC chip in which a copper metallization layer is protected by a conductive stack to prevent corrosion, the conductive stack being partially sacrificial. In this figure, only a small portion of the IC chip is shown, including the final copper metallization layer 102, although any number of other metallization layers may be below the copper metallization layer 102. The copper metallization layer 102 is surrounded by an interlevel dielectric 104 and is covered with a protective overcoat 106. In one embodiment, the protective overcoat 106 includes an oxide layer 106A, which may be silicon oxide, and an oxynitride layer 106B. A nitride layer (not specifically shown) may be utilized in conjunction with or in place of the oxynitride 106B.

[0023] After a window 108 is opened through the protective overcoat 106 to the contact copper metallization layer 102, two conductive stacks are deposited on the surface of the wafer 100 to provide the necessary corrosion protection. The stacks serve two somewhat different purposes, and each includes one or more layers of conductive material.

[0024] The first stack is a barrier conductive stack 112, which acts to provide a barrier between the copper metallization layer 102 and further layers. In one embodiment, the barrier conductive stack 112 includes a layer 114 of Ta or TaN deposited to a thickness in the range of 100 Å to 800 Å, and Ni 116 deposited to a thickness in the range of 2000 Å to 30,000 Å. Another embodiment of the barrier conductive stack 112 may include a layer of TaN, followed by a layer of Ni, and a further layer of TaN. In another embodiment, the layer of TaN may be followed by a layer of tungsten (W) with or without a further layer of tantalum nitride.

[0025] The second stack is a sacrificial conductive stack 118 that prevents oxidation of the barrier conductive stack and may be utilized for wafer probing, if desired. The sacrificial conductive stack 118 may be a single layer, as shown in FIG. 1. Suitable materials for the sacrificial conductive stack 118 include precious metals, such as, for example, gold, platinum, palladium, and ruthenium, as well as any combination of these metals. Other suitable conductive materials for the sacrificial conductive stack 118 include metals that do not significantly oxidize at or below 260° C., such as, for example, chromium. In one embodiment, the sacrificial conductive stack 118 has a thickness in the range of 50-500 Å. In one embodiment, the sacrificial conductive stack 118 has a thickness in the range of 50-400 Å. In another embodiment, the sacrificial conductive stack 118 has a thickness in the range of 50-250 Å. In yet another embodiment, the sacrificial conductive stack 118 has a thickness in the range of 50-100 Å. Although shown as a single layer, the sacrificial conductive stack 118 may include multiple sacrificial layers, such as, for example, platinum overlying gold. It is desirable to keep the sacrificial conductive stack 118 as thin as possible so that the cleaning processes typically used in bump shops can remove the sacrificial conductive stack 118 with little or no additional time required when compared to the normal cleaning processes for wafers.

[0026] Although the described process is designed for use with bump arrays on a wafer or chip, the process is not limited to bump arrays formed using any particular method, nor is it limited to bump arrays. Figures 2A-2G each show an IC chip 200 having a connection method that may use the described sacrificial conductive stack to provide these connectors in a cost-effective manner. Each of these examples uses the same base wafer shown in Figures 1, 5, and 6, but in each example a slightly different connector is utilized or bonded to the copper metallization layer 202 in a different manner.

[0027] 2A-2D each show an IC chip 200A-200D having an under-bump metallization configuration formed in accordance with an embodiment. In FIG. 2A, a copper metallization layer 202 is bonded to a re-distribution layer RDL 204 via a barrier conductive stack 203. A first polyimide layer 206A is deposited on top of a protective overcoat 205 prior to formation of the re-distribution layer RDL 204, and a second polyimide layer 206B is deposited on top of the re-distribution layer 204. An under-bump metal 208 is formed on the re-distribution layer 204 to provide a landing area for a solder bump 210.

[0028] In Figure 2B, a copper interconnect layer 212 is formed on top of the protective overcoat 205 and contacts the copper metallization layer 202 through the barrier conductive stack 203, while a polyimide 214 is deposited on top of the copper interconnect layer 212. An underbump metallization 208 is formed on top of the polyimide 214 and contacts the copper interconnect layer 212, and a solder bump 210 is formed on the underbump metallization 208. Figure 2C shows an embodiment where the underbump metallization 208 is separated from the protective overcoat 205 only by the polyimide 216 and directly contacts the barrier conductive stack 203 to bond to the copper metallization layer 202. Figure 2D shows a further embodiment where the underbump metallization 208 is formed on top of the protective overcoat 205 and directly contacts the barrier conductive stack 203 to bond to the copper metallization 202. Other variations on these embodiments are possible.

[0029] 2E-2G show other IC chips 200E-200G with means for providing bonding to further chips. In FIG. 2E, copper pillars 218 are bonded to copper metallization layer 202 via barrier conductive stack 203 and are also separated from protective overcoat 205 by polyimide 220. In FIG. 2F, the polyimide layer is omitted and a metal bonding layer METTOP 222 is deposited directly over protective overcoat 205 and barrier conductive stack 203 to provide bonding to copper metallization layer 202. FIG. 2G shows an embodiment in which a metal bonding layer METTOP 224 is deposited over protective overcoat 205 and barrier conductive stack 203 and then etched, followed by deposition of polyimide 228. Copper posts 226 provide contact to metal bonding layer METTOP 203. These methods of bonding a chip to a printed circuit board or another chip are provided as examples of how the described methods of using a sacrificial conductive stack to prevent corrosion can be incorporated. Other approaches may also use the described process to provide corrosion protection with fewer process steps and less expense. It should be noted that although each of these examples shows only the barrier conductive stack 203 lining the pre-drilled window, in embodiments using a sputter etch process, there may be residue of the sacrificial conductive stack (not specifically shown) on the sidewalls of the pre-drilled window.

[0030] FIG. 3 shows a flow chart for a method 300 of using a sacrificial conductive stack to prevent corrosion of a copper metallization layer, according to one embodiment. When method 300 begins, active devices have already been formed on an IC chip, as well as metallization layers that bond together devices on the IC chip. The top metallization layer, which is copper, is covered with a passivation overcoat. Typical passivations may consist of oxynitride, silicon nitride, a combination of silicon dioxide and oxynitride, or a combination of silicon dioxide and silicon nitride. Method 300 begins with opening a window (305) through the passivation overcoat on a first surface of the IC chip to expose the copper metallization layer. The window is defined as having a sidewall adjacent to the passivation overcoat and a bottom adjacent to the copper metallization layer.

[0031] The method 300 continues with depositing (310) a barrier conductive stack over the passivation overcoat and the exposed portions of the copper metallization layer. In one embodiment, the barrier conductive stack includes a layer of TaN and a layer of Ni on top of the TaN. A sacrificial conductive stack is then deposited (315) over the barrier conductive stack. The sacrificial conductive stack has a thickness between 50 Å and 500 Å. In one embodiment, the sacrificial conductive stack is formed of palladium. Finally, the first surface of the semiconductor chip is polished (320) to remove the sacrificial conductive stack and the barrier conductive stack from the surface of the passivation overcoat. In one embodiment, the copper metallization layer is the last metallization layer formed at the fabrication facility, with other metallization processes, such as preparing the chip for bonding to a printed circuit board or other chips, being performed at other facilities.

[0032] In one embodiment, data is written (325) to the memory formed on the chip. This may be done using probes and access to the copper metallization layers provided by the sacrificial conductive stack and the barrier conductive stack. After the data is written, a thermal stress may be applied to the chip via a firing cycle (330). Following this, the data from the memory is read (335) and tested for retention. Memory that does not retain data may be marked and not shipped to the customer. Each of elements 325, 330, 335 are shown within dotted lines to indicate that they are optional.

[0033] Preparing the chip for bonding to a printed circuit board or other chips is generally performed at a different facility, although some manufacturing facilities may perform these tasks in-house. In one embodiment, following memory testing, the sacrificial conductive stack is removed from the pre-fabricated window. In this embodiment, the method 300 continues with performing an etching process 340 to remove the sacrificial conductive stack from at least the bottom of the window. If the etching process is a wet etch, the sacrificial conductive stack is also removed from the sides of the window, although this is not required for this process. In addition to removing the sacrificial conductive stack, the etching process also removes contaminants that may have been introduced during the reading of the memory. Finally, a further metallization layer 345 is formed that substantially fills the window. In at least one embodiment, the further metallization layer completely fills the window. In one embodiment, a dielectric layer, such as a polyimide layer, is first deposited on the protective overcoat, and a smaller window is opened through the dielectric layer to contact the copper metallization layer. In this latter embodiment, the further metallization layer fills this smaller window and then substantially fills the original window. The additional metallization layers may be any of the processes shown in Figures 2A-2G, or may be any other metallization process, whether currently known or unknown.

[0034] FIG. 4 shows a flow chart for a method 400 of forming interconnects on a copper metallization layer. The method may generally be performed at a bump facility or similar facility. The method 400 begins with receiving (405) a semiconductor chip including a window through a protective overcoat to the copper metallization layer. As received, the window has a barrier conductive stack adjacent to the copper metallization layer and the protective overcoat, and a sacrificial conductive stack adjacent to the barrier conductive stack. The facility performs (410) an etching process to remove the sacrificial conductive stack. Because the sacrificial conductive stack is formed as thin as possible, in one embodiment, the process does not require additional time to remove the sacrificial conductive stack beyond that normally allocated to removing contaminants. In one embodiment, the additional time for removal of the sacrificial conductive stack is minimal. As discussed above, the etching process may remove only the portion of the sacrificial conductive stack that is on the bottom of the window, or the etching process may remove all of the portion of the sacrificial conductive stack. In either case, the etching process is followed by the formation of a further metallization layer that couples to the copper metallization layer through the barrier conductive stack (415). This process of forming the additional metallization layers may use any method, whether currently known or unknown.

[0035] Modifications may be made to the exemplary embodiments described, and other embodiments are possible, within the scope of the invention.

Claims

1. 1. A method comprising: receiving a wafer including a semiconductor chip at a facility, the semiconductor chip including a window through a protective overcoat to a copper metallization layer, the window having a barrier conductive stack adjacent the copper metallization layer at a bottom of the window and the protective overcoat at a sidewall of the window, and a sacrificial conductive stack on the barrier conductive stack, the barrier conductive stack and the sacrificial conductive stack not on the protective overcoat; performing an etching process to remove the sacrificial conductive stack from at least a bottom of the window; A method comprising:

2. 2. The method of claim 1 , The method, wherein performing the etching process includes performing a wet etching process to remove the entirety of the sacrificial conductive stack.

3. 2. The method of claim 1 , The method, wherein performing the etching process includes performing a sputter etch process to remove the sacrificial conductive stack from a surface of the window adjacent the copper metallization layer.

4. 2. The method of claim 1 , The method further includes forming an additional metallization layer that couples to the copper metallization layer through the barrier conductive stack.

5. 5. The method of claim 4, The method, wherein forming the further metallization layer comprises plating a copper interconnect layer.

6. 5. The method of claim 4, The method, wherein forming the further metallization layer includes depositing an under-bump metal layer overlying the window.

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