Processing device and processing method

Abstract

To reduce the ratio of the size of a determination part for determining a cache hit of a cache including a plurality of banks to the size of the cache.SOLUTION: An arithmetic processing unit includes a data array including a plurality of banks for dividing and storing data read from a storage device, a second determination part, and a cache control part for accessing a cache or the storage device on the basis of a determination result of the second determination part. The second determination part has a second holding part for holding identification information for identifying a first tag address included in a tag address and a second tag address included in the tag address in each value of an index address, and determines a cache hit in the case that identification information corresponding to the first tag address included in an access address and the second tag address included in the access address coincide with the identification information and the second tag address held by the second holding part in correspondence with the index address.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a processor and a processing method. [Background technology]

[0002] A cache installed in a processor such as a CPU (Central Processing Unit) holds a portion of data stored in a main memory. When the cache holds target data for a memory access request issued from a processor (cache hit), the cache transfers the data held in the cache to the processor without issuing a memory access request to the main memory. This improves data access efficiency and CPU processing performance.

[0003] A cache includes a data array that holds data, and a tag array that determines whether the data to be accessed is held in the data array (see, for example, Patent Document 1). For example, a high-performance processor has a hierarchical cache, each of which includes multiple ways (see, for example, Patent Document 2). In addition, a processor may have multiple banks to improve cache throughput (see, for example, Patent Document 3). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Special Publication No. 2007-504552 [Patent Document 2] Special Publication No. 2020-536308 [Patent Document 3] Japanese Patent Application Publication No. 08-320829 Summary of the Invention [Problem to be solved by the invention]

[0005] For example, when one cache line of data, which is a unit of management in a cache, is divided into multiple parts and stored in multiple banks of the cache, the more the number of banks increases, the more the number of tag arrays increases, and the ratio of the number of bits of the tag array to the data of one cache line increases. Also, in a processor capable of executing Single Instruction Multiple Data (SIMD) arithmetic instructions, the number of cache banks tends to increase.

[0006] In one aspect, the present invention aims to reduce the ratio of the size of a determination unit that determines a cache hit in a cache including multiple banks to the size of the cache. [Means for solving the problem]

[0007] According to one aspect, a processing device has a plurality of request issuing units that issue memory access requests to a storage device, a data array including a plurality of banks each capable of holding sub-data obtained by dividing data read from the storage device based on the memory access request, a switch unit that transfers the memory access request to one of the plurality of banks, at least one first determination unit that has a first holding unit that holds a tag address included in the access address for each value of an index address in the access address and determines a cache hit when the tag address included in the access address matches a tag address held in the first holding unit corresponding to the index address included in the access address, at least one second determination unit that has a second holding unit that holds identification information for identifying a first tag address included in the tag address and a second tag address included in the tag address for each value of the index address and determines a cache hit when the identification information corresponding to the first tag address included in the access address and the second tag address included in the access address match the identification information and the second tag address held in the second holding unit corresponding to the index address included in the access address, and a cache control unit that accesses the cache or the storage device based on a determination result of the first determination unit or the second determination unit. Effect of the Invention

[0008] It is possible to reduce the ratio of the size of a determination unit that determines a cache hit in a cache including multiple banks to the size of the cache. [Brief description of the drawings]

[0009] [Figure 1] FIG. 2 is a block diagram illustrating an example of a processor according to an embodiment. [Diagram 2] 2 is an explanatory diagram showing an example of data held in the cache of FIG. 1; [Diagram 3]1. FIG. 4 is an explanatory diagram showing another example of data stored in the cache of FIG. [Figure 4] 2 is a flow chart showing an example of a memory access operation of the arithmetic processing device of FIG. 1; [Diagram 5] FIG. 13 is a block diagram showing an example of a processor according to another embodiment. [Figure 6] FIG. 6 is a block diagram showing an example of a subtag section in FIG. 5. [Figure 7] 6 is a flow chart showing an example of a memory access operation of the arithmetic processing device of FIG. 5. [Figure 8] FIG. 13 is a block diagram showing an example of a subtag unit in a processor according to another embodiment. [Figure 9] FIG. 13 is a block diagram showing an example of a processor according to another embodiment. [Figure 10] 10 is an explanatory diagram showing an example of address calculation in the load store unit of FIG. 9; [Figure 11] FIG. 13 is a block diagram showing an example of the configuration of a main tag section and a sub tag section in another embodiment. [Figure 12] FIG. 13 is a block diagram showing an example of the configuration of a main tag section and a sub tag section in another embodiment. [Figure 13] FIG. 13 is a block diagram showing an example of the configuration of a main tag section and a sub tag section in yet another embodiment. [Figure 14] FIG. 13 is a block diagram showing an example of a processor in the configuration example 4 of FIG. [Figure 15] FIG. 11 is a block diagram showing an example of a main tag section and a sub tag section in a processor according to another embodiment. [Figure 16] FIG. 11 is an explanatory diagram showing an example of a tag array / data array ratio for each cache structure. [Figure 17] FIG. 11 is an explanatory diagram showing an example of an improvement in the tag array / data array ratio when a tag array cache is provided. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, embodiments will be described with reference to the drawings.

[0011] Fig. 1 shows an example of a processing device according to an embodiment. The processing device 100 shown in Fig. 1 is a processor such as a CPU that executes operations using single instruction multiple data (SIMD) instructions. The processing device 100 can execute multiple multiply-add operations in parallel by using SIMD instructions.

[0012] The arithmetic processing device 100 has m+1 (m is an integer equal to or greater than 1) load store units LDST (LDST#0-LDST#m) and a cache 60 connected to a main memory 50. The load store units LDST are an example of a request issuing unit that issues a memory access request to the main memory 50. The main memory 50 is an example of a storage device. The cache 60 operates as an L1 (Level 1) data cache that holds a portion of data stored in the main memory 50 for the load store units LDST.

[0013] Cache 60 has an arbitration unit 10, a switch unit 20, one main tag unit MTAG, n (n is an integer equal to or greater than 1) subtag units STAG (STAG#0-STAG#n), a data array 30, and a cache control unit 40. Cache control unit 40 controls the overall operation of cache 60. Note that cache control unit 40 may be disposed outside cache 60. Main tag unit MTAG is an example of a first determination unit, and subtag unit STAG is an example of a second determination unit.

[0014] The data array 30 has n+1 banks BK (BK#0-BK#n) corresponding to the main tag portion MTAG and the subtag portion STAG, respectively. By dividing the data array 30 into a plurality of banks BK, it is possible to improve the so-called gather / scatter performance.

[0015] Cache 60 may also be connected to main memory 50 via a lower level cache such as an L2 (Level 2) cache. Cache 60 may have a minimum of two banks BK#0 and BK#1. In this case, cache 60 has one main tag section MTAG and one subtag section STAG.

[0016] The arithmetic processing device 100 has an instruction fetch unit, an instruction decode unit, a reservation station, an arithmetic unit including various arithmetic units, a register file, etc., which are not shown. In Fig. 1, blocks related to memory access are mainly shown. For example, the instruction fetch unit, the instruction decode unit, the reservation station, the arithmetic unit including various arithmetic units, the register file, and the load store unit LDST are included in a CPU core, which is not shown.

[0017] When the load store unit LDST executes a load instruction, it outputs a memory access request to a bank BK indicated by an address AD via the switch unit 20, and receives read data from the bank BK via the switch unit 20. The address AD includes a tag address TAG, an index address IDX, an offset address, and a bank address BA. The address AD is an example of an access address included in a memory access request. The memory access request issued in response to a load instruction includes the address AD to be accessed and read control information indicating a read request.

[0018] When the load store unit LDST executes a store instruction, it outputs a memory access request to the bank BK indicated by the address AD via the switch unit 20. The memory access request issued in response to the store instruction includes the address AD to be accessed, write data, and write control information indicating the write request.

[0019] The m+1 load store units LDST receive load or store instructions independently of each other, and output memory access requests independently of each other. For this reason, memory access requests to one bank BK may conflict. When memory access requests conflict, the arbitration unit 10 selects one of the memory access requests. In the following, in this embodiment and in the embodiment described later, an example will be described in which the load store unit LDST that executes a load instruction issues a memory access request (read request).

[0020] The switch unit 20 outputs a memory access request to a bank BK indicated by a bank address BA included in the memory access request. The switch unit 20 receives read data DT from the bank BK that has output a memory access request for a load instruction, and outputs the received read data DT to the load store unit LDST that has issued the memory access request.

[0021] The main tag unit MTAG has a tag array TGA and a comparator CMP1. The tag array TGA is an example of a first holding unit. The tag array TGA has a plurality of entries that hold a tag address TAG for each value of the index address IDX. For example, when the index address IDX is 10 bits, the tag array TGA has 1024 entries. The tag array TGA outputs the tag address TAG held in the entry corresponding to the index address IDX received from the switch unit 20 to the comparator CMP1.

[0022] The comparator CMP1 compares the tag address TAG output from the tag array TGA with the tag address TAG output from the switch unit 20. If the tag addresses TAG match each other, the comparator CMP1 outputs a hit signal HIT of an active level (cache hit). If the tag addresses TAG do not match each other, the comparator CMP1 outputs a hit signal HIT of an inactive level (cache miss).

[0023] A cache hit indicates that the data to be accessed in the memory access request is held in the bank BK to be accessed in the data array 30. A cache miss indicates that the data to be accessed in the memory access request is not held in the bank BK to be accessed in the data array 30. In this case, the cache 60 reads the data to be accessed from the main memory 50.

[0024] The subtag unit STAG has a tag conversion unit TCNV, a tag array cache TGAC, and a comparator CMP2. The tag conversion unit TCNV is an example of a third holding unit, and the tag array cache TGAC is an example of a second holding unit. The tag conversion unit TCNV has a plurality of entries identifiable by the identification information ID. For example, when the identification information ID is 2 bits, the tag conversion unit TCNV has four entries. The number of entries in the tag conversion unit TCNV is less than the number of entries in the tag array cache TGAC.

[0025] Each entry of the tag conversion unit TCNV stores a first tag address TAG1, which is a part of the bits of the tag address TAG. When the tag conversion unit TCNV holds the first tag address TAG1 included in the memory access request in any of the entries, the tag conversion unit TCNV outputs the identification information ID of the entry to the comparator CMP2. In this way, the tag conversion unit TCNV functions as a CAM (Content Addressable Memory) that outputs the identification information ID indicating the entry holding the received first tag address TAG1. Note that, as long as the first tag address TAG1 can be associated with the identification information ID that identifies the first tag address TAG1, elements other than the tag conversion unit TCNV may be provided in the subtag unit STAG.

[0026] The tag array cache TGAC has a plurality of entries that hold identification information ID and a second tag address TAG2 for each value of the index address IDX. The second tag address TAG2 is indicated by a bit in the tag address TAG that is different from the bit of the first tag address TAG1. For example, the tag address TAG is a combination of the bit of the first tag address TAG1 and the bit of the second tag address TAG2. The tag array cache TGAC outputs the identification information ID and the second tag address TAG2 held in the entry corresponding to the index address IDX output from the switch unit 20 to the comparator CMP2.

[0027] The comparator CMP2 compares the identification information ID output from the tag conversion unit TCNV with the identification information ID output from the tag array cache TGAC. The comparator CMP2 also compares the second tag address TAG2 output from the switch unit 20 with the second tag address TAG2 output from the tag array cache TGAC.

[0028] When the identification information IDs match and the second tag addresses TAG2 match, the comparator CMP2 outputs a hit signal HIT of an active level (cache hit).When at least one of the identification information IDs and the second tag addresses TAG2 do not match, the comparator CMP2 outputs a hit signal HIT of an inactive level (cache miss).

[0029] Like a cache hit in the main tag section MTAG, a cache hit in the subtag section STAG indicates that the data to be accessed in the memory access request is held in the bank BK to be accessed in the data array 30. Like a cache hit in the main tag section MTAG, a cache miss in the subtag section STAG indicates that the data to be accessed in the memory access request is not held in the bank BK to be accessed in the data array 30.

[0030] For example, assume that the tag address TAG is 36 bits, the first tag address TAG1 is 28 bits, the second tag address TAG2 is 8 bits, the identification information ID is 2 bits, and the index address IDX is 10 bits. In this case, the memory area of ​​the tag array cache TGAC can be reduced by about 26 kilobits compared to the memory area of ​​the tag array TGA ((28-2)*1024; the sign * indicates multiplication). The memory area of ​​the tag conversion unit TCNV is 120 bits ((28+2)*4).

[0031] Also, the comparator CMP1 compares the 36-bit tag address TAG, whereas the comparator CMP2 compares 10 bits (2-bit identification information ID and 8-bit second tag address TAG2). Therefore, the circuit scale of the subtag section STAG is smaller than the circuit scale of the main tag section MTAG. Therefore, the arithmetic processing device 100 can reduce the scale of the determination circuit that determines a cache hit, compared to a case in which a main tag section MTAG is provided for each bank BK. As a result, the manufacturing costs, etc. of the arithmetic processing device 100 can be reduced, compared to a arithmetic processing device in which a main tag section MTAG is provided for each bank BK.

[0032] Each bank BK has multiple entries that hold sub-data SDT for each value of the index address IDX. Here, the sub-data SDT has a size obtained by dividing the cache line size by the number of banks BK. The size of the sub-data SDT is described in FIG. 2 and FIG. 3.

[0033] Upon a cache hit, each bank BK outputs the sub-data SDT held in an entry corresponding to the index address IDX included in the memory access request to the switch unit 20 under the control of the cache control unit 40. Upon a cache miss, each bank BK holds the corresponding sub-data SDT of one cache line's worth of data DT read from the main memory 50 in the entry corresponding to the index address IDX under the control of the cache control unit 40.

[0034] The cache control unit 40 receives a hit signal HIT from the main tag unit MTAG and the subtag unit STAG, and controls the cache 60 as described above. The cache control unit 40 executes data transfer between the banks BK and the main memory 50. Furthermore, if the sub-data held in each bank BK has been updated, the cache control unit 40 writes the sub-data back to the main memory 50 in the event of a cache miss.

[0035] 1 shows a direct-mapped cache 60, but a set-associative cache having multiple ways may be used. In this case, the tag array TGA and the tag array cache TGAC are also partitioned into a number corresponding to the number of ways. In the following embodiments, a direct-mapped cache 60 is shown, but a set-associative cache may be used.

[0036] Figures 2 and 3 show an example of data held in the cache 60 of Figure 1. In Figures 2 and 3, the arithmetic processing device 100 has four banks BK#0-BK#3. Each of the banks BK#0-BK#3 holds 64-bit sub-data SDT for each entry identified by an index address IDX.

[0037] In FIG. 2, in the banks BK#0-BK#3, four sub-data SDTs included in one entry indicated by an index address IDX correspond to one cache line CL. In the example shown in FIG. 2, the data size of the cache line CL is 256 bits. In this case, the cache control unit 40 in FIG. 1 executes a cache fill to transfer data from the main memory 50 to the cache 60. In the cache fill, the sub-data SDTs included in the cache line CL are stored in the order of addresses AD in an entry with a common index address IDX in each of the banks BK#0-BK#3. In addition, the cache control unit 40 executes a write back to transfer data from the cache 60 to the main memory 50. In the write back, the four sub-data SDTs held in an entry with a common index address IDX in each of the banks BK#0-BK#3 are stored in the main memory 50 in the order of addresses.

[0038] In FIG. 3, eight sub-data SDTs included in two entries indicated by two consecutive index addresses IDX in four banks BK#0-BK#3 correspond to one cache line CL. In the example shown in FIG. 3, the data size of the cache line CL is 512 bits. In this case, the cache control unit 40 executes a cache fill. In the cache fill, the sub-data SDTs included in the two cache lines CL are stored in two entries indicated by two consecutive index addresses IDX in each bank BK#0-BK#3 in the order of addresses AD. In addition, in the write back, the cache control unit 40 stores the eight sub-data SDTs held in the two entries indicated by two consecutive index addresses IDX in each bank BK#0-BK#3 in the main memory 50 in the order of addresses.

[0039] For example, if the cache 60 has four 64-bit banks BK and the size of the cache line CL is 1024 bits, the cache control unit 40 executes cache fill and write back for four entries for each bank BK. If the cache 60 has eight 64-bit banks BK and the size of the cache line CL is 1024 bits, the cache control unit 40 executes cache fill and write back for two entries for each bank BK.

[0040] Fig. 4 shows an example of a memory access operation of the arithmetic processing device 100 of Fig. 1. That is, Fig. 4 shows an example of an arithmetic processing method of the arithmetic processing device 100. The operation shown in Fig. 4 is executed by the cache control unit 40 based on the issuance of a memory access request corresponding to a load instruction from at least one of the multiple load store units LDST.

[0041] When memory access requests from the multiple load store units LDST to different banks BK result in a cache hit, the operation shown in Fig. 4 is executed in each of the accessed banks BK. When a memory access request from the multiple load store units LDST to different banks BK results in a cache miss, the write back due to the cache miss and the cache fill after the write back are executed in common in all of the banks BK.

[0042] First, in step S10, cache control unit 40 determines whether the memory access request indicates bank BK (in this example, BK#0) corresponding to main tag part MTAG by using bank address BA. If the memory access request indicates bank BK corresponding to main tag part MTAG, cache control unit 40 shifts the operation to step S20. Then, cache control unit 40 executes access processing using main tag part MTAG by steps S22, S24, S26, and S28 included in step S20.

[0043] If the memory access request does not indicate the bank BK corresponding to the main tag portion MTAG, the cache control unit 40 shifts the operation to step S30. Then, the cache control unit 40 executes the access process using the subtag portion STAG by steps S32, S34, S36, and S38 included in step S30.

[0044] In step S22, the cache control unit 40 accesses the main tag part MTAG based on the index address IDX included in the memory access request, and reads out the tag address TAG. The cache control unit 40 also causes the comparator CMP1 to compare the tag address TAG included in the memory access request with the tag address TAG read out from the main tag part MTAG, and outputs a hit signal HIT.

[0045] Next, in step S24, the cache control unit 40 judges whether or not there is a hit in the main tag part MTAG based on the hit signal HIT output from the comparator CMP1. If there is a hit in the main tag part MTAG, the cache control unit 40 shifts the operation to step S26, and if there is a miss in the main tag part MTAG, the cache control unit 40 shifts the operation to step S28.

[0046] In step S26, the cache control unit 40 executes normal cache hit processing, and outputs the data read from the bank BK where the cache hit occurred to the load store unit LDST that issued the memory access request via the switch unit 20. Then, the cache control unit 40 ends the operation shown in FIG.

[0047] In step S28, the cache control unit 40 executes normal cache miss processing. That is, the cache control unit 40 executes, for example, the cache fill operation shown in FIG. 2 or FIG. 3, and updates the data held in each bank BK. The cache control unit 40 also updates the main tag unit MTAG, the tag conversion unit TCNV, and the tag array cache TGAC in response to the update of the data in each bank BK. Note that, if the data in the bank BK has been updated, the cache control unit 40 executes a write-back operation. Then, the cache control unit 40 ends the operation shown in FIG. 4.

[0048] On the other hand, in step S32, the cache control unit 40 accesses the subtag unit STAG corresponding to the bank BK indicated by the bank address BA included in the memory access request. The cache control unit 40 accesses the tag conversion unit TCNV based on the tag address TAG1 included in the memory access request and reads out the identification information ID. The cache control unit 40 also accesses the tag array cache TGAC based on the index address IDX included in the memory access request and reads out the identification information ID and the tag address TAG2.

[0049] The cache control unit 40 then causes the comparator CMP2 to compare the tag address TAG2 included in the memory access request with the tag address TAG2 read from the tag array cache TGAC. The cache control unit 40 also causes the comparator CMP2 to compare the identification information ID read from the tag conversion unit TCNV with the identification information ID read from the tag array cache TGAC. The cache control unit 40 then causes the comparator CMP2 to output a hit signal HIT based on the comparison result.

[0050] Next, in step S34, the cache control unit 40 judges whether or not there is a hit in the subtag unit STAG based on the hit signal HIT output from the comparator CMP2. If there is a hit in the subtag unit STAG, the cache control unit 40 shifts the operation to step S36, and if there is a miss in the subtag unit STAG, the cache control unit 40 shifts the operation to step S38.

[0051] In step S36, cache control unit 40 executes normal cache hit processing similar to step S26, and ends the operation shown in Fig. 4. In step S38, cache control unit 40 executes normal cache miss processing similar to step S28, and ends the operation shown in Fig. 4.

[0052] As described above, in this embodiment, the arithmetic processing device 100 can determine a cache hit in the bank BK by the tag array cache TGAC that holds the identification information ID for identifying the first tag address TAG1 and the second tag address TAG2. The bit width of an entry in the tag array cache TGAC is smaller than the bit width of an entry in the tag array TGA. As described above, the circuit scale of the subtag unit STAG having the tag conversion unit TCNV and the tag array cache TGAC is smaller than the circuit scale of the main tag unit MTAG having the tag array TGA.

[0053] Therefore, the arithmetic processing device 100 can determine cache hits in the banks BK#1-BK#n by using the subtag section STAG, which has a smaller circuit scale than the main tag section MTAG. In other words, the arithmetic processing device 100 can reduce the scale of the determination circuit for determining cache hits compared to when a main tag section MTAG is provided for each bank BK. As a result, the manufacturing cost of the arithmetic processing device 100 can be reduced compared to a arithmetic processing device in which a main tag section MTAG is provided for each bank BK.

[0054] In this embodiment, a main tag section MTAG or a subtag section STAG is provided on the bank BK side of the switch section 20 corresponding to each bank BK. The switch section 20 determines the bank BK to be accessed based on the access address output from the load store unit LDST, and outputs the access address to the main tag section MTAG or the subtag section STAG corresponding to the determined bank BK. Therefore, the hit signal HIT output from the main tag section MTAG or the subtag section STAG contains information about the bank BK. Therefore, the cache control section 40 can control the bank BK according to the hit signal HIT from the main tag section MTAG and the subtag section STAG without using the bank address BA.

[0055] Fig. 5 shows an example of a processor in another embodiment. The same elements as those in the above-mentioned embodiment are given the same reference numerals, and detailed description is omitted. The processor 100A shown in Fig. 5 is a processor such as a CPU having a function of executing multiple multiply-and-accumulate operations in parallel using, for example, a SIMD arithmetic instruction.

[0056] The arithmetic processing device 100A has the same configuration as the arithmetic processing device 100 shown in FIG. 1, except that it has a multiplexer MUX1 and a cache control unit 40A instead of the cache control unit 40 in FIG. 1. For ease of explanation, it is assumed that the arithmetic processing device 100A has four load store units LDST (LDST#0-LDST#3), three subtag units STAG (STAG#1-STAG#3), and four banks BK (BK#0-BK#3). In this embodiment, an example in which a load instruction is issued from the load store unit LDST will also be described.

[0057] The main tag portion MTAG is provided corresponding to bank BK#0. The subtag portions STAG#1-STAG#3 are provided corresponding to banks BK#1-BK#3, respectively. The multiplexer MUX1 receives addresses AD for the main tag portion MTAG and the subtag portion STAG output from the switch portion 20, and outputs one of the received addresses AD to the main tag portion MTAG.

[0058] The subtag unit STAG has the same configuration as the subtag unit STAG in Fig. 1, except that the tag conversion unit TCNV outputs a hit signal HTI1 and has a multiplexer MUX2. The multiplexer MUX2 of each subtag unit STAG outputs either the hit signal HIT2 output from the comparator CMP2 or the hit signal HIT output from the comparator CMP1 of the main tag unit MTAG. The operations of the multiplexers MUX1 and MUX2 are controlled by the cache control unit 40A.

[0059] When the cache control unit 40A receives an inactive hit signal HIT1 from any of the tag conversion units TCNV, it determines that there is a tentative cache miss. A tentative cache miss is a cache miss determined by the tag conversion unit TCNV of the subtag unit STAG, and there is also a possibility that there is a cache hit.

[0060] Then, the cache control unit 40A controls the multiplexer MUX1 to output the address AD supplied to the subtag unit STAG in which the tentative cache miss has occurred to the main tag unit MTAG. This allows the cache control unit 40A to determine whether there is a cache hit or a cache miss in the bank BK corresponding to the subtag unit STAG in which the tentative cache miss has occurred, by using the tag array TGA of the main tag unit MTAG.

[0061] The cache control unit 40A causes the multiplexer MUX2 of the subtag unit STAG in which a tentative cache miss has occurred to select the hit signal HIT output from the tag array TGA of the tag conversion unit TCNV and output it as a hit signal HIT2. This allows the cache control unit 40A to use the determination result by the tag array TGA to determine whether the bank BK corresponding to the subtag unit STAG in which a tentative cache miss has occurred is a true cache hit / cache miss. The cache control unit 40A can then control the operation of the cache 60 in accordance with the determination result. Note that when the tag conversion unit TCNV outputs a hit signal HIT1 at an inactive level, the hit signal HIT output by the comparator CMP2 always indicates an inactive level.

[0062] Fig. 6 shows an example of the subtag section STAG in Fig. 5. The address AD output by the switch section 20 in Fig. 5 includes a tag address TAG including a first tag address TAG1 and a second tag address TAG2, an index address IDX, and an offset address OFS. The offset address OFS includes a bank address BA (e.g., 2 bits) that identifies a bank BK. Any of the symbols a to f is added to the first tag address TAG1 and the second tag address TAG2 for operational explanation.

[0063] For example, the tag conversion unit TCNV has four entries ENT1 identified by identification information ID, a comparator CMP3 corresponding to each entry ENT1, an OR circuit OR, and an encoder ENC. A first tag address TAG1 is stored in each entry ENT1 by the cache control unit 40A that has determined a cache miss.

[0064] Each comparator CMP3 compares the first tag address TAG1 held in the corresponding entry ENT1 with the first tag address TAG1 included in the memory access request, and outputs the comparison result to the OR circuit OR and the encoder ENC. For example, each comparator CMP3 outputs a logic 1 when the comparison result is a match.

[0065] The OR circuit OR sets the hit signal HIT1 to an active level when the output of any one of the comparators CMP3 is logic 1, and sets the hit signal HIT1 to an inactive level when the outputs of all the comparators CMP3 are logic 0.

[0066] The encoder ENC outputs the identification information ID of the entry ENT1 corresponding to the comparator CMP3 that outputs a logical 1. In other words, the encoder ENC outputs the identification information ID of the entry ENT1 that holds the first tag address TAG1 included in the memory access request. In this way, the tag conversion unit TCNV operates as a CAM. The identification information ID output by the encoder ENC and the second tag address TAG2 included in the memory access request are output to the comparator CMP2 as a reduced tag obtained by encoding the first tag address TAG1.

[0067] The tag array cache TGAC has a plurality of entries ENT2 each holding a second tag address TAG2 and identification information ID for each value of the index address IDX, and a comparator CMP4 and a flag FLG corresponding to each entry ENT2. In the initial state, each flag FLG is reset to logic 0 indicating that the corresponding entry ENT2 is invalid. Each flag FLG is set or reset by the cache control unit 40A. The set state (logic 1) of each flag FLG indicates that the corresponding entry ENT2 holds a valid second tag address TAG2 and valid identification information ID. The reset state (logic 0) of each flag FLG indicates that the corresponding entry ENT2 holds an invalid second tag address TAG2 or invalid identification information ID.

[0068] Each comparator CMP4 sets the corresponding flag FLG to logic 1 when the identification information ID held in the entry ENT2 matches the identification information ID output from the cache control unit 40 together with the set signal SET. Each comparator CMP4 resets the corresponding flag FLG to logic 0 when the identification information ID held in the entry ENT2 matches the identification information ID output from the cache control unit 40A together with the reset signal RESET.

[0069] By providing a flag FLG for each entry ENT2 of the tag array cache TGAC, the cache control unit 40A can invalidate the entry ENT2 by only resetting the flag FLG, without rewriting the second tag address TAG2 or the identification information ID. This makes it possible to suppress, with simple control, the output of an erroneous hit signal HIT2 to the cache control unit 40A.

[0070] Based on a cache miss, the cache control unit 40A updates each bank BK#0-BK#3 with the sub-data SDT (cache line) read from the main memory 50 in Fig. 5. In response to the update of each bank BK#0-BK#3, the cache control unit 40A updates the tag array TGA of the main tag unit MTAG in Fig. 5, and updates the tag conversion unit TCNV and the tag array cache TGAC. The operation of the tag array TGA at the time of a cache miss is the same as in normal cache miss processing, so the update processing of the subtag unit STAG will be explained below.

[0071] In the update process, the cache control unit 40A stores the first tag address TAG1 included in the memory access request in one of the entries ENT1. The cache control unit 40A outputs the identification information ID of the entry ENT1 storing the first tag address TAG1 and a reset signal RESET to the comparator CMP4. The cache control unit 40A resets the flag FLG corresponding to the entry ENT2 that holds the identification information ID output to the comparator CMP4.

[0072] The cache control unit 40A stores the second tag address TAG2 included in the memory access request in the entry ENT2 corresponding to the index address IDX included in the memory access request. The cache control unit 40A also stores the identification information ID of the entry ENT1 storing the first tag address TAG1 in the entry ENT2 storing the second tag address TAG2. The cache control unit 40A then outputs the identification information ID of the entry ENT1 storing the first tag address TAG1 and a set signal SET to the comparator CMP4. The cache control unit 40A sets the flag FLG corresponding to the entry ENT2 holding the identification information ID output to the comparator CMP4.

[0073] 6, it is assumed that first tag addresses TAG1a, TAG1b, TAG1c, and TAG1d are held in four entries ENT1 of a tag translation unit TCNV in one of the subtag units STAG, and second tag addresses TAG2d, TAG2f, TAG2b, TAG2e, ..., TAG2a are held in an entry ENT2 of the tag array cache TGAC.

[0074] In this state, the subtag section STAG receives a memory access request including, for example, the first tag address TAG1b and the second tag address TAG2b. The entry ENT2 corresponding to the index address IDX included in the memory access request holds the second tag address TAG2b and the identification information ID="01", and the corresponding flag FLG is set to logic 1.

[0075] Since the identification information ID of the entry ENT1 holding the first tag address TAG1b included in the memory access request is "01", the tag conversion unit TCNV sets the hit signal HIT1 to an active level and outputs the identification information ID="01" from the encoder ENC. The reduced tag that the comparator CMP2 receives from the tag conversion unit TCNV includes the identification information ID="01" and the second tag address TAG2b.

[0076] The tag array cache TGAC outputs, as a reduced tag, the second tag address TAG2b and the identification information ID="01" held in the entry ENT2 corresponding to the index address IDX included in the memory access request. The tag array cache TGAC also outputs the logic 1 held in the flag FLG corresponding to the index address IDX included in the memory access request.

[0077] Since the reduced tags match, the comparator CMP2 outputs a logic 1 to the AND circuit AND. The AND circuit AND receives the logic 1 from the comparator CMP2 and the logic 1 from the flag FLG, and sets the hit signal HIT to an active level. When a memory access request is issued, the cache control unit 40A causes the multiplexer MUX2 to select the output of the AND circuit AND. Therefore, the multiplexer MUX2 outputs the hit signal HIT of the active level as the hit signal HIT2 to the cache control unit 40A. The cache control unit 40A detects a cache hit in the bank BK corresponding to the subtag unit STAG based on the hit signal HIT2 of the active level, and outputs the sub-data SDT held in the bank BK to the load store unit LDST.

[0078] On the other hand, there are cases where the first tag address TAG1 included in the memory access request is held in the entry ENT1, but the reduced tag corresponding to the tag conversion unit TCNV does not match the reduced tag output from the entry ENT2. Alternatively, there are cases where the reduced tags match, but the flag FLG is reset to logic 0. In these cases, the cache control unit 40A receives the inactive hit signal HIT2 and executes cache miss processing. Then, the cache control unit 40A executes update processing of each bank BK, and update processing of the tag array cache TGAC and the tag conversion unit TCNV.

[0079] Furthermore, if the first tag address TAG1 included in the memory access request is not held in the entry ENT1, the tag conversion unit TCNV sets the hit signal HIT1 to an inactive level (logic 0) as described above. When the cache control unit 40A receives the hit signal HIT1 at the inactive level, it detects a tentative cache miss and causes the multiplexer MUX1 in Fig. 5 to select the address AD supplied to the subtag unit STAG. Furthermore, the cache control unit 40A causes the multiplexer MUX2 to select the hit signal HIT from the main tag unit MTAG.

[0080] The main tag unit MTAG receives the address AD that caused the tentative cache miss via the multiplexer MUX1, judges whether it is a cache hit or a cache miss using the tag array TGA, and outputs a hit signal HIT. The cache control unit 40A receives the hit signal HIT output from the main tag unit MTAG as a hit signal HIT2 via the multiplexer MUX2, and executes a cache hit process or a cache miss process according to the hit signal HIT2.

[0081] In cache hit processing, the cache control unit 40A outputs the sub-data SDT held in the bank BK to the load store unit LDST. In cache miss processing, the cache control unit 40A executes update processing of the data in each bank BK and update processing of the tag array TGA, the tag conversion unit TCNV, and the tag array cache TGAC as described above.

[0082] Fig. 7 shows an example of a memory access operation of the arithmetic processing device 100A of Fig. 5. That is, Fig. 7 shows an example of an arithmetic processing method of the arithmetic processing device 100A. Detailed description of operations similar to those described in Fig. 4 and Fig. 6 will be omitted. The operation shown in Fig. 7 is executed by the cache control unit 40A based on the issuance of a memory access request corresponding to a load instruction from at least one of the multiple load store units LDST.

[0083] First, in step S40, cache control unit 40 uses bank address BA to determine whether the memory access request indicates bank BK (in this example, BK#0) corresponding to main tag section MTAG. If the memory access request indicates bank BK corresponding to main tag section MTAG, cache control unit 40A shifts the operation to step S42. If the memory access request does not indicate bank BK corresponding to main tag section MTAG, cache control unit 40A shifts the operation to step S44.

[0084] The process in step S42 is similar to the access process using the main tag part MTAG shown in step S20 of Fig. 4. After executing the operation of step S42, the cache control unit 40A ends the operation shown in Fig. 7.

[0085] In step S44, the cache control unit 40A accesses the subtag unit STAG corresponding to the bank BK indicated by the bank address BA included in the memory access request, similar to step S32 in Fig. 4. Then, the cache control unit 40A causes the subtag unit STAG to determine a hit / miss in the tag conversion unit TCNV and a hit / miss in the tag array cache TGAC.

[0086] Next, in step S46, the cache control unit 40A judges whether or not there is a hit in the tag conversion unit TCNV based on the hit signal HIT1 output from the tag conversion unit TCNV. If there is a hit in the tag conversion unit TCNV, the cache control unit 40A shifts the operation to step S50, and if there is a miss in the tag conversion unit TCNV, the cache control unit 40A shifts the operation to step S48. The process in step S48 is the same as the access process using the main tag unit MTAG shown in step S20 of FIG. 4. After executing the operation of step S48, the cache control unit 40A shifts the operation to step S56.

[0087] In step S50, the cache control unit 40A judges whether or not there is a hit in the tag array cache TGAC. If there is a hit in the tag array cache TGAC, since there is a hit in both the tag conversion unit TCNV and the tag array cache TGAC, the cache control unit 40A shifts the operation to step S52 and executes normal cache hit processing. The processing in step S52 is the same as the processing in step S36 in FIG. 4.

[0088] On the other hand, if there is a miss in the tag array cache TGAC, the cache control unit 40A transitions the operation to step S54. The process in step S54 is similar to the process in step S38 in FIG. 4, except that the process of updating the tag conversion unit TCNV and the tag array cache TGAC is not included. After the process in step S54, the cache control unit 40A executes step S56. In step S56, the cache control unit 40A executes the process of updating the tag conversion unit TCNV and the tag array cache TGAC, and ends the operation shown in FIG.

[0089] As described above, this embodiment can also provide the same effects as the above-mentioned embodiment. For example, the arithmetic processing device 100A can reduce the scale of the determination circuit for determining a cache hit compared to a case where a main tag part MTAG is provided for each bank BK. As a result, the manufacturing cost of the arithmetic processing device 100A can be reduced compared to a arithmetic processing device in which a main tag part MTAG is provided for each bank BK.

[0090] Furthermore, in this embodiment, when a tentative cache miss is determined by the tag conversion unit TCNV, the cache control unit 40A supplies the access address to the main tag unit MTAG via the multiplexer MUX1. This makes it possible to determine whether the cache hit / cache miss of the bank BK corresponding to the tentative cache miss is caused by using the tag array TGA of the main tag unit MTAG.

[0091] By providing a flag FLG for each entry ENT2 of the tag array cache TGAC, the cache control unit 40A can invalidate the entry ENT2 by only resetting the flag FLG, without rewriting the second tag address TAG2 or the identification information ID. This makes it possible to suppress, with simple control, the output of an erroneous hit signal HIT2 to the cache control unit 40A.

[0092] FIG. 8 shows an example of a subtag section in a processing device according to another embodiment. The same elements as those in FIG. 6 are given the same reference numerals, and detailed description is omitted. The processing device 100B shown in FIG. 8 is a processor such as a CPU having a function of executing a plurality of multiply-add operations in parallel using, for example, a SIMD arithmetic instruction. The processing device 100B has a subtag section STAG2 and a cache control section 40B instead of the subtag section STAG and the cache control section 40A shown in FIG. 5. In the processing device 100B, the configuration other than the subtag section STAG2 and the cache control section 40B is the same as that shown in FIG. 5 and FIG. 6.

[0093] The subtag unit STAG2 has a tag conversion unit TCNV2, a tag array cache TGAC2, a comparator CMP2, an AND circuit AND, and a multiplexer MUX2. The tag conversion unit TCNV2 has one entry ENT1 and a comparator CMP3 corresponding to the entry ENT1, and does not have the encoder ENC and the OR circuit OR of FIG. 6. The comparator CMP3 sets a hit signal HIT1 to an active level when the first tag address TAG1 held in the entry ENT1 matches the first tag address TAG1 included in the memory access request. The comparator CMP3 sets a hit signal HIT1 to an inactive level when the first tag address TAG1 held in the entry ENT1 does not match the first tag address TAG1 included in the memory access request. The hit signal HIT1 is output to the cache control unit 40B.

[0094] The tag array cache TGAC2 has the same configuration as the tag array cache TGAC in Fig. 6, except that it does not have a comparator CMP4 and the entry ENT2 does not hold the identification information ID. The cache control unit 40B outputs an index address IDX and a set signal SET to the tag array cache TGAC2 to set the corresponding flag FLG to logic 1. The cache control unit 40B outputs an index address IDX and a reset signal RESET to the tag array cache TGAC2 to reset the corresponding flag FLG to logic 0.

[0095] The comparator CMP2 outputs a logic 1 when the second tag address TAG2 included in the memory access request matches the second tag address TAG2 output from the entry ENT2 corresponding to the index address IDX included in the memory access request. The comparator CMP2 outputs a logic 0 when the second tag address TAG2 included in the memory access request does not match the second tag address TAG2 output from the entry ENT2 corresponding to the index address IDX included in the memory access request. When the AND circuit AND receives a logic 1 from the comparator CMP2 and the flag FLG, it sets the hit signal HIT to an active level. The operation of the multiplexer MUX2 is the same as that of the multiplexer MUX2 in FIG. 6. When a memory access request is issued, the cache control unit 40B causes the multiplexer MUX2 to select the output of the AND circuit AND.

[0096] The operation of the arithmetic processing device 100B of this embodiment is the same as that of Fig. 7. However, the number of entries ENT1 in the tag conversion unit TCNV2 is smaller than the number of entries ENT1 in Fig. 6. The tag array cache TGAC2 does not have a comparator CMP4, and the entries ENT2 do not hold identification information ID. Therefore, the circuit scale of the subtag unit STAG2 can be made smaller than that of the subtag unit STAG in Fig. 6.

[0097] As described above, this embodiment can also provide the same effects as the above-mentioned embodiment. Furthermore, in this embodiment, the circuit scale of the subtag section STAG2 can be made smaller than the circuit scale of the subtag section STAG, so that the circuit scale of the arithmetic processing device 100B can be made smaller than the circuit scale of the arithmetic processing device 100A. As a result, the manufacturing cost of the arithmetic processing device 100B can be reduced.

[0098] FIG. 9 shows an example of a processing device in another embodiment. The same elements as those in the above-mentioned embodiment are given the same reference numerals, and detailed description is omitted. The processing device 100C shown in FIG. 9 is a processor such as a CPU having a function of executing a plurality of multiply-add operations in parallel using, for example, a SIMD arithmetic instruction. The processing device 100C has a tag conversion unit TCNV common to three subtag units STAG3#1-STAG3#3. The other configurations of the processing device 100C are the same as those of the processing device 100A in FIG. 5. The configuration of the tag conversion unit TCNV is the same as that of the tag conversion unit TCNV in FIG. 6. Although not shown in FIG. 9, the cache 60 is configured such that the load store unit LDST and the main memory 50 are excluded from the elements shown in FIG. 9.

[0099] Fig. 10 shows an example of address calculation in the load store unit LDST of Fig. 9. For example, each load store unit LDST calculates the address AD of a memory access request by adding a value held in a scalar register and a value held in a SIMD register. For example, a 64-bit base address BASE_AD is held in the scalar register, and a 32-bit index address INDEX_AD (lower bits) is held in the SIMD register.

[0100] In this case, the tag addresses TAG on the higher-order bit side of the address AD generated by each load store unit LDST are the same except when a carry occurs due to addition. Therefore, the information held in the tag conversion unit TCNV in Fig. 9 can be made common to the four load store units LDST. As a result, the tag conversion unit TCNV can be made common to multiple subtag units STAG3.

[0101] As described above, this embodiment can also provide the same effects as the above-mentioned embodiment. Furthermore, in this embodiment, by providing the tag conversion unit TCNV in common to a plurality of subtag units STAG3, the circuit scale of the subtag unit STAG3 can be made smaller than that of the subtag unit STAG2. As a result, the circuit scale of the arithmetic processing device 100C can be made smaller than that of the arithmetic processing device 100A, and the manufacturing cost of the arithmetic processing device 100C can be reduced.

[0102] 11 to 13 show configuration examples of the main tag section MTAG and the subtag section STAG in another embodiment. In configuration example 1, each of a plurality of main tag sections MTAG is provided corresponding to a predetermined number of banks BK. For example, as shown in FIG. 7, when an entry ENT1 of the tag conversion section TCNV is missed in step S22, the tag array TGA of the main tag section MTAG is used to determine whether it is a cache hit or a cache miss. Therefore, when an entry ENT1 of the tag conversion section TCNV of a plurality of subtag sections STAG is missed, the tag array TGA competes, and the determination of whether it is a cache hit or a cache miss is delayed.

[0103] Also, during the determination of the main tag part MTAG for the bank BK#0, the determination of a cache hit / cache miss by the main tag part MTAG based on a tentative cache miss of the entry ENT1 of the tag conversion unit TCNV is put on hold. In the configuration example 1, by providing a plurality of main tag parts MTAG, it is possible to suppress the contention of the main tag part MTAG due to a tentative cache miss of the entry ENT1 of the tag conversion unit TCNV. Also, it is possible to reduce the possibility of contention between the determination of a cache hit / cache miss of the bank BK#0 and the determination of a cache hit / cache miss due to a miss of the entry ENT1 of the tag conversion unit TCNV.

[0104] In the second configuration example, the subtag section STAG is provided corresponding to each bank BK, and the main tag section MTAG is provided independently of the multiple banks BK. This makes it possible to repeatedly arrange pairs of the subtag section STAG and the bank BK, and enables a design that takes into account the symmetry of the circuit arrangement. As a result, for example, the layout design of the arithmetic processing device can be made easier, or the electrical characteristics, such as the frequency characteristics, of the arithmetic processing device can be improved.

[0105] In configuration example 3 to configuration example 6 shown in Figures 12 and 13, the main tag part MTAG and the subtag part STAG are arranged on the load store unit LDST side of the switch part. That is, the main tag part MTAG and the subtag part STAG receive memory access requests from a plurality of load store units LDST before being supplied to the switch part. In Figures 12 and 13, the hit signal HIT supplied to banks BK#1-BK#n other than bank BK#0 indicates hit signals HIT1 and HIT2.

[0106] For example, when the number m+1 of load store units LDST is smaller than the number n+1 of banks BK, the total number of main tag sections MTAG and subtag sections STAG can be reduced in configuration examples 3 to 6 compared to configuration examples 1 and 2. This makes it possible to further reduce the circuit scale of the arithmetic processing device compared to configuration examples 1 and 2.

[0107] In the configuration example 3 of Fig. 12, a main tag section MTAG is provided corresponding to each of the load store units LDST. In the configuration example 4 of Fig. 12, a main tag section MTAG is provided corresponding to the load store unit LDST#0, and a subtag section STAG is provided corresponding to each of the load store units LDST#1-LDST#m.

[0108] In the configuration example 5 of FIG. 13, a plurality of main tag parts MTAG are provided. As a result, similar to the configuration example of FIG. 12, the possibility that the main tag part MTAG will compete due to a plurality of memory access requests can be reduced. In the configuration example 6 of FIG. 13, the subtag part STAG is provided corresponding to each of the load store units LDST, and the main tag part MTAG is provided independently for a plurality of load store units LDST. As a result, it becomes possible to repeatedly arrange pairs of the subtag part STAG and the load store unit LDST, and it becomes possible to design in consideration of the symmetry of the circuit arrangement. As a result, for example, the layout design of the arithmetic processing device can be made easier, or the electrical characteristics such as the frequency characteristics of the arithmetic processing device can be improved.

[0109] Note that the subtag unit STAG in configuration examples 1, 2, and 4 to 6 may use the subtag unit STAG in Fig. 1 or 5, or may use the subtag unit STAG2 in Fig. 8 or the subtag unit STAG3 in Fig. 9. When the subtag unit STAG3 in Fig. 9 is used, the tag conversion unit TCNV is provided independently of the subtag unit STAG3.

[0110] FIG. 14 shows an example of a processing device in the configuration example 4 of FIG. 12. The same elements as those in the above-mentioned embodiment are given the same reference numerals, and detailed description is omitted. In the processing device 100D shown in FIG. 14, the main tag section MTAG, the subtag section STAG, and the multiplexer MUX1 are arranged between the load store unit LDST and the switch section 20D. For ease of explanation, the processing device 100D has three load store units LDST#1-LDST#3, three subtag sections STAG#1-STAG#3, and four banks BK#0-BK#3. Although not shown in FIG. 14, the cache 60 has a configuration in which the load store unit LDST and the main memory 50 are excluded from the elements shown in FIG. 14.

[0111] As shown in the configuration example 4 of Fig. 12, the main tag section MTAG is provided corresponding to the load store unit LDST#0. The subtag sections STAG#1-STAG#3 are provided corresponding to the load store units LDST#1-LDST#3, respectively. The memory access operation of the arithmetic processing device 100D is the same as that of Fig. 7.

[0112] The switch unit 20D receives an index address IDX and hit signals HIT, HIT1, and HIT2 from the main tag unit MTAG and subtag unit STAG, in addition to the address AD from the load store unit LDST and the bank address BA from the arbitration unit 10. The switch unit 20D outputs the received index address IDX and hit signals HIT, HIT1, and HIT2 to the corresponding bank BK of the cache 60 according to the bank address BA. The switch unit 20D also outputs control signals for the main tag unit MTAG and subtag unit STAG generated by the cache control unit 40 to the main tag unit MTAG and subtag unit STAG.

[0113] FIG. 15 shows an example of the main tag part MTAG and the subtag part STAG in a processing device of another embodiment. The main tag part MTAG and the subtag part STAG may be shared between a plurality of banks BK. The processing device 100E of this embodiment has a main tag part MTAG4 shared by a pair of adjacent banks BK, and a subtag part STAG4 shared by another pair of adjacent banks BK other than the pair of banks BK shared by the main tag part MTAG4. In the processing device 100E, the configuration except for the main tag part MTAG4 and the subtag part STAG4 is the same as the configuration of the processing device 100A of FIG. 5. In FIG. 15, an example in which the main tag part MTAG and the subtag part STAG are shared between a pair of adjacent banks BK, respectively, are shown, but they may be shared between any plurality of banks BK.

[0114] For example, the main tag section MTAG4 outputs a hit signal HIT for banks BK#0 and BK#1. The subtag section STAG4 outputs hit signals HIT1 and HIT (HIT2) for banks BK#2 and BK#3. If the arithmetic processing device 100E has eight banks BK#0-BK#7, a subtag section STAG4 corresponding to banks BK#4 and BK#5 and a subtag section STAG4 corresponding to banks BK#6 and BK#7 may be provided.

[0115] For example, the main tag unit MTAG4 is a multi-port type and can simultaneously receive the tag address TAG and the index address IDX output from the two load store units LDST. The main tag unit MTAG4 can output the hit signals HIT corresponding to the two load store units LDST independently of each other.

[0116] The subtag unit STAG4 is a multi-port type and can simultaneously receive the tag addresses TAG (TAG1, TAG2) and index addresses IDX output from the two load store units LDST. The subtag unit STAG4 can output hit signals HIT1, HIT (HIT2) corresponding to the two load store units LDST independently of each other.

[0117] In this embodiment, a multi-port type main tag section MTAG4 and subtag section STAG4 are provided. Therefore, the total number of main tag sections MTAG4 and subtag sections STAG4 can be reduced compared to the total number of main tag sections MTAG and subtag sections STAG in Fig. 5. This allows the circuit scale of the main tag section MTAG4 and the subtag section STAG4 to be reduced, and the circuit scale of the arithmetic processing device 100E to be reduced.

[0118] The arithmetic processing device 100E may have the main tag section MTAG4 of Fig. 15 and the subtag section STAG of Fig. 5. The arithmetic processing device 100E may have the main tag section MTAG of Fig. 5 and the subtag section STAG4 of Fig. 15. Furthermore, the main tag section MTAG4 may be arranged in place of the other main tag sections MTAG in the above-mentioned embodiments. The subtag section STAG4 may be arranged in place of the other subtag sections STAG, STAG2, and STAG3 in the above-mentioned embodiments.

[0119] Also, the main tag section MTAG4 in Fig. 15 may be provided in place of the main tag section MTAG in Configuration Example 1 in Fig. 11, Configuration Example 3 and Configuration Example 4 in Fig. 12, and Configuration Example 5 in Fig. 13. Also, the subtag section STAG4 in Fig. 15 may be provided in place of the subtag section STAG in Configuration Examples 1 to 6 in Figs. 11 to 13.

[0120] As described above, this embodiment can also provide the same effects as the above-mentioned embodiment. Furthermore, in this embodiment, by providing at least one of the main tag section MTAG4 and the sub tag section STAG4 of the multi-port type, the circuit scale of the arithmetic processing device 100E can be reduced.

[0121] Fig. 16 shows an example of the tag array / data array ratio for each cache structure. In Fig. 16, only the tag array TGA is used, and the tag array cache TGAC shown in Fig. 1 is not used. The symbol (A) shown in the cache line size is used in the explanation of Fig. 17.

[0122] When a tag array TGA is provided for each bank BK, the ratio of the tag array TGA to the data array DTA for each bank BK increases as the number of banks BK increases and as the cache line size decreases. The ratio of the tag array TGA to the data array DTA increases as the number of ways increases and as the number of bits F of the physical address increases. Here, the number of bits (a) of the tag array TGA is expressed by equation (1).

[0123] (a)=F+log2(number of ways)-log2(cache size) ‥(1) Furthermore, the ratio of the tag array TGA to the data array DTA increases as the cache size decreases.

[0124] Fig. 17 shows an example of the effect of improving the tag array / data array ratio when a tag array cache is provided. In the cache structure shown in Fig. 16(A), the tag array / data array ratio is 56.3%. In contrast, in the cache structure of Fig. 1 using the tag array cache TGAC, the tag array / data array ratio can be reduced to 16.9%, which is about 1 / 3 of that in Fig. 16(A). Furthermore, in the cache structure of configuration example 4 of Fig. 12 using the tag array cache TGAC, the tag array / data array ratio can be reduced to 9.1%, which is about 1 / 6 of that in Fig. 16(A).

[0125] The features and advantages of the embodiments will be apparent from the above detailed description. It is intended that the claims cover the features and advantages of the embodiments as described above without departing from the spirit and scope of the claims. In addition, any improvements and modifications can be easily made by a person having ordinary skill in the art. Therefore, it is not intended to limit the scope of the inventive embodiments to the above, and appropriate improvements and equivalents within the scope of the embodiments disclosed can be used. [Explanation of symbols]

[0126] 10 Mediation Department 20 Switch section 30 Data Array 40, 40A, 40B Cache control unit 50 Main memory 60 Cash 100, 100A, 100B Processing unit 100C, 100D, 110E Processing unit AD Address BA Bank Address BK Bank CL Cache Line CMP1, CMP2, CMP3 comparators DT Data DTA Data Array ENT1, ENT2 entries FLG flag HIT, HIT1, HIT2 Hit signal ID Identification information IDX Index Address LDST Load Store Unit MTAG, MTAG4 main tag MUX1, MUX2 Multiplexers OFS offset address SDT Subdata STAG, STAG2, STAG3, STAG4 subtag parts TAG Tag address TAG1 First tag address TAG2 Second tag address TCNV, TCNV2 tag conversion unit TGAC, TGAC2 Tag Array Cache TGAC

Claims

1. a plurality of request issuing units for issuing memory access requests to the storage device; a data array including a plurality of banks each capable of holding sub-data obtained by dividing data read from the storage device based on the memory access request; a switch unit that transfers the memory access request to one of the plurality of banks; at least one first determination unit having a first holding unit that holds a tag address included in the access address for each value of an index address in the access address included in the memory access request, and that determines a cache hit indicating that data to be accessed is held in the data array when the tag address included in the access address matches a tag address held in the first holding unit corresponding to the index address included in the access address; at least one second determination unit having a second holding unit that holds identification information for identifying a first tag address included in the tag address and a second tag address included in the tag address for each value of an index address, and that determines a cache hit when the identification information corresponding to the first tag address included in the access address and the second tag address included in the access address match the identification information and the second tag address held in the second holding unit corresponding to the index address included in the access address; a cache control unit that accesses the data array or the storage device based on a determination result of the first determination unit or the second determination unit; A processing device having:

2. The second determination unit is a third storage unit including a plurality of entries for storing the first tag addresses; identification information for identifying the first tag address is identification information for identifying the entry in the third holding unit, A cache hit is determined when identification information for identifying the entry in the third storage section that holds the first tag address included in the access address and the second tag address included in the access address are stored in the second storage section in correspondence with an index address included in the access address. The processor according to claim 1 .

3. The third holding unit is provided in common to the plurality of second determination units. The processor according to claim 2 .

4. The cache control unit causes the first determination unit to determine a cache hit based on the access address when a first tag address included in the access address is not held in the third holding unit. The processor according to claim 2 or 3.

5. The second storage unit has a flag indicating that the stored identification information is valid for each index address value. The processor according to any one of claims 1 to 4.

6. The first determination unit and the second determination unit receive the memory access requests from the plurality of request issuing units via the switch unit. The processor according to any one of claims 1 to 5.

7. the first determination units are provided corresponding to the two or more banks, The second determination unit is provided corresponding to a bank not corresponding to the first determination unit. The processor according to claim 6.

8. the first determination unit is provided independently of the plurality of banks; The second determination units are provided corresponding to the plurality of banks, respectively. The processor according to claim 6.

9. the second determination unit is shared by a plurality of the banks; The first determination unit is provided corresponding to at least one of the banks other than the plurality of banks shared by the second determination unit. The processor according to claim 6.

10. the first determination unit is shared by a plurality of the banks; The second determination unit is provided corresponding to at least one of the banks other than the plurality of banks shared by the first determination unit. The processor according to claim 6 or 9.

11. The first determination unit and the second determination unit receive the memory access requests from the plurality of request issuing units before the memory access requests are supplied to the switch unit. The processor according to any one of claims 1 to 5.

12. the first determination unit is provided corresponding to two or more of the request issuing units, The second determination unit is provided corresponding to a request issuing unit that does not correspond to the first determination unit. The processor according to claim 11.

13. the first determination unit is provided independently of the plurality of request issuing units, The second determination units are provided corresponding to the plurality of request issuing units, respectively. The processor according to claim 11.

14. the second determination unit is shared by a pair of the request issue units adjacent to each other, The first determination unit is provided corresponding to at least one of the request issue units other than the pair of request issue units shared by the second determination unit. The processor according to claim 11.

15. the first determination unit is shared by a pair of the request issue units adjacent to each other, The second determination unit is provided corresponding to at least one of the request issue units other than the pair of request issue units shared by the first determination unit. The processor according to claim 11 or 14.

16. 1. A processing method for a processing device having a plurality of request issuing units which issue memory access requests to a storage device, a data array including a plurality of banks each capable of holding sub-data obtained by dividing data read from the storage device based on the memory access requests, and a switch unit which transfers the memory access requests to any one of the plurality of banks, at least one first determination unit included in the arithmetic processing device and having a first holding unit that holds a tag address included in the access address for each value of an index address in the access address included in the memory access request, determines a cache hit indicating that data to be accessed is held in the data array when the tag address included in the access address matches a tag address held in the first holding unit corresponding to the index address included in the access address; at least one second determination unit, which is included in the arithmetic processing device and has a second holding unit that holds identification information for identifying a first tag address included in the tag address and a second tag address included in the tag address for each value of an index address, determines a cache hit when the identification information corresponding to the first tag address included in the access address and the second tag address included in the access address match the identification information and the second tag address held in the second holding unit corresponding to the index address included in the access address; A cache control unit included in the arithmetic processing device accesses the data array or the storage device based on a determination result of the first determination unit or the second determination unit. Calculation processing method.

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