Semiconductor Device

Abstract

To provide a semiconductor device capable of maintaining write characteristics and read characteristics in normal operation and reducing leak current in a static random access memory (SRAM) built in the semiconductor device.SOLUTION: A semiconductor device includes: a first regulator that generates a first power supply potential; a second regulator that generates a second power supply potential lower than the first power supply potential; a static type random access memory (SRAM) having a normal operation mode and a resume standby mode. The SRAM includes: a power switch circuit that receives the first power supply potential and the second power supply potential; and a memory array including a plurality of memory cells. The power switch circuit is controlled so that the first power supply potential is supplied from the power switch circuit to the memory cell array when the SRAM is in the normal operation mode and the second power supply potential is supplied from the power switch circuit to the memory cell array when the SRAM is in the resume standby mode.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device, and in particular to a technology that is effective when applied to a semiconductor device having a storage device such as a static random access memory (SRAM). [Background technology]

[0002] Semiconductor Device Proposals for reducing leakage current in a static random access memory (SRAM) built into a semiconductor device include, for example, Patent Document 1 (Japanese Patent Laid-Open Publication No. 2004-206745) and Patent Document 2 (Japanese Patent Laid-Open Publication No. 2003-132683). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2004-206745 A [Patent Document 2] JP 2003-132683 A Summary of the Invention [Problem to be solved by the invention]

[0004] When the power supply potential of a memory cell is lowered to reduce the leakage current, the write and read characteristics may deteriorate. Also, when the power supply potential and ground potential of a memory cell are determined by transistor characteristics such as the threshold voltage (Vt) of a MOS transistor, the leakage current may not be sufficiently reduced.

[0005] An object of the present disclosure is to provide a technique capable of reducing leakage current while maintaining write and read characteristics during normal operation in a static random access memory (SRAM) built into a semiconductor device.

[0006] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0007] A brief summary of representative aspects of this disclosure is as follows.

[0008] According to one embodiment, a semiconductor device includes a first regulator that generates a first power supply potential, a second regulator that generates a second power supply potential lower than the first power supply potential, and a static random access memory (SRAM) having a normal operation mode and a resume standby mode. The SRAM includes a power switch circuit that receives the first power supply potential and the second power supply potential, and a memory array including a plurality of memory cells. The power switch circuit is controlled so that when the SRAM is in the normal operation mode, the first power supply potential is supplied from the power switch circuit to the memory array, and when the SRAM is in the resume standby mode, the second power supply potential is supplied from the power switch circuit to the memory array. Effect of the Invention

[0009] According to the semiconductor device according to the above embodiment, it is possible to reduce the leakage current while maintaining the write and read characteristics during normal operation. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a block diagram illustrating a configuration example of a semiconductor device according to a first embodiment. [Diagram 2] FIG. 2 is a diagram for explaining a configuration example of the power switch circuit of FIG. [Diagram 3] FIG. 3 is a circuit diagram showing an example of the configuration of a memory cell. [Figure 4] FIG. 4 is a circuit diagram showing an example of the configuration of the first switch control signal generating circuit. [Diagram 5] FIG. 5 is a circuit diagram showing a configuration example of the second switch control signal generating circuit. [Figure 6] FIG. 6 is a diagram for explaining the normal operation of the SRAM 2. In FIG. [Figure 7]FIG. 7 is a diagram for explaining the first resume standby operation of the SRAM2. [Figure 8] FIG. 8 is a diagram for explaining the second resume standby operation of the SRAM2. [Figure 9] FIG. 9 is a diagram for explaining the third resume standby operation of the SRAM2. [Figure 10] FIG. 10 is a diagram for explaining the first shutdown mode operation of the SRAM 2. In FIG. [Figure 11] FIG. 11 is a diagram for explaining the second shutdown mode operation of the SRAM2. [Figure 12] FIG. 12 is a diagram for explaining the third shutdown mode operation of the SRAM 2. In FIG. [Figure 13] FIG. 13 is a diagram showing the resume standby mode transition in a VDD supply state (VDD=1.18 V). [Figure 14] FIG. 14 is a diagram showing the transition to the shutdown mode when VDD is supplied (VDD=1.18 V). [Figure 15] FIG. 15 is a diagram showing the resume standby mode transition in a state where VDD is not supplied (VDD=HiZ). [Figure 16] FIG. 16 is a diagram showing the shutdown mode transition when VDD is not supplied (VDD=HiZ). [Figure 17] FIG. 17 is a diagram showing the resume standby mode transition in the VDD=0V state. [Figure 18] FIG. 18 is a diagram showing the transition to the shutdown mode when VDD=0V. [Figure 19] FIG. 19 is a diagram illustrating a configuration example of a power switch circuit according to a second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, the embodiments will be described with reference to the drawings. However, in the following description, the same components are given the same reference numerals and the repeated description may be omitted. Note that the drawings may be shown more diagrammatically than the actual embodiment in order to clarify the description, but they are merely examples and do not limit the interpretation of the present invention.

[0012] Before describing the embodiments, the problem will be described in order to facilitate understanding of the present disclosure.

[0013] In Patent Document 1, the power supply dd is connected to the VDD of the memory cell, and the source line ss1 is connected to the source of the drive MOS of the memory cell. In order to further reduce the leakage current in the configuration of Patent Document 1, it is necessary to lower the power supply dd. However, when the power supply dd is lowered, the following problem occurs. 1) When the memory cell power supply is lowered to reduce leakage, the write / read characteristics deteriorate. 2) A real-time OS does not allow the regulator's output voltage to be changed dynamically. 3) It is difficult to control the power supply for each memory unit.

[0014] In Patent Document 2, the power supply to the SRAM is changed during ResumeStandby to reduce the leakage current. The configuration of Patent Document 2 has the following problems. 4) Since the potential states of the power supply potential Vddma and the ground potential Vssma are determined by the threshold voltage Vt of the transistor, the leakage current cannot be reduced sufficiently (the precision of the leakage current reduction is poor). 5) Since the potential states of the power supply potential Vddma and the ground potential Vssma are determined by the threshold voltage Vt of the transistors, it is difficult to retain memory data.

[0015] In an embodiment of the present disclosure, the following configuration is adopted in a static random access memory (SRAM) having a power supply for memory cells (VDDR) and a power supply for peripheral circuits (VDD). A) The power supply to the memory array (22) or memory cells (MC) is switched between the power supply for peripheral circuits (VDD) and the power supply for memory cells (VDDR) by a resume standby signal RS (switched by the power switch circuit (21)). B) In the resume standby mode, there are control signals (RSSW, LCMSW, LCMRSW, LCMNRSW, LCMNSW) for switching the power supply to the memory array (22) or the memory cells (MC). C) When switching to resume standby mode and when returning from resume standby mode, the well potential of the memory array (22) or the N-type well (NW3) of the memory cell (MC) changes dynamically.

[0016] As a result, the embodiment of the present disclosure can achieve the following effects. 1) Since the power supply level (VDD, VDDR) of the memory array (22) is switched by the power supply switch circuit (21), there is no deterioration in the write characteristics and read characteristics. 2) Since the power supply level (VDD, VDDR) of the memory array (22) is switched by the power supply switch circuit (21), there is no need to change the output voltage (VDD, VDDR) of the regulators (25, 26). 3) Since the power switch circuit (21) can be switched between the resume standby mode and the normal operation mode, there is no need to control the power supply to the memory (SRAM2) individually. 4) The power supply for memory cells (power supply for data retention) (VDDR) is supplied from the regulator (26), so that leakage current of the memory array (22) or memory cells (MC) can be reduced with high accuracy. 5) The power supply for memory cells (power supply for data retention) (VDDR) is supplied from the regulator (26), so that the precision of the potential level is high and the retention characteristics of the memory array (22) or memory cells (MC) can be stabilized.

[0017] Hereinafter, an embodiment will be described with reference to the drawings. EXAMPLES

[0018] Fig. 1 is a block diagram illustrating a configuration example of a semiconductor device according to a first embodiment. Fig. 2 is a diagram illustrating a configuration example of a power switch circuit of Fig. 1. Fig. 3 is a circuit diagram illustrating a configuration example of a memory cell.

[0019] 1 shows an example of the configuration of a static random access memory (SRAM) 2 formed on a semiconductor substrate 10 made of, for example, single crystal silicon. The SRAM 2 is a volatile memory built into the semiconductor device 1, and is formed on the semiconductor substrate 10 together with a central processing unit CPU constituting a processor (not shown), peripheral function circuits, and non-volatile memories such as ROM.

[0020] The SRAM 2 includes, for example, a power switch circuit 21, a memory array 22 including a plurality of memory cells, a memory peripheral circuit 23, and a switch control signal generation circuit unit 24 including a switch control signal generation circuit that generates a control signal for the power switch circuit 21. The memory peripheral circuit 23 includes, for example, a decoder, a read circuit including a sense amplifier, a write circuit including a write amplifier, an input / output circuit, etc. A resume standby signal RS, a switch control signal RSSW, and a shutdown mode signal SDM are constantly supplied to the SRAM 2.

[0021] The semiconductor substrate 10 further includes a first regulator 25 and a second regulator 26 for generating power to be supplied to the SRAM 2. The first regulator (VDD REG) 25 is a first power supply potential generating circuit, which generates a first power supply potential (VDD) of 1.18V from its output terminal during operation, and sets its output terminal to a high impedance (HiZ) state during non-operation. The second regulator (VDDR REG) 26 is a second power supply potential generating circuit, which generates a second power supply potential (VDDR) of 1.00V from its output terminal during operation. The first power supply potential (VDD) generated by the first regulator 25 can be called a power supply for peripheral circuits. The second power supply potential (VDDR) generated by the second regulator (VDDR REG) 26 can be called a power supply for memory cells or a power supply for holding.

[0022] The second regulator (VDDR REG) 26 is configured to constantly generate a second power supply potential (VDDR) of 1.00 V when a power supply potential is supplied to the semiconductor device 1 or the SRAM 2. As a result, the switch control signal generating circuit unit 24 is constantly supplied with the second power supply potential (VDDR) of 1.00 V from the second regulator (VDDR REG) 26, and the switch control signal generating circuit formed in the switch control signal generating circuit unit 24 is configured to constantly generate a control signal that controls the operation of the power switch circuit 21.

[0023] During a read operation (read) and a write operation (write), which are normal operations of the SRAM 2, a first power supply potential (VDD) of 1.18 V is supplied from the first regulator (VDD REG) 25 to the memory array 22 and the memory peripheral circuit 23. During a resume operation (Resurme or ResurmeStandby) of the SRAM 2, a second power supply potential (VDDR) of 1.00 V is supplied from the second regulator (VDDR REG) 26 to the memory array 22, and the first power supply potential (VDD) of 1.18 V or a high impedance (HiZ) state is supplied from the first regulator (VDD REG) 25 to the memory peripheral circuit 23. During a shutdown mode (SDM) of the SRAM 2, the power supply potentials of the memory array 22 and the memory peripheral circuit 23 are set to a high impedance (HiZ) state.

[0024] The power switch circuit 21 has three types of N-type wells in which PMOSFETs (P-type metal oxide semiconductor field effect transistors) are formed. That is, the first N-type well NW1, the second N-type well NW2, and the third N-type well NW3. Similarly, the SRAM2 also has three types of N-type wells (the first N-type well NW1, the second N-type well NW2, and the third N-type well NW3). The first N-type well NW1 of the SRAM2 is an N-type well in which the PMOSFETs of the memory peripheral circuit 23 are formed. The second N-type well NW2 of the SRAM2 is an N-type well in which the PMOSFETs of the switch control signal generation circuit unit 24 are formed. The third N-type well NW3 of the SRAM2 is an N-type well in which the PMOSFETs (PQ1 and PQ2 in FIG. 3) of the memory cells of the memory array 22 are formed.

[0025] The first N-type well NW1 is configured to receive a first power supply potential (VDD) of 1.18 V from the first regulator 25. The second N-type well NW2 is configured to receive a second power supply potential (VDDR) of 1.00 V from the second regulator 26. The third N-type well NW3 is configured to receive an internal power supply potential (CARVDD) of the memory array 22.

[0026] 2, the power switch circuit 21 includes first to fourth PMOS transistors P1 to P4. The power switch circuit 21 is provided between a first regulator 25, a second regulator 26, and a fifth PMOS transistor P5 connected to the power supply side of the memory array 22.

[0027] The source-drain path of the first PMOS transistor P1 and the source-drain path of the second PMOS transistor P2 are connected in series between the output terminal of the first regulator 25 and the source-drain path of the fifth PMOS transistor P5.

[0028] A source-drain path of the first PMOS transistor P1 is configured to receive a first power supply potential (VDD) of 1.18 V from the output terminal of the first regulator 25. A gate of the first PMOS transistor P1 is configured to receive a first switch control signal LCMSW of 0.00 V or 1.18 V. The PMOS transistor P1 is formed in the first N-type well NW1, and its source and back gate are configured to receive the voltage of the output terminal of the first regulator 25.

[0029] The gate of the second PMOS transistor P2 is configured to receive a second switch control signal LCMRSW of 0.00 V or 1.00 V. The second PMOS transistor P2 is formed in the third N-type well NW3, and has its drain and back gate connected to the internal power supply potential CARVDD of the memory array 22.

[0030] The source-drain path of the third PMOS transistor P3 and the source-drain path of the fourth PMOS transistor P4 are connected in series between the output terminal of the second regulator 26 and the source-drain path of the fifth PMOS transistor P5. The directly connected source-drain path of the third and fourth PMOS transistors P3 and P4 is connected in parallel to the series connected source-drain path of the first and second PMOS transistors P1 and P2, and to the source-drain path of the fifth PMOS transistor P5.

[0031] A source-drain path of the third PMOS transistor P3 is configured to receive a second power supply potential (VDDR) of 1.00 V from the output terminal of the second regulator 26. A gate of the third PMOS transistor P3 is configured to receive a third switch control signal LCMNRSW of 0.00 V or 1.00 V. The PMOS transistor P3 is formed in the second N-type well NW2, and its source and back gate are configured to receive the voltage of the output terminal of the second regulator 26.

[0032] The gate of the fourth PMOS transistor P4 is configured to receive a fourth switch control signal LCMNSW of 0.00 V or 1.18 V. The fourth PMOS transistor P4 is formed in the third N-type well NW3, and has its drain and back gate connected to the internal power supply potential CARVDD of the memory array 22.

[0033] The fifth PMOS transistor P5 connected to the power supply side of the memory array 22 has a gate receiving a fifth switch control signal ARVDDSW of 0.00 V or 1.00 V, and a source-drain path connected between the memory array 22 and the internal power supply potential CARVDD of the memory array 22. The fifth PMOS transistor P5 is formed in the third N-type well NW3, and its back gate is configured to receive the internal power supply potential CARVDD.

[0034] First to third NMOS transistors N1 to N3 are provided between the memory array 22 and the ground potential VSS.

[0035] The source-drain path of the first NMOS transistor N1 is connected between the gate of the third NMOS transistor N3 and the internal ground potential ARVSS. The gate of the first NMOS transistor N1 is configured to receive a sixth switch control signal DIOSW of 0.00 V or 1.00 V.

[0036] The source-drain path of the second NMOS transistor N2 is connected between the internal ground potential ARVSS and the ground potential VSS of the memory array 22. The gate of the second NMOS transistor N2 is configured to receive a seventh switch control signal ARVSSNOE of 0.00V or 1.00V.

[0037] The source-drain path of the third NMOS transistor N3 is connected between the internal ground potential ARVSS of the memory array 22 and the ground potential VSS. The gate of the third NMOS transistor N3 is configured to receive an eighth switch control signal LCMNARY. When the first NMOS transistor N1 is turned on by a sixth switch control signal DIOSW of 1.00 V, the third NMOS transistor N3 is configured to be diode-connected. As a result, the internal ground potential ARVSS is set to a potential higher than the ground potential VSS by the forward voltage (VF) of the diode.

[0038] (Example of memory cell configuration) Next, an example of the configuration of a memory cell will be described with reference to FIG.

[0039] 3, the circuit configuration of each of the memory cells MC provided in the memory array 22 includes two access transistors NA1 and NA2, two load transistors PQ1 and PQ2, and two drive transistors NQ1 and NQ2. The access transistors NA1 and NA2 and the drive transistors NQ1 and NQ2 are each an N-channel type MOS field effect transistor, and the load transistors PQ1 and PQ2 are each a P-channel type MOS field effect transistor. The load transistors PQ1 and PQ2 are formed in a third N-type well NW3, and their back gates are configured to receive the internal power supply potential CARVDD. The load transistors PQ1 and PQ2 are sometimes called P-channel type load MOS transistors.

[0040] The source-drain path of the load transistor PQ1 and the source-drain path of the drive transistor NQ1 are connected in series between the internal power supply potential (memory cell power supply potential) CARVDD of the memory array 22 and the internal ground potential ARVSS of the memory array 22. The source-drain path of the load transistor PQ2 and the source-drain path of the drive transistor NQ2 are connected in series between the internal power supply potential CARVDD and the internal ground potential ARVSS.

[0041] The gate of the load transistor PQ1 and the gate of the drive transistor NQ1 are connected to form a common gate, the drain of the load transistor PQ2 and the drain of the drive transistor NQ2 are connected to form a common drain, and the common gate of the load transistor PQ1 and the drive transistor NQ1 is connected to the common drain of the load transistor PQ2 and the drive transistor NQ2.

[0042] Similarly, the gate of the load transistor PQ2 and the gate of the drive transistor NQ2 are connected to form a common gate, the drain of the load transistor PQ1 and the drain of the drive transistor NQ1 are connected to form a common drain, and the common gate of the load transistor PQ2 and the drive transistor NQ2 is connected to the common drain of the load transistor PQ1 and the drive transistor NQ1.

[0043] The source-drain path of the access transistor NA1 is connected between the bit line BT of the complementary bit line pair BT, / BT and the common drain of the load transistor PQ1 and the drive transistor NQ1. The gate of the access transistor NA1 is connected to the word line WL by a connection node ND1. The source-drain path of the access transistor NA2 is connected between the bit line / BT of the complementary bit line pair BT, / BT and the common drain of the load transistor PQ2 and the drive transistor NQ2. The gate of the access transistor NA2 is connected to the word line WL by a connection node ND2.

[0044] (Example of the switch control signal generation circuit) An example of the configuration of the first switch control signal generating circuit 40 and the second switch control signal generating circuit 50 formed in the switch control signal generating circuit section 24 will be described with reference to Figs. 4 and 5. circuit FIG. 5 is a circuit diagram showing a configuration example of a second switch control signal generation circuit. circuit 4 and 5. Since a person skilled in the art can understand the connection configuration by looking at Fig. 4 and Fig. 5, the specific connection configuration will not be described in the following explanation of Fig. 4 and Fig. 5.

[0045] 4, the first switch control signal generation circuit 40 receives a resume standby (ResumeStandby) signal RS and generates four internal control signals (LCM, LCMN, LCMR, LCMNR). The first switch control signal generation circuit 40 includes four inverters IV1 to IV4 and two diodes Di1 and Di2 in order to form the internal control signals LCMR and LCMNR. The inverters IV1 to IV4 are connected to the output terminal of the second regulator 26 and are configured to receive a second power supply potential (VDDR) of 1.00V. Therefore, the internal control signals LCMR and LCMNR are set to a value of 1.00V or 0.00V.

[0046] The first switch control signal generating circuit 40 includes four PMOS transistors P10 to P13, two NMOS transistors N10 and N11, and two inverters IN5 and IN6 to generate the internal control signals LCM and LCMN. The PMOS transistors P10 and P12 and the inverters IN5 and IN6 are connected to the output terminal of the first regulator 25 and configured to receive a first power supply potential (VDD) of 1.18V. Therefore, the internal control signals LCM and LCMN are set to a value of 1.18V or 0.00V.

[0047] As shown in FIG. 5, the second switch control signal generation circuit 50 receives the switch control signal RSSW and the internal control signal LCMR generated by the first switch control signal generation circuit 40, and forms a first switch control signal LCMSW having a signal level of 0.00V (low level: L level) which is the signal level of the ground potential or 1.18V (high level: H level) which is the signal level of the first power supply potential VDD, and a second switch control signal LCMRSW having a signal level of 0.00V (low level: L level) which is the signal level of the ground potential or 1.00V (high level: H level) which is the signal level of the second power supply potential VDDR.

[0048] The second switch control signal generation circuit 50 includes one NAND circuit NAND, three inverters IV7 to IV9, and two diodes Di3 and Di4 to generate the second switch control signal LCMRSW. The NAND circuit NAND and the inverters IV7 to IV9 are connected to the output terminal of the second regulator 26 and configured to receive a second power supply potential (VDDR) of 1.00 V.

[0049] The second switch control signal generating circuit 50 includes four PMOS transistors P14 to P17, two NMOS transistors N12, N13, and two inverters IN10, IN11 to generate the first switch control signal LCMSW. The PMOS transistors P14, P16 and the inverters IN10, IN11 are connected to the output terminal of the first regulator 25 and configured to receive a first power supply potential (VDD) of 1.18 V.

[0050] Although not shown, the third switch control signal LCMNRSW having a signal level of 0.00 V (low level: L level) which is the ground potential or 1.00 V (high level: H level) which is the signal level of the second power supply potential VDDR, and the fourth switch control signal LCMNSW having a signal level of 0.00 V (low level: L level) or 1.18 V (high level: H level) which is the signal level of the first power supply potential VDD can be generated by changing the internal control signal LCMR to the internal control signal LCMNR in the second switch control signal generation circuit 50 shown in FIG. 5.

[0051] As shown in Figure 5, during the normal read and write operations of SRAM2, a countermeasure is taken to ensure that operation is not affected even if the switch control signal RSSW transitions, by taking the logic of the resume standby signal RS (internal control signals LCMR, LCMNR) at the first stage of the switch control signal RSSW.

[0052] (Explanation of SRAM operation) The operation of the SRAM 2 will be described below with reference to FIGS.

[0053] (1. Normal operation) 6 is a diagram for explaining the normal operation of the SRAM 2. As shown in FIG. 6, each transistor is controlled.

[0054] The first PMOS transistor P1 is turned on when the first switch control signal LCMSW is 0.00V. The second PMOS transistor P2 is turned on when the second switch control signal LCMRSW is 0.00V. The third PMOS transistor P3 is turned off when the third switch control signal LCMNRSW is 1.00V. The fourth PMOS transistor P4 is turned off when the fourth switch control signal LCMNSW is 1.18V. The fifth PMOS transistor P5 is turned on when the fifth switch control signal ARVDDSW is 0.00V. The first NMOS transistor N1 is turned off when the sixth switch control signal DIOSW is 0.00V. The second NMOS transistor N2 is turned on when the seventh switch control signal ARVSSNOE is 1.00V. The third NMOS transistor N3 is turned off when the eighth switch control signal LCMNARY is 1.00V. on It is considered to be in this state.

[0055] The back gate of the first PMOS transistor P1 is set to the first power supply potential (VDD) of 1.18V. The back gate of the second PMOS transistor P2 is set to the internal power supply potential CARVDD. The back gate of the fourth PMOS transistor P4 is set to the internal power supply potential CARVDD. The internal power supply potential CARVDD is 1.18V. The back gate of the fifth PMOS transistor P5 is set to the internal power supply potential CARVDD, and the internal power supply potential CARVDD (1.18V) is supplied to the memory cell.

[0056] (2. 1st Resume Standby Operation) Fig. 7 is a diagram for explaining the first resume standby operation of the SRAM 2. As shown in Fig. 7, each transistor is controlled. In the first resume standby operation, the first regulator 25 is in the on state (VDD=ON, 1.18V), and the switch control signal RSSW is in the off state (RSSW=0).

[0057] The first PMOS transistor P1 is turned on when the first switch control signal LCMSW is 0.00V. The second PMOS transistor P2 is turned on when the second switch control signal LCMRSW is 0.00V. The third PMOS transistor P3 is turned off when the third switch control signal LCMNRSW is 1.00V. The fourth PMOS transistor P4 is turned off when the fourth switch control signal LCMNSW is 1.18V. The fifth PMOS transistor P5 is turned on when the fifth switch control signal ARVDDSW is 0.00V. The first NMOS transistor N1 is turned on when the sixth switch control signal DIOSW is 1.00V. The second NMOS transistor N2 is turned off when the seventh switch control signal ARVSSNOE is 0.00V. The third NMOS transistor N3 is diode-connected when the eighth switch control signal LCMNARY is set to the drain potential of the third NMOS transistor N2.

[0058] The back gate of the first PMOS transistor P1 is set to the first power supply potential (VDD) of 1.18V. The back gate of the second PMOS transistor P2 is set to the internal power supply potential CARVDD. The back gate of the fourth PMOS transistor P4 is set to the internal power supply potential CARVDD. The internal power supply potential CARVDD is 1.18V. The back gate of the fifth PMOS transistor P5 is set to the internal power supply potential CARVDD, and the internal power supply potential CARVDD (1.18V) is supplied to the memory cell.

[0059] (3. Second Resume Standby Operation) Fig. 8 is a diagram for explaining the second resume standby operation of the SRAM 2. As shown in Fig. 8, each transistor is controlled. In the second resume standby operation, the first regulator 25 is in the on state (VDD=ON, 1.18V), and the switch control signal RSSW is in the on state (RSSW=1).

[0060] The first PMOS transistor P1 is in an off state when the first switch control signal LCMSW is 1.18V. The second PMOS transistor P2 is in an off state when the second switch control signal LCMRSW is 1.00V. The third PMOS transistor P3 is in an on state when the third switch control signal LCMNRSW is 0.00V. The fourth PMOS transistor P4 is in an on state when the fourth switch control signal LCMNSW is 0.00V. The fifth PMOS transistor P5 is in an on state when the fifth switch control signal ARVDDSW is 0.00V. The first NMOS transistor N1 is in an on state when the sixth switch control signal DIOSW is 1.00V. The second NMOS transistor N2 is in an off state when the seventh switch control signal ARVSSNOE is 0.00V. The third NMOS transistor N3 is in a diode-connected state when the eighth switch control signal LCMNARY is set to the drain potential of the third NMOS transistor N3.

[0061] The back gate of the third PMOS transistor P3 is connected to the second power supply potential (VD DR). The back gate of the fourth PMOS transistor P4 is at the internal power supply potential CARVDD. The internal power supply potential CARVDD is 1.00V. The back gate of the fifth PMOS transistor P5 is at the internal power supply potential CARVDD, and the internal power supply potential CARVDD (1.00V) is supplied to the memory cell.

[0062] (4. Third Resume Standby Operation) Fig. 9 is a diagram for explaining the third resume standby operation of the SRAM 2. As shown in Fig. 9, each transistor is controlled. In the third resume standby operation, the first regulator 25 is in the off state (VDD=OFF, 0.00V), and the switch control signal RSSW is in the on state (RSSW=1).

[0063] The first PMOS transistor P1 has a first switch control signal LCMSW of 0.00V. The second PMOS transistor P2 has a second switch control signal LCMRSW of 1.00V and is in an off state. The third PMOS transistor P3 has a third switch control signal LCMNRSW of 0.00V and is in an on state. The fourth PMOS transistor P4 has a fourth switch control signal LCMNSW of 0.00V and is in an on state. The fifth PMOS transistor P5 has a fifth switch control signal ARVDDSW of 0.00V and is in an on state. The first NMOS transistor N1 has a sixth switch control signal DIOSW of 1.00V and is in an on state. The second NMOS transistor N2 has a seventh switch control signal ARVSSNOE of 0.00V and is in an off state. The third NMOS transistor N3 has an eighth switch control signal LCMNARY set to the drain potential of the third NMOS transistor N3 and is in a diode-connected state.

[0064] The back gate of the first PMOS transistor P1 is set to 0.00V. The back gate of the second PMOS transistor P2 is at the internal power supply potential CARVDD. The back gate of the fourth PMOS transistor P4 is at the internal power supply potential CARVDD. The internal power supply potential CARVDD is 1.00V. The back gate of the fifth PMOS transistor P5 is at the internal power supply potential CARVDD, and the internal power supply potential CARVDD (1.00V) is supplied to the memory cell.

[0065] (5. First Shutdown Mode Operation) Fig. 10 is a diagram for explaining the first shutdown mode operation of the SRAM 2. As shown in Fig. 10, each transistor is controlled. In the first shutdown mode operation, the first regulator 25 is in the on state (VDD=ON, 1.18V), and the switch control signal RSSW is in the off state (RSSW=0).

[0066] The first PMOS transistor P1 is turned on when the first switch control signal LCMSW is 0.00V. The second PMOS transistor P2 is turned on when the second switch control signal LCMRSW is 0.00V. The third PMOS transistor P3 is turned off when the third switch control signal LCMNRSW is 1.00V. The fourth PMOS transistor P4 is turned off when the fourth switch control signal LCMNSW is 1.18V. The fifth PMOS transistor P5 is in a partial off state when the fifth switch control signal ARVDDSW is 1.00V. The first NMOS transistor N1 is turned off when the sixth switch control signal DIOSW is 0.00V.

[0067] The second NMOS transistor N2 is turned off when the seventh switch control signal ARVSSNOE is 0.00 V. The third NMOS transistor N3 is turned off when the eighth switch control signal LCMNARY is 0.00 V.

[0068] The back gate of the first PMOS transistor P1 is set to 1.18V. The back gate of the second PMOS transistor P2 is at the internal power supply potential CARVDD. The back gate of the fourth PMOS transistor P4 is at the internal power supply potential CARVDD. The internal power supply potential CARVDD is 1.18V. The back gate of the fifth PMOS transistor P5 is at the internal power supply potential CARVDD, and the internal power supply potential CARVDD (1.18V) is supplied to the memory cell with a weak power.

[0069] (6. Second Shutdown Mode Operation) Fig. 11 is a diagram for explaining the second shutdown mode operation of the SRAM 2. As shown in Fig. 11, each transistor is controlled. In the second shutdown mode operation, the first regulator 25 is in the on state (VDD=ON, 1.18V), and the switch control signal RSSW is in the on state (RSSW=1).

[0070] The first PMOS transistor P1 is in the OFF state when the first switch control signal LCMSW is 1.18V. The second PMOS transistor P2 is in the OFF state when the second switch control signal LCMRSW is 1.00V. The third PMOS transistor P3 is in the ON state when the third switch control signal LCMNRSW is 0.00V. The fourth PMOS transistor P4 is in the ON state when the fourth switch control signal LCMNSW is 0.00V. The fifth PMOS transistor P5 is in the OFF state when the fifth switch control signal ARVDDSW is 1.00V. The first NMOS transistor N1 is in the OFF state when the sixth switch control signal DIOSW is 0.00V. The second NMOS transistor N2 is in the OFF state when the seventh switch control signal ARVSSNOE is 0.00V. The third NMOS transistor N3 is in the OFF state when the eighth switch control signal LCMNARY is 0.00V.

[0071] The back gate of the first PMOS transistor P1 is set to 1.18V. The back gate of the second PMOS transistor P2 is at the internal power supply potential CARVDD. The back gate of the fourth PMOS transistor P4 is at the internal power supply potential CARVDD. The internal power supply potential CARVDD is 1.00V. The back gate of the fifth PMOS transistor P5 is at the internal power supply potential CARVDD, and the internal power supply potential CARVDD (1.00V) is not supplied to the memory cell.

[0072] (7. Third Shutdown Mode Operation) Fig. 12 is a diagram for explaining the third shutdown mode operation of the SRAM 2. As shown in Fig. 12, each transistor is controlled. In the third shutdown mode operation, the first regulator 25 is in the off state (VDD=OFF, 0.00V), and the switch control signal RSSW is in the on state (RSSW=1).

[0073] The first PMOS transistor P1 is in an OFF state when the first switch control signal LCMSW is 0.00V. The second PMOS transistor P2 is in an OFF state when the second switch control signal LCMRSW is 1.00V. The third PMOS transistor P3 is in an ON state when the third switch control signal LCMNRSW is 0.00V. The fourth PMOS transistor P4 is in an ON state when the fourth switch control signal LCMNSW is 0.00V. The fifth PMOS transistor P5 is in an OFF state when the fifth switch control signal ARVDDSW is 1.00V. The first NMOS transistor N1 is in an OFF state when the sixth switch control signal DIOSW is 0.00V. The second NMOS transistor N2 is in an OFF state when the seventh switch control signal ARVSSNOE is 0.00V. The third NMOS transistor N3 is in an OFF state when the eighth switch control signal LCMNARY is 0.00V.

[0074] The back gate of the first PMOS transistor P1 is set to 0.00V. The back gate of the second PMOS transistor P2 is at the internal power supply potential CARVDD. The back gate of the fourth PMOS transistor P4 is at the internal power supply potential CARVDD. The internal power supply potential CARVDD is 1.00V. The back gate of the fifth PMOS transistor P5 is at the internal power supply potential CARVDD, and the internal power supply potential CARVDD (1.00V) is not supplied to the memory cell.

[0075] (SRAM mode transition) Next, the mode transition of the SRAM 2 will be described below with reference to Figures 13 to 18. In Figures 13 to 18, the shutdown mode SMD, resume standby signal RS, switch control signal RSSW, and NMA signal are always set to a fixed value (=0V or VDDR (=1.00V)).

[0076] (1. Resume standby mode transition with VDD supplied (VDD=1.18V)) Fig. 13 is a diagram showing the resume standby mode transition in a VDD supply state (VDD=1.18V). As shown in Fig. 13, the first regulator 25 generates a first power supply potential (VDD) of 1.18V (VDD=1.18V), and the second regulator 26 generates a second power supply potential (VDDR) of 1.00V, which are constantly being supplied (VDDR=1.00V).

[0077] First, when transitioning SRAM2 from shutdown mode to resume standby mode, first, the shutdown mode signal SMD is transitioned from 1.00 V to 0.00 V, and then the resume standby signal RS is transitioned from 0.00 V to 1.00 V. Then, the switch control signal RSSW is transitioned from 0.00 V to 1.00 V. This transitions SRAM2 from shutdown mode to resume standby mode.

[0078] When SRAM2 is transitioned from resume standby mode to shutdown mode, the switch control signal RSSW is transitioned from 1.00 V to 0.00 V, and then the resume standby signal RS is transitioned from 1.00 V to 0.00 V. Then, the shutdown mode signal SMD is transitioned from 0.00 V to 1.00 V. This causes SRAM2 to transition from resume standby mode to shutdown mode.

[0079] For example, there is a time tssd_f between the fall of the shutdown mode signal SMD and the rise of the resume standby signal RS. For example, there is a time thrssw_r between the rise of the resume standby signal RS and the rise of the switch control signal RSSW. For example, there is a time thsrsw_f between the fall of the switch control signal RSSW and the fall of the resume standby signal RS. For example, there is a time thsrsw_f between the fall of the resume standby signal RS and the rise of the shutdown mode signal SMD.

[0080] (2.Shutdown mode transition with VDD supplied (VDD=1.18V)) Fig. 14 is a diagram showing the transition to the shutdown mode in the VDD supply state (VDD=1.18V). As shown in Fig. 14, the first regulator 25 generates a first power supply potential (VDD) of 1.18V (VDD=1.18V), and the second regulator 26 generates a second power supply potential (VDDR) of 1.00V, which are constantly being supplied (VDDR=1.00V).

[0081] When SRAM2 is to be transitioned to the shutdown mode, the shutdown mode signal SMD is transitioned from 0.00V0 to 1.00V.

[0082] To release the shutdown mode of SRAM2, with the shutdown mode signal SMD at 1.00 V, first the resume standby signal RS is made to transition from 0.00 V to 1.00 V, and then the switch control signal RSSW is made to transition from 0.00 V to 1.00 V. After that, the shutdown mode signal SMD is made to transition from 1.00V0 to 0.00 V, then the switch control signal RSSW is made to transition from 1.00 V to 0.00 V, and finally the resume standby signal RS is made to transition from 1.00 V to 0.00 V.

[0083] There is a time tssd between the rising edge of the shutdown mode signal SMD and the rising edge of the resume standby signal RS. There is a time thrssw between the rising edge of the resume standby signal RS and the rising edge of the switch control signal RSSW. There is a time thsd between the rising edge of the resume standby signal RS and the falling edge of the shutdown mode signal SMD. There is a time tsrssw between the falling edge of the switch control signal RSSW and the falling edge of the resume standby signal RS.

[0084] (3. Resume standby mode transition when VDD is not supplied (VDD=HiZ)) Fig. 15 is a diagram showing the resume standby mode transition in a state where VDD is not supplied (VDD=HiZ). Fig. 15 differs from Fig. 13 in that in Fig. 15, the output terminal (output potential) of the first regulator 25 goes from 1.18V to a high impedance (HiZ) state during the period when the switch control signal RSSW is 1.00V. Other configurations in Fig. 15 are the same as those in Fig. 13, so their explanation will be omitted.

[0085] The output terminal (output potential) of the first regulator 25 becomes a high impedance (HiZ) state after a time thvdd_f has elapsed since the switch control signal RSSW transitioned from 0.00 V to 1.00 V. When the output terminal (output potential) of the first regulator 25 transitions from the high impedance (HiZ) state to 1.18 V, the switch control signal RSSW falls from 1.00 V to 0.00 V after a time tsvdd_r has elapsed.

[0086] (4.Shutdown mode transition when VDD is not supplied (VDD=HiZ)) Fig. 16 is a diagram showing the shutdown mode transition when VDD is not supplied (VDD=HiZ). Fig. 16 differs from Fig. 14 in that in Fig. 16, the output terminal (output potential) of the first regulator 25 goes from 1.18V to a high impedance (HiZ) state during the period when the switch control signal RSSW is 1.00V. Other configurations in Fig. 16 are the same as those in Fig. 14, so their explanation will be omitted.

[0087] The output terminal (output potential) of the first regulator 25 becomes a high impedance (HiZ) state after a time thvdd_f has elapsed since the switch control signal RSSW transitioned from 0.00 V to 1.00 V. When the output terminal (output potential) of the first regulator 25 transitions from the high impedance (HiZ) state to 1.18 V, the switch control signal RSSW falls from 1.00 V to 0.00 V after a time tsvdd_r has elapsed.

[0088] (5. Resume standby mode transition when VDD=0V) Fig. 17 is a diagram showing the resume standby mode transition when VDD=0 V. Fig. 17 differs from Fig. 13 in that in Fig. 17, the output terminal (output potential) of first regulator 25 changes from 1.18 V to 0.00 V during the period when switch control signal RSSW is 1.00 V. Other configurations in Fig. 17 are the same as those in Fig. 13, so description thereof will be omitted.

[0089] After the time thvdd_f has elapsed since the resume standby signal RS transitioned from 1.00 V to 0.00 V, the output terminal (output potential) of the first regulator 25 becomes 0.00 V. When the output terminal (output potential) of the first regulator 25 transitions from the 0.00 V state to 1.18 V, the switch control signal RSSW falls after the time tsvdd_r has elapsed.

[0090] (6.Shutdown mode transition when VDD=0V) Fig. 18 is a diagram showing the shutdown mode transition when VDD=0 V. Fig. 18 differs from Fig. 14 in that in Fig. 18, the output terminal (output potential) of first regulator 25 changes from 1.18 V to 0.00 V during the period when switch control signal RSSW is 1.00 V. Other configurations in Fig. 18 are the same as those in Fig. 14, so description thereof will be omitted.

[0091] A time thvdd_f after the switch control signal RSSW transitions from 0.00 V to 1.00 V, the output terminal (output potential) of the first regulator 25 becomes 0.00 V. When the output terminal (output potential) of the first regulator 25 transitions from 0.00 V to 1.18 V, the switch control signal RSSW falls from 1.00 V to 0.00 V after a time tsvdd_r has elapsed.

[0092] In the first embodiment, the following configuration is adopted in a static random access memory (SRAM) having a power supply for memory cells (VDDR) and a power supply for peripheral circuits (VDD). A) The power supply to the memory cells MC (memory array 22) is switched between the power supply for peripheral circuits (VDD) and the power supply for memory cells (VDDR) by the resume standby signal RS (switched by the power supply switch circuit 21). B) During resume standby, control signals (RSSW, LCMSW, LCMRSW, LCMNRSW, LCMNSW) are provided to switch the power supply to the memory cells MC (memory array 22). C) When switching to resume standby mode and when returning from resume standby mode, the well potential of the N-type well (NW3) of the memory cell MC (memory array 22) changes dynamically.

[0093] As a result, in the first embodiment, the following effects can be obtained.

[0094] 1) The power supply level of the memory cells MC (memory array 22) is switched by the power supply switch circuit 21, so the leakage current can be reduced without deteriorating the write and read characteristics. During normal operation (Write / Read), the peripheral circuit power supply (VDD) is supplied to the memory cells MC, so the transistor characteristics of the memory cells MC do not deteriorate.

[0095] 2) Since the power supply level of the memory cells MC (memory array 22) is switched by the power supply switch circuit 21, there is no need to dynamically change the regulator's output voltage (dynamic potential control of the regulator is not required). Since the SRAM switches the power supply according to each mode, it is only necessary to connect regulators (25, 26) capable of generating constant levels of the power supply VDD for the peripheral circuits used during normal operation and the power supply VDDR for the memory cells used for data retention to each power supply.

[0096] 3) Since the power switch circuit 21 can be switched between the resume standby mode and the normal operation mode, there is no need to control the power supply for each SRAM individually. When multiple SRAMs are provided in a semiconductor device, each SRAM has its own resume standby signal RS, making it easy to control each SRAM separately.

[0097] 4) The power supply for memory cells (power supply for data retention) VDDR is supplied from the second regulator 26, so that the leakage current of the memory array (22) can be reduced with high accuracy.

[0098] 5) The power supply for memory cells (power supply for data retention) VDDR is supplied from the second regulator 26, so that the precision of the potential level is high, and the retention characteristics of the memory array (22) or memory cells (MC) can be stabilized.

[0099] 6) The data retention power regulator (second regulator 26) can be made smaller. Since the memory cell power supply VDDR only needs to have a potential level that can retain data, the power supply voltage can be set lower than in the normal mode. This reduces the current capacity required for the regulator 26.

[0100] 7) Even if the power supply VDD for peripheral circuits is turned off, data in the memory array 22 can be retained. By switching the power supply to the memory cells MC with the power switch circuit 21, data retention of the memory array 22 is possible with the retention power supply (VDDR). Since the switch control signal generation circuit unit 24 is constantly supplied with the second power supply potential (VDDR) of 1.00V from the second regulator (VDDR REG) 26, the switch control signal generation circuit (40, 50) formed in the switch control signal generation circuit unit 24 can constantly generate control signals for controlling the operation of the power switch circuit 21.

[0101] 8) Even when multiple SRAMs are provided in one semiconductor device (semiconductor chip), the N-type well is independent for each SRAM, so the potential of the N-type well NW3 of the memory cell MC can be dynamically changed for each SRAM by the resume standby signal RS. In other words, when laying out multiple SRAMs on the surface of a semiconductor chip, there is no need to consider well isolation for each SRAM, because the N-type well is independent for each SRAM. EXAMPLES

[0102] Fig. 19 is a diagram for explaining a configuration example of a power supply switch circuit according to Example 2. A power supply switch circuit 21A shown in Fig. 19 differs from the power supply switch circuit 21 in Fig. 2 in that in the power supply switch circuit 21A, the fourth PMOS transistor P4 is deleted and only the third PMOS transistor P3 is connected in series between the output terminal of the second regulator 26 and the source-drain path of the fifth PMOS transistor P5.

[0103] The configuration of the second embodiment can also provide the same effects as those of the first embodiment.

[0104] The invention made by the present inventor has been specifically described above based on examples. However, it goes without saying that the present invention is not limited to the above-mentioned embodiments and examples, and various modifications are possible. [Explanation of symbols]

[0105] 1: Semiconductor device 2: Static Random Access Memory (SRAM) 21: Power switch circuit 22: Memory array 25: First regulator 26: Second regulator VDD: First power supply potential (power supply for peripheral circuits) VDDR: 2nd power supply potential (holding power supply) NW1, NW2, NW3: N-type well P1, P2, P3, P4: first to fourth PMOS transistors

Claims

1. a first regulator that generates a first power supply potential; a second regulator that generates a second power supply potential lower than the first power supply potential; a static random access memory (SRAM) having a normal operation mode and a resume standby mode; The SRAM includes: a power supply switch circuit receiving the first power supply potential and the second power supply potential; a memory array including a plurality of memory cells; a power supply switch circuit controlled so that when the SRAM is in the normal operation mode, the first power supply potential is supplied from the power supply switch circuit to the memory array, and when the SRAM is in the resume standby mode, the second power supply potential is supplied from the power supply switch circuit to the memory array.

2. 2. The semiconductor device according to claim 1, the SRAM further includes a switch control signal generation circuit that generates a switch control signal to be supplied to the power supply switch circuit; a semiconductor device, wherein the switch control signal generation circuit supplies the switch control signal to the power switch circuit so that, when the SRAM is in the normal operation mode, the first power supply potential is supplied from the power switch circuit to the memory array, and, when the SRAM is in the resume standby mode, the second power supply potential is supplied from the power switch circuit to the memory array.

3. 2. The semiconductor device according to claim 1, Each of the plurality of memory cells includes an N-type well in which a P-channel type load MOS transistor is formed; A semiconductor device in which the potential of the N-type well is dynamically changed so that it is set to the first power supply potential when the SRAM is in the normal operation mode and is set to the second power supply potential when the SRAM is in the resume standby mode.

4. 2. The semiconductor device according to claim 1, the power switch circuit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, and a fourth PMOS transistor; the first PMOS transistor has a gate receiving a first switch control signal, a source-drain path connected to an output terminal of the first regulator, and a back gate connected to the output terminal of the first regulator; the second PMOS transistor has a gate receiving a second switch control signal, a source-drain path connected in series with the source-drain path of the first PMOS transistor and connected to an internal power supply potential of the memory array, and a back gate connected to the internal power supply potential of the memory array; the third PMOS transistor has a gate receiving a third switch control signal, a source-drain path connected to an output terminal of the second regulator, and a back gate connected to the output terminal of the second regulator; the fourth PMOS transistor has a gate receiving a fourth switch control signal, a source-drain path connected in series to the source-drain path of the third PMOS transistor and connected to the internal power supply potential of the memory array, and a back gate connected to the internal power supply potential of the memory array.

5. 5. The semiconductor device according to claim 4, the SRAM further includes a switch control signal generation circuit that generates the first to fourth switch control signals to be supplied to the power supply switch circuit based on a resume standby signal and a switch control signal; the switch control signal generating circuit is adapted to receive the first power supply potential and the second power supply potential; the first switch control signal and the fourth switch control signal are set to a signal level of the first power supply potential or a ground potential; the second switch control signal and the third switch control signal are set to a signal level of the second power supply potential or the ground potential.

6. 2. The semiconductor device according to claim 1, the power switch circuit includes a first PMOS transistor, a second PMOS transistor, and a third PMOS transistor; the first PMOS transistor has a gate receiving a first switch control signal, a source-drain path connected to an output terminal of the first regulator, and a back gate connected to the output terminal of the first regulator; the second PMOS transistor has a gate receiving a second switch control signal, a source-drain path connected in series with the source-drain path of the first PMOS transistor and connected to an internal power supply potential of the memory array, and a back gate connected to the internal power supply potential of the memory array; the third PMOS transistor has a gate receiving a third switch control signal, a source-drain path connected to an output terminal of the second regulator and to the internal power supply potential of the memory array, and a back gate connected to the output terminal of the second regulator.

7. 7. The semiconductor device according to claim 6, the SRAM further includes a switch control signal generation circuit that generates the first to third switch control signals to be supplied to the power switch circuit based on a resume standby signal and a switch control signal; the switch control signal generating circuit is adapted to receive the first power supply potential and the second power supply potential; the first switch control signal is set to a signal level of the first power supply potential or a ground potential; the second switch control signal and the third switch control signal are set to a signal level of the second power supply potential or the ground potential.

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