Imaging device

Abstract

To provide an imaging apparatus capable of further improving a dynamic range and further reducing noises.SOLUTION: An imaging apparatus is structured by laminating a first substrate, a second substrate, and a third substrate in this order. The first substrate includes a plurality of sensor pixels. The second substrate includes a plurality of reading circuits that output a pixel signal based on an electric charge output from a sensor pixel. The third substrate includes a control circuit that controls each sensor pixel and a reading circuit. A lamination body formed by the first and second substrates includes a plurality of junction electrodes in a region opposite to the plurality of sensor pixels. The sensor pixel and the reading circuit are electrically connected to each other by jointing junction electrodes.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to an imaging device. [Background technology]

[0002] Conventionally, miniaturization of the area per pixel of a two-dimensional imaging device has been achieved by introducing a microprocess and improving the mounting density. In recent years, imaging devices with a three-dimensional structure have been developed to further miniaturize imaging devices. In an imaging device with a three-dimensional structure, as described in Patent Documents 1 to 3, for example, a photodiode, a circuit (readout circuit) that reads out the charge obtained by the photodiode, a circuit (control circuit) that controls the reading out of the charge from the photodiode, and the like are formed on two stacked semiconductor substrates. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2014-22561 A [Patent Document 2] JP 2010-219339 A [Patent Document 3] JP 2017-117828 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, in a three-dimensional imaging device, it is desired to further improve the dynamic range and further reduce noise. Therefore, it is desirable to provide an imaging device that enables a further improvement in the dynamic range and a further reduction in noise. [Means for solving the problem]

[0005] An imaging device according to a first aspect of the present disclosure is configured by stacking a first substrate, a second substrate, and a third substrate in this order. The first substrate has a pixel region including a plurality of sensor pixels that perform photoelectric conversion. The second substrate has a plurality of readout circuits, one for each of one or a plurality of sensor pixels, that output pixel signals based on electric charges output from the sensor pixels. The third substrate has a control circuit that controls the sensor pixels and the readout circuits. The stacked body consisting of the first substrate and the second substrate has an interlayer insulating film and a plurality of junction electrodes that are provided in the interlayer insulating film and in a region facing the pixel region. The sensor pixels and the readout circuits are electrically connected to each other by junctions between the junction electrodes. Each readout circuit has a negative feedback circuit including an operational amplifier, and the reference potential of the first substrate is lower than the reference potential of the second substrate. .

[0006] In the imaging device according to the first aspect of the present disclosure, a plurality of sensor pixels are formed on a first substrate, a plurality of readout circuits are formed on a second substrate, and a control circuit is formed on a third substrate. This allows each sensor pixel to be sufficiently large, so that a reproduced image with a wide dynamic range can be obtained. In addition, the size of the readout circuit can be made sufficiently large, so that dark noise such as RTS (Random Telegraph Signal) noise is not increased. In addition, in the imaging device according to an embodiment of the present disclosure, the sensor pixel and the readout circuit are electrically connected to each other by bonding between bonding electrodes provided in an area facing the pixel area. This allows the unit pixel size to be reduced compared to when the sensor pixel and the readout circuit are electrically connected within one pixel of a common substrate. [Brief description of the drawings]

[0007] [Figure 1] 1 is a diagram illustrating an example of an exploded perspective configuration of an imaging device according to an embodiment of the present disclosure. [Diagram 2] 2 is a diagram illustrating an example of functional blocks of the logic circuit of FIG. 1. [Diagram 3] 2 is a diagram illustrating an example of a sensor pixel and a readout circuit of FIG. [Figure 4] 2 is a diagram illustrating an example of a cross-sectional configuration of the imaging device in FIG. 1 in the vertical direction. [Diagram 5] 2 is a diagram illustrating an example of a cross-sectional configuration of the imaging device in FIG. 1 in the horizontal direction. [Figure 6A] 5 is a diagram illustrating an example of a cross-sectional configuration in the vicinity of the through-hole wiring in FIG. 4. [Figure 6B] 5 is a diagram illustrating an example of a cross-sectional configuration in the vicinity of the through-hole wiring in FIG. 4. [Figure 6C] 5 is a diagram illustrating an example of a cross-sectional configuration in the vicinity of the through-hole wiring in FIG. 4. [Figure 7A] 5 is a diagram illustrating an example of a cross-sectional configuration in the vicinity of the through-hole wiring in FIG. 4. [Figure 7B] 5 is a diagram illustrating an example of a cross-sectional configuration in the vicinity of the through-hole wiring in FIG. 4. [Figure 7C] 5 is a diagram illustrating an example of a cross-sectional configuration in the vicinity of the through-hole wiring in FIG. 4. [Figure 8] 2 is a diagram illustrating a modification of the horizontal cross-sectional configuration of the imaging device in FIG. 1. [Figure 9] 2 is a diagram illustrating a modified example of the sensor pixel and the readout circuit of FIG. 1. [Figure 10] 2 is a diagram illustrating a modification of the horizontal cross-sectional configuration of the imaging device in FIG. 1. [Figure 11] 2 is a diagram illustrating a modified example of the vertical cross-sectional configuration of the imaging device in FIG. [Figure 12] 2 is a diagram illustrating a modified example of the vertical cross-sectional configuration of the imaging device in FIG. [Figure 13] 2 is a diagram illustrating a modified example of the vertical cross-sectional configuration of the imaging device in FIG. [Figure 14] 2 is a diagram illustrating a modified example of the vertical cross-sectional configuration of the imaging device in FIG. [Figure 15] 2 is a diagram illustrating a modified example of the vertical cross-sectional configuration of the imaging device in FIG. [Figure 16] 2 is a diagram illustrating a modified example of the sensor pixel and the readout circuit of FIG. 1. [Figure 17] FIG. 2 is a diagram illustrating a modified example of the readout circuit of FIG. [Figure 18] 2 is a diagram illustrating a modified example of the sensor pixel and the readout circuit of FIG. 1. [Figure 19]1. FIG. 4 is a diagram illustrating a modified example of the developed perspective configuration of the imaging device in FIG. [Figure 20] 2 is a diagram illustrating an example of a cross-sectional configuration of a transistor in a first substrate in FIG. 1. [Figure 21] 2 is a diagram illustrating an example of a cross-sectional configuration of a transistor in a second substrate in FIG. 1. [Figure 22] FIG. 2 illustrates a modified example of the sensor pixel in FIG. 1 in which the sensor pixel is shared by a readout circuit. [Diagram 23] FIG. 2 illustrates a modified example of the sensor pixel in FIG. 1 in which the sensor pixel is shared by a readout circuit. [Figure 24] 1. FIG. 4 is a diagram illustrating a modified example of the developed perspective configuration of the imaging device in FIG. [Diagram 25] FIG. 20 is a diagram illustrating a modified example of the developed perspective configuration of the imaging device in FIG. 19. [Figure 26] 2 is a diagram illustrating a modified example of the circuit configuration of the imaging device in FIG. [Figure 27] 2 is a diagram illustrating a modified example of the vertical cross-sectional configuration of the imaging device in FIG. [Figure 28] 28 is a diagram illustrating an example of a horizontal cross-sectional configuration of an imaging device having the cross-sectional configuration of FIG. 27. [Figure 29] 28 is a diagram illustrating an example of a sensor pixel and a readout circuit of an imaging device having the cross-sectional configuration of FIG. 27. [Figure 30A] 28A to 28C are schematic vertical cross-sectional views illustrating an example of a manufacturing method for the wiring structure of FIG. 27. [Figure 30B] FIG. 30B is a schematic cross-sectional view showing a step subsequent to FIG. 30A. [Figure 30C] FIG. 30C is a schematic cross-sectional view showing a step following FIG. 30B. [Figure 30D] FIG. 30D is a schematic cross-sectional view showing a step subsequent to FIG. 30C. [Figure 30E] FIG. 30B is a schematic cross-sectional view showing the step following FIG. 30D. [Figure 30F] FIG. 30C is a schematic cross-sectional view showing a step following FIG. 30E. [Figure 30G] FIG. 30C is a schematic cross-sectional view showing the step following FIG. 30F. [Figure 30H] FIG. 30C is a schematic cross-sectional view showing the step following FIG. 30G. [Figure 30I] FIG. 30C is a schematic cross-sectional view showing the step following FIG. 30H. [Diagram 31] 28 is a diagram illustrating a modified example of the bonding surface of the imaging device in FIG. 27 and the wiring structure in the vicinity thereof. [Diagram 32] 1 is a diagram illustrating a cross-sectional configuration in the vertical direction of a bonding surface of an imaging device serving as Comparative Example 1 and a wiring structure in the vicinity of the bonding surface. [Diagram 33] 13 is a diagram illustrating a cross-sectional configuration in the vertical direction of a bonding surface of an imaging device serving as Comparative Example 2 and a wiring structure in the vicinity of the bonding surface. FIG. [Diagram 34] 28 is a schematic cross-sectional view illustrating misalignment in the imaging device of FIG. 27. [Diagram 35] 31 is a schematic cross-sectional view illustrating misalignment in the imaging device of FIG. 30. [Diagram 36] 2 is a diagram illustrating a modified example of the vertical cross-sectional configuration of the imaging device in FIG. [Figure 37] 2 is a diagram illustrating a modified example of the vertical cross-sectional configuration of the imaging device in FIG. [Figure 38] 2 is a diagram illustrating a modified example of the vertical cross-sectional configuration of the imaging device in FIG. [Figure 39] 2 is a diagram illustrating a modified example of the vertical cross-sectional configuration of the imaging device in FIG. [Diagram 40] 2 is a diagram illustrating a modified example of the vertical cross-sectional configuration of the imaging device in FIG. [Diagram 41] 28 is a diagram illustrating a modified example of a sensor pixel and a readout circuit of an imaging device having the cross-sectional configuration of FIG. 27. [Diagram 42] 28 is a diagram illustrating a modified example of a sensor pixel and a readout circuit of an imaging device having the cross-sectional configuration of FIG. 27. [Diagram 43] 28 is a diagram illustrating an example of a sensor pixel and a readout circuit when the wiring structure of FIG. 27 is applied to another position. [Diagram 44] 28 is a diagram illustrating a modification of the horizontal cross-sectional configuration of the imaging device having the cross-sectional configuration of FIG. 27. [Diagram 45] 28 is a diagram illustrating a modification of the horizontal cross-sectional configuration of the imaging device having the cross-sectional configuration of FIG. 27. [Diagram 46] 28 is a diagram illustrating a modification of the horizontal cross-sectional configuration of the imaging device having the cross-sectional configuration of FIG. 27. [Figure 47] 28 is a diagram illustrating a modification of the horizontal cross-sectional configuration of the imaging device having the cross-sectional configuration of FIG. 27. [Figure 48] 28 is a diagram illustrating a modification of the horizontal cross-sectional configuration of the imaging device having the cross-sectional configuration of FIG. 27. [Figure 49] 28 is a diagram illustrating a modification of the horizontal cross-sectional configuration of the imaging device having the cross-sectional configuration of FIG. 27. [Figure 50] 28 is a diagram illustrating a modification of the horizontal cross-sectional configuration of the imaging device having the cross-sectional configuration of FIG. 27. [Figure 51] FIG. 1 is a diagram illustrating an example of a schematic configuration of an imaging system including an imaging device according to the above embodiment and its modified example. [Figure 52] 52 is a diagram showing an example of an imaging procedure in the imaging system of FIG. 51. [Figure 53] 1 is a block diagram showing an example of a schematic configuration of a vehicle control system; [Figure 54] 4 is an explanatory diagram showing an example of the installation positions of an outside-vehicle information detection unit and an imaging unit; FIG. [Figure 55] 1 is a diagram illustrating an example of a schematic configuration of an endoscopic surgery system. [Figure 56] 2 is a block diagram showing an example of a functional configuration of a camera head and a CCU. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The description will be made in the following order. 1. Embodiment (imaging device)...FIGS. 1 to 7 2. Modifications (imaging device)...Figs. 8 to 50 3. Application Examples The imaging device according to the above embodiment and its modified example Example of application to an imaging system: Figures 51 and 52 4. Application Examples Application Example 1: The imaging device according to the above embodiment and its modified example Application to moving objects: Figure 53, Figure 54 Application Example 2: The imaging device according to the above embodiment and its modified example Example of application to a surgical system: Figure 55, Figure 56

[0009] <1. Preferred embodiment> [composition] 1 illustrates an example of a schematic configuration of an imaging device 1 according to an embodiment of the present disclosure. The imaging device 1 includes three substrates (a first substrate 10, a second substrate 20, and a third substrate 30). The imaging device 1 is an imaging device with a three-dimensional structure configured by bonding together the three substrates (the first substrate 10, the second substrate 20, and the third substrate 30). The first substrate 10, the second substrate 20, and the third substrate 30 are stacked in this order.

[0010] The first substrate 10 has a plurality of sensor pixels 12 that perform photoelectric conversion on a semiconductor substrate 11. The plurality of sensor pixels 12 are arranged in a matrix in a pixel region 13 of the first substrate 10. The first substrate 10 has a plurality of drive wirings 14 that extend, for example, in the row direction. The plurality of drive wirings 14 are electrically connected to a vertical drive circuit 32a (described later).

[0011] The second substrate 20 has a semiconductor substrate 21 provided with a readout circuit 22 for each of one or more sensor pixels 12, the readout circuit 22 outputting a pixel signal based on the charge output from the sensor pixel 12. The readout circuits 22 are arranged in a matrix in a readout circuit region 23 in the second substrate 20. The second substrate 20 has, for example, a plurality of drive wirings extending in the row direction and a plurality of vertical signal lines VSL (described later) extending in the column direction. The drive wirings provided on the second substrate 20 are electrically connected to a vertical drive circuit 32a described later. The vertical signal lines VSL are electrically connected to a column signal processing circuit 32b described later.

[0012] The third substrate 30 has a logic circuit 32 and a boost circuit 33 on a semiconductor substrate 31. The logic circuit 32 controls each sensor pixel 12 and each readout circuit 22, and processes pixel signals obtained from each readout circuit 22. The logic circuit 32 has, for example, a vertical drive circuit 32a, a column signal processing circuit 32b, a horizontal drive circuit 32c, and a system control circuit 32d, as shown in Fig. 2. The logic circuit 32 outputs an output voltage Vout obtained for each sensor pixel 12 to the outside.

[0013] The vertical drive circuit 32a, for example, sequentially selects the multiple sensor pixels 12 on a row-by-row basis. The vertical drive circuit 32a is, for example, electrically connected to the multiple drive wirings 14, and sequentially outputs selection signals to the multiple drive wirings 14 to sequentially select the multiple sensor pixels 12 on a row-by-row basis.

[0014] The column signal processing circuit 32b performs, for example, correlated double sampling (CDS) processing on pixel signals output from each sensor pixel 12 in a row selected by the vertical drive circuit 32a. The column signal processing circuit 32b extracts a signal level of the pixel signal by performing, for example, CDS processing, and holds pixel data according to the amount of light received by each sensor pixel 12. The column signal processing circuit 32b is, for example, electrically connected to a plurality of vertical signal lines VSL described below, and acquires pixel signals from each sensor pixel 12 in a row selected by the vertical drive circuit 32a via the plurality of vertical signal lines VSL. The column signal processing circuit 32b has, for example, an ADC (analog-to-digital) for each vertical signal line VSL, Analog pixel signals acquired via multiple vertical signal lines VSL are converted into digital pixel signals.

[0015] The horizontal drive circuit 32c, for example, sequentially outputs the pixel data held in the column signal processing circuit 32b to the outside as an output voltage Vout. The system control circuit 32d, for example, controls the driving of each block (the vertical drive circuit 32a, the column signal processing circuit 32b, and the horizontal drive circuit 32c) in the logic circuit 32. The boost circuit 33, for example, generates a power supply potential VDD of a predetermined magnitude.

[0016] Fig. 3 shows an example of the sensor pixels 12 and the readout circuit 22. Below, a case will be described in which four sensor pixels 12 share one readout circuit 22 as shown in Fig. 3. Here, "shared" refers to the outputs of the multiple sensor pixels 12 being input to a common readout circuit 22.

[0017] The sensor pixels 12 have components in common with each other. In Fig. 3, in order to distinguish the components of each sensor pixel 12 from one another, identification numbers (1, 2, 3, 4) are added to the end of the reference numerals of the components of each sensor pixel 12. In the following, when it is necessary to distinguish the components of each sensor pixel 12 from one another, an identification number is added to the end of the reference numerals of the components of each sensor pixel 12, but when it is not necessary to distinguish the components of each sensor pixel 12 from one another, the identification number at the end of the reference numerals of the components of each sensor pixel 12 is omitted.

[0018] Each sensor pixel 12 has, for example, a photodiode PD, a transfer transistor TR electrically connected to the photodiode PD, and a floating diffusion FD that temporarily holds the charge output from the photodiode PD via the transfer transistor TR. For example, one floating diffusion FD is provided for a plurality of sensor pixels 12 that share the readout circuit 22. Note that one floating diffusion FD may be provided for one sensor pixel 12. In this case, wiring is provided to electrically connect the floating diffusions FD to each other in the plurality of sensor pixels 12 that share the readout circuit 22.

[0019] The photodiode PD performs photoelectric conversion to generate charges according to the amount of received light. The cathode of the photodiode PD is electrically connected to the source of the transfer transistor TR, and the anode of the photodiode PD is electrically connected to a region (a p-well region 41 described later) in the semiconductor substrate 11 that serves as a reference potential VSS. The drain of the transfer transistor TR is electrically connected to the floating diffusion FD, and the gate of the transfer transistor TR is electrically connected to the logic circuit 32 via the drive wiring 14 and a through wiring 42 described later. The transfer transistor TR is, for example, a CMOS (Complementary Metal Oxide Semiconductor) transistor.

[0020] The floating diffusion FD is a floating diffusion region that temporarily holds the charge output from the photodiode PD via the transfer transistor TR. The input terminal of the readout circuit 22 is connected to the floating diffusion FD. Specifically, the floating diffusion FD is connected to a reset transistor RST described later, and is connected to a vertical signal line VSL via an amplification transistor AMP described later and a selection transistor SEL described later. A capacitance Cfd is generated in the floating diffusion FD. For example, as shown in FIG. 3, the capacitance Cfd is generated between the wiring that connects each sensor pixel 12 and the FD junction electrode 17 and a region (e.g., the p-well region 41) that serves as the reference potential VSS in the first substrate 10.

[0021] The read circuit 22 includes, for example, a reset transistor RST, a selection transistor SEL, and an amplification transistor AMP. The selection transistor SEL may be omitted as necessary. The source of the reset transistor RST (the input terminal of the read circuit 22) is electrically connected to the floating diffusion FD, and the drain of the reset transistor RST is electrically connected to a wiring to which a power supply potential VDD is applied and to the drain of the amplification transistor AMP via a through-wire 43 described later. The gate of the reset transistor RST is electrically connected to the logic circuit 32 via the through-wire 42. The source of the amplification transistor AMP is electrically connected to the drain of the selection transistor SEL, and the gate of the amplification transistor AMP is electrically connected to the source of the reset transistor RST. The source of the selection transistor SEL (the output terminal of the read circuit 22) is electrically connected to the logic circuit 32 via the vertical signal line VSL and the through-wire 42, and the gate of the selection transistor SEL is electrically connected to the logic circuit 32 via the through-wire 42.

[0022] When the transfer transistor TR is turned on, the transfer transistor TR transfers the charge of the photodiode PD to the floating diffusion FD. The reset transistor RST resets the potential of the floating diffusion FD to a predetermined potential. When the reset transistor RST is turned on, the potential of the floating diffusion FD is reset to the power supply potential VDD. The selection transistor SEL controls the output timing of the pixel signal from the readout circuit 22. The amplification transistor AMP generates a signal having a voltage corresponding to the level of the charge held in the floating diffusion FD as the pixel signal. The amplification transistor AMP constitutes a source follower type amplifier and outputs a pixel signal having a voltage corresponding to the level of the charge generated in the photodiode PD. When the selection transistor SEL is turned on, the amplification transistor AMP amplifies the potential of the floating diffusion FD and outputs a voltage corresponding to the potential to the logic circuit 32 via the vertical signal line VSL. The reset transistor RST, the amplification transistor AMP, and the selection transistor SEL are, for example, CMOS transistors.

[0023] The selection transistor SEL may be provided between the power supply line VDD and the amplification transistor AMP. In this case, the drain of the reset transistor RST is electrically connected to a line to which the power supply potential VDD is applied and the drain of the selection transistor SEL. The source of the selection transistor SEL is electrically connected to the drain of the amplification transistor AMP, and the gate of the selection transistor SEL is electrically connected to the logic circuit 32 via the through-wire 42. The source of the amplification transistor AMP (the output end of the readout circuit 22) is electrically connected to the logic circuit 32 via the vertical signal line VSL and the through-wire 42, and the gate of the amplification transistor AMP is electrically connected to the source of the reset transistor RST.

[0024] FIG. 4 shows an example of a vertical cross-sectional configuration of the imaging device 1. FIG. 4 illustrates the cross-sectional configuration of a portion of the imaging device 1 facing the pixel region 13 (sensor pixel 12) and the cross-sectional configuration of a region around the pixel region 13. The imaging device 1 is configured by laminating a first substrate 10, a second substrate 20, and a third substrate 30 in this order, and further includes a color filter layer 40 and a light receiving lens 50 on the back surface side (light incident surface side) of the first substrate 10. The color filter layer 40 and the light receiving lens 50 are each provided, for example, one for each sensor pixel 12. That is, the imaging device 1 is a back-illuminated imaging device.

[0025] The first substrate 10 is configured by laminating an insulating film 19 on a semiconductor substrate 11. The first substrate 10 has the insulating film 19 as an interlayer insulating film. The insulating film 19 is provided between the semiconductor substrate 11 and the second substrate 20. The first substrate 10 has a plurality of drive wirings 14 in the insulating film 19. The plurality of drive wirings 14 are provided for each row of the plurality of sensor pixels 12 arranged in a matrix. The semiconductor substrate 11 is configured of a silicon substrate. The semiconductor substrate 11 has, for example, a p-well region 41 in a part of the surface and in its vicinity, and has a photodiode PD of a different conductivity type from the p-well region 41 in the other region (region deeper than the p-well region 41). The p-well region 41 is configured of a p-type semiconductor region. The photodiode PD is configured of a semiconductor region of a different conductivity type (specifically, n-type) from the p-well region 41. The semiconductor substrate 11 has a floating diffusion FD in the p-well region 41 as a semiconductor region of a different conductivity type (specifically, n-type) from the p-well region 41.

[0026] The first substrate 10 has a photodiode PD, a transfer transistor TR, and a floating diffusion FD for each sensor pixel 12. The first substrate 10 is configured such that the transfer transistor TR and the floating diffusion FD are provided on the front surface side (the side opposite to the light incident surface side, the second substrate 20 side) of the semiconductor substrate 11. The first substrate 10 has an element isolation portion that isolates each sensor pixel 12. The element isolation portion is formed extending in the normal direction (direction perpendicular to the front surface of the semiconductor substrate 11) of the semiconductor substrate 11. The element isolation portion is provided between two sensor pixels 12 adjacent to each other. The element isolation portion electrically isolates the sensor pixels 12 adjacent to each other. The element isolation portion is made of, for example, silicon oxide. The first substrate 10 further has, for example, a fixed charge film in contact with the rear surface of the semiconductor substrate 11. The fixed charge film is negatively charged in order to suppress the generation of dark current caused by the interface state on the light receiving surface side of the semiconductor substrate 11. The fixed charge film is formed, for example, by an insulating film having a negative fixed charge. Examples of materials for such an insulating film include hafnium oxide, zirconium oxide, aluminum oxide, titanium oxide, and tantalum oxide. A hole accumulation layer is formed at the interface on the light receiving surface side of the semiconductor substrate 11 by an electric field induced by the fixed charge film. This hole accumulation layer suppresses the generation of electrons from the interface. The color filter layer 40 is provided on the back side of the semiconductor substrate 11. The color filter layer 40 is provided, for example, in contact with the fixed charge film, and is provided at a position facing the sensor pixel 12 via the fixed charge film. The light receiving lens 50 is provided, for example, in contact with the color filter layer 40, and is provided at a position facing the sensor pixel 12 via the color filter layer 40 and the fixed charge film.

[0027] The first substrate 10 has a plurality of FD through wirings 15 and a plurality of VSS through wirings 16 in the insulating film 19. The plurality of FD through wirings 15 and the plurality of VSS through wirings penetrate the insulating film 19. The FD through wirings 15 correspond to a specific example of the "third through wiring" in the present disclosure. The VSS through wirings 16 correspond to a specific example of the "second through wiring" in the present disclosure. Each VSS through wiring 16 is disposed in a gap between two adjacent FD through wirings 15 in the plurality of FD through wirings 15. The first substrate 10 further has a plurality of FD junction electrodes 17 and one VSS junction electrode 18 in the insulating film 19. Both the plurality of FD junction electrodes 17 and one VSS junction electrode 18 are exposed on the surface of the insulating film 19. The FD junction electrode 17 corresponds to a specific example of the "first junction electrode" in the present disclosure. The VSS junction electrode 18 corresponds to a specific example of the "wiring electrode" in the present disclosure. The multiple FD through wirings 15 and the multiple VSS through wirings 16 are provided in a region facing the pixel region 13. Each VSS junction electrode 18 is formed in the same plane as each FD junction electrode 17. The VSS junction electrode 18 is disposed in a gap between two adjacent FD junction electrodes 17 among the multiple FD junction electrodes 17.

[0028] When one floating diffusion FD is provided for multiple sensor pixels 12 that share the readout circuit 22, multiple FD through wirings 15 are provided for each of the multiple sensor pixels 12 that share the readout circuit 22. When one floating diffusion FD is provided for each sensor pixel 12, multiple FD through wirings 15 are provided for each sensor pixel 12.

[0029] Each FD through wiring 15 is connected to a floating diffusion FD and an FD junction electrode 17. When one floating diffusion FD is provided for a plurality of sensor pixels 12 sharing a readout circuit 22, a plurality of VSS through wirings 16 are provided for each of the plurality of sensor pixels 12 sharing the readout circuit 22. When one floating diffusion FD is provided for a single sensor pixel 12, a plurality of VSS through wirings 16 are provided for each of the sensor pixels 12. Each VSS through wiring 16 is connected to a p-well region 41 and a VSS junction electrode 18. In either case, a plurality of VSS through wirings 16 are provided for each of the readout circuits 22.

[0030] The second substrate 20 is configured by laminating an insulating layer 28 on a semiconductor substrate 21. The second substrate 20 has the insulating layer 28 as an interlayer insulating film. The insulating layer 28 is provided between the semiconductor substrate 21 and the first substrate 10. The semiconductor substrate 21 is configured of a silicon substrate. The second substrate 20 has one readout circuit 22 for every four sensor pixels 12. The second substrate 20 is configured such that the readout circuit 22 is provided on a portion on the front surface side (the third substrate 30 side) of the semiconductor substrate 21. The second substrate 20 is bonded to the first substrate 10 with the front surface of the semiconductor substrate 21 facing the front surface side of the semiconductor substrate 11.

[0031] The second substrate 20 has a plurality of FD through wirings 26 and a plurality of VSS through wirings 27 in the insulating layer 28. The plurality of FD through wirings 26 and the plurality of VSS through wirings 27 penetrate the insulating layer 28. The FD through wirings 26 correspond to a specific example of the "third through wiring" in the present disclosure. The VSS through wirings 27 correspond to a specific example of the "second through wiring" in the present disclosure. Each VSS through wiring 27 is disposed in a gap between two adjacent FD through wirings 26 in the plurality of FD through wirings 26. The second substrate 20 further has a plurality of FD junction electrodes 24 and one VSS junction electrode 25 in the insulating layer 28. The plurality of FD junction electrodes 24 and one VSS junction electrode 25 are both exposed on the surface of the insulating layer 28. The FD junction electrode 24 corresponds to a specific example of the "first junction electrode" in the present disclosure. The VSS junction electrode 25 corresponds to a specific example of the "wiring electrode" in the present disclosure. The multiple FD junction electrodes 24 are provided for each FD junction electrode 17 of the first substrate 10. The FD junction electrode 24 is electrically connected to the FD junction electrode 17. The FD junction electrode 24 and the FD junction electrode 17 are formed of, for example, copper and are joined to each other. The VSS junction electrode 25 is electrically connected to the VSS junction electrode 18 of the first substrate 10. The VSS junction electrode 25 and the VSS junction electrode 18 are formed of, for example, copper and are joined to each other. Each VSS junction electrode 25 is formed, for example, in the same plane as each FD junction electrode 24. The VSS junction electrode 25 is disposed in a gap between two FD junction electrodes 24 adjacent to each other in the multiple FD junction electrodes 24. The sensor pixel 12 and the readout circuit 22 are electrically connected to each other by joining the FD junction electrodes 17 and 24 to each other.

[0032] Each of the FD junction electrodes 17 and 24 is disposed at a position facing the floating diffusion FD, for example, as shown in FIG. 5. FIG. 5 shows a cross-sectional configuration example of the FD junction electrode 17 and the VSS junction electrode 18, or a cross-sectional configuration example of the FD junction electrode 24 and the VSS junction electrode 25. When the floating diffusion FD is shared by four sensor pixels 12, the floating diffusion FD is provided in the center of the area consisting of the four sensor pixels 12. Therefore, when the floating diffusion FD is shared by four sensor pixels 12, each of the FD junction electrodes 17 and 24 is disposed at a position facing the center of the area consisting of the four sensor pixels 12. Each of the FD junction electrodes 17 and 24 is, for example, rectangular.

[0033] The VSS junction electrodes 18, 25 are formed in a lattice shape so as to surround each of the FD junction electrodes 17, 24 in the in-plane direction of the stacking as shown in FIG. 5. The VSS junction electrodes 18, 25 have openings at each location facing four sensor pixels 12 when viewed from the stacking direction of the imaging device 1. The VSS junction electrode 18 has a lattice shape formed in the same plane so that a plurality of junction wires extending in a first arrangement direction (for example, row direction) and a plurality of junction wires extending in a second arrangement direction (for example, column direction) cross each other (orthogonal to each other). Similarly, the VSS junction electrode 25 has a lattice shape formed in the same plane so that a plurality of junction wires extending in a first arrangement direction (for example, row direction) and a plurality of junction wires extending in a second arrangement direction (for example, column direction) cross each other (orthogonal to each other). Here, the first arrangement direction is one arrangement direction (for example, row direction) of a plurality of floating diffusions FDs (or a plurality of sensor pixels 12). The second arrangement direction is the other arrangement direction (for example, the column direction) of the plurality of floating diffusions FD (or the plurality of sensor pixels 12).

[0034] The FD junction electrodes 24 and the FD through wirings 26 are provided in a region facing the pixel region 13. The FD through wirings 26 are provided for each FD through wiring 15. Each FD through wiring 26 is connected to the FD junction electrode 24 and the readout circuit 22 (specifically, the gate of the amplification transistor AMP). The VSS junction electrodes 25 and the VSS through wirings 27 are provided in a region facing the pixel region 13. Each VSS through wiring 27 is provided for each VSS through wiring 16. Each VSS through wiring 27 is connected to the VSS junction electrode 25 and a region to which the reference potential VSS is applied in the second substrate 20 (reference potential region of the readout circuit 22).

[0035] The laminated body consisting of the first substrate 10 and the second substrate 20 has a plurality of through-wires 42 penetrating the first substrate 10 and the second substrate 20 in the region around the pixel region 13. The through-wires 42 correspond to a specific example of the "first through-wire" of the present disclosure. The plurality of through-wires 42 are provided for each of the drive wires 14 of the first substrate 10. Each through-wire 42 is connected to the drive wire 14 and the vertical drive circuit 32a of the logic circuit 32. Therefore, the logic circuit 32 controls the sensor pixels 12 and the readout circuit 22 via the plurality of through-wires 42. Each through-wire 42 is, for example, configured by a TSV (Through Silicon Via). Instead of each through wire 42, a through wire (hereinafter referred to as "through wire a") that penetrates the insulating film 19, a through wire (hereinafter referred to as "through wire b") that penetrates the insulating layer 28, a bonding electrode (hereinafter referred to as "bonding electrode c") connected to the through wire a, and a bonding electrode (hereinafter referred to as "bonding electrode d") connected to the through wire b may be provided. In this case, the bonding electrodes c and d are made of, for example, copper, and the bonding electrodes c and d are bonded to each other.

[0036] The laminated body made up of the first substrate 10 and the second substrate 20 further has through-wires 43 and 44 penetrating the first substrate 10 and the second substrate 20 around the pixel region 13. The through-wires 43 and 44 are, for example, configured by TSV. The through-wire 43 is connected to the boost circuit 33 of the third substrate 30 and is at a power supply potential VDD. The power supply potential VDD is, for example, a value within a range of 2.5V to 2.8V. The through-wire 44 is electrically connected to a region in the third substrate 30 to which a reference potential VSS is applied (a reference potential region of the third substrate 30) and is at the reference potential VSS. The reference potential VSS is, for example, zero volts.

[0037] The third substrate 30 is configured, for example, by laminating an insulating layer 36 on a semiconductor substrate 31. The third substrate 30 has the insulating layer 36 as an interlayer insulating film. The insulating layer 36 is provided between the semiconductor substrate 31 and the second substrate 20. The semiconductor substrate 31 is configured of a silicon substrate. The third substrate 30 is configured such that a logic circuit 32 is provided on a portion of the front surface side (second substrate 20 side) of the semiconductor substrate 31. The third substrate 30 is bonded to the second substrate 20 with the front surface of the semiconductor substrate 31 facing the back surface side of the semiconductor substrate 21.

[0038] FIG. 6A shows an example of a wiring structure for extracting the output voltage Vout output from the logic circuit 32 from the imaging device 1. FIG. 6B shows an example of a wiring structure for supplying a reference potential to the boost circuit 33. FIG. 6C shows an example of a wiring structure for supplying a reference potential VSS to the third substrate 30. The laminated body made up of the first substrate 10 and the second substrate 20 has openings 45a, 46a, and 47a penetrating the first substrate 10 and the second substrate 20 around the pixel region 13. A connection pad 45b is provided on the bottom surface of the opening 45a, and the connection pad 45b is connected to the output end of the logic circuit 32. For example, a bonding wire is connected to the connection pad 45b. A connection pad 46b is provided on the bottom surface of the opening 46a, and the connection pad 46b is connected to the boost circuit 33. For example, a bonding wire is connected to the connection pad 46b. A connection pad 47b is provided on the bottom surface of the opening 47a, and the connection pad 47b is connected to a region for applying the reference potential VSS on the third substrate 30. For example, a bonding wire is connected to the connection pad 47b.

[0039] As shown in FIG. 7A, the through wiring 45c may be provided in the opening 45a. In this case, for example, the connection pad 45d may be provided on the surface of the first substrate 10 of the through wiring 45c, and a bonding wire may be connected to the connection pad 45d. Also, as shown in FIG. 7B, the through wiring 46c may be provided in the opening 46a. In this case, for example, the connection pad 46d may be provided on the surface of the first substrate 10 of the through wiring 46c, and a bonding wire may be connected to the connection pad 46d. Also, as shown in FIG. 7C, the through wiring 47c may be provided in the opening 47a. In this case, for example, the connection pad 47d may be provided on the surface of the first substrate 10 of the through wiring 47c, and a bonding wire may be connected to the connection pad 47d.

[0040] [effect] Next, the effects of the imaging device 1 according to the present embodiment will be described.

[0041] Conventionally, miniaturization of the area per pixel of two-dimensional imaging devices has been achieved by introducing microprocesses and improving packaging density. In recent years, three-dimensional imaging devices have been developed to further miniaturize imaging devices and increase pixel density. In three-dimensional imaging devices, for example, photodiodes, a circuit for reading out the charge obtained by the photodiode (readout circuit), and a circuit for controlling the reading out of the charge from the photodiode (control circuit) are formed on two stacked semiconductor substrates.

[0042] In this embodiment, a plurality of sensor pixels 12 are formed on the first substrate 10, a plurality of readout circuits 22 are formed on the second substrate 20, and a logic circuit 32 is formed on the third substrate 30. As a result, each sensor pixel 12 can be made sufficiently large, so that a reproduced image with a wide dynamic range can be obtained. In addition, the size of the readout circuit 22 can be made sufficiently large, so that dark noise such as RTS noise is not increased. In addition, the size of the logic circuit 32 can be made sufficiently large, so that, for example, the output data rate can be made sufficiently fast, so that a moving image with a high frame rate can be obtained. In addition, in this embodiment, the sensor pixel 12 and the readout circuit 22 are electrically connected to each other by the junction between the FD junction electrodes 17, 24 provided in the area facing the pixel area 13. As a result, the unit pixel size can be reduced compared to the case where the sensor pixel 12 and the readout circuit 22 are electrically connected within one pixel of a common substrate.

[0043] In addition, in this embodiment, a plurality of through-wires 42 are formed in the stacked body consisting of the first substrate 10 and the second substrate 20 in the region around the pixel region 13. The sensor pixels 12 and the readout circuit 22 are controlled by the logic circuit 32 via the plurality of through-wires 42. As a result, each through-wire 42 is disposed away from the FD through-wires 15, 26 electrically connected to the floating diffusion FD, compared to the case where each through-wire 42 is disposed in the region facing the pixel region 13. As a result, it is possible to reduce signal interference between each through-wire 42 and each FD through-wire 15, 26. Therefore, it is possible to achieve further reduction in noise.

[0044] In addition, in this embodiment, a plurality of VSS through wirings 16 are provided for each readout circuit 22 in the insulating film 19 and in a region facing the pixel region 13, and a plurality of VSS through wirings 27 are provided for each readout circuit 22 in the insulating layer 28 and in a region facing the pixel region 13. Furthermore, in this embodiment, each VSS through wiring 16 is electrically connected to a region (p-well region 41) that is the reference potential VSS in the first substrate 10, and each VSS through wiring 27 is electrically connected to a region that is the reference potential VSS in the second substrate 20. This allows each VSS through wiring 16 to function as a shield that reduces signal interference between adjacent FD through wirings 15, and each VSS through wiring 27 to function as a shield that reduces signal interference between adjacent FD through wirings 26. Therefore, it is possible to achieve a further reduction in noise.

[0045] In addition, in this embodiment, a plurality of FD through wirings 15 electrically connected to each of the plurality of FD junction electrodes 17 are provided in a region in the insulating film 19 facing the pixel region 13, and a plurality of FD through wirings 26 electrically connected to each of the plurality of FD junction electrodes 24 are provided in a region in the insulating layer 28 facing the pixel region 13. Furthermore, in this embodiment, each VSS through wiring 16 is disposed in a gap between two adjacent FD through wirings 15 in the plurality of FD through wirings 15, and each VSS through wiring 27 is disposed in a gap between two adjacent FD through wirings 26 in the plurality of FD through wirings 26. This allows each VSS through wiring 16 to function as a shield that reduces signal interference between adjacent FD through wirings 15, and further allows each VSS through wiring 27 to function as a shield that reduces signal interference between adjacent FD through wirings 26. Therefore, a further reduction in noise can be achieved.

[0046] In addition, in this embodiment, a VSS junction electrode 18 (wiring electrode) electrically connected to each VSS through-wire 16 is provided in the insulating film 19, and the VSS junction electrode 18 is formed in a lattice shape so as to surround each FD junction electrode 17. Furthermore, in this embodiment, a VSS junction electrode 25 (wiring electrode) electrically connected to each VSS through-wire 27 is provided in the insulating layer 28, and the VSS junction electrode 25 is formed in a lattice shape so as to surround each FD junction electrode 24. This allows the VSS junction electrode 18 to function as a shield that reduces signal interference between the FD junction electrodes 17 adjacent to each other, and further allows each VSS junction electrode 25 to function as a shield that reduces signal interference between the FD junction electrodes 24 adjacent to each other. Therefore, a further reduction in noise can be achieved.

[0047] <2. Modifications> Modifications of the imaging device 1 according to the above embodiment will be described below. In the following modifications, the same reference numerals are given to configurations common to the above embodiment.

[0048] [Variation A] 8 shows a modified example of the cross-sectional configuration of the FD junction electrode 17 and the VSS junction electrode 18, or a modified example of the cross-sectional configuration of the FD junction electrode 24 and the VSS junction electrode 25. In the imaging device 1 according to the above embodiment, for example, as shown in FIG. 8, each VSS junction electrode 18 may be composed of a plurality of junction electrodes 18a and wiring 18b that electrically connects the plurality of junction electrodes 18a to each other. Furthermore, in the imaging device 1 according to the above embodiment, for example, as shown in FIG. 8, each VSS junction electrode 25 may be composed of a plurality of junction electrodes 25a and wiring 25b that electrically connects the plurality of junction electrodes 25a to each other.

[0049] At this time, the multiple junction electrodes 18a are provided for each of the VSS through wirings 16, and the multiple junction electrodes 25a are provided for each of the VSS through wirings 27. That is, the first substrate 10 has multiple junction electrodes 18a electrically connected to each of the multiple VSS through wirings 16 in the insulating film 19, and the second substrate 20 has multiple junction electrodes 25a electrically connected to each of the multiple VSS through wirings 27 in the insulating layer 28. The junction electrodes 18a and the junction electrodes 25a correspond to a specific example of the "second junction electrode" of the present disclosure. Furthermore, the multiple junction electrodes 18a are arranged in the gap between two FD junction electrodes 17 adjacent to each other in the multiple FD junction electrodes 17, and the multiple junction electrodes 25a are arranged in the gap between two FD junction electrodes 24 adjacent to each other in the multiple FD junction electrodes 24.

[0050] Even in this case, the VSS junction electrode 18 can function as a shield that reduces signal interference between the adjacent FD junction electrodes 17, and each VSS junction electrode 25 can function as a shield that reduces signal interference between the adjacent FD junction electrodes 24. Therefore, a further reduction in noise can be achieved.

[0051] [Variation B] Fig. 9 shows a modified example of the sensor pixel 12 and the readout circuit 22. Fig. 10 shows a modified example of the cross-sectional configuration of the FD junction electrode 17 and the VSS junction electrode 18, or a modified example of the cross-sectional configuration of the FD junction electrode 24 and the VSS junction electrode 25.

[0052] In the imaging device 1 according to the above embodiment and its modified example, one readout circuit 22 may share eight sensor pixels 12 (2×4 sensor pixels 12), for example, as shown in FIG. 9. In this case, the VSS junction electrodes 18, 25 are formed in a lattice shape so as to surround each of the FD junction electrodes 17, 24 in the in-plane direction of the stacking layers, for example, as shown in FIG. 10. The VSS junction electrode 18 has a lattice shape formed in the same plane so that a plurality of junction wires extending in the first direction and a plurality of junction wires extending in the second direction intersect (orthogonal) with each other. Similarly, the VSS junction electrode 25 has a lattice shape formed in the same plane so that a plurality of junction wires extending in the first direction and a plurality of junction wires extending in the second direction intersect (orthogonal) with each other. Here, the first direction is a direction intersecting with the arrangement direction (for example, row direction, column direction) of the plurality of floating diffusions FD (or the plurality of sensor pixels 12). Moreover, the second direction is a direction intersecting with the arrangement direction (for example, row direction, column direction) of the plurality of floating diffusions FD (or the plurality of sensor pixels 12) and also intersecting (orthogonal to) the first direction. In this way, compared to the layout shown in FIG. 5, the interval between two adjacent FD junction electrodes 17 and the interval between two adjacent FD junction electrodes 24 can be widened, so that the distance between the FD junction electrodes 17 and the VSS junction electrode 18 and the distance between the FD junction electrodes 24 and the VSS junction electrode 25 can also be widened. As a result, even with a finer unit pixel size, the VSS junction electrode 18 can be disposed between two adjacent FD junction electrodes 17, and the VSS junction electrode 25 can be disposed between two adjacent FD junction electrodes 24. Therefore, even with a finer unit pixel size, the VSS junction electrode 18 can function as a shield that reduces signal interference between the adjacent FD junction electrodes 17, and further, each VSS junction electrode 25 can function as a shield that reduces signal interference between the adjacent FD junction electrodes 24. Therefore, a further reduction in noise can be achieved.

[0053] [Variation C] FIG. 11 shows a modified example of the vertical cross-sectional configuration of the imaging device 1. In the imaging device 1 according to the above embodiment and its modified example, the insulating layer 71 provided in the same layer as the FD junction electrode 17 and the VSS junction electrode 18 of the insulating film 19 provided on the first substrate 10 may be formed of an insulating material having a lower dielectric constant than the dielectric constant of the insulating film 19 provided on the first substrate 10 other than the insulating layer 71. In addition, in the imaging device 1 according to the above embodiment and its modified example, the insulating layer 72 provided in the same layer as the FD junction electrode 24 and the VSS junction electrode 25 of the insulating layer 28 provided on the second substrate 20 may be formed of an insulating material having a lower dielectric constant than the dielectric constant of the insulating layer 28 provided on the second substrate 20 other than the insulating layer 72. In this case, the capacitance Cfd can be reduced, so that the decrease in conversion efficiency can be suppressed.

[0054] Furthermore, in the imaging device 1 according to the above embodiment and its modified example, for example, as shown in FIG. 12, the insulating layer 73 provided in the insulating film 19 provided on the first substrate 10 in the same layer as the connection wiring 47 (e.g., via) connected to the FD junction electrode 17 and the VSS junction electrode 18 may be formed of an insulating material having a lower dielectric constant than the insulating layer 71, 73 of the insulating film 19 provided on the first substrate 10. Also, in the imaging device 1 according to the above embodiment and its modified example, the insulating layer 74 provided in the insulating layer 28 provided on the second substrate 20 in the same layer as the connection wiring 48 (e.g., via) connected to the FD junction electrode 24 and the VSS junction electrode 25 may be formed of an insulating material having a lower dielectric constant than the insulating layer 72, 74 of the insulating layer 28 provided on the second substrate 20. In this case, the capacitance Cfd can be further reduced, so that the decrease in conversion efficiency can be suppressed.

[0055] [Variation D] FIG. 13 shows a modified example of the vertical cross-sectional configuration of the imaging device 1. In the imaging device 1 according to the above embodiment and its modified example, for example, as shown in FIG. 13, the connection wiring 48 connected to the VSS junction electrode 25 may be omitted, and the wiring connecting the VSS junction electrode 25 and the region to which the reference potential VSS is applied in the second substrate 20 may not be provided in the region facing the pixel region 13. In this case, each VSS through wiring 16 is electrically connected to the p-well region 41, and each VSS through wiring 27 is electrically connected to the region to which the reference potential VSS is applied in the second substrate 20. Even in this case, each VSS through wiring 16 can function as a shield that reduces signal interference between the FD through wirings 15 adjacent to each other, and each VSS through wiring 27 can function as a shield that reduces signal interference between the FD through wirings 26 adjacent to each other. Therefore, noise reduction can be realized.

[0056] [Variation E] FIG. 14 shows a modified example of the vertical cross-sectional configuration of the imaging device 1. In the imaging device 1 according to the above embodiment and its modified example, for example, as shown in FIG. 14, the VSS junction electrodes 18, 25 may be omitted, and the wiring connecting the p-well region 41 of the first substrate 10 and the region to which the reference potential VSS is applied in the second substrate 20 may not be provided in the region facing the pixel region 13. In this case, each VSS through wiring 16 is electrically connected to the p-well region 41, and each VSS through wiring 27 is electrically connected to the region to which the reference potential VSS is applied in the second substrate 20. Even in this case, each VSS through wiring 16 can function as a shield that reduces signal interference between the FD through wirings 15 adjacent to each other, and each VSS through wiring 27 can function as a shield that reduces signal interference between the FD through wirings 26 adjacent to each other. Therefore, noise reduction can be realized.

[0057] [Variation F] FIG. 15 shows a modified example of the vertical cross-sectional configuration of the imaging device 1. In the imaging device 1 according to the above embodiment and its modified example, for example, as shown in FIG. 15, the VSS junction electrodes 18, 25 and the connection wirings 47, 48 connected to the VSS junction electrodes 18, 25 may be omitted, and the wirings connecting the p-well region 41 of the first substrate 10 and the region to which the reference potential VSS is applied in the second substrate 20 may not be provided in the region facing the pixel region 13. In this case, each VSS through wiring 16 is electrically connected to the p-well region 41, and each VSS through wiring 27 is electrically connected to the region to which the reference potential VSS is applied in the second substrate 20. Even in this case, each VSS through wiring 16 can function as a shield that reduces signal interference between the FD through wirings 15 adjacent to each other, and each VSS through wiring 27 can function as a shield that reduces signal interference between the FD through wirings 26 adjacent to each other. Therefore, noise reduction can be realized.

[0058] [Variation G] 16 shows a modified example of the sensor pixel 12 and the readout circuit 22. In the above modified examples D, E, and F, a through-hole wiring 44 may be used as wiring for connecting the p-well region 41 of the first substrate 10 and a region to which the reference potential VSS is applied in the second substrate 20. In this case, the potential of the p-well region 41 of the first substrate 10 and the potential of the region to which the reference potential VSS is applied in the second substrate 20 can be set to the same value (reference potential VSS).

[0059] [Variation H] FIG. 17 shows a modified example of the readout circuit 22. In the imaging device 1 according to the above embodiment and its modified example, the readout circuit 22 may have a negative feedback circuit including an operational amplifier OP and a feedback capacitance Cf, instead of the amplification transistor AMP and the selection transistor SEL, as shown in FIG. 17. The feedback capacitance Cf is connected to one input terminal of the operational amplifier OP and an output terminal of the operational amplifier OP. The reset transistor RST is connected to a wiring to which a power supply potential VDD is applied, one input terminal of the operational amplifier OP, and one terminal of the feedback capacitance Cf. A wiring to which a power supply potential VDD is applied is connected to the other input terminal of the operational amplifier OP. For example, a power supply potential VDD and a reference potential VSS are applied to the operational amplifier OP as a power supply voltage.

[0060] In this modification, a negative feedback circuit including an operational amplifier OP and a feedback capacitance Cf is provided in the read circuit 22. As a result, the charge detection capacitance becomes the feedback capacitance Cf, so that high conversion efficiency can be obtained even if the capacitance Cfd of the floating diffusion FD is large.

[0061] FIG. 18 shows a modified example of the sensor pixel 12 and the readout circuit 22. In the imaging device 1 according to the modified examples D to G, when the readout circuit 22 shown in FIG. 17 is provided, the reference potential VSS1 of the first substrate 10 may be lower than the reference potential VSS2 of the second substrate 20. The reference potential VSS1 is a potential lower than the reference potential VSS2, and is, for example, a value within a range of −0.5V to −1V. The reference potential VSS2 is, for example, a potential equal to the above-mentioned reference potential VSS, and is, for example, zero volts. Note that the region to which the reference potential VSS2 is applied in the second substrate is equal to the region to which the reference potential VSS is applied in the second substrate according to the above-mentioned embodiment and its modified examples.

[0062] In this case, in the imaging device 1, the stacked body made up of the first substrate 10 and the second substrate 20 may have a through-wire 45 in the region around the pixel region 13, as shown in FIG. 19. The through-wire 45 corresponds to a specific example of a "fourth through-wire" in the present disclosure. The through-wire 45 is a wire to which a reference potential VSS1 is applied, and is formed of, for example, a TSV. The through-wire 45 is electrically connected to a negative boost circuit 34 described later and a p-well region 41 of the first substrate 10.

[0063] Furthermore, in the imaging device 1, the stacked body made up of the second substrate 20 and the third substrate 30 may have a through-wire 46 in a region around the pixel region 13, as shown in Fig. 19. The through-wire 46 is a wire to which the reference potential VSS2 is applied, and is formed of, for example, a TSV. The through-wire 46 is electrically connected to a region in the third substrate 30 to which the reference potential VSS2 is applied and a region in the second substrate 20 to which the reference potential VSS2 is applied.

[0064] Furthermore, in the imaging device 1, the third substrate 30 has a negative boost circuit 34 that generates a reference potential VSS1 of a predetermined magnitude. The negative boost circuit 34 controls the reference potential of the first substrate 10 via the through-wire 45, thereby making the reference potential of the first substrate 10 lower than the reference potential of the second substrate 20.

[0065] In this modification, the reference potential VSS1 of the first substrate 10 is lower than the reference potential VSS2 of the second substrate 20. This makes it possible to expand the dynamic range of the floating diffusion FD compared to a case in which the reference potentials of the first substrate 10 and the second substrate are equal to each other. As a result, it is possible to suppress the occurrence of charge transfer failure and black sunkenness when displaying images.

[0066] [Variation I] Fig. 20 shows an example of a cross-sectional configuration of a transistor in the first substrate 10. Fig. 21 shows an example of a cross-sectional configuration of a transistor in the second substrate 20. In the imaging devices 1 according to the above-described embodiments and their variations, the design conditions of the transistors in the first substrate 10 and the transistors in the second substrate 20 may be different from each other.

[0067] 20, the transistor in the first substrate 10 has a gate insulating film 51 formed on the semiconductor substrate 11, a gate electrode 52 formed in contact with the gate insulating film 51, a sidewall layer 53 formed in contact with the side surface of the gate electrode 52, and a source region and a drain region formed on the surface of the semiconductor substrate 11. Around the transistor in the first substrate 10, as shown in FIG. 20, a silicon oxide film 54 formed to cover the gate insulating film 51, the gate electrode 52, and the sidewall layer 53, a silicon nitride film 55 formed in contact with the silicon oxide film 54, an insulating layer 56 formed in contact with the silicon nitride film 55, a through wiring 58 electrically connected to the gate electrode 52, and a through wiring 57 electrically connected to the floating diffusion FD are formed. The silicon oxide film 54 is provided to protect the surface portion of the semiconductor substrate 11 and to make the thickness of the silicon oxide film on the surface portion of the semiconductor substrate 11 uniform during ion implantation. The silicon nitride film 55 serves as an etching stopper when through holes for forming the through wirings 57 and 58 are formed in the insulating layer 56 .

[0068] 21, the transistor in the second substrate 20 has a gate insulating film 61 formed on the semiconductor substrate 21, a gate electrode 62 formed in contact with the gate insulating film 61, a sidewall layer 63 formed in contact with the side surface of the gate electrode 62, and a source region and a drain region (impurity diffusion region 69) formed on the surface of the semiconductor substrate 21. Around the transistor in the second substrate 20, as shown in FIG. 21, for example, a silicon oxide film 64 formed so as to cover the gate insulating film 61, the gate electrode 62, and the sidewall layer 63, a silicon nitride film 65 formed in contact with the silicon oxide film 64, an insulating layer 56 formed in contact with the silicon nitride film 65, a through wiring 68 electrically connected to the gate electrode 62, and a through wiring 67 electrically connected to the impurity diffusion region 69 are formed. The silicon oxide film 64 is provided to protect the surface portion of the semiconductor substrate 11 and to make the thickness of the silicon oxide film on the surface portion of the semiconductor substrate 11 uniform during ion implantation. The silicon nitride film 65 serves as an etching stopper when through holes for forming the through wirings 67 and 68 are formed in the insulating layer 66 .

[0069] In this modification, the gate insulating film 51 may be formed thicker than the gate insulating film 61. Also, in this modification, the sidewall layer 53 may be formed wider than the sidewall layer 63. Also, in this modification, the impurity concentrations of the source region and the drain region formed in the semiconductor substrate 11 may be lower than the impurity concentration of the impurity diffusion region 69 formed in the semiconductor substrate 21. Also, in this modification, the silicon oxide film 54 may be formed thicker than the silicon oxide film 64, and the silicon nitride film 55 may be formed thinner than the silicon nitride film 65.

[0070] In this manner, in this modification, the design conditions of the transistors in the first substrate 10 and the transistors in the second substrate 20 are different from each other. This makes it possible to apply design conditions suitable for the transistors in the first substrate 10 to the transistors in the first substrate 10, and to apply design conditions suitable for the transistors in the second substrate 20 to the transistors in the second substrate 20. As a result, it is possible to achieve reduced noise, high efficiency, and the like.

[0071] [Variation J] 22 and 23 show a modified example of sharing the sensor pixels 12 by the readout circuits 22. In the imaging device 1 according to the above embodiment and its modified example, the number of sensor pixels 12 shared by one readout circuit 22 may be, for example, two as shown in Fig. 22. Also, in the imaging device 1 according to the above embodiment and its modified example, one sensor pixel 12 may be provided for each readout circuit 22 as shown in Fig. 23.

[0072] [Variation K] 24 and 25 show the configuration of an imaging device 2 according to an embodiment of the present disclosure. The imaging device 2 is provided on a second substrate 80 instead of the second substrate 20 and the third substrate 30 in the imaging device 1 according to the above embodiment and its modified example, and the circuits provided on the second substrate 20 and the third substrate 30 (specifically, a plurality of readout circuits 22, logic circuit 32, boost circuit 33, negative boost circuit 34) are provided on the second substrate 80. Even in this case, as in the imaging device 1 according to the above embodiment and its modified example, each sensor pixel 12 can be made sufficiently large, so that a reproduced image with a wide dynamic range can be obtained. In addition, the size of the readout circuit 22 can be made sufficiently wide, so that dark noise such as RTS noise is not increased.

[0073] [Variation L] 26 shows an example of a circuit configuration of the imaging device 1 according to the above embodiment and its modified example. The imaging device 1 according to this modified example is a CMOS image sensor equipped with a column-parallel ADC.

[0074] As shown in FIG. 26, the solid-state imaging device 1 of this modified example has a pixel area 13 in which a plurality of sensor pixels 12, each including a photoelectric conversion element, are two-dimensionally arranged in a matrix, as well as a vertical driving circuit 32a, a column signal processing circuit 32b, a reference voltage supply unit 38, a horizontal driving circuit 32c, a horizontal output line 37, and a system control circuit 32d.

[0075] In this system configuration, the system control circuit 32d generates clock signals and control signals that serve as standards for the operation of the vertical drive circuit 32a, the column signal processing circuit 32b, the reference voltage supply unit 38, the horizontal drive circuit 32c, etc., based on the master clock MCK, and provides these signals to the vertical drive circuit 32a, the column signal processing circuit 32b, the reference voltage supply unit 38, the horizontal drive circuit 32c, etc.

[0076] The vertical drive circuit 32a is formed on the first substrate 10 together with each sensor pixel 12 in the pixel region 13, and is also formed on the second substrate 20 on which the readout circuit 22 is formed. The column signal processing circuit 32b, the reference voltage supply unit 38, the horizontal drive circuit 32c, the horizontal output line 37, and the system control circuit 32d are formed on the third substrate 30.

[0077] Although not shown here, the sensor pixel 12 may have, for example, a photodiode PD and a transfer transistor TR that transfers the charge obtained by photoelectric conversion in the photodiode PD to the floating diffusion FD. Although not shown here, the readout circuit 22 may have, for example, a three-transistor configuration that includes a reset transistor RST that controls the potential of the floating diffusion FD, an amplification transistor AMP that outputs a signal according to the potential of the floating diffusion FD, and a selection transistor SEL that selects pixels.

[0078] In the pixel region 13, the sensor pixels 12 are arranged two-dimensionally, and drive wiring 14 is wired for each row in this pixel arrangement of m rows and n columns, and vertical signal lines VSL are wired for each column. One end of each of the drive wirings 14 is connected to an output terminal corresponding to each row of the vertical drive circuit 32a. The vertical drive circuit 32a is composed of a shift register or the like, and controls row addresses and row scanning of the pixel region 13 via the drive wirings 14.

[0079] The column signal processing circuit 32b has, for example, ADCs (analog-to-digital conversion circuits) 35-1 to 35-m provided for each pixel column in the pixel region 13, i.e., for each vertical signal line VSL, and converts analog signals output from each sensor pixel 12 in the pixel region 13 for each column into digital signals and outputs them.

[0080] The reference voltage supply unit 38 has, for example, a DAC (digital-analog conversion circuit) 38A as a means for generating a reference voltage Vref having a so-called ramp waveform whose level changes in a sloping manner as time passes. Note that the means for generating the reference voltage Vref having a ramp waveform is not limited to the DAC 38A.

[0081] The DAC 38A generates a reference voltage Vref having a ramp waveform based on a clock CK provided from the system control circuit 32d under the control of a control signal CS1 provided from the system control circuit 32d, and supplies the reference voltage Vref to the ADCs 35-1 to 35-m of the column signal processing circuit 32b.

[0082] Each of the ADCs 35-1 to 35-m is configured to selectively perform AD conversion operations corresponding to each operation mode, namely, a normal frame rate mode in a progressive scanning system in which information of all the sensor pixels 12 is read out, and a high frame rate mode in which the exposure time of the sensor pixels 12 is set to 1 / N and the frame rate is increased to N times, for example, 2 times, compared to the normal frame rate mode. The switching of the operation modes is executed under the control of control signals CS2 and CS3 provided from the system control circuit 32d. An external system controller (not shown) provides the system control circuit 32d with instruction information for switching between the normal frame rate mode and the high frame rate mode.

[0083] The ADCs 35-1 to 35-m all have the same configuration, and the ADC 35-m will be described here as an example. The ADC 35-m has a comparator 35A, a counting means such as an up / down counter (denoted as U / DCNT in the figure) 35B, a transfer switch 35C, and a memory device 35D.

[0084] The comparator 35A compares the signal voltage Vx of the vertical signal line VSL corresponding to the signal output from each sensor pixel 12 in the nth column of the pixel area 13 with a ramp-wave reference voltage Vref supplied from the reference voltage supply unit 38, and, for example, when the reference voltage Vref is greater than the signal voltage Vx, the output Vco becomes an “H” level, and when the reference voltage Vref is equal to or lower than the signal voltage Vx, the output Vco becomes an “L” level.

[0085] The up / down counter 35B is an asynchronous counter, and under the control of a control signal CS2 provided from the system control circuit 32d, a clock CK is provided from the system control circuit 32d simultaneously with the DAC 38A, and the up / down counter 35B measures the comparison period from the start of the comparison operation in the comparator 35A to the end of the comparison operation by counting down (DOWN) or counting up (UP) in synchronization with the clock CK.

[0086] Specifically, in the normal frame rate mode, in the readout operation of a signal from one sensor pixel 12, the comparison time during the first readout operation is measured by counting down during the first readout operation, and the comparison time during the second readout operation is measured by counting up during the second readout operation.

[0087] On the other hand, in the high-speed frame rate mode, the count result for the sensor pixels 12 in a certain row is retained as is, and then, for the sensor pixels 12 in the next row, counting down from the previous count result during the first read operation is performed to measure the comparison time during the first read operation, and counting up during the second read operation is performed to measure the comparison time during the second read operation.

[0088] In the normal frame rate mode, under the control of a control signal CS3 provided from the system control circuit 32d, the transfer switch 35C turns on (closed) when the counting operation of the up / down counter 35B for a certain row of sensor pixels 12 is completed, and transfers the counting result of the up / down counter 35B to the memory device 35D.

[0089] On the other hand, at a high frame rate of, for example, N=2, the up / down counter 35B remains in the off (open) state when it completes its counting operation for the sensor pixels 12 in a certain row, and then turns on when it completes its counting operation for the sensor pixels 12 in the next row, and transfers the counting result of the up / down counter 35B for two vertical pixels to the memory device 35D.

[0090] In this manner, the analog signals supplied for each column from each sensor pixel 12 in the pixel area 13 via the vertical signal line VSL are converted into N-bit digital signals by the operation of each of the comparators 35A and the up / down counters 35B in the ADCs 35-1 to 35-m and stored in the memory device 35D.

[0091] The horizontal drive circuit 32c is configured with a shift register and controls the column addresses and column scanning of the ADCs 35-1 to 35-m in the column signal processing circuit 32b. Under the control of the horizontal drive circuit 32c, the N-bit digital signals AD-converted by each of the ADCs 35-1 to 35-m are sequentially read out to a horizontal output line 37 and output as imaging data via the horizontal output line 37.

[0092] In addition, although not specifically shown because it is not directly related to the present disclosure, it is also possible to provide circuits, etc. that perform various types of signal processing on the imaging data output via the horizontal output line 37 in addition to the above-mentioned components.

[0093] In the imaging device 1 equipped with a column-parallel ADC according to this modified example of the above configuration, the count result of the up / down counter 35B can be selectively transferred to the memory device 35D via the transfer switch 35C, so that it is possible to independently control the count operation of the up / down counter 35B and the read operation of the count result of the up / down counter 35B to the horizontal output line 37.

[0094] [Variation M] Fig. 27 shows a modified vertical cross-sectional configuration of the imaging device 1, and in particular shows a modified wiring structure of the bonding surface between the first substrate 10 and the second substrate 20 facing the pixel region 13 and the vicinity thereof. Fig. 28 shows an example of a horizontal cross-sectional configuration of the FD bonding electrodes 17, 24 and the VSS bonding electrodes 18, 25 at the bonding surface between the first substrate 10 and the second substrate 20 shown in Fig. 27. Fig. 29 shows an example of a sensor pixel and a readout circuit of the imaging device 1 having the bonding surface between the first substrate 10 and the second substrate 20 and the vicinity thereof shown in Fig. 27. In this modified example, the FD junction electrodes 17, 24 and the VSS junction electrodes 18, 25 that electrically connect the sensor pixel 12 and the readout circuit 22 in the region facing the pixel region 13 are directly connected to the FD through wirings 15, 26 and the VSS through wirings 16, 27, respectively, without going through vias (the above-mentioned connection wirings 47, 48), and differ from the above-mentioned embodiment and modified example in that they have two or more types of shapes.

[0095] For example, as shown in FIG. 27, the widths of the FD junction electrode 17, the FD junction electrode 24, and the VSS junction electrodes 18 and 25 may be different from each other. For example, the width of the VSS junction electrodes 18 and 25 may be narrower than the width of the FD junction electrodes 17 and 24. For example, the lengths of the FD junction electrodes 17 and 24 and the VSS junction electrodes 18 and 25 in the stacking direction may be different from each other. Alternatively, for example, as shown in FIG. 27, the lengths of the VSS junction electrode 18 on the first substrate 10 side and the VSS junction electrode 25 on the second substrate 20 side in the optical axis direction may be different from each other. In this case, for example, each VSS junction electrode 18 on the first substrate 10 side is formed in the insulating film 19 and is not exposed to the bonding surface with the second substrate 20. That is, the opposing VSS junction electrodes 18 and VSS junction electrodes 25 are separated with the insulating film 19 between them. Even in this case, each VSS through wiring 16 can function as a shield to reduce signal interference between adjacent FD through wirings 15, and further, each VSS through wiring 27 can function as a shield to reduce signal interference between adjacent FD through wirings 26.

[0096] The above-mentioned wiring structure can be manufactured, for example, as follows.

[0097] 30A to 30I show an example of a manufacturing method of the FD junction electrode 17 and the VSS junction electrode 18 on the first substrate 10 in the order of steps. First, as shown in FIG. 30A, the FD through wiring 15 and the VSS through wiring 16 are formed, for example, by the damascene technique, and then, as shown in FIG. 30B, an insulating film 19B is formed to a predetermined thickness on the insulating film 19A including the FD through wiring 15 and the VSS through wiring 16. Next, as shown in FIG. 30C, the insulating film 19B on the FD through wiring 15 and the VSS through wiring 16 is selectively etched to form an opening H1, and then, as shown in FIG. 30D, a metal film M1 such as copper (Cu) is embedded in the opening H1 and deposited on the insulating film 19B. Next, as shown in FIG. 30E, the metal film M1 on the insulating film 19B is removed, for example, by etching. As a result, a part of the FD junction electrode 17 (FD junction electrode 17A) and the VSS junction electrode 18 are formed. 30F, an insulating film 19C is formed to a predetermined thickness on the insulating film 19B including the FD junction electrode 17A and the VSS junction electrode 18. Next, as shown in FIG. 30G, the insulating film 19 on the FD junction electrode 17A is selectively etched to form an opening H2, and then, as shown in FIG. 30H, a metal film M2 such as copper (Cu) is embedded in the opening H2 and deposited on the insulating film 19. Finally, as shown in FIG. 30I, the metal film M2 on the insulating film 19 is removed by, for example, etching. As a result, the first substrate 10 having the FD junction electrode 17 and the VSS junction electrode 18 whose lengths in the stacking direction are different from each other is completed.

[0098] In addition, although Fig. 27 shows an example in which the FD junction electrodes 17 and 24 have different widths, the FD junction electrodes 17 and 24 may have the same width as shown in Fig. 31. Although not shown, in Fig. 27, an example in which the VSS junction electrodes 18 and 25 have the same width, the VSS junction electrodes 18 and 25 may have different widths like the FD junction electrodes 17 and 24 shown in Fig. 27.

[0099] As shown in Fig. 1, in an imaging device 1 in which a first substrate 10 having a plurality of sensor pixels 12 and floating diffusions FD and a second substrate 20 having a readout circuit 22 that outputs pixel signals based on charges output from the sensor pixels 12 are stacked, it is desirable to arrange shield wirings (e.g., VSS through wirings 16, 27) between at least four signal terminals adjacent in the row and column direction per signal terminal (e.g., FD through wirings 15, 26). When providing shield wirings, in addition to FD junction electrodes 17, 24 that electrically connect the sensor pixels 12 and the readout circuit 22, junction electrodes of the shield wirings (e.g., VSS junction electrodes 18, 25) are arranged on the junction surfaces of the first substrate 10 and the second substrate 20. However, in an imaging device requiring high resolution, the pixel size becomes smaller as the number of pixels increases, and therefore the distance between the signal terminals becomes shorter, and the space for arranging the junction electrodes of the shield wirings between them becomes smaller.

[0100] In particular, when the first substrate 10 and the second substrate 20 are bonded, the wiring pitch and the connection misalignment amount of the FD bonding electrodes 17, 24 and the VSS bonding electrodes 18, 25 on the respective bonding surfaces become close to each other, making it difficult to arrange the shield wiring between adjacent signal terminals. For example, if the connection misalignment amount is large, as shown in Figures 32 and 33, regardless of whether the bonding electrodes 17, 18, 24, 25 on the through-wires 15, 16, 26, 27 have a single-layer structure (Figure 32) or a multilayer structure (Figure 33), for example, the VSS bonding electrode 18 on the first substrate 10 side and the FD bonding electrode 24 on the second substrate 20 side and the FD bonding electrode 17 on the first substrate 10 side and the VSS bonding electrode 25 on the second substrate 20 side are conductive, and signal transmission between the first substrate 10 and the second substrate 20 is not possible, and there is a risk of significant image defects occurring on the reproduced image.

[0101] In contrast, in this modification, for example, the length in the optical axis direction of the VSS bonding electrode 18 on the first substrate 10 side is made shorter than the VSS bonding electrode 25 on the second substrate 20 side, so that the VSS bonding electrode 18 is not exposed on the bonding surface between the first substrate 10 and the second substrate 20. This makes it possible to prevent contact between the VSS bonding electrode 18 on the first substrate 10 side and the FD bonding electrode 24 on the second substrate 20 side, as shown in Figs. 34 and 35, even if a misalignment occurs in the connection between the first substrate 10 and the second substrate.

[0102] In addition, in this modification, since the VSS junction electrodes 18, 25 are provided at the ends of the VSS through-wires 16, 27, the separation distance from the VSS junction electrode 25 on the second substrate 20 side is shorter than in the wiring structure of the imaging device 1 shown in Fig. 15. This makes it possible to improve the function as a shield that reduces signal interference between the FD through-wires 15, 26 adjacent to each other. This makes it possible to further reduce noise compared to the case where the wiring structure shown in Fig. 15 is adopted.

[0103] [Variation N] 36 shows a modified example of the vertical cross-sectional configuration of the imaging device 1, and in particular, a modified example of the bonding surface between the first substrate 10 and the second substrate 20 facing the pixel region 13 and the wiring structure in the vicinity thereof. In the above modification M, an example in which the length of the VSS junction electrode 18 on the first substrate 10 side is shortened has been shown, but as shown in FIG. 36, the length of the VSS junction electrode 25 on the second substrate 20 side may be shortened. Even in this case, as in the above modification M, the function as a shield for reducing signal interference between the FD through-wires 15 and 26 adjacent to each other can be improved, and noise can be reduced.

[0104] [Variation O] Fig. 37 shows a modified example of the vertical cross-sectional configuration of the imaging device 1, and in particular, a modified example of the bonding surface between the first substrate 10 and the second substrate 20 facing the pixel region 13 and the wiring structure in the vicinity thereof. In the above modification M, the ends of the VSS through-wires 16 and 27 are formed as the VSS bonding electrodes 18 and 25, but as shown in Fig. 37, they may be formed as wiring layers 78 and 85 through vias v78 and v85, respectively. In this case, each wiring layer 78 is electrically connected to the p-well region 41 through each via v78 and each VSS through-wire 16, and each wiring layer 85 is electrically connected to a region to which the reference potential VSS is applied through each via v85 and each VSS through-wire 27. Therefore, even in this case, each VSS through wire 16 and each wiring layer 78 can function as a shield that reduces signal interference between adjacent FD through wires 15, 26, and each VSS through wire 27 and each wiring layer 85 can function as a shield that reduces signal interference between adjacent FD through wires 26. In addition, by forming the wiring layers 78, 85 wider than the VSS junction electrode 18 shown in the modification M, etc., the function as a shield can be further improved. Therefore, noise can be further reduced compared to the case where the wiring structure shown in FIG. 15 is adopted, for example.

[0105] [Variation P] FIG. 38 shows a modified example of the vertical cross-sectional configuration of the imaging device 1, and in particular, a modified example of the bonding surface between the first substrate 10 and the second substrate 20 facing the pixel region 13 and the wiring structure in the vicinity thereof. In the above modified example O, the ends of the VSS through-wires 16 and 27 are formed as wiring layers 78 and 85, but as shown in FIG. 38, one may be formed as a wiring layer (for example, the wiring layer 78 on the first substrate 10 side) and the other may be formed as a via (for example, the via v85 on the second substrate 20 side). Even in this case, each VSS through-wire 16 can function as a shield that reduces signal interference between adjacent FD through-wires 15, and each VSS through-wire 27 can function as a shield that reduces signal interference between adjacent FD through-wires 26. Therefore, noise reduction can be achieved.

[0106] [Variation Q] 39 shows a modified example of the vertical cross-sectional configuration of the imaging device 1, and in particular, a modified example of the bonding surface between the first substrate 10 and the second substrate 20 facing the pixel region 13 and the wiring structure in the vicinity thereof. The ends of the VSS through-wires 16 and 27 may be vias v78 and v85, respectively. Even in this case, each VSS through-wire 16 can function as a shield for reducing signal interference between adjacent FD through-wires 15, and each VSS through-wire 27 can function as a shield for reducing signal interference between adjacent FD through-wires 26. Therefore, noise reduction can be achieved.

[0107] [Variation R] FIG. 40 shows a modified example of the vertical cross-sectional configuration of the imaging device 1, and in particular, a modified example of the bonding surface between the first substrate 10 and the second substrate 20 facing the pixel region 13 and the wiring structure in the vicinity thereof. One end of the VSS through-wires 16 and 27 may be a VSS bonding electrode (for example, the VSS bonding electrode 18 on the first substrate 10 side) and the other may be a via (for example, the via v85 on the second substrate 20 side). Even in this case, each VSS through-wire 16 can function as a shield that reduces signal interference between the FD through-wires 15 adjacent to each other, and each VSS through-wire 27 can function as a shield that reduces signal interference between the FD through-wires 26 adjacent to each other. Therefore, noise reduction can be achieved.

[0108] [Variation S] 41 shows a modified example of the sensor pixel 12 and the readout circuit 22. In the above modified examples M to R, a reference potential such as VSS or GND may be applied to the VSS through wiring 16 of the first substrate 10, and another voltage may be applied to the VSS through wiring 27 of the second substrate 20.

[0109] [Variation T] 42 shows a modified example of the sensor pixel 12 and the readout circuit 22. In the above modified examples M to R, a reference potential such as VSS or GND may be applied to the VSS through wiring 27 of the second substrate 20, and another voltage may be applied to the VSS through wiring 16 of the first substrate 10.

[0110] [Variation U] Fig. 43 shows an example of a sensor pixel and a readout circuit when the junction surface and the wiring structure in the vicinity thereof shown in Fig. 27 are applied to another position. In the above modifications M to T, the pixel signal is on the floating diffusion FD terminal, but as shown in Fig. 43, the pixel signal may be on the output terminal (for example, Vsig) of the readout circuit 22.

[0111] In the case of a structure in which the floating diffusion FD is connected between two silicon substrates (between the semiconductor substrate 11 and the semiconductor substrate 21) as in the above-mentioned modified examples M to T, the capacitance between the terminals of the floating diffusion FD and other terminals increases, and there is a risk of a decrease in the conversion efficiency of the pixel. In contrast, in the case of a structure in which the output terminal of the amplifying transistor AMP is connected between two silicon substrates as in this modified example, the capacitance of the terminals of the floating diffusion FD is equivalent to that of a general imaging device, so it is possible to prevent a decrease in the conversion efficiency.

[0112] [Variation V] 44 to 50 show a modified example of the horizontal cross-sectional configuration of the FD junction electrode 17 and the VSS junction electrode 18 of the imaging device 1 having the wiring structure shown in Fig. 27 etc., and a modified example of the horizontal cross-sectional configuration of the FD junction electrode 24 and the VSS junction electrode 25. Note that Figs. 44 to 50 show an example in which the floating diffusion FD is shared by four sensor pixels 12, similar to Fig. 5.

[0113] For example, as shown in FIG. 44, a plurality of VSS junction electrodes 18, 25 may be arranged between each of the FD junction electrodes 17, 24 arranged in a matrix. For example, as shown in FIG. 45, in addition to the configuration shown in FIG. 44, a plurality of VSS junction electrodes 18, 25 may be arranged between each of the FD junction electrodes 17, 24 adjacent in the diagonal direction. For example, as shown in FIG. 46, a plurality of VSS junction electrodes 18, 25 may be arranged between each of the FD junction electrodes 17, 24 adjacent in the row direction, and VSS junction electrodes 18, 25 continuous in the row direction may be arranged between each of the FD junction electrodes 17, 24 adjacent in the column direction. For example, as shown in FIG. 47, a plurality of VSS junction electrodes 18, 25 may be arranged between each of the FD junction electrodes 17, 24 adjacent in the column direction, and VSS junction electrodes 18, 25 continuous in the column direction may be arranged between each of the FD junction electrodes 17, 24 adjacent in the row direction. For example, as shown in Fig. 48, for each of the FD junction electrodes 17, 24 arranged in a matrix, a plurality of VSS junction electrodes 18 may be arranged between each of the FD junction electrodes 17, 24 on the first substrate 10 side, and a VSS junction electrode 25 formed continuously in a lattice shape may be arranged on the second substrate 20 side. For example, as shown in Fig. 49, among the plurality of VSS junction electrodes 18, 25 arranged between each of the FD junction electrodes 17, 24 arranged in a matrix, the length of the VSS junction electrode 25 may be longer than the VSS junction electrode 18. For example, as shown in Fig. 50, among the plurality of VSS junction electrodes 18, 25 arranged between each of the FD junction electrodes 17, 24 arranged in a matrix, the length of the VSS junction electrode 25 may be shorter than the VSS junction electrode 18.

[0114] 44 to 50, each of the VSS through wirings 16, 27 and each of the VSS junction electrodes 18, 25 can function as a shield that reduces signal interference between the adjacent FD through wirings 15, 26. Therefore, noise reduction can be achieved.

[0115] <3. Application Examples> FIG. 51 shows an example of a schematic configuration of an imaging system 3 including the imaging device 1 according to the above embodiment and its modified example.

[0116] The imaging system 3 is, for example, an electronic device such as an imaging device such as a digital still camera or a video camera, or a mobile terminal device such as a smartphone or a tablet terminal. The imaging system 3 includes, for example, the imaging device 1 according to the above embodiment and its modified example, an optical system 141, a shutter device 142, a control circuit 143, a DSP circuit 144, a frame memory 145, a display unit 146, a storage unit 147, an operation unit 148, and a power supply unit 149. In the imaging system 3, the imaging device 1 according to the above embodiment and its modified example, the DSP circuit 144, the frame memory 145, the display unit 146, the storage unit 147, the operation unit 148, and the power supply unit 149 are connected to each other via a bus line 150.

[0117] The optical system 141 is configured with one or more lenses, and guides light (incident light) from a subject to the imaging device 1, forming an image on the light receiving surface of the imaging device 1. The shutter device 142 is disposed between the optical system 141 and the imaging device 1, and controls the light irradiation period and light blocking period of the imaging device 1 according to the control of the control circuit 143. The imaging device 1 accumulates signal charges for a certain period according to the light that is imaged on the light receiving surface via the optical system 141 and the shutter device 142. The signal charges accumulated in the imaging device 1 are transferred as image data according to a drive signal (timing signal) supplied from the control circuit 143. The control circuit 143 outputs a drive signal that controls the transfer operation of the imaging device 1 and the shutter operation of the shutter device 142 to drive the imaging device 1 and the shutter device 142.

[0118] The DSP circuit 144 is a signal processing circuit that processes image data output from the imaging device 1. The frame memory 145 temporarily holds the image data processed by the DSP circuit 144 on a frame-by-frame basis. The display unit 146 is, for example, a panel-type display device such as a liquid crystal panel or an organic EL (Electro Luminescence) panel, and displays moving images or displays a still image. The storage unit 147 records image data of a moving image or a still image captured by the imaging device 1 in a recording medium such as a semiconductor memory or a hard disk. The operation unit 148 issues operation commands for various functions of the imaging system 3 in accordance with operations by a user. The power supply unit 149 appropriately supplies various types of power to these targets as operating power sources for the imaging device 1, the DSP circuit 144, the frame memory 145, the display unit 146, the storage unit 147, and the operation unit 148.

[0119] Next, the imaging procedure in the imaging system 3 will be described.

[0120] FIG. 52 shows an example of a flowchart of the imaging operation in the imaging system 3. The user issues an instruction to start imaging by operating the operation unit 148 (step S101). Then, the operation unit 148 transmits an imaging command to the control circuit 143 (step S102). Upon receiving the imaging command, the control circuit 143 starts controlling the shutter device 142 and the imaging device 1. The imaging device 1 (specifically, the system control circuit 32d) performs imaging in a predetermined imaging method under the control of the control circuit 143 (step S103). The shutter device 142 controls the light irradiation period and the light blocking period for the imaging device 1 under the control of the control circuit 143.

[0121] The imaging device 1 outputs image data obtained by imaging to the DSP circuit 144. Here, the image data refers to data for all pixels of pixel signals generated based on charges temporarily stored in the floating diffusion FD. The DSP circuit 144 performs predetermined signal processing (e.g., noise reduction processing, etc.) based on the image data input from the imaging device 1 (step S104). The DSP circuit 144 stores the image data that has been subjected to the predetermined signal processing in the frame memory 145, and the frame memory 145 stores the image data in the storage unit 147 (step S105). In this manner, imaging is performed in the imaging system 3.

[0122] In this application example, the imaging device 1 according to the above-described embodiment and its modified example is applied to an imaging system 3. This allows the imaging device 1 to be made smaller, have a higher dynamic range, and have lower noise, so that a small, high-definition imaging system 3 with a wide dynamic range can be provided.

[0123] <4. Application Examples> [Application example 1] The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of moving body such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility device, an airplane, a drone, a ship, a robot, etc.

[0124] FIG. 53 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a moving object control system to which the technology of the present disclosure can be applied.

[0125] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 53, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also, as functional configurations of the integrated control unit 12050, a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053 are illustrated.

[0126] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0127] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as head lamps, back lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves or signals of various switches transmitted from a portable device that replaces a key may be input to the body system control unit 12020. The body system control unit 12020 receives the input of these radio waves or signals and controls the door lock device, power window device, lamps, and the like of the vehicle.

[0128] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture an image outside the vehicle and receives the captured image. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for a person, a car, an obstacle, a sign, or characters on a road surface, based on the received image.

[0129] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of light received. The imaging unit 12031 can output the electrical signal as an image, or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0130] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing.

[0131] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, the steering mechanism, or the braking device based on the information inside and outside the vehicle acquired by the outside-of-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane departure warning, etc.

[0132] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on the driver's operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle acquired by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0133] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside-vehicle information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detection unit 12030, and perform cooperative control for the purpose of preventing glare, such as switching from high beams to low beams.

[0134] The audio / video output unit 12052 transmits at least one output signal of audio and video to an output device capable of visually or audibly notifying information to passengers in the vehicle or the outside of the vehicle. In the example of Fig. 53, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified as the output device. The display unit 12062 may include at least one of an on-board display and a head-up display, for example.

[0135] FIG. 54 is a diagram showing an example of the installation position of the imaging unit 12031.

[0136] In FIG. 54, a vehicle 12100 has imaging units 12101, 12102, 12103, 12104, and 12105 as an imaging unit 12031.

[0137] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided at positions such as the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided at the front nose and the imaging unit 12105 provided at the upper part of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided at the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided at the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The images of the front acquired by the imaging units 12101 and 12105 are mainly used to detect a preceding vehicle, a pedestrian, an obstacle, a traffic light, a traffic sign, a lane, or the like.

[0138] 54 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, an overhead image of the vehicle 12100 viewed from above is obtained by superimposing the image data captured by the imaging units 12101 to 12104.

[0139] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera made up of a plurality of imaging elements, or may be an imaging element having pixels for detecting a phase difference.

[0140] For example, the microcomputer 12051 can extract, as a preceding vehicle, a three-dimensional object that is the closest three-dimensional object on the travel path of the vehicle 12100 and travels at a predetermined speed (for example, 0 km / h or more) in approximately the same direction as the vehicle 12100, by calculating the distance to each three-dimensional object in the imaging ranges 12111 to 12114 and the change over time of this distance (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104. Furthermore, the microcomputer 12051 can set a vehicle distance to be secured in advance in front of the preceding vehicle, and perform automatic brake control (including follow-up stop control) and automatic acceleration control (including follow-up start control). In this way, cooperative control can be performed for the purpose of automatic driving that travels autonomously without relying on the driver's operation.

[0141] For example, the microcomputer 12051 classifies and extracts three-dimensional object data on three-dimensional objects, such as two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects, based on the distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. Then, the microcomputer 12051 determines a collision risk indicating the degree of danger of collision with each obstacle, and when the collision risk is equal to or exceeds a set value and there is a possibility of collision, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0142] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the captured images of the imaging units 12101 to 12104. The recognition of such a pedestrian is performed, for example, by a procedure of extracting feature points in the captured images of the imaging units 12101 to 12104 as infrared cameras, and a procedure of performing pattern matching processing on a series of feature points that indicate the contour of an object to determine whether or not the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the captured images of the imaging units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating a pedestrian at a desired position.

[0143] An example of a mobile object control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the imaging unit 12031 among the configurations described above. Specifically, the imaging device 1 according to the above embodiment and its modified example can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the imaging unit 12031, a high-definition captured image with little noise can be obtained, and therefore, high-precision control using the captured image can be performed in the mobile object control system.

[0144] [Application example 2] FIG. 55 is a diagram showing an example of a schematic configuration of an endoscopic surgery system to which the technology according to the present disclosure (the present technology) can be applied.

[0145] 55 shows a state in which an operator (doctor) 11131 is performing surgery on a patient 11132 on a patient bed 11133 using an endoscopic surgery system 11000. As shown in the figure, the endoscopic surgery system 11000 is composed of an endoscope 11100, other surgical tools 11110 such as an insufflation tube 11111 and an energy treatment tool 11112, a support arm device 11120 that supports the endoscope 11100, and a cart 11200 on which various devices for endoscopic surgery are mounted.

[0146] The endoscope 11100 is composed of a lens barrel 11101, a region of a predetermined length from the tip of which is inserted into a body cavity of a patient 11132, and a camera head 11102 connected to the base end of the lens barrel 11101. In the illustrated example, the endoscope 11100 is configured as a so-called rigid scope having a rigid lens barrel 11101, but the endoscope 11100 may be configured as a so-called flexible scope having a flexible lens barrel.

[0147] An opening into which an objective lens is fitted is provided at the tip of the lens barrel 11101. A light source device 11203 is connected to the endoscope 11100, and light generated by the light source device 11203 is guided to the tip of the lens barrel by a light guide extending inside the lens barrel 11101, and is irradiated via the objective lens toward an observation target in the body cavity of the patient 11132. The endoscope 11100 may be a direct-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0148] An optical system and an image sensor are provided inside the camera head 11102, and reflected light (observation light) from an observation target is collected on the image sensor by the optical system. The observation light is photoelectrically converted by the image sensor to generate an electrical signal corresponding to the observation light, i.e., an image signal corresponding to an observation image. The image signal is transmitted to a camera control unit (CCU) 11201 as RAW data.

[0149] The CCU 11201 is configured with a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc., and performs overall control of the operations of the endoscope 11100 and the display device 11202. Furthermore, the CCU 11201 receives an image signal from the camera head 11102, and performs various types of image processing on the image signal, such as development processing (demosaic processing), for displaying an image based on the image signal.

[0150] Under the control of the CCU 11201, the display device 11202 displays an image based on an image signal that has been subjected to image processing by the CCU 11201.

[0151] The light source device 11203 is composed of a light source such as an LED (Light Emitting Diode), and supplies the endoscope 11100 with irradiation light when photographing an operation site or the like.

[0152] The input device 11204 is an input interface for the endoscopic surgery system 11000. A user can input various information and instructions to the endoscopic surgery system 11000 via the input device 11204. For example, the user inputs an instruction to change the imaging conditions (type of irradiated light, magnification, focal length, etc.) of the endoscope 11100.

[0153] The treatment tool control device 11205 controls the driving of the energy treatment tool 11112 for cauterizing tissue, incising, sealing blood vessels, etc. The insufflation device 11206 sends gas into the body cavity of the patient 11132 via the insufflation tube 11111 to inflate the body cavity for the purpose of securing the field of view of the endoscope 11100 and securing the working space of the surgeon. The recorder 11207 is a device capable of recording various information related to the surgery. The printer 11208 is a device capable of printing various information related to the surgery in various formats such as text, image, or graph.

[0154] The light source device 11203 that supplies irradiation light to the endoscope 11100 when photographing the surgical site can be composed of a white light source composed of, for example, an LED, a laser light source, or a combination of these. When the white light source is composed of a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, so that the white balance of the captured image can be adjusted in the light source device 11203. In this case, it is also possible to capture images corresponding to each of the RGB colors in a time-division manner by irradiating the observation object with laser light from each of the RGB laser light sources in a time-division manner and controlling the driving of the image sensor of the camera head 11102 in synchronization with the irradiation timing. According to this method, a color image can be obtained without providing a color filter to the image sensor.

[0155] The light source device 11203 may be controlled to change the intensity of the light it outputs at predetermined time intervals. The driving of the image sensor of the camera head 11102 may be controlled in synchronization with the timing of the change in the light intensity to obtain images in a time-division manner, and the images may be synthesized to generate an image with a high dynamic range that is free of so-called blackout and whiteout.

[0156] The light source device 11203 may be configured to supply light of a predetermined wavelength band corresponding to the special light observation. In the special light observation, for example, by utilizing the wavelength dependency of light absorption in body tissue, a narrow band light is irradiated compared to the irradiated light (i.e., white light) during normal observation, and a predetermined tissue such as blood vessels on the mucous membrane surface is photographed with high contrast, so-called narrow band imaging is performed. Alternatively, in the special light observation, a fluorescent observation may be performed in which an image is obtained by fluorescence generated by irradiating an excitation light. In the fluorescent observation, it is possible to irradiate an excitation light to a body tissue and observe the fluorescence from the body tissue (autofluorescence observation), or to locally inject a reagent such as indocyanine green (ICG) into the body tissue and irradiate the body tissue with excitation light corresponding to the fluorescent wavelength of the reagent to obtain a fluorescent image. The light source device 11203 may be configured to supply narrow band light and / or excitation light corresponding to such special light observation.

[0157] FIG. 56 is a block diagram showing an example of the functional configuration of the camera head 11102 and the CCU 11201 shown in FIG.

[0158] The camera head 11102 has a lens unit 11401, an imaging unit 11402, a drive unit 11403, a communication unit 11404, and a camera head control unit 11405. The CCU 11201 has a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera head 11102 and the CCU 11201 are connected to each other by a transmission cable 11400 so as to be able to communicate with each other.

[0159] The lens unit 11401 is an optical system provided at the connection portion with the lens barrel 11101. Observation light taken in from the tip of the lens barrel 11101 is guided to the camera head 11102 and enters the lens unit 11401. The lens unit 11401 is configured by combining a plurality of lenses including a zoom lens and a focus lens.

[0160] The imaging unit 11402 is composed of an imaging element. The imaging element constituting the imaging unit 11402 may be one (so-called single-plate type) or multiple (so-called multi-plate type). When the imaging unit 11402 is composed of a multi-plate type, for example, each imaging element may generate an image signal corresponding to each of RGB, and a color image may be obtained by combining the image signals. Alternatively, the imaging unit 11402 may be configured to have a pair of imaging elements for acquiring image signals for the right eye and the left eye corresponding to 3D (Dimensional) display. By performing 3D display, the surgeon 11131 can more accurately grasp the depth of the biological tissue in the surgical site. Note that when the imaging unit 11402 is composed of a multi-plate type, multiple lens units 11401 may be provided corresponding to each imaging element.

[0161] Furthermore, the imaging unit 11402 does not necessarily have to be provided in the camera head 11102. For example, the imaging unit 11402 may be provided inside the lens barrel 11101, immediately behind the objective lens.

[0162] The driving unit 11403 is configured by an actuator, and moves the zoom lens and focus lens of the lens unit 11401 by a predetermined distance along the optical axis under the control of the camera head control unit 11405. This allows the magnification and focus of the image captured by the imaging unit 11402 to be appropriately adjusted.

[0163] The communication unit 11404 is configured by a communication device for transmitting and receiving various information to and from the CCU 11201. The communication unit 11404 transmits the image signal obtained from the imaging unit 11402 to the CCU 11201 via the transmission cable 11400 as RAW data.

[0164] Furthermore, the communication unit 11404 receives a control signal for controlling the driving of the camera head 11102 from the CCU 11201, and supplies the control signal to the camera head control unit 11405. The control signal includes information on the imaging conditions, such as information specifying the frame rate of the captured image, information specifying the exposure value at the time of capturing the image, and / or information specifying the magnification and focus of the captured image.

[0165] The image capturing conditions such as the frame rate, exposure value, magnification, and focus may be appropriately specified by a user, or may be automatically set by the control unit 11413 of the CCU 11201 based on an acquired image signal. In the latter case, the endoscope 11100 is equipped with a so-called AE (Auto Exposure) function, AF (Auto Focus) function, and AWB (Auto White Balance) function.

[0166] The camera head control unit 11405 controls the driving of the camera head 11102 based on a control signal received from the CCU 11201 via the communication unit 11404.

[0167] The communication unit 11411 is configured with a communication device for transmitting and receiving various information to and from the camera head 11102. The communication unit 11411 receives an image signal transmitted from the camera head 11102 via the transmission cable 11400.

[0168] Furthermore, the communication unit 11411 transmits, to the camera head 11102, a control signal for controlling the driving of the camera head 11102. The image signal and the control signal can be transmitted by electrical communication, optical communication, or the like.

[0169] The image processing unit 11412 performs various types of image processing on the image signal, which is RAW data sent from the camera head 11102 .

[0170] The control unit 11413 performs various controls related to imaging of the surgical site etc. by the endoscope 11100 and display of the captured image obtained by imaging the surgical site etc. For example, the control unit 11413 generates a control signal for controlling the driving of the camera head 11102.

[0171] Further, the control unit 11413 causes the display device 11202 to display the captured image showing the surgical site, etc., based on the image signal that has been image-processed by the image processing unit 11412. At this time, the control unit 11413 may recognize various objects in the captured image using various image recognition techniques. For example, the control unit 11413 can recognize surgical tools such as forceps, specific living body parts, bleeding, mist when the energy treatment tool 11112 is used, etc., by detecting the shape and color of the edge of an object included in the captured image. When the control unit 11413 causes the display device 11202 to display the captured image, it may use the recognition result to superimpose various types of surgery support information on the image of the surgical site. By superimposing and presenting the surgery support information to the surgeon 11131, the burden on the surgeon 11131 can be reduced and the surgeon 11131 can proceed with the surgery reliably.

[0172] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 is an electrical signal cable for communication of electrical signals, an optical fiber for optical communication, or a composite cable of these.

[0173] Here, in the illustrated example, communication is performed wired using a transmission cable 11400, but communication between the camera head 11102 and the CCU 11201 may also be performed wirelessly.

[0174] An example of an endoscopic surgery system to which the technology according to the present disclosure can be applied has been described above. Of the configurations described above, the technology according to the present disclosure can be suitably applied to the imaging unit 11402 provided in the camera head 11102 of the endoscope 11100. By applying the technology according to the present disclosure to the imaging unit 11402, the imaging unit 11402 can be made smaller or have higher resolution, so that a small or high-resolution endoscope 11100 can be provided.

[0175] The present disclosure has been described above by giving embodiments and their modified examples, application examples, and application examples, but the present disclosure is not limited to the above-mentioned embodiments, etc., and various modifications are possible. Note that the effects described in this specification are merely examples. The effects of the present disclosure are not limited to the effects described in this specification. The present disclosure may have effects other than those described in this specification.

[0176] Furthermore, for example, the present disclosure can have the following configuration. (1) a first substrate having a pixel region including a plurality of sensor pixels that perform photoelectric conversion; a second substrate having a plurality of readout circuits provided for one or more of the sensor pixels, the readout circuits outputting pixel signals based on the charges output from the sensor pixels; a third substrate having a control circuit for controlling the sensor pixels and the readout circuit; Equipped with the first substrate, the second substrate, and the third substrate are laminated in this order; a laminated body including the first substrate and the second substrate includes an interlayer insulating film and a plurality of first bonding electrodes provided in the interlayer insulating film and in a region facing the pixel region; The sensor pixel and the readout circuit are electrically connected to each other by bonding the first bonding electrodes. Imaging device. (2) the stack has a plurality of first through-wires in a region surrounding the pixel region, The control circuit controls the sensor pixels and the readout circuit via the first through-wires. The imaging device described in (1). (3) the stack includes a plurality of second through-wires provided in the interlayer insulating film and in a region facing the pixel region, the second through-wires being provided for each of the readout circuits; Each of the second through-hole wirings is electrically connected to a region that serves as a reference potential in at least one of the first substrate and the second substrate. An imaging device according to (1) or (2). (4) the stack includes a plurality of third through-wires in the interlayer insulating film and in a region facing the pixel region, the third through-wires being electrically connected to the plurality of first bonding electrodes, respectively; Each of the second through wirings is disposed in a gap between two of the third through wirings adjacent to each other among the plurality of third through wirings. The imaging device according to (3). (5) the stack includes wiring electrodes in the interlayer insulating film that are electrically connected to the second through-hole wirings, The wiring electrodes are formed in a lattice shape so as to surround each of the first bonding electrodes. The imaging device according to (4). (6) The wiring electrode has a lattice shape in which a plurality of first connecting wires extending in a first arrangement direction of the plurality of sensor pixels and a plurality of second connecting wires extending in a second arrangement direction of the plurality of sensor pixels are formed on the same plane so as to intersect with each other. The imaging device according to (5). (7) The wiring electrode has a lattice shape formed on the same plane such that a plurality of first bonding wires extending in a first direction intersecting with the arrangement direction of the plurality of sensor pixels and a plurality of second bonding wires extending in a second direction intersecting with the arrangement direction of the plurality of sensor pixels and also intersecting with the first direction intersect with each other. The imaging device according to (5). (8) the stacked body includes a plurality of second bonding electrodes in the interlayer insulating film, the second bonding electrodes being electrically connected to the plurality of second through wirings, The second bonding electrodes are disposed in the gaps between two adjacent first bonding electrodes in the first bonding electrodes. The imaging device according to (4). (9) Each of the readout circuits has a negative feedback circuit including an operational amplifier. An imaging device according to any one of (1) to (8). (10) The reference potential of the first substrate is lower than the reference potential of the second substrate. The imaging device according to (9). (11) the stack has a plurality of fourth through-vias in a region surrounding the pixel region, the third substrate has a negative boost circuit; The negative boost circuit controls a reference potential of the first substrate via the fourth through-wires to make the reference potential of the first substrate lower than the reference potential of the second substrate. The imaging device according to (10). (12) the laminate includes a plurality of wiring electrodes in the interlayer insulating film, the wiring electrodes being electrically connected to the plurality of second through-hole wirings, and being disposed in gaps between two of the first bonding electrodes adjacent to each other, among the plurality of first bonding electrodes; The first bonding electrodes and the wiring electrodes have two or more types of shapes. An imaging device according to any one of (3) to (11). (13) At least some of the first bonding electrodes and the wiring electrodes have two different shapes. The imaging device according to (12). (14) At least a portion of the wiring electrodes is shorter than the first bonding electrodes; The wiring electrodes facing each other on the first substrate side and the second substrate side have the interlayer insulating film therebetween. The imaging device according to (12) or (13). (15) At least one of the length and the width of the wiring electrodes on the first substrate side is different from that on the second substrate side, The wiring electrodes facing each other on the first substrate side and the second substrate side have the interlayer insulating film therebetween. An imaging device according to any one of (12) to (14). (16) One of the plurality of wiring electrodes on the first substrate side and the plurality of wiring electrodes on the second substrate side is exposed at a bonding surface between the first substrate and the second substrate, and the other is formed within the interlayer insulating film. The imaging device according to (15). (17) a first substrate having a pixel region including a plurality of sensor pixels that perform photoelectric conversion; a second substrate including a plurality of readout circuits provided for one or more of the sensor pixels, the readout circuits outputting pixel signals based on charges output from the sensor pixels, and a control circuit for controlling the sensor pixels and the readout circuits; Equipped with the first substrate and the second substrate are stacked on each other; a laminated body including the first substrate and the second substrate includes an interlayer insulating film and a plurality of first bonding electrodes provided in the interlayer insulating film and in a region facing the pixel region; The sensor pixel and the readout circuit are electrically connected to each other by bonding the first bonding electrodes. Imaging device. (18) the stack has a plurality of first through-wires in a region surrounding the pixel region, The control circuit controls the sensor pixels via the first through-wires. The imaging device according to (17). (19) the stack includes a plurality of second through-wires provided in the interlayer insulating film and in a region facing the pixel region, the second through-wires being provided for each of the readout circuits; Each of the second through-hole wirings is electrically connected to a region that serves as a reference potential in at least one of the first substrate and the second substrate. The imaging device according to (17) or (18). (20) the stack includes a plurality of third through-wires in the interlayer insulating film and in a region facing the pixel region, the third through-wires being electrically connected to the plurality of first bonding electrodes, respectively; Each of the second through wirings is disposed in a gap between two of the third through wirings adjacent to each other among the plurality of third through wirings. The imaging device according to (19). (twenty one) the stack includes wiring electrodes in the interlayer insulating film that are electrically connected to the second through-hole wirings, The wiring electrodes are formed in a lattice shape so as to surround each of the first bonding electrodes. The imaging device according to (20). (twenty two) The wiring electrode has a lattice shape in which a plurality of first connecting wires extending in a first arrangement direction of the plurality of sensor pixels and a plurality of second connecting wires extending in a second arrangement direction of the plurality of sensor pixels are formed on the same plane so as to intersect with each other. The imaging device according to (21). (twenty three) The wiring electrode has a lattice shape formed on the same plane such that a plurality of first bonding wires extending in a first direction intersecting with the arrangement direction of the plurality of sensor pixels and a plurality of second bonding wires extending in a second direction intersecting with the arrangement direction of the plurality of sensor pixels and also intersecting with the first direction intersect with each other. The imaging device according to (21). (twenty four) the stacked body includes a plurality of second bonding electrodes in the interlayer insulating film, the second bonding electrodes being electrically connected to the plurality of second through wirings, The second bonding electrodes are disposed in the gaps between two adjacent first bonding electrodes in the first bonding electrodes. The imaging device according to (20).

[0177] According to an imaging device of an embodiment of the present disclosure, a plurality of sensor pixels are formed on a first substrate, a plurality of readout circuits are formed on a second substrate, and a control circuit is formed on a third substrate, thereby enabling further improvement of the dynamic range and further reduction of noise to be achieved. [Explanation of symbols]

[0178] Reference Signs List 1, 2...imaging device, 3...imaging system, 10...first substrate, 11...semiconductor substrate, 12...sensor pixel, 13...pixel region, 14...drive wiring, 15...FD through wiring, 16...VSS through wiring, 17...FD junction electrode, 18, 18a...VSS junction electrode, 18b...wiring, 19...insulating film, 20...second substrate, 21...semiconductor substrate, 22...readout circuit, 23...readout circuit region, 24...FD junction electrode, 25, 25a...VSS junction electrode, 25b...wiring, 26...FD Through wiring, 27...VSS through wiring, 28...insulating layer, 30...third substrate, 31...semiconductor substrate, 32...logic circuit, 32a...vertical drive circuit, 32b...column signal processing circuit, 32c...horizontal drive circuit, 32d...system control circuit, 33...booster circuit, 34...negative boost circuit, 36...insulating layer, 40...color filter layer, 41...p-well region, 42...through wiring, 43...through wiring, 44...through wiring, 45, 46...through wiring, 45a, 46a, 47a...openings, 45b, 46b, 47b...connection pads, 45c, 46c, 47c...through wiring, 45d, 46d, 47d...connection pads, 50...light receiving lens, 51, 61...gate insulating film, 52, 62...gate electrode, 53, 63...sidewall layer, 54, 64...silicon oxide film, 55, 65...silicon nitride film, 56, 66...insulating layer, 57, 58, 67, 68...through wiring, 69...impurity diffusion region, 71, 72, 73, 74...insulating layer, 80...second substrate, AMP... Amplification transistor, Cf...feedback capacitance, Cfd...capacitor, FD...floating diffusion, PD, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8...photodiode, RST...reset transistor, SEL...selection transistor, TR, TR1, TR2, TR3, TR4, TR5, TR6, TR7, TR8...transfer transistor, VDD...power supply potential, VSS, VSS1, VSS2...reference potential, VSL...vertical signal line.

Claims

[Claim 1] a first substrate having a pixel region including a plurality of sensor pixels that perform photoelectric conversion; a second substrate including a plurality of readout circuits each provided for one or more of the sensor pixels, the readout circuits outputting pixel signals based on charges output from the sensor pixels; a third substrate having a control circuit for controlling the sensor pixels and the readout circuit; Equipped with the first substrate, the second substrate, and the third substrate are stacked in this order; a laminated body including the first substrate and the second substrate includes an interlayer insulating film and a plurality of first bonding electrodes provided in the interlayer insulating film and in a region facing the pixel region; the sensor pixel and the readout circuit are electrically connected to each other by bonding the first bonding electrodes together; Each of the readout circuits has a negative feedback circuit including an operational amplifier; The reference potential of the first substrate is lower than the reference potential of the second substrate. Imaging device.

Images