Semiconductor Module
By using a metal substrate with moderate thickness in the LED module and adding an electrical insulation layer, combined with the layout optimization of the LED chip and connector, the problem of solder cracks and substrate deformation caused by thermal strain is solved, and the stable fixation of the LED chip and the stability of the substrate is achieved.
Patent Information
- Application Number
- JP2021174596
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- Filing Date
- 2021-10-26
- Publication Date
- 2025-05-09
- Estimated Expiration
- 2041-10-26
AI Technical Summary
In LED modules, thermal strain caused by thermal discharge of metal substrates can easily cause cracks in the solder, which causes the LED chip to detach from the substrate, and thinning the metal substrate to reduce thermal strain will cause the substrate to bend and deform.
The thickness of the metal substrate is between 0.5 mm and 1.2 mm, and an electrical insulation layer is added to the substrate to isolate the metal substrate and the circuit layer. At the same time, the layout of the LED chip and connector is optimized so that it is not prone to cracks when thermally strained, and the bending rigidity of the substrate is enhanced by the design of the connector.
It effectively suppresses the phenomenon that the LED chip is disengaged from the substrate due to thermal strain, and reduces the deformation of the metal substrate during manufacturing and installation, thereby improving the reliability and stability of the LED module.
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Abstract
Description
[Technical field]
[0001] The present invention relates to a semiconductor module. [Background technology]
[0002] As a light source module, an LED module having a configuration in which a plurality of LED elements (light emitting diode elements) and a connector connected to the plurality of LED elements are arranged on a circuit board is known (Patent Document 1). This LED module using a plurality of LED elements is used as a light source for lighting devices such as headlights of vehicles such as automobiles. [Prior art documents] [Patent documents]
[0003] [Patent Document 1] JP 2019-29058 A Summary of the Invention [Problem to be solved by the invention]
[0004] It is desirable that the solder that joins the LED elements in an LED module using multiple LED elements does not crack even after long-term use. However, when a metal base substrate based on a metal substrate is used as the circuit substrate of an LED module, the heat generated by the LED elements when emitting light causes the metal substrate to expand and contract, which may cause the solder to crack due to thermal stress. If the solder cracks due to thermal stress, the LED elements may become easily detached from the substrate. In order to suppress the thermal stress applied to the solder due to the expansion and contraction of the metal substrate, it is possible to reduce the thickness of the metal substrate. However, if the thickness of the metal substrate is reduced to a level where the thermal stress can be suppressed, the bending rigidity of the metal base substrate decreases, and the metal base substrate becomes more likely to warp and deform during the manufacturing of the LED module or during the screwing operation of the LED module.
[0005] This invention has been made in consideration of the above-mentioned circumstances, and its object is to provide a semiconductor module in which a plurality of semiconductor chips, such as LED elements, are bonded to a metal base substrate, in which the semiconductor chips are not easily detached from each other and the metal base substrate is not easily deformed. [Means for solving the problem]
[0006] In order to solve the above problems, a semiconductor module of the present invention has a metal base substrate, a connector, and a plurality of semiconductor chips, the metal base substrate includes a metal substrate having a thickness within a range of 0.5 mm to 1.2 mm, and a circuit layer provided on at least one surface of the metal substrate via an insulating layer, the plurality of semiconductor chips form a semiconductor chip arrangement section arranged along one direction and are arranged on the circuit layer, the connector has a housing section equipped with terminals, the housing section is arranged on the circuit layer so as to face the semiconductor chip arrangement section along the one direction, and a ratio B / A of a length B of the housing section in the one direction to a length A of the semiconductor chip arrangement section in the one direction is 1 or more. The flexural rigidity of the housing portion of the connector is equal to or greater than the flexural rigidity of the metal substrate. It is considered to be composed.
[0007] According to the semiconductor module configured as described above, the thickness of the metal substrate of the metal base substrate is within the range of 0.5 mm to 1.2 mm, so deformation due to expansion and contraction of the metal substrate caused by heat generation from the semiconductor chips is suppressed. This suppresses detachment of the semiconductor chips and deformation of the metal base substrate caused by heat generation from the semiconductor chips. In addition, the semiconductor chip arrangement section and the connector housing section are arranged on the circuit layer so as to face each other in one direction, and the ratio B / A of the length B of the connector housing section in one direction to the length A of the semiconductor chip arrangement section in one direction is 1 or more, so deformation such as warping of the metal base substrate during screw fastening work is also suppressed.
[0008] Here, in the semiconductor module of the present invention, the housing portion of the connector may have a bending rigidity equal to or greater than the bending rigidity of the metal substrate. In this case, the metal base board is reinforced by the connector and becomes less prone to bending, so deformation such as warping of the metal base board during the screw fastening operation is further suppressed. The bending stiffness can be calculated by (moment of inertia) x (Young's modulus), and the moment of inertia is calculated for a section perpendicular to the one direction of the semiconductor chip arrangement section. If the moment of inertia or Young's modulus cannot be determined individually, the housing section and metal substrate of the connector can be used as test pieces, and bending stresses can be applied under the same conditions using a three-point bending tester, and the smaller the amount of distortion, the greater the bending stiffness.
[0009] In the semiconductor module of the present invention, the number of the semiconductor chips arranged in the semiconductor chip arrangement portion may be three or more. In the semiconductor module of the present invention, even if the number of semiconductor chips arranged in the semiconductor chip arrangement section is three or more, deformation due to expansion and contraction of the metal substrate caused by heat generation from the semiconductor chips is suppressed, so that the multiple semiconductor chips are less likely to detach from each other and the metal base substrate is less likely to deform. Effect of the Invention
[0010] According to the present invention, it is possible to provide a semiconductor module in which a plurality of semiconductor chips are unlikely to come off and the metal base substrate is unlikely to deform. [Brief description of the drawings]
[0011] [Figure 1] 1 is a perspective view of a semiconductor module according to an embodiment of the present invention; [Diagram 2] FIG. 2 is a plan view of the semiconductor module shown in FIG. [Diagram 3] FIG. 2 is a cross-sectional view taken along line III-III in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0012] Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings. Fig. 1 is a perspective view of a semiconductor module according to an embodiment of the present invention, Fig. 2 is a plan view of the semiconductor module shown in Fig. 1, and Fig. 3 is a cross-sectional view taken along line III-III in Fig. 1. As shown in FIGS. 1 to 3, the semiconductor module 10 includes a metal base substrate 20, a connector 30, and a semiconductor chip arrangement section 50 on which seven semiconductor chips 51a to 51g are arranged.
[0013] The metal base substrate 20 includes a metal substrate 21, and a first circuit layer 23 and a second circuit layer 24 provided on at least one surface of the metal substrate 21 via an insulating layer 22. The first circuit layer 23 includes circuit wirings 23a-23h that are bonded to the semiconductor chips 51a-51g. The second circuit layer 24 includes connector fixing portions 24a, 24b that are bonded to the connector 30.
[0014] The metal substrate 21 is a member that serves as the base of the metal base substrate 20 . The thickness of the metal substrate 21 is within the range of 0.5 mm to 1.2 mm. With a thickness of 0.5 mm or more, the strength of the metal substrate 21 is increased, and deformation such as warping due to heat can be suppressed. Furthermore, with a thickness of 1.2 mm or less, the amount of volume change of the metal substrate 21 due to expansion and contraction due to heat is reduced.
[0015] The metal substrate 21 is preferably a copper substrate, an aluminum substrate, or an iron substrate. The copper substrate is made of copper or a copper alloy. The aluminum substrate is made of aluminum or an aluminum alloy. The iron substrate is made of iron or an iron alloy. The iron alloy includes carbon steel.
[0016] The insulating layer 22 is a layer for insulating the metal substrate 21 from the circuit layers (first circuit layer 23, second circuit layer 24). The insulating layer 22 also has a heat transfer function for transferring heat generated in the semiconductor chips 51a to 51g to the metal substrate 21, and a stress relaxation function for absorbing the volumetric change of the metal substrate 21 due to heat and relaxing the stress applied to the bonding material bonding the first circuit layer 23 to the semiconductor chips.
[0017] The insulating layer 22 is preferably formed from an insulating resin composition containing an insulating resin and an inorganic filler. By forming the insulating layer 22 from an insulating resin composition containing an insulating resin having high insulating properties and an inorganic filler having high thermal conductivity, it is possible to improve the heat transfer function while maintaining the insulation properties.
[0018] The insulating resin may be, for example, a polyimide resin, a polyamide-imide resin, or a mixture thereof. These resins have excellent properties such as insulation, voltage resistance, chemical resistance, and mechanical properties, and therefore these properties of the metal base substrate 20 are improved.
[0019] Examples of inorganic fillers that can be used include alumina (Al2O3) particles, alumina hydrate particles, aluminum nitride (AlN) particles, silica (SiO2) particles, silicon carbide (SiC) particles, titanium oxide (TiO2) particles, boron nitride (BN) particles, etc. The average particle size of the inorganic filler is preferably within the range of 0.1 μm to 20 μm.
[0020] The inorganic filler content of insulating layer 22 is preferably within the range of 30 volume % or more and 85 volume % or less. When the inorganic filler content is 30 volume % or more, the heat transfer function of insulating layer 22 is improved. On the other hand, when the inorganic filler content is 85 volume % or less, the heat transfer function of insulating layer 22 is improved. From the viewpoint of improving the heat transfer function of insulating layer 22, it is particularly preferable that the inorganic filler content is within the range of 50 volume % or more and 80 volume % or less.
[0021] The thickness of the insulating layer 22 is preferably 100 μm or less. By making the thickness of the insulating layer 22 100 μm or less, the heat transfer function of the insulating layer 22 is improved, and the heat generated in the semiconductor chips 51a to 51g can be efficiently transferred to the metal substrate 21. The thickness of the insulating layer 22 is preferably 30 μm or more. By making the thickness of the insulating layer 22 30 μm or more, the metal substrate 21 and the circuit layers (first circuit layer 23, second circuit layer 24) can be reliably insulated, the stress relaxation function of the insulating layer 22 is improved, and the stress applied to the bonding material 40 can be reduced. The thickness of the insulating layer 22 is preferably 50 μm or more, and preferably 80 μm or less.
[0022] The insulating layer 22 has an elastic modulus E R (Unit: GPa) vs. thickness T R (Unit: mm) Ratio T R / E R is in the range of 30 to 1000, and the thermal conductivity C R (Unit: W / mK) vs. film thickness T R (Unit: mm) Ratio T R / C R It is preferable that T is in the range of 2 or more and 40 or less. R / E R is preferably 30 or more, and more preferably 100 or more. R / E R is preferably 300 or less, and particularly preferably 200 or less. R / C R is preferably 3 or more, and more preferably 5 or more. R / C R is preferably 30 or less, and more preferably 20 or less. When the insulating layer 22 is a laminate of two or more layers, the T R / E R The sum of is within the above range, and T R / C R It is preferable that the T of the insulating layer 22 is within the above range. R / E RBy setting T within the above range, the stress relaxation function is improved, and the semiconductor chips 51a to 51g are prevented from coming off due to heat generation, thereby improving reliability. R / C R When the thickness is within the above range, the heat transfer function is improved, and the heat generated by the semiconductor chips 51a to 51g can be efficiently released to the outside.
[0023] Metals such as copper, aluminum, and gold can be used as the material of the first circuit layer 23 and the second circuit layer 24. The film thickness of the first circuit layer 23 and the second circuit layer 24 is preferably in the range of 2 μm to 200 μm, and particularly preferably 80 μm or less.
[0024] The connector 30 includes a housing portion 31 and support members 33a, 33b arranged on both ends of the housing portion 31. The support members 33a, 33b are fixed to support member fixing portions 32 arranged on both ends of the housing portion 31. The support members 33a, 33b are joined to the connector fixing portions 24a, 24b via a bonding material 40. The housing portion 31 includes a terminal portion 34. The terminal portion 34 has eight terminals 34a to 34h. The eight terminals 34a to 34h are respectively joined to the eight circuit wirings 23a to 23h via the bonding material 40. As the bonding material 40, for example, a solder material such as Sn-Ag, Sn-Cu, Sn-In, or Sn-Ag-Cu (so-called lead-free solder material) can be used.
[0025] The housing portion 31 has external terminals (not shown) connected to the terminals 34a to 34h. The housing portion 31 of the connector 30 is connected to a power source and a control device. The shape of the housing portion 31 is a rectangle having a longitudinal direction in a plan view.
[0026] The semiconductor chips 51a to 51g may be an LED element, an LED chip, an LED-CSP (LED-Chip Size Package), a MOSFET (Metal-oxide-semiconductor field effect transistor), an IGBT (Insulated Gate Bipolar Transistor), or an LSI (Large Scale Integration).
[0027] Each of the semiconductor chips 51a to 51g is connected to two circuit wirings. The semiconductor chip 51a is connected to the circuit wirings 23a and 23b, the semiconductor chip 51b is connected to the circuit wirings 23b and 23c, the semiconductor chip 51c is connected to the circuit wirings 23c and 23d, the semiconductor chip 51d is connected to the circuit wirings 23d and 23e, the semiconductor chip 51e is connected to the circuit wirings 23e and 23f, the semiconductor chip 51f is connected to the circuit wirings 23f and 23g, and the semiconductor chip 51g is connected to the circuit wirings 23g and 23h.
[0028] In the semiconductor module 10 of this embodiment, the semiconductor chips 51a to 51g form a semiconductor chip arrangement portion 50 arranged along one direction (X direction) (hereinafter, the direction in which the semiconductor chips 51a to 51g are arranged may be referred to as the arrangement direction).
[0029] On the other hand, the connector 30 is arranged so that the housing portion 31 faces the semiconductor chip arrangement portion 50 along the arrangement direction (X direction) of the semiconductor chip arrangement portion 50. The connector 30 is preferably arranged so that the longitudinal surface of the housing portion 31 faces the semiconductor chip arrangement portion 50. The ratio B / A of the length B (the longitudinal length of the housing portion 31) in the arrangement direction of the housing portion 31 of the connector 30 to the length A in the arrangement direction of the semiconductor chip arrangement portion 50 is set to be 1 or more (see FIG. 2). The ratio B / A is preferably in the range of 1.1 to 2.0, and particularly preferably in the range of 1.3 to 1.7. The connector 30 is preferably arranged in the vicinity of the semiconductor chip arrangement portion 50. The shortest distance between the housing portion 31 of the connector 30 and the semiconductor chip arrangement portion 50 may be, for example, in the range of 0.1 mm to 50 mm, and is preferably in the range of 1 mm to 30 mm. The length B in the arrangement direction of the connector 30 (the longitudinal length of the housing portion 31) is the distance between the support members 33a and 33b. In this embodiment, the distance between the support members 33a and 33b and the length of the housing portion 31 are the same.
[0030] The flexural rigidity of the housing portion 31 is preferably equal to or greater than the flexural rigidity of the metal substrate 21. The ratio of the flexural rigidity of the metal substrate 21 to the flexural rigidity of the housing portion 31 is preferably within a range of 2 to 50, more preferably 3 to 30. As the connector 30, a commercially available connector that is used as a connector for semiconductor modules can be used.
[0031] According to the semiconductor module 10 of the present embodiment configured as described above, the thickness of the metal substrate 21 of the metal base substrate 20 is within a range of 0.5 mm to 1.2 mm, so that deformation of the metal substrate 21 due to the heat generated by the semiconductor chips 51a to 51g caused by expansion and contraction is suppressed. This suppresses the detachment of the semiconductor chips 51a to 51g and deformation of the metal base substrate 20 due to the heat generated by the semiconductor chips 51a to 51g. In addition, the semiconductor chip arrangement portion 50 and the housing portion 31 of the connector 30 are arranged to face each other along the arrangement direction, and the ratio B / A of the length B in the arrangement direction of the housing portion 31 of the connector 30 to the length A in the arrangement direction of the semiconductor chip arrangement portion 50 is 1 or more, so that deformation such as warping of the metal base substrate during screwing is also suppressed.
[0032] In the semiconductor module 10 of this embodiment, when the bending rigidity of the housing portion 31 of the connector 30 is equal to or greater than the bending rigidity of the metal substrate 21, the metal base substrate 20 is reinforced by the connector 30, making the metal base substrate 20 less likely to bend, thereby further suppressing deformation such as warping of the metal base substrate during the screwing operation.
[0033] Although the embodiment of the present invention has been described above, the present invention is not limited to this, and can be modified as appropriate without departing from the technical concept of the invention. For example, in the semiconductor module 10 of this embodiment, the number of semiconductor chips 51a-51g arranged in the semiconductor chip arrangement section 50 is seven, but there is no particular limit to the number of semiconductor chips 51a-51g. However, the number of semiconductor chips 51a-51g arranged in the semiconductor chip arrangement section 50 is preferably three or more.
[0034] In addition, in the semiconductor module 10 of this embodiment, the semiconductor chip arrangement portion 50 is in one row, but there may be multiple rows of the semiconductor chip arrangement portion 50. In the semiconductor module 10 of this embodiment, the housing portion 31 of the connector 30 is in a rectangular shape in a plan view, but there is no limitation on the shape of the housing portion 31 as long as the ratio B / A of the length B in the arrangement direction of the housing portion 31 to the length A in the arrangement direction of the semiconductor chip arrangement portion 50 is 1 or more. The shape of the housing portion 31 may be, for example, a square shape in a plan view, or a rounded shape such as a circle or an oval. EXAMPLES
[0035] [Example 1] (Preparation of metal base substrate) A polyimide solution with a polyimide concentration of 10% by mass was prepared by mixing polyimide with NMP (N-methyl-2-pyrrolidone) and dissolving the polyimide. An α-alumina particle dispersion with an α-alumina particle concentration of 10% by mass was prepared by mixing α-alumina powder (crystal structure: single crystal, average particle size: 0.3 μm) with NMP and subjecting the mixture to ultrasonic treatment for 30 minutes. The polyimide solution and the α-alumina particle dispersion were mixed in such a ratio that the α-alumina concentration was 60% by volume. The mixture obtained was subjected to a dispersion treatment by repeating a high-pressure injection treatment at a pressure of 50 MPa 10 times using a Starburst manufactured by Sugino Machine Co., Ltd., to prepare an α-alumina particle-dispersed polyimide solution. The α-alumina concentration is the content of α-alumina particles in the solid matter generated when the α-alumina particle-dispersed polyimide solution is heated and dried.
[0036] A coating film was formed on the surface of a copper substrate having a thickness of 0.8 mm and a size of 35 mm x 35 mm by applying an α-alumina particle-dispersed polyimide solution by a bar coating method. The copper substrate on which the coating film was formed was then placed on a hot plate, heated from room temperature to 60°C at 3°C / min, heated at 60°C for 100 minutes, and then further heated to 120°C at 1°C / min, and heated at 120°C for 100 minutes to dry the coating film. The copper substrate was then heated at 250°C for 1 minute, and then heated at 400°C for 1 minute. In this way, a copper substrate with an insulating layer was prepared in which an insulating layer made of a polyimide resin in which α-alumina single crystal particles were dispersed was formed on the surface of the copper substrate. The thickness of the insulating layer was set to 30 μm. The elastic modulus E of the insulating layer at 100°C was R (Unit: GPa) and thermal conductivity C R (unit: W / mK) and T R / E R and T R / C R As a result of calculating R / E R is 111, T R / C R was 15.
[0037] A 70 μm thick copper foil (T4X: manufactured by Fukuda Metal Foil and Powder Co., Ltd.) was laminated on the insulating layer of the obtained metal substrate with insulating layer. Next, the obtained laminate was heated in a vacuum at a pressure bonding temperature of 300° C. for 120 minutes while applying a pressure of 5 MPa using a carbon jig, thereby bonding the insulating layer and the copper foil. In this way, a metal base substrate was produced in which the copper substrate, the insulating layer, and the copper foil were laminated in this order.
[0038] (LED module production) The copper foil of the metal base substrate was etched to create a pattern, forming the first and second circuit layers. Next, a solder resist was applied on the first and second circuit layers, and lead-free solder was applied on top of that to a thickness of 100 μm. Seven LED elements (Oslon compact) were placed on the lead-free solder applied to the first circuit layer, spaced 0.5 mm apart, to form a semiconductor chip array section (length A in the array direction: 20 mm) arranged in one direction, and a connector (model number SM08B1-CPTK-1A-TB, manufactured by Japan Solderless Terminal Mfg. Co., Ltd., length B in the longitudinal direction: 30 mm) was placed on the lead-free solder applied to the second circuit layer, with the longitudinal surface facing the semiconductor array section. After that, reflow was performed to fabricate an LED module. The semiconductor chip array section was placed in the center of the metal base substrate, and the shortest distance between the connector and the semiconductor chip array section was 3.3 mm.
[0039] [Inventive Examples 2 to 3, Comparative Example 1] An LED module was produced in the same manner as in Example 1 of the present invention, except that a connector having a longitudinal length B of the size shown in Table 1 below was used.
[0040] [Example 4] An LED module was fabricated in the same manner as in Example 1 of the present invention, except that a copper substrate having a thickness of 0.8 mm and a size of 50 mm×50 mm was used.
[0041] [Examples 5 to 7 of the present invention, Comparative Examples 2 to 3] An LED module was produced in the same manner as in Example 1 of the present invention, except that a copper substrate having a thickness as shown in Table 1 below was used.
[0042] [Example 8] An LED module was fabricated in the same manner as in Example 1 of the present invention, except that an aluminum substrate having a thickness of 1.0 mm and a size of 35 mm×35 mm was used instead of the copper substrate.
[0043] [evaluation] The warpage of the LED modules obtained in Inventive Examples 1 to 8 and Comparative Examples 1 to 3 and the reliability (crack resistance rate) of the metal base substrate were measured by the following method. The results are shown in Table 1.
[0044] (warp) The LED module was placed on a flat substrate, and the gap between the substrate and the metal base substrate of the LED module was measured at room temperature using a gap gauge. The gap was measured at the four corners of the metal base substrate. The maximum gap measured at the four corners was taken as the warpage.
[0045] (Reliability) The LED module (test specimen) was subjected to 3,000 cycles of thermal cycles, with each cycle being -30°C x 30 minutes to 105°C x 30 minutes. After thermal cycles, the test specimen was embedded in resin, and the cross section was polished to observe the specimen, and the length (mm) of the cracks that occurred in the solder layer was measured. The crack resistance rate was calculated from the length of one side of the solder layer and the measured crack length using the following formula. Crack resistance rate (%) = {(length of one side of solder layer (25 mm) - 2 x crack length) / length of one side of bonding layer (25 mm)} x 100 The reliability was rated as ◯ when the crack resistance rate was 80% or more, and as × when the crack resistance rate was less than 80%.
[0046] [Table 1]
[0047] From the results of Table 1, in the present invention examples 1 to 8 in which the thickness of the metal substrate and the ratio B / A of the length B of the connector in the longitudinal direction to the length A in the arrangement direction of the semiconductor chip arrangement part are within the range of the present invention, the warpage was small and the reliability was good. In contrast, in the comparative example 1 in which B / A is smaller than the range of the present invention, the warpage was large. This is considered to be because the reinforcement of the metal base substrate by the connector is insufficient, and the copper substrate is deformed by heating due to reflow during the manufacture of the LED module. In the comparative example 2 in which the thickness of the copper substrate is thinner than the range of the present invention, the warpage was large. This is considered to be because the thickness of the copper substrate is too thin, the connector cannot sufficiently reinforce the metal base substrate, and the copper substrate is deformed by heating due to reflow during the manufacture of the LED module. On the other hand, in the comparative example 3 in which the thickness of the copper substrate is thicker than the range of the present invention, the reliability was reduced. This is considered to be because the thickness of the copper substrate is too thick, the deformation amount of the copper substrate due to the thermal cycle is large, and the stress applied to the solder is large. [Explanation of symbols]
[0048] 10 Semiconductor Module 20 Metal base board 21 Metal Substrate 22 Insulating layer 23 1st circuit layer 23a, 23b, 23c, 23d, 23e, 23f, 23g, 23h Circuit wiring 24 2nd circuit layer 24a, 24b Connector fixing part 30 Connectors 31 Housing section 32 Support member fixing part 33a, 33b Support member 34 Terminal section 34a, 34b, 34c, 34d, 34e, 34f, 34g, 34h terminals 40 Bonding material 50 Semiconductor chip array section 51a, 51b, 51c, 51d, 51e, 51f, 51g Semiconductor chips
Claims
1. The semiconductor device includes a metal base substrate, a connector, and a plurality of semiconductor chips. The metal base substrate includes a metal substrate having a thickness in the range of 0.5 mm to 1.2 mm, and a circuit layer provided on at least one surface of the metal substrate via an insulating layer, the semiconductor chips are arranged on the circuit layer to form a semiconductor chip arrangement portion in which the semiconductor chips are arranged in one direction; the connector has a housing portion having terminals, and the housing portion is disposed on the circuit layer so as to face the semiconductor chip arrangement portion along the one direction; a ratio B / A of a length B of the housing portion in the one direction to a length A of the semiconductor chip arrangement portion in the one direction is 1 or more; A semiconductor module, wherein the flexural rigidity of the housing portion of the connector is equal to or greater than the flexural rigidity of the metal substrate.
2. 2. The semiconductor module according to claim 1, wherein the number of said semiconductor chips arranged in said semiconductor chip arrangement section is three or more.
Citation Information
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