Integrated capacitor filter and integrated capacitor filter with varistor function - Patents.com

Abstract

To provide an integrated multi-terminal multilayer ceramic device with three or more capacitive elements and a method of providing the same that result in improved miniaturization as well as increased functionality and / or operational characteristics.SOLUTION: In a multi-terminal multilayer ceramic device that has three or more capacitive elements, two (654, 656) of the capacitive elements may be in series, with a third capacitive element 658 being in parallel. The device may be packaged as an overmolded three-leaded (648, 650, 652) component, or can be mounted as an SMD (surface mount device). The device may also be combined with a separate varistor 660 in a stacked arrangement of leaded components.SELECTED DRAWING: Figure 6B

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of U.S. Provisional Patent Application No. 62 / 455,076, filed February 6, 2017, which is incorporated by reference in its entirety. [Background technology]

[0002]

[0002] For some time now, the design of various electronic components has been motivated by a general industry trend toward miniaturization as well as increased functionality. In light of this, there exists a need for smaller electronic components with improved operating characteristics. For example, some applications can benefit from the equivalent of multiple components, but the amount of space that such electronic components can occupy on a circuit board is severely limited.

[0003]

[0003] Multilayer ceramic devices, such as multilayer ceramic capacitors or varistors, are often constructed using multiple dielectric electrode layers in a stacked arrangement. During manufacture, the layers may be pressed and formed into a vertically stacked structure. Multilayer ceramic devices may contain a single element or multiple elements. Examples of previously issued U.S. patents or published U.S. patent applications include U.S. Pat. No. 9,025,306, U.S. Pat. No. 6,223,311, and U.S. Pat. No. 6,223,311. No. Nos. 7,307,829 and 5,870,273, and U.S. Patent Application Publication No. 2012 / No. 0188681, No. 2009 / No. 0154055, No. 2009 / No. 0147440 and No. 2006 / No. 0262490, all of which are incorporated by reference into this disclosure for all purposes and as if fully set forth herein. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] U.S. Pat. No. 9,025,306 [Patent Document 2] U.S. Patent No. 7,307,829 [Patent Document 3] U.S. Patent No. 5,870,273 [Patent Document 4] US Patent Application Publication No. 2012 / 0188681 [Patent Document 5] US Patent Application Publication No. 2009 / 0154055 [Patent Document 6] US Patent Application Publication No. 2009 / 0147440 [Patent Document 7] US Patent Application Publication No. 2006 / 0262490 Summary of the Invention [Problem to be solved by the invention]

[0005]

[0004] It would therefore be advantageous if devices and corresponding methods could be provided that result in improved miniaturization and increased functionality and / or operating characteristics. [Means for solving the problem]

[0006] According to one embodiment of the present invention, a multi-terminal multi-layer ceramic device having a plurality of capacitance elements is disclosed, the multi-terminal multi-layer ceramic device comprising a body having a plurality of cooperating layers including electrode layers for forming an integrated capacitance structure, a first region of the electrode layers forming a split feed-through type structure of two respective capacitors, a second region of the electrode layers forming an overlap type structure of a multi-layer ceramic capacitor, a first pair of terminations having opposite polarity outside the body, and a second pair of terminations having the same polarity outside the body, the first pair of terminations being in series connection with the second region capacitor, and at least one of the first pair of terminations and the second pair of terminations being in parallel connection with the two respective capacitors of the first region, thus integrating a plurality of capacitance elements into a single package device.

[0007] According to another embodiment of the present invention, an integrated capacitor filter with varistor function is disclosed, which includes a discrete multi-terminal multi-layer ceramic capacitor device having a plurality of capacitive elements, the discrete multi-terminal multi-layer ceramic capacitor device comprising a body having a plurality of cooperating layers including electrode layers to form an integrated capacitive structure, a first pair of capacitor device terminations having opposite polarity outside the body, a second pair of capacitor device terminations having the same polarity outside the body, a first region of the electrode layers forming two respective capacitors, and a second region of the electrode layers forming a multi-layer ceramic capacitor received in series connection between the first pair of terminations, a discrete varistor comprising a body, the discrete varistor having a pair of varistor terminations having opposite polarity outside the varistor body, a first lead and a second lead attached to the first pair of capacitor device terminations and the pair of varistor terminations, respectively, and a third lead attached to at least one of the second pair of capacitor device terminations.

[0008] According to another embodiment of the present invention, a method for providing a multi-terminal multi-layer ceramic device having a plurality of capacitive elements is disclosed, the method comprising the steps of: providing a body having a plurality of cooperating layers including electrode layers used to form an integrated capacitive structure, forming a split feed-through type structure of two respective capacitors in a designated first region of the electrode layers, forming an overlap type structure of multi-layer ceramic capacitors in a designated second region of the electrode layers, adding a first pair of terminations external to each of a pair of opposing faces of the body, the second region capacitors being connected in series between the first pair of terminations, and adding a second pair of terminations having the same polarity external to at least a portion of each of another pair of opposing faces of the body, the second pair of terminations and at least one of the first pair of terminations being connected in parallel with the two respective capacitors of the first region, thus integrating a plurality of capacitive elements into a single package device.

[0009]

[0008] Other features and aspects of the present invention are discussed in greater detail below.

[0010] A complete and enabling description of the presently disclosed subject matter, including the best mode thereof, directed to one of ordinary skill in the art, is set forth in this specification, which makes reference to the accompanying figures. [Brief description of the drawings]

[0011] [Figure 1A] 1 is an external perspective view of an exemplary embodiment of a multi-terminal, multi-layer device for use in SMD configurations and the like in accordance with the presently disclosed subject matter. [Figure 1B] FIG. 1B is a perspective view of an exemplary embodiment of the application FIG. 1A, partially in perspective to illustrate multiple components formed therein by a multi-layer structure. [Figure 1C]

[0012] FIG. 1B is a perspective view of an exemplary embodiment of the application of FIG. 1A with the addition of a lead configuration. [Figure 1D]

[0013] 1B is a schematic diagram of an exemplary embodiment of the application FIG. 1A. [Diagram 2]

[0014] FIG. 2 is a perspective view of another exemplary embodiment of the presently disclosed subject matter, partially in perspective to illustrate multiple components formed therein by a multi-layer structure. [Figure 3A]

[0015] 1 is an exterior perspective view of another exemplary embodiment of a multi-terminal, multi-layer device in accordance with the presently disclosed subject matter. [Figure 3B]

[0016] FIG. 3B is a perspective view of an example embodiment of the application FIG. 3A, partially in perspective to illustrate multiple components formed therein by a multi-layer structure. [Figure 3C]

[0017] 3B is a schematic diagram of an exemplary embodiment of the application FIG. 3A. [Figure 4A]

[0018] FIG. 2 is a perspective view of yet another exemplary embodiment of the presently disclosed subject matter, partially in perspective to illustrate multiple components formed therein by a multi-layer structure. [Figure 4B]

[0019] FIG. 4B is a top view of selected layers within the multi-layer structure of the exemplary embodiment of FIG. 4A. [Figure 4C]

[0020] 4B is a schematic diagram of an exemplary embodiment of the application FIG. 4A. [Figure 5A]

[0021] FIG. 2 is a perspective view of yet another exemplary embodiment of the presently disclosed subject matter, partially in perspective to illustrate multiple components formed therein by a multi-layer structure. [Figure 5B]

[0022] FIG. 5B is a top view of selected layers within the multi-layer structure of the exemplary embodiment of FIG. 5A. [Figure 6A]

[0023] FIG. 1 is an external perspective view of an exemplary embodiment of a multi-terminal multi-layer device in accordance with the presently disclosed subject matter for use in a stack configuration with varistor devices, all with added leads as illustrated. [Figure 6B]

[0024] 6B is a schematic diagram of an exemplary embodiment of the application of FIG. 6A. [Figure 6C]

[0025] 1 is an exterior perspective view of an exemplary embodiment of a multi-terminal, multi-layer device in accordance with the presently disclosed subject matter; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012]

[0026] Repeated use of reference characters throughout the present specification and the accompanying drawings is intended to represent the same or similar features, elements or steps thereof.

[0013]

[0027] Reference will now be made in detail to various embodiments of the invention, one or more examples of which are set forth below. Each example is provided by way of a non-limiting illustration of the invention. Indeed, it will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the scope or spirit of the invention. For example, features illustrated or described as part of one embodiment may be used on another embodiment to yield still further embodiments. It is therefore intended that the present invention encompass such modifications and variations as come within the scope of the appended claims and their equivalents.

[0014]

[0028] Generally speaking, the present invention is directed to filter devices such as integrated capacitor filters, and in particular integrated capacitor filters with varistor functionality. In general, a multi-terminal multi-layer ceramic device is provided. In one embodiment, the device may comprise discrete varistors.

[0015]

[0029] Generally, a multilayer ceramic device, such as a multilayer ceramic capacitor, can include a ceramic body having external electrodes. The ceramic body is fabricated by sintering a laminated body formed of alternating stacked dielectric layers and internal electrodes. Adjacent internal electrodes of each pair face each other with a dielectric layer therebetween and are each electrically coupled to a different external electrode.

[0016]

[0030] In general, the dielectric layer may be constructed of any material commonly used in the art. For example, the dielectric layer may be constructed of a ceramic material containing titanate as a main component. The titanate may include, but is not limited to, barium titanate (BaTiO3). The ceramic material may also contain oxides of rare earth metals and / or compounds of acceptor-type elements such as Mn, V, Cr, Mo, Fe, Ni, Cu, Co, and the like. The titanate may also contain MgO, CaO, Mn3O4, Y2O3, V2O5, ZnO, ZrO2, Nb2O5, Cr2O3, Fe2O3, P2O5, SrO, Na2O, K2O, Li2O, SiO2, WO3, and the like. The ceramic material may also include other additives, organic solvents, softeners, binders, dispersants, and the like in addition to ceramic powders.

[0017]

[0031] In general, the internal electrodes may be constructed of any material commonly used in the art. For example, the internal electrodes may be formed by sintering a conductive paste whose main component is a precious metal material. These materials may include, but are not limited to, palladium, palladium-silver alloy, nickel, and copper. For example, in one embodiment, the electrodes may be constructed of nickel or a nickel alloy. The alloy may contain one or more of Mn, Cr, Co, Al, W, and the like, and the Ni content in the alloy is preferably 95% by weight or more. The Ni or Ni alloy may contain various trace elements of 0.1% by weight or less, such as P, C, Nb, Fe, Cl, B, Li, Na, K, F, S, and the like.

[0018]

[0032] The ceramic body may be formed using any method commonly known in the art, for example, by forming a laminated body using alternating stacked ceramic sheets and patterned internal electrodes, removing the binder from the laminated body, sintering the debindered laminated body in a non-oxidizing atmosphere at an elevated temperature ranging from 1200° C. to 1300° C., and re-oxidizing the sintered laminated body in an oxidizing atmosphere.

[0019]

[0033] In general, a varistor may include a ceramic body having an external electrode, which is manufactured by sintering a laminate body formed of alternating ceramic layers and internal electrodes, with adjacent internal electrodes of each pair facing each other with a ceramic layer therebetween and each electrically coupled to a different external electrode.

[0020]

[0034] In general, the ceramic layer can be constructed of any material commonly used in the art. For example, the ceramic layer can be constructed of a metal oxide. In particular, the metal oxide can include zinc oxide, and can also include other oxides, such as oxides of bismuth, cobalt, antimony, manganese, chromium, boron, and / or tin.

[0021]

[0035] In general, the internal electrodes may be constructed of any material commonly used in the art. For example, the internal electrodes may be formed by sintering a conductive paste whose main component is a precious metal material. These materials may include, but are not limited to, palladium, palladium-silver alloy, silver, nickel, and copper. For example, in one embodiment, the electrodes may be constructed of nickel or a nickel alloy. The alloy may contain one or more of Mn, Cr, Co, Al, W, and the like, and the Ni content in the alloy is preferably 95% by weight or more. The Ni or Ni alloy may contain various trace elements of 0.1% by weight or less, such as P, C, Nb, Fe, Cl, B, Li, Na, K, F, S, and the like.

[0022]

[0036] Without intending to be limited by theory, a capacitor is an electrical component that stores electrical energy in an electric field. Without intending to be limited by theory, a varistor is an electrical component that has an electrical resistance that can change with an applied voltage, making the varistor a voltage dependent resistor. Capacitors and resistors can be combined to provide an RC circuit, i.e., a filter.

[0023]

[0037] In one embodiment, a multi-terminal multilayer ceramic device is provided having three or more capacitive elements. The three capacitors may include two series capacitors, and these two capacitors are in parallel with a third element. The device may be provided in parallel with a discrete varistor. The multi-terminal multilayer ceramic device may be a co-fired device and / or the discrete varistor may be a discrete co-fired varistor.

[0024]

[0038] In one embodiment, the device of the present disclosure may be packaged in an overmolded three-lead component. In another embodiment, the device of the present disclosure may alternatively be packaged as a surface mount device (SMD). With respect to the overmolded three-lead component, the overmolded three-lead component may provide an advantage in that it may be simply assembled by replacing three single discrete caps with a single integrated capacitance device. With respect to the surface mount device, the surface mount device may provide an advantage in that it may provide a replacement of multiple discrete components on a printed circuit board (PCB), thereby saving space and in some instances reducing inductance.

[0025]

[0039] Some presently disclosed exemplary embodiments provide for integration of capacitive elements in a single co-fired package. In yet another alternative, the addition of a varistor element provides transient protection.

[0026]

[0040] Additionally, there may be other advantages. For example, a substantial reduction in device size may be obtained, which may result in fewer solder connections, which in turn may be more reliable. Another advantage is that the resulting integrated device may have much less parasitic inductance than a corresponding number of discrete devices. Additionally, the lead wires allow for installation of the exemplary device within the motor housing. Such devices may also be constructed as SMDs.

[0027]

[0041] Another aspect of the present disclosure is that EMI and EMI / ESD circuit protection may be obtained that may be particularly useful in certain applications, such as automotive applications. The presently disclosed subject matter may also be useful in motor start-stop applications.

[0028]

[0042] One embodiment of the present disclosure relates to a multi-terminal multi-layer ceramic device, such as a multi-terminal co-fired multi-layer ceramic device, having a plurality of capacitive elements. The device comprises a body, such as a generally rectangular six-sided body, having a plurality of cooperating layers including electrode layers that will form an integrated capacitive structure, a first region of such electrode layers forming a split feed-through type structure of two respective capacitors, a second region of such electrode layers forming an overlap type structure of a multi-layer ceramic capacitor, a first pair of terminations having an opposite polarity outside such body, and a second pair of terminations having the same polarity outside such body. Moreover, such first pair of terminations are preferably in series with such second region capacitors, and at least one of such first pair of terminations and such second pair of terminations are in parallel with such two respective capacitors of such first region, such that a plurality of capacitive elements are integrated into a single package device, such as a single package co-fired device.

[0029]

[0043] In one embodiment, such a first region of such an electrode layer may comprise at least a pair of layers, such as generally rectangular layers, located on opposite sides of a generally cross-shaped layer having respective front and rear extending edges that respectively contact such second pair of terminal ends, and having side extending edges that respectively contact such first pair of terminal ends.

[0030]

[0044] In another embodiment, such second region of such electrode layer may comprise at least paired alternating layers in an overlapping configuration, with an extended portion of each of these alternating layers contacting each of the terminal ends of such first pair.

[0031]

[0045] In one embodiment, two such respective capacitors in such first region may be in series with each other and either may be in parallel with such multi-layer ceramic capacitor in such second region.

[0032]

[0046] In another embodiment, such first pair of terminations and second pair of terminations may be disposed on respective opposite pairs of sides of such body and respectively wrap therefrom to a designated bottom side of such body to form a surface mounted device (SMD) configuration for such device.

[0033]

[0047] According to one embodiment, a first lead and a second lead may be attached to each of such a first pair of terminal ends, and a third lead may be attached to at least one of such second pair of terminal ends.

[0034]

[0048] According to another embodiment, such a multi-terminal multilayer ceramic device may further comprise a third region of such electrode layer forming a split-feed-through type structure of two respective additional capacitors. According to such alternative, at least one of such first pair of terminations and such second pair of terminations may be in parallel connection with each of such two respective additional capacitors of such third region.

[0035]

[0049] In yet another embodiment, such second region of such electrode layer may be between such first and third regions of such electrode layer. According to another variation, such body may have a pair of relatively elongated sides and a pair of relatively shorter sides, and such first pair of terminations may be on each of such pair of relatively elongated sides and such second pair of terminations may be on each of such pair of relatively shorter sides.

[0036]

[0050] For some embodiments, each of such pairs of layers of such first layers, such as generally rectangular layers, may have different overlap areas with such generally cross-shaped layers of such first layers, thereby obtaining different capacitance values ​​for each of such capacitors in such first regions. In other cases, such exemplary multi-terminal multilayer ceramic devices may further comprise a third region of such electrode layers forming a split-feed-through type structure of two respective additional capacitors, such third region comprising at least a pair of layers, such as generally rectangular layers, having respective front and rear extending edges that respectively contact the terminations of such second pair, and having side extending edges that respectively contact the terminations of such first pair. In some embodiments, each of such pairs of layers of such third layers, such as generally rectangular layers, may have different overlap areas with such generally cross-shaped layers of such third layers, thereby obtaining different capacitance values ​​for each of such additional capacitors in such third regions.

[0037]

[0051] In one embodiment, such electrode layers in such second regions may include a relatively large area for forming a relatively large capacitance value overlap-type multi-layer ceramic capacitor.

[0038]

[0052] In one embodiment, a discrete varistor having a pair of external terminations may be stacked onto such a device, with such first and second leads attached respectively to the external terminations of such a pair of such varistors, such that such a device and such discrete varistor are connected in parallel.

[0039]

[0053] Another exemplary embodiment in accordance with the presently disclosed subject matter relates to an integrated capacitor filter with varistor functionality, preferably comprising a discrete multi-terminal multilayer ceramic capacitor device, such as a co-fired multilayer ceramic capacitor device having a plurality of capacitive elements, comprising a generally rectangular, six-sided, etc. body having a plurality of cooperating layers including electrode layers that will form an integrated capacitive structure, a first pair of capacitor device terminations having opposite polarity exterior to such body, a second pair of capacitor device terminations having the same polarity exterior to such body, a first region of such electrode layers forming two respective capacitors, and a second region of such electrode layers forming a multilayer ceramic capacitor received in series connection between such first pair of terminations. Such discrete multi-terminal multilayer ceramic capacitor devices are preferably further combined with a discrete varistor, such as a discrete co-fired varistor, comprising a body, such as a generally rectangular six-sided body having a pair of varistor terminations of opposite polarity exterior to such varistor body, first and second leads attached to such first pair of capacitor device terminations and such pair of varistor terminations, respectively, and a third lead attached to at least one of such second pair of capacitor device terminations.

[0040]

[0054] In one embodiment, at least one of such first pair of capacitor device terminations and such second pair of capacitor device terminations may be in parallel with each of such two respective capacitors in such first region. In another embodiment, such first region of such electrode layers may form a split feed-through type structure of such two respective capacitors and such second region of such electrode layers may form an overlap type structure of such multilayer ceramic capacitor.

[0041]

[0055] According to another embodiment, methods are provided, including, for example, methods for manufacturing such devices. For example, one exemplary embodiment of the presently disclosed subject matter relates to a method for providing a multi-terminal multi-layer ceramic device, such as a co-fired multi-layer ceramic device having a plurality of capacitive elements. Such a method includes the steps of providing a body, such as a generally rectangular six-sided body, having a plurality of cooperating layers including electrode layers used to form an integrated capacitive structure; forming a split feedthrough type structure of two respective capacitors in a designated first region of such electrode layers; forming an overlap type structure of multilayer ceramic capacitors in a designated second region of such electrode layers; adding a first pair of terminations external to respective opposing faces of a pair of such bodies, such second region capacitors being connected in series between such first pair of terminations; and adding a second pair of terminations having the same polarity external to at least a portion of respective opposing faces of another pair of such bodies, such second pair of terminations and at least one of such first pair of terminations each being connected in parallel with such two respective capacitors of such first region, thereby integrating a plurality of capacitive elements into a single packaged device, such as a single package co-fired device.

[0042]

[0056] In one embodiment, such a first region of such electrode layer may comprise at least a pair of layers, such as generally rectangular layers, located on opposite sides of a generally cross-shaped layer having respective front and back extending edges in contact with each of such second pair of terminal ends, and having side extending edges in contact with each of such first pair of terminal ends, and such a second region of such electrode layer may comprise at least paired alternating layers in an overlapping configuration, with respective extended portions of the alternating layers in contact with each of such first pair of terminal ends.

[0043]

[0057] For one embodiment, such first pair of terminations and second pair of terminations may each be wrapped around a designated bottom surface of such body to form a surface mounted device (SMD) configuration for such device.

[0044]

[0058] For one embodiment, the method may further include forming another split-feedthrough type structure of two respective capacitors in a designated third region of such electrode layer, each of such two respective capacitors in such third region being connected in parallel to at least one of such second pair of terminations and such first pair of terminations.

[0045]

[0059] In one embodiment, the method may include providing such a pair of such first layers, such as a generally rectangular layer, having respective different overlap areas of such first layer with such generally cross-shaped layer, thereby obtaining different capacitance values ​​for such respective capacitors in such first regions.

[0046]

[0060] The method may further include forming two respective additional capacitor split-feedthrough type structures in a designated third region of such electrode layer, such third region comprising at least a pair of layers, such as generally rectangular layers, having respective front and back extending edges in contact with such second pair of terminations, and having respective side extending edges in contact with such first pair of terminations.

[0047]

[0061] In one embodiment, the method may further include attaching a first lead and a second lead, respectively, to such first pair of terminations, and attaching a third lead to at least one of such second pair of terminations. In one embodiment, the method may further include stacking, with such device, a discrete varistor having a pair of external terminations, with such first lead and second lead, respectively, attached to the external terminations of such pair of such varistors, such device and such discrete varistor being connected in parallel.

[0048]

[0062] 1A illustrates an exterior perspective view of an exemplary embodiment of a multi-terminal, multi-layer device, generally 100, in accordance with the presently disclosed subject matter. As illustrated, exemplary embodiment 100 generally has a body, generally 102, such as a six-sided body, having external terminations 104, 106, 108 and 110. All such external terminations are provided on a designated bottom side, generally 112, of device 100 for use in a surface mounted device (SMD) configuration or the like.

[0049]

[0063] The device 100 in the illustrated exemplary embodiment may comprise a multi-terminal multi-layer ceramic device with three or more capacitive elements. In some such embodiments, such three capacitors may include two series capacitors, these two capacitors in parallel with a third element. As will be appreciated by those skilled in the art related to all of the embodiments described herein, cooperating layers in the subject multi-layer structure comprise electrode layers, which will form an integrated capacitive structure.

[0050]

[0064] FIG. 1B illustrates a perspective view of an exemplary embodiment of application FIG. 1A, generally 100, partially in perspective to illustrate multiple components formed therein by the multi-layer structure. More specifically, as shown in such FIG. 1B, an upper or first region of device 100, generally 114, is internally provided with a split-feedthrough type structure to provide two respective exemplary capacitors, while a lower or second region of device 100, generally 116, is internally provided with a more standard overlapping multi-layer capacitor structure. This exemplary exemplary embodiment of FIG. 1A and FIG. 1B thus provides for the integration of capacitive elements in a single package, such as a single co-fired package.

[0051]

[0065] More particularly, with respect to upper region 114, a pair of layers 118 and 120, such as generally rectangular layers 118 and 120, are juxtaposed on opposite sides of a typically cruciform layer 122. As shown, front and back extending edges 124 and 126 of layer 122 contact central (i.e., second pair) exterior terminations 108 and 110, respectively, while side extending edges 128 and 130 contact side / end (i.e., first pair) terminations 104 and 106, respectively.

[0052]

[0066] With respect to the lower region 116, the paired alternating layers 132 / 134 and 136 / 138 are in the standard overlap configuration for forming a multilayer capacitor in such region 116 of the device 100. As also shown, ends 140 and 142 of each of these alternating layers contact the external end termination 104, while ends 144 and 146 of each of these alternating layers contact the external end termination 106.

[0053]

[0067] FIG. 1C illustrates a perspective view of the exemplary embodiment 100 of application FIG. 1A with the addition of a lead configuration. More specifically, leads 148, 150, and 152 are attached to external terminations 104, 108, and 106, respectively. Leads 148 and 152 may constitute a first lead and a second lead attached to a first pair of terminations 104 and 106, respectively, while lead 150 may constitute a third lead attached to at least one of the second pair of terminations 108 and 110. Those skilled in the art will also appreciate that terminations 108 and 110 are both connected to layer 122 of top region 114 of device 100 such that lead 150 may be connected to either such termination 108 or 110 with the same electrical circuitry consequences. The resulting configuration of application FIG. 1C is an overmolded three-lead component.

[0054]

[0068] FIG 1D illustrates a schematic diagram of an exemplary embodiment of application FIG 1A, generally 100, with the connection / mounting configuration as shown in application FIG 1C. More specifically, leads 148, 150 and 152 are shown contacting series and parallel capacitors, respectively. The capacitance values ​​shown are not intended to be limiting, but merely exemplary.

[0055]

[0069] As illustrated, device 100 provides a single device solution for incorporating series and parallel capacitors. The upper region of device 100, collectively 114, includes exemplary layers 118, 122 and 120 1 shows two typical 10 nF capacitors 154 and 156 formed by the split feedthrough configuration of FIG. 1. The lower region of device 100, collectively 116, shows a typical single 1 μF capacitor 158, such as a capacitor that would be formed from a standard multi-layer capacitor construction.

[0056]

[0070] Although various sizes may be implemented for any exemplary embodiment disclosed herein, device 100 may be considered to be a typical standard MLC case size, e.g., 1206 case size. Of course, various sizes may be implemented in various embodiments as needed or desired for a particular application. All such variations and variations of the exemplary capacitance values ​​are intended to be within the spirit and scope of the presently disclosed subject matter. Device 100 according to the presently disclosed subject matter otherwise represents an integrated three-terminal device having a standard multilayer capacitor (MLC) at a designated lower region of device 100 coupled with a split feedthrough at a designated upper region of device 100. In terms of method, device 100 (a single package integrated multiple capacitance element) as described and used herein simplifies the assembly of leaded or SMD components by replacing three single discrete capacitors with a single integrated capacitance device. Particularly when used in SMD configurations, multiple discrete components on a PCB are avoided, which saves space on the PCB while reducing inductance.

[0057]

[0071] FIG. 2 illustrates a perspective view of another exemplary embodiment of the presently disclosed subject matter, generally 200. FIG. 2 provides a partial perspective view to illustrate multiple components formed therein by a multi-layer structure, similar to application FIG. 1B. More specifically, device 200 has a pair of series capacitors located generally in an upper region 214, and a similar pair of series capacitors located generally in a lower region 214', with regions 214 and 214' on either side of a central region, generally 216, in which a single parallel capacitor is formed. Thus, those skilled in the art will recognize from a full disclosure together with this disclosure that the internal configuration embodiment of device 200 of application FIG. 2 may nevertheless be used with the standard package size (or other sizes) and external termination configuration illustrated by application FIG. 1A.

[0058]

[0072] More particularly, as shown in such Figure 2, the top and bottom (first and third) regions of device 200, collectively 214 and 214', are internally provided with respective split-feedthrough type structures resulting in two pairs of respective exemplary capacitors, while the central or intermediate (second) region of device 200 between regions 214 and 214', collectively 216, is internally provided with a more standard overlapping multi-layer capacitor structure. This exemplary illustrative embodiment of Figure 2 thus provides another illustrative embodiment of the presently disclosed integration of capacitive elements in a single package, such as a single co-fired package.

[0059]

[0073] More specifically, with respect to the upper region 214, a pair of layers 218 and 220, such as generally rectangular coplanar layers 218 and 220, are juxtaposed on opposite sides of a typical cruciform layer 222. As shown, front and back extending edges 224 and 226 of layer 222 will contact central exterior terminations 108 and 110 (of application FIG. 1A), respectively, while side extending edges 228 and 230 contact side / end terminations 104 and 106 (of application FIG. 1A), respectively. Similarly, with respect to the lower region 214', a pair of layers 218' and 220', such as generally rectangular layers 218' and 220', are juxtaposed on opposite sides of a typical cruciform layer 222'. As shown, front and back extending edges 224' and 226' of layer 222' will contact central exterior terminations 108 and 110 (of application FIG. 1A), respectively, while side extending edges 228' and 230' will contact side / end terminations 104 and 106 (of application FIG. 1A), respectively.

[0060]

[0074] With respect to the intermediate or central region 216, the paired alternating layers 232 / 234 and 236 / 238 are in the standard overlap configuration for forming a multilayer capacitor in such region 216 of device 200. As also shown, respective ends 240 and 242 of these alternating layers contact external end termination 104 (of application FIG. 1A), while respective ends 244 and 246 of these alternating layers contact external end termination 106 (of application FIG. 1A).

[0061]

[0075] Similar to the potential alternative implementation of application embodiment 100 of FIG. 1A in the leaded configuration of application FIG. 1C, device 200 of application FIG. 2 may be implemented as a surface mount device or may be coupled with leads in the configuration of application FIG. 1C.

[0062]

[0076] Figure 3A illustrates an exterior perspective view of another exemplary embodiment 300 of a multi-terminal multi-layer device in accordance with the presently disclosed subject matter. Figure 3B illustrates a perspective view of such an exemplary embodiment 300 of application Figure 3A, partially in perspective to illustrate multiple components formed therein by the multi-layer structure, while Figure 3C illustrates a schematic diagram of the exemplary embodiment 300 of application Figure 3A.

[0063]

[0077] More specifically, the alternative embodiment device 300 of the presently disclosed subject matter may be considered as a so-called inverted configuration, which results in a relatively smaller inductance, as will be understood by those skilled in the art. Compared to the exemplary embodiment 100 of application Figs. 1A and 1B, the elongated sides of the exemplary body 302, such as the six-sided body 302, are terminated by external terminations 304 and 306, while strip-like external terminations 308 and 310 are formed at the respective short side ends of the body 302. Similar to application Fig. 1B, the device 300 has multiple components formed by multiple layers in the respective lower and upper regions 314 and 316 of the device 300. However, such layers are rotated 90 degrees relative to the internal multi-layer structure of the device 100, referring to the relatively elongated and relatively short sides of the device 300.

[0064]

[0078] Additionally, the partial perspective view of Figure 3A illustrates multiple components formed therein by a multi-layer structure, including an upper region, collectively 314, of device 300 that internally provides a split-feedthrough type structure resulting in two respective exemplary capacitors, and a lower region, collectively 316, of device 300 that internally provides a more standard overlapping multi-layer capacitor structure. This exemplary alternative exemplary embodiment of Figures 3A and 3B thus again provides for the integration of capacitive elements in a single package, such as a single co-fired package.

[0065]

[0079] With respect to upper region 314, a pair of complementary coplanar layers 318 and 320 (which may be generally T-shaped or otherwise shaped) are juxtaposed on opposite sides of a typically cross-shaped layer 322. As shown, side extending edges 324 and 326 of layer 322 contact strip / side exterior terminations 308 and 310, respectively, while front and back extending edges 328 and 330 of members 318 and 320, respectively, contact elongated side terminations 304 and 306, respectively.

[0066]

[0080] With respect to the lower region 316, the typical alternating layers 332 and 336 are in a standard overlap configuration for forming a multilayer capacitor in such region 316 of the device 300. As also shown, respective ends 340 and 342 of these alternating layers contact the exterior elongated side terminations 304 and 306, respectively.

[0067]

[0081] From the full disclosure herein, those skilled in the art will appreciate that although device 300 is illustrated in an SMD configuration in FIG. 3A, such device 300 may equally be practiced in a leaded configuration, as shown by the exemplary embodiment of FIG. 1C.

[0068]

[0082] Similar to Figure 1D, Figure 3C illustrates a schematic diagram of an example embodiment of application Figure 3A, generally 300, in its connection configuration as shown by application Figure 3A. More specifically, the connections are listed as respective terminations 304, 308 and 306 for circuitry connections shown in contact with series and parallel capacitors, respectively. The capacitance values ​​shown are not intended to be limiting, but merely exemplary.

[0069]

[0083] As illustrated, device 300 provides a single device solution for including series and parallel capacitors. The upper region of device 300, generally 314, shows two exemplary 10 nF capacitors 354 and 356 formed by a split feedthrough configuration of exemplary layers 318, 322 and 330. The lower region of device 300, generally 316, shows a typical single 1 μF capacitor 358, such as a capacitor that would be formed from a standard multi-layer capacitor structure.

[0070]

[0084] 4A illustrates a perspective view of yet another exemplary embodiment of the presently disclosed subject matter, generally 400, partially in perspective to illustrate multiple components formed therein by a multi-layer structure. In particular, such exemplary embodiment 400 utilizes different overlap areas (relative to exemplary embodiment 200) to provide different resulting capacitances in an integrated device, such as an integrated co-fired device.

[0071]

[0085] More specifically, device 400 has a pair of series capacitors located generally in an upper region 414 and a similar pair of series capacitors located generally in a lower region 414', with regions 414 and 414' on either side of a central region, generally 416, forming a single parallel capacitor in the central region. Thus, those skilled in the art will recognize from a full disclosure together with this disclosure that the internal configuration embodiment of device 400 of application FIG. 4A may nevertheless be used with the standard package size (or other sizes) and external termination configuration illustrated by application FIG. 1A.

[0072]

[0086] More specifically, as shown in such Figure 4, the top and bottom regions of device 400, collectively 414 and 414', are internally provided with respective split-feedthrough type structures resulting in two pairs of respective exemplary capacitors, while the central or intermediate region of device 400 between regions 414 and 414', collectively 416, is internally provided with a more standard overlapping multi-layer capacitor structure. This exemplary illustrative embodiment of Figure 4 thus provides another illustrative embodiment of the presently disclosed integration of capacitive elements in a single package, such as a single co-fired package.

[0073]

[0087] More specifically, with respect to the upper region 414, a pair of layers 418 and 420, such as generally rectangular coplanar layers 418 and 420, are juxtaposed on opposite sides of a typical crisscross layer 422. As shown, front and rear extending edges 424 and 426 of layer 422 will contact central exterior terminations 108 and 110 (of application FIG. 1A), respectively, while side extending edges 428 and 430 contact side / end terminations 104 and 106 (of application FIG. 1A), respectively. Similarly, with respect to the lower region 414', a pair of layers 418' and 420', such as generally rectangular layers 418' and 420', are juxtaposed on opposite sides of a typical crisscross layer 422'. As shown, front and back extending edges 424' and 426' of layer 422' will contact central exterior terminations 108 and 110 (of application FIG. 1A), respectively, while side extending edges 428' and 430' will contact side / end terminations 104 and 106 (of application FIG. 1A), respectively.

[0074]

[0088] With respect to the intermediate or central region 416, the paired alternating layers 432 / 434 and 436 / 438 are in the standard overlap configuration for forming a multilayer capacitor in such region 416 of device 400. As also shown, respective ends 440 and 442 of these alternating layers contact external end termination 104 (of application FIG. 1A), while respective ends 444 and 446 of these alternating layers contact external end termination 106 (of application FIG. 1A).

[0075]

[0089] Similar to the potential alternative implementation of application embodiment 100 of FIG. 1A in the leaded configuration of application FIG. 1C, device 400 of application FIG. 4A may be implemented as a surface mount device or may be coupled with leads in the configuration of application FIG. 1C.

[0076]

[0090] FIG. 4B generally illustrates a top view of selected layers in the upper region 414 of the multi-layer structure of the exemplary embodiment 400 of FIG. 4A. More specifically, exemplary layers 418, 420, and 422 are shown. As will be appreciated by those skilled in the art, the amount of overlapping surface area between opposing layers contributes to determining the resulting capacitance value formed therewith. In this example, each layer 418, 420, and 422 is configured such that the overlapping area 423 on one side of the region 414 is larger than the overlapping area 425 on the other side of the region 414, as shown. As will be appreciated, such different overlapping areas facilitate the formation of different capacitances, as otherwise reflected herein. In particular, FIG. 4C illustrates a schematic diagram of the exemplary embodiment 400 of the application of FIGS. 4A and 4B. As shown, the two series capacitances are formed with different values ​​of capacitance as a reflection of the degree of non-uniformity of their respective overlaps over areas 423 and 425. Although variations may be practiced, the illustrated example embodiment 400 provides example capacitances for capacitors 454 and 45 of 20 nF and 10 nF, respectively, and 1 μF for capacitor 458. Terminations 404, 408 and 406 are shown in the simplified diagram of FIG. 3C to reflect a surface mounted device configuration of embodiment 400, although leaded configurations may be practiced.

[0077]

[0091] 5A illustrates a perspective view of yet another exemplary embodiment 500 of the presently disclosed subject matter, partially in perspective to illustrate multiple components formed therein by a multi-layer structure. In particular, relatively large electrodes (such as T-shaped designs) may be used to increase the relative degree of overlap and correspondingly increase the capacitance value. Also, relatively large electrodes may be used to provide other advantageous features, including, but not limited to, reduced inductance and / or equivalent series resistance (ESR).

[0078]

[0092] More specifically, as shown in such Figure 5A, an upper region of device 500, generally 514, is internally provided with a split feedthrough type structure resulting in two respective exemplary capacitors, while a lower region of device 500, generally 516, is internally provided with an overlapping multi-layer capacitor structure. This exemplary illustrative embodiment of Figure 5A thus provides for the integration of capacitive elements in a single package, such as a single co-fired package.

[0079]

[0093] More specifically, with respect to the upper region 514, a pair of layers 518 and 520, such as generally rectangular layers 518 and 520, are juxtaposed on opposite sides of a typical cruciform layer 522. As shown, front and back extending edges 524 and 526 of layer 522 contact central exterior terminations 108 and 110, respectively (application FIG. 1A for SMD configuration), while side extending edges 528 and 530 contact side / end terminations 104 and 106, respectively (application FIG. 1A).

[0080]

[0094] With respect to the lower region 516, the paired alternating layers 532 / 534 and 536 / 538 are in a standard overlap configuration for forming a multilayer capacitor in such region 516 of device 500. As also shown, respective ends 540 and 542 of these alternating layers contact external end termination 104 (Application FIG. 1A), while respective ends 544 and 546 of these alternating layers contact external end termination 106 (Application FIG. 1A).

[0081]

[0095] 5B illustrates a top view of selected layers 532 and 536 in the lower region 516 of the multi-layer structure of the exemplary embodiment 500 of FIG. 5A. As shown, such capacitor electrode layers 532 and 536 may comprise T-shaped layers in some instances, although various shapes may be implemented. As will be appreciated by those skilled in the art, the overlap region or area 533 contributes to the formation of the resulting capacitance such that making such overlap area relatively large results in a relatively large corresponding capacitance value (all other factors held constant). Again, using a relatively large area may provide other advantageous features, including, but not limited to, reduced inductance and / or equivalent series resistance (ESR).

[0082]

[0096] By adding the exemplary embodiments herein in parallel with a discrete varistor, such as a discrete co-fired varistor, as disclosed elsewhere herein, the element helps provide transient protection to the resulting combination. More specifically, Figure 6A illustrates an exterior perspective view of an exemplary embodiment of a multi-terminal multi-layer device, collectively 600, in accordance with the presently disclosed subject matter for use in a stacked configuration having varistor devices, collectively 660, all with added leads 648, 650 and 652, respectively, as illustrated. As discussed further herein, Figure 6B illustrates a schematic diagram of the exemplary embodiment 600 of application Figure 6A.

[0083]

[0097] 6A illustrates an exterior perspective view of an exemplary embodiment of a multi-terminal multi-layer device, generally 600, in accordance with the presently disclosed subject matter. As illustrated, the exemplary embodiment 600 generally includes a body, generally 602, such as a six-sided body, having external terminations 604, 606, 608, and 610. The device 600 in the illustrated exemplary embodiment may comprise a multi-terminal multi-layer ceramic device, such as a co-fired multi-layer ceramic device, which includes three or more capacitive elements. In some such embodiments, such three capacitors may include two series capacitors, with these two capacitors in parallel with a third element.

[0084]

[0098] FIG. 6A also illustrates a perspective view of the exemplary embodiment 600 with the addition of a varistor device, generally 660. Such device 660 may have a standard 1206 case size or other standard or non-standard case size. As shown, the varistor 660 also has external terminations, generally 662 and 664. Further, according to FIG. 6A, the device 600 and the varistor 660 may be placed in parallel with each other using a lead configuration arrangement. More specifically, leads 648, 650 and 652 are attached to the external (capacitor device) terminations 604, 608 and 606, respectively, of the device 600, while leads 648 and 652 are connected to the external side (varistor) terminations 662 and 664, respectively, of the varistor 660, as shown. The resulting application FIG. 6A configuration is an overmolded three-lead component.

[0085]

[0099] FIG. 6B illustrates a schematic diagram of an exemplary embodiment of application FIG. 6A, generally 600, in its connection / mounting configuration as illustrated by application FIG. 6A. More specifically, the leads 648, 650 and 652 shown are in contact with series and parallel capacitors, respectively. The capacitance values ​​shown are intended to be exemplary only and not limiting. Similarly, varistor 660 is in contact with leads 648 and 652 as illustrated, and thus in parallel with device 600. The varistor characteristics shown are intended to be exemplary only and not limiting.

[0086]

[0100] FIG. 6C illustrates a perspective view of a multi-terminal multi-layer device. In general, FIG. 6C illustrates the device of FIG. 6A in another perspective. For example, the embodiment of FIG. 6C provides a device 600, such as a multi-layer ceramic device, at the bottom with a varistor 660 on top. Such a configuration may allow for use as a surface mount device after bonding the device 600 and varistor 660 together, such as by soldering. Additionally, the embodiment illustrated in FIG. 6C is provided without the leads illustrated in FIG. 6A. However, it should be understood that in such a configuration, leads may also be used.

[0087]

[0101] As illustrated, device 600 provides a single device solution for including series and parallel capacitors. Device 600 shows two exemplary 10 nF capacitors 654 and 656, such as may be formed by a multiple layer split feedthrough configuration in an isolated region of device 600. Device 600 also provides a single exemplary 1 μF capacitor 658, such as may be formed from a standard multi-layer capacitor structure in another region of device 600, as shown.

[0088]

[0102] Although various sizes may be implemented for any of the exemplary embodiments disclosed herein, the device 600 and varistor 660 may be considered to be a typical standard MLC case size, such as a 1206 case size. Of course, various sizes may be implemented in various embodiments as needed or desired for a particular application. All such variations and variations in the exemplary capacitance values ​​are intended to be within the spirit and scope of the presently disclosed subject matter.

[0089]

[0103] As shown by the disclosure herein, in some embodiments used in SMD configurations, the presently disclosed subject matter may provide for the replacement of multiple discrete components on a printed circuit board (PCB), thereby saving space and, in some instances, reducing inductance. All of these presently disclosed exemplary embodiments may, in some uses, be packaged into an overmolded three-lead component. The presently disclosed subject matter provides a substantial reduction in device size, which in turn results in fewer solder connections and, in turn, greater reliability.

[0090]

[0104] Additionally, the individual steps for achieving the disclosed configurations are intended to be exemplary only and not indicative of the necessary use of other aspects beyond the general nature of the disclosure as otherwise set forth. For example, one of ordinary skill in the art will recognize that selected steps may be implemented to result in a particular design selected for a given application of the presently disclosed subject matter.

[0105] Although such presently disclosed subject matter has been described in detail above with respect to specific embodiments thereof, it will be recognized that those skilled in the art, upon understanding the above description, can readily effect modifications to such embodiments, variations of such embodiments, and equivalents thereto. Accordingly, the scope of the present disclosure is by way of example, not by way of limitation, and the subject matter disclosure does not exclude the inclusion of such modifications, variations, and / or additions to the presently disclosed subject matter, as would be readily apparent to those skilled in the art.

Claims

1. An integrated capacitor filter having a varistor function, 1. A discrete multi-terminal multilayer ceramic capacitor device having a plurality of capacitive elements, comprising: a body having a plurality of cooperating layers including electrode layers that will form an integrated capacitive structure; a first pair of capacitor device terminations having opposite polarity external to the body; a second pair of capacitor device terminations having the same polarity external to the body; a first region of the electrode layer forming two respective capacitors, the first region comprising at least a pair of layers on opposite sides of a third layer having respective front and back extending edges that respectively contact the second pair of capacitor device terminations, the pair of layers having side extending edges that respectively contact the first pair of capacitor device terminations, the third layer being a generally cross-shaped layer; a second region of the electrode layer forming a multilayer ceramic capacitor received in series connection between the first pair of capacitor device terminations; a third region of the electrode layer forming two respective additional capacitors, the third region comprising at least a pair of layers on opposite sides of a third layer having respective front and back extending edges that respectively contact the second pair of capacitor device terminations, the pair of layers having side extending edges that respectively contact the first pair of capacitor device terminations, the third region being a generally cross-shaped layer; Equipped with the pair of layers and the third layer of the third region of the electrode layer are stacked along a stack direction in the same order as the pair of layers and the third layer of the first region of the electrode layer; a discrete multi-terminal multilayer ceramic capacitor device; a discrete varistor having a body with a pair of varistor terminations having opposite polarities on an exterior of the body; a first lead and a second lead attached to the first pair of capacitor device terminations and the pair of varistor terminations, respectively; a third lead attached to at least one of the second pair of capacitor device terminations; Equipped with The discrete multi-terminal multilayer ceramic capacitor device is an integrated capacitor filter having a varistor function, wherein the third lead is disposed on an upper surface of the discrete varistor and extends from the discrete multi-terminal multilayer ceramic capacitor device through the discrete varistor.

2. 2. The integrated capacitor filter with varistor functionality as claimed in claim 1, wherein at least one of the first pair of capacitor device terminations and the second pair of capacitor device terminations is in parallel connection with the two respective capacitors in the first region.

3. The discrete multi-terminal multilayer ceramic capacitor device comprises:

2. The integrated capacitor filter with varistor functionality as claimed in claim 1, wherein at least one of the first pair of capacitor device terminations and the second pair of capacitor device terminations is in parallel connection with the two respective additional capacitors in the third region.

4. 2. The integrated capacitor filter with varistor functionality as claimed in claim 1, wherein the pair of layers in the first region each have a different overlap area with the third layer in the first region, thus resulting in a different capacitance value for the respective capacitors in the first region.

5. An integrated capacitor filter having a varistor function, 1. A discrete multi-terminal multilayer ceramic capacitor device having a plurality of capacitive elements, comprising: a body having a plurality of cooperating layers including electrode layers that will form an integrated capacitive structure; a first pair of capacitor device terminations having opposite polarities exterior to the body and residing on respective relatively elongated sides of the pair of the body; a second pair of capacitor device terminations having the same polarity exterior to the body and residing on shorter sides of the pair of the body, respectively; a first region of the electrode layer forming two respective capacitors, the first region comprising at least a pair of layers having side extending edges respectively contacting the first pair of terminations and positioned opposite a third layer having respective front and back extending edges respectively contacting the second pair of terminations, the third layer being a generally cross-shaped layer; a second region of the electrode layers forming a multilayer ceramic capacitor received in series connection between the first pair of terminations, the second region comprising a plurality of paired electrode layers forming the multilayer ceramic capacitor; a third region of the electrode layer forming two respective additional capacitors, the third region comprising at least a pair of layers on opposite sides of a third layer having respective front and back extending edges that respectively contact the second pair of capacitor device terminations, the pair of layers having side extending edges that respectively contact the first pair of capacitor device terminations, the third region being a generally cross-shaped layer; Equipped with the pair of layers and the third layer of the third region of the electrode layer are stacked along a stack direction in the same order as the pair of layers and the third layer of the first region of the electrode layer; a discrete multi-terminal multilayer ceramic capacitor device; a discrete varistor having a body with a pair of varistor terminations having opposite polarities on an exterior of the body; Equipped with An integrated capacitor filter with varistor functionality, wherein the discrete varistor is attached to a top surface of the discrete multi-terminal multi-layer ceramic capacitor device to form a surface mounted device (SMD) configuration for the integrated capacitor filter.

6. the first pair of capacitor device terminations and the second pair of capacitor device terminations are disposed on respective opposite pairs of sides of the body of the discrete multi-terminal multilayer ceramic capacitor device and wrap therefrom to designated top and bottom sides of the body of the discrete multi-terminal multilayer ceramic capacitor device, respectively; 6. An integrated capacitor filter with varistor functionality as claimed in claim 5, wherein the pair of varistor terminations are disposed on respective opposite pairs of sides of the body of the discrete varistor and wrap therefrom to designated top and bottom sides of the body of the discrete varistor, respectively.

7. 6. The integrated capacitor filter with varistor functionality as described in claim 5, wherein the body has a pair of relatively elongated sides and a pair of relatively shorter sides, the first pair of capacitor device terminations each present on the pair of relatively elongated sides of the body, and the second pair of capacitor device terminations each present on the pair of relatively shorter sides of the body.

8. 6. The integrated capacitor filter with varistor function as claimed in claim 5, wherein each electrode layer of said plurality of paired electrode layers in said second region is T-shaped.

9. At least one of the first pair of capacitor device terminations and the second pair of capacitor device terminations is respectively connected in parallel with the two respective additional capacitors in the third region; 6. The integrated capacitor filter with varistor function as claimed in claim 5, wherein each layer of said pair of layers in said first region is T-shaped, and each layer of said pair of layers in said third region is T-shaped.

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