Circuit structure optimization method and system based on FPGA carry chain

Abstract

The present invention provides a circuit structure optimization method and system based on FPGA carry chain. The method includes: logically integrating a target logic operation by a logic integration tool to obtain a integration network table; obtaining a key path in the integration network table; and, if the actual number of inputs of the lookup table on the key path is not greater than a preset threshold and the adjacent elements at both ends of the reference path on the key path are carry chains, converting the lookup table on the key path into a carry chain, and the reference path is a path consisting of consecutive adjacent lookup tables. The embodiment of the present invention finds a lookup table that meets the conversion requirement on the key path, and converts the lookup table into a carry chain. Since the time delay between two elements of the carry chain and the lookup table is large and the time delay between the carry chain and the carry chain is small, the adjacent carry chain and the lookup table are converted into two adjacent carry chains, thereby reducing the circuit time delay, increasing the circuit frequency, and improving the performance of the FPGA chip.

Description

[Technical field]

[0001] This application claims priority to a Chinese patent application filed with the China Patent Office, with the filing date being July 20, 2021, the application number being CN202110819418.5, and the title of the invention being "Circuit structure optimization method and system based on FPGA carry chain", the entire contents of which are incorporated herein by reference.

[0002] The present invention relates to the field of circuit technology, and in particular to a method and system for optimizing a circuit structure based on an FPGA carry chain. [Background technology]

[0003] With the development of digitalization and intelligence, Field Programmable Gate Array (FPGA) chip components have become indispensable core devices in fields such as communications, spaceflight, and defense industry, and are an important supporting basis for national strategic security. In FPGA software, logic synthesis tools map digital designs into gate-level tables and optimize their redundant circuit structures, and the resulting performance level has a great impact on the subsequent layout and routing results. 、 This directly affects important performance such as timing sequence and power consumption in final chip application.

[0004] During the integration process, the FPGA chip integrator needs to reference one or more function libraries containing the target technology due to the characteristics and limitations of its own hardware structure, such as multi-bit adders, registers, and memories. The integrator generates an RLT description by a compiler by analyzing the hardware description language, and effectively integrates the design part into the actual gate-level network table. The integrator can not only convert the description of a high level of abstraction into a description of a low level, but also optimize the logical structure during the design, for example, by removing redundant circuit structures or repeatedly operating circuit modules with the same function.

[0005] Generally, in FPGAs, logic functions are realized using small query tables (abbreviated as Look Up Tables, LUTs) and logic functions with any n inputs and one output can be realized by storing a truth table. The inputs generally range from 4 to 6. One important step in FPGA logic integration is to decompose large multi-input logic blocks into small logic functions with 4 to 6 inputs and realize these small logic functions using LUTs.

[0006] However, in the process of implementing logic functions using LUTs, a large time delay occurs, so a circuit structure optimization method based on FPGA carry chain is necessary. Summary of the Invention [Problem to be solved by the invention]

[0007] The present invention mainly aims to provide a circuit structure optimization method and system based on FPGA carry chain, which can reduce the time delay of the key path of the circuit timing sequence, effectively increase the maximum frequency of the whole circuit, and enhance the performance of the target FPGA chip.

[0008] In a first aspect, an embodiment of the present invention provides a method for optimizing a circuit structure based on an FPGA carry chain, comprising: logically integrating the target logical operations by a logical integration tool to obtain an integrated network table; Obtaining a key path in a unified network table; If the number of actual entries of the lookup table on the key path is not greater than a preset threshold, and the adjacent elements at both ends of the reference path on the key path are carry chains, convert the lookup table on the key path into a carry chain, and the reference path is a path consisting of consecutive adjacent lookup tables; Includes.

[0009] Preferably, the preset threshold is determined based on a target FPGA chip for implementing a target logic operation.

[0010] Preferably, the preset threshold is the number of theoretical inputs of the lookup table in the target FPGA chip carry chain plus the number of cin pins.

[0011] Preferably, the preset threshold is one plus the theoretical number of inputs of the look-up table in the target FPGA chip carry chain.

[0012] Preferably, there is one or more key paths.

[0013] Preferably, there are multiple key paths, and when the number of actual inputs of the lookup table on the key path is not greater than a preset threshold and the adjacent elements at both ends of the reference path on the key path are carry chains, converting the lookup table on the key path into a carry chain includes separately checking whether a lookup table exists on each key path, calculating the number of actually input signals on the lookup table if a lookup table exists on the key path, and converting the lookup table on the key path into a carry chain if the number of actually input signals is not greater than a preset threshold and the adjacent elements at both ends of the reference path on which the lookup table exists are carry chains.

[0014] Preferably, the key path includes the path in the integrated network table that has the greatest time delay.

[0015] Preferably, the reference path includes one or more look-up tables.

[0016] Preferably, the reference path includes a plurality of consecutive adjacent lookup tables, and converting the lookup table on the key path into a carry chain when the actual number of entries of the lookup table on the key path is not greater than a preset threshold and adjacent elements at both ends of the reference path on the key path are carry chains includes converting the lookup table on the key path into a carry chain when the actual number of entries of the lookup table on the key path is not greater than a preset threshold and adjacent elements at at least one end of the reference path on the key path are carry chains.

[0017] Preferably, obtaining a key path in the integrated network table includes performing a timing sequence analysis on the integrated network table using a static timing sequence analysis tool to determine a key path in the integrated network table.

[0018] Preferably, converting the lookup table on the key path to a carry chain includes replacing the lookup table on the key path with a carry chain, where an input pin of the carry chain replaces an actual signal input pin of the lookup table on the key path, and an output pin of the carry chain replaces an actual signal output pin of the lookup table on the key path.

[0019] Preferably, the logic synthesis tool is Design Compiler.

[0020] In a second aspect, an embodiment of the present invention provides a circuit structure optimization system based on FPGA carry chain, comprising a synthesis module, a path module and a transformation module. The synthesis module is used to logically synthesize target logic operations by a logic synthesis tool to obtain a synthesis network table. The path module is used to obtain a key path in the synthesis network table. The transformation module is used to transform the lookup table on the key path into a carry chain when the actual number of inputs of the lookup table on the key path is not greater than a preset threshold and the adjacent elements at both ends of the reference path on the key path are carry chains, and the reference path is a path consisting of consecutive adjacent lookup tables.

[0021] In a third aspect, an embodiment of the present invention provides a computer device, comprising: a memory; a processor; and a computer program stored in the memory and executable on the processor, the computer program, when executed by the processor, implementing steps of the above-mentioned FPGA carry chain based circuit structure optimization method.

[0022] In a fourth aspect, an embodiment of the present invention provides a computer storage medium having a computer program stored thereon, the computer program, when executed by a processor, implementing steps of the above-mentioned FPGA carry chain based circuit structure optimization method.

[0023] The circuit structure optimization method and system based on FPGA carry chain proposed by the present invention finds a lookup table that meets the conversion requirements on the key path, and converts the lookup table into a carry chain. Because the time delay between the two elements of the carry chain and the lookup table is large, and the time delay between the carry chain and the carry chain is small, the adjacent carry chain and the lookup table are converted into two adjacent carry chains, thereby reducing the circuit time delay, increasing the circuit frequency, and improving the performance of the FPGA chip. [Brief description of the drawings]

[0024] [Figure 1] FIG. 1 is a flowchart of a circuit structure optimization method based on an FPGA carry chain provided by an embodiment of the present invention. [Diagram 2] FIG. 2 is a schematic diagram of the use of logical integration in an embodiment of the present invention. [Diagram 3] FIG. 3 is a schematic diagram of a carry chain structure in an embodiment of the present invention. [Figure 4] FIG. 4 is a schematic diagram of one reference path in an embodiment of the present invention. [Diagram 5] FIG. 5 is a schematic diagram of another reference path in an embodiment of the present invention. [Figure 6] FIG. 6 is a schematic diagram showing a basic configuration of a carry chain element in an embodiment of the present invention. [Figure 7] FIG. 7 is a schematic diagram showing a configuration of a sum sublogic in a carry chain element in the embodiment of the present invention. [Figure 8] FIG. 8 is a schematic diagram showing a configuration of a logical unification operation in an embodiment of the present invention. [Figure 9] FIG. 9 is a schematic diagram showing a circuit configuration after converting logical operations in an embodiment of the present invention. [Figure 10] FIG. 10 is a schematic diagram showing the configuration of a circuit structure optimization system based on an FPGA carry chain provided by an embodiment of the present invention. [Figure 11] FIG. 11 is a schematic diagram showing the configuration of a computer device provided according to an embodiment of the present invention.

[0025] The realization of the objectives, functional features and advantages of the present invention will be further explained with reference to the drawings in combination with the embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0026] It should be understood that the specific embodiments described herein are used only to illustrate the present invention and not to limit the present invention.

[0027] 1 is a flowchart of a circuit structure optimization method based on an FPGA carry chain provided by an embodiment of the present invention. As shown in FIG. 1, the method includes the following steps:

[0028] Step S110: the target logic operations are logic-integrated by a logic integration tool to obtain an integrated network table.

[0029] First, when integrating a target logic algorithm, a logic integration tool is generally employed. A logic integration tool is generally software that integrates various operational functions. The target logic algorithm is generally a logic operation. Logic integration is the process of using a tool to convert Register Transfer Level (RTL) code into a gate-level network table. A common logic integration tool is Design Compiler from Synopsys. The process of integrating logic operations starts with reading the RTL code, applying timing sequence constraint relationships, and generating a gate-level net table file through mapping, which can be divided into three steps.

[0030] 1. Translation: Read the RTL level description of the circuit and translate the language description into the corresponding functional blocks and topology structures between the functional blocks. The result of this process is to generate the Boolean function expression of the circuit inside the synthesizer, without any logic reshuffling or optimization.

[0031] 2. Optimization: Based on the applied timing sequence and area constraints, the translation result is reorganized and optimized according to a certain algorithm.

[0032] 3. Mapping: According to the applied timing sequence and area constraints, search for units that meet the conditions from a target process library to construct a logic integration network table of an actual circuit, and the logic integration network is the integration network table in the embodiment of the present invention.

[0033] For example, to realize the following design, the target logic algorithm is an AND operation on a 10-bit input, and the synthesis result of the logic synthesis tool is to realize this logic function using two connected lookup tables. As shown in Figure 2, Figure 2 is a schematic diagram of the use of logic synthesis in an embodiment of the present invention.

[0034] The design is as follows: module_test ( input [9:0] I, Output Z ); assign Z = &I; endmodule

[0035] The basic hardware structure of an FPGA also includes a high-speed carry chain. FIG. 3 is a schematic diagram of a carry chain structure in an embodiment of the present invention. As shown in FIG. 3, the carry chain structure is generally a ripple carry adder (RCA) carry chain structure, which is used to realize arithmetic operations such as addition and subtraction of a large bit width. The basic structure of the hardware structure carry chain is generally a two-output look-up table (LUT) with an input range of 4 to 6 plus other logic gates such as a selector.

[0036] S120, obtaining a key path in the integrated network table.

[0037] Then, a static timing sequence analysis tool is used to perform timing sequence analysis on the generated integrated network table to find key paths in the integrated network table.

[0038] In embodiments of the present invention, a key path can be any path that significantly impacts the time delay of a circuit.

[0039] S130, if the actual number of entries of the lookup table on the key path is not greater than a preset threshold and the adjacent elements at both ends of the reference path on the key path are carry chains, convert the lookup table on the key path into a carry chain, and the reference path is a path consisting of consecutive adjacent lookup tables.

[0040] If there are multiple key paths, a search is performed for each key path to see whether a lookup table exists for each key path. If a lookup table exists on the key path, the number of signals actually input to the lookup table is calculated. If the number of signals actually input is not greater than a preset threshold and the adjacent elements at both ends of the reference path on which the lookup table exists are carry chains, it indicates that the lookup table meets the conversion requirements, and the lookup table can be converted.

[0041] In an embodiment of the present invention, FIG. 4 is a schematic diagram of one reference path in an embodiment of the present invention, as shown in FIG. 4, the reference path can only include one lookup table, and when the reference path only includes one lookup table, when at least one in two adjacent elements of the lookup table is a carry chain, the lookup table meets the conversion requirements, and converts the lookup table.

[0042] In addition, FIG. 5 is a schematic diagram of another reference path in an embodiment of the present invention. As shown in FIG. 5, the reference path can also include multiple consecutive adjacent lookup tables, and at both ends of the reference path, if at least one adjacent element is a carry chain, all lookup tables on the reference path are converted to carry chains.

[0043] The circuit structure optimization method based on FPGA carry chain proposed by the present invention finds a lookup table that meets the conversion requirements on the key path, and converts the lookup table into a carry chain. Because the time delay between the two elements of the carry chain and the lookup table is large, and the time delay between the carry chain and the carry chain is small, the adjacent carry chain and the lookup table are converted into two adjacent carry chains, thereby reducing the circuit time delay, increasing the circuit frequency, and improving the performance of the FPGA chip.

[0044] In addition, in the embodiment of the present invention, only a small number of lookup table conversion operations on the key path are required to obtain a better timing sequence optimization effect, which reduces the burden on the software execution time, and uses less carry chain resources, and the carry chain resources in the FPGA chip are very abundant, so there is no impact on the resource usage of the chip.

[0045] In addition to the above-mentioned embodiment, the preset threshold value is preferably determined based on a target FPGA chip for implementing a target logic operation.

[0046] Specifically, the preset threshold is determined based on the target FPGA chip. Different chip models have different pin numbers and usage methods of the target FPGA chip, so the preset thresholds corresponding to different target FPGA chips are different.

[0047] In addition to the above embodiment, the preset threshold value is preferably set to add 1 to the theoretical number of inputs of the lookup table in the target FPGA chip carry chain.

[0048] Specifically, the preset threshold value is the theoretical number of inputs of the lookup table in the target FPGA chip carry chain plus one.

[0049] Specifically, the theoretical number of inputs of a carry chain in an FPGA chip is the theoretical number of inputs of the LUT plus the number of cin pins, for example, 1 indicates that the number of cin pins is 1.

[0050] Only if the number of actual input pins of the lookup table in the reference path is not greater than a preset threshold, the available input pins of the carry chain in the target FPGA chip are sufficient.

[0051] In addition to the above embodiments, it is preferred that there is one or more key paths.

[0052] Specifically, in the embodiment of the present invention, the number of key paths may be one or more. Since the frequency of the circuit is determined by the worst time delay, that is, the path with the largest time delay, optimizing the timing sequence of other paths is not very useful for increasing the frequency of the circuit, but other paths can still be optimized.

[0053] If the number of key paths is one, the key path is the path with the largest time delay, that is, the path that plays a critical role in the timing sequence performance of the design. If the number of key paths is multiple, the key path must include the path with the largest time delay.

[0054] In addition to the above-mentioned embodiments, preferably, converting the lookup table on the key path to a carry chain includes replacing the lookup table on the key path with a carry chain, where an input pin of the carry chain replaces an actual signal input pin of the lookup table on the key path, and an output pin of the carry chain replaces an actual signal output pin of the lookup table on the key path.

[0055] Specifically, the logic functions of FPGA chips are usually realized by programmable interconnected lookup tables, so cascaded lookup tables often appear in the designed key path. If the time delay in this case can be reduced, it can have a direct and effective optimization effect on the timing sequence performance of the design.

[0056] Because the carry chain generally adopts clever signal topology structure and high-speed technology, the time delay of the internal transmission is extremely small, and the overall time delay of the realized circuit is much lower than the total delay realized by the programmable interconnection of ordinary look-up tables in an FPGA chip.

[0057] 6 is a schematic diagram showing the basic configuration of a carry chain element in an embodiment of the present invention. As shown in FIG. 6, compared to a normal LUT, the CARRY (carry chain) includes a LUT with dual outputs to realize arithmetic functions such as addition and subtraction of carries, as well as logic gates such as selector mux to complete the calculation of sum and carry cout.

[0058] The addition operation can be simplified to sum=A^B^CIN, in which ^ is an exclusive OR operation, and the LUTn inside CARRY can realize the logic function of A^B. Figure 7 is a schematic diagram showing the configuration of the sum partial logic in the carry chain element in an embodiment of the present invention. The structure shown in Figure 7 can realize the logic realization of sum in the carry chain element, and the operation part of the sum logic in the figure and the LUT input to n+1 bits are consistent, and can realize any logic function of n+1 inputs, and can also replace the logic function of a normal LUT in FPGA.

[0059] Therefore, if the number of inputs to the LUT in the FPGA device is equal to or less than the number of inputs to the LUT in the carry chain element plus one, it can be replaced by the CARRY resources in the chip.

[0060] For example, the result of the logic integration tool that calculates the target logic operation Z=(A==B)?(&I):0 is usually as shown in FIG. 8, which is a schematic diagram showing the configuration of the logic integration operation in an embodiment of the present invention. In this case, the actual number of inputs of LUT6 is 6, the theoretical number of inputs of LUT6 in CARRY is 5, and the preset threshold is 5+1=6. The actual number of inputs of LUT6 is equal to the preset threshold, and LUT6 can be converted into one stage of the previous carry chain, and the connection time delay between the carry chain and LUT6 and the time delay of LUT6 itself are converted into the minimum time delay inside the carry chain. FIG. 9 is a schematic diagram showing the circuit configuration after converting the logic operation in an embodiment of the present invention. As shown in FIG. 9, the purpose of reducing the circuit time delay is achieved.

[0061] 10 is a schematic diagram showing the configuration of a circuit structure optimization system based on an FPGA carry chain according to an embodiment of the present invention. As shown in FIG. 10, the system includes a synthesis module 1010, a path module 1020 and a transformation module 1030.

[0062] The synthesis module 1010 is used to logically synthesize the target logic operations by a logic synthesis tool to obtain a synthetic network table.

[0063] The path module 1020 is used to obtain a key path in the integrated network table.

[0064] The conversion module 1030 is used to convert the lookup table on the key path into a carry chain if the actual number of entries of the lookup table on the key path is not greater than a preset threshold and the adjacent elements at both ends of the reference path on the key path are carry chains, and the reference path is a path consisting of consecutive adjacent lookup tables.

[0065] In some embodiments, the preset threshold is determined based on a target FPGA chip for implementing a target logic operation.

[0066] In some embodiments, the preset threshold is the number of theoretical inputs of the lookup table in the target FPGA chip carry chain plus the number of cin pins.

[0067] In some embodiments, the preset threshold is one plus the theoretical number of inputs of the lookup table in the target FPGA chip carry chain.

[0068] In some embodiments, the key path is one or more.

[0069] In some embodiments, there are multiple key paths. The conversion module 1030 is used to check whether a lookup table exists on each key path separately, calculate the number of actually input signals on the lookup table if the lookup table exists on the key path, and convert the lookup table on the key path to a carry chain if the number of actually input signals is not greater than a preset threshold and the adjacent elements on both ends of the reference path where the lookup table exists are carry chains.

[0070] In some embodiments, the key path comprises the path in the integrated network table that has the greatest time delay.

[0071] In some embodiments, the reference path includes one or more lookup tables.

[0072] In some embodiments, the reference path includes multiple consecutive adjacent lookup tables, and the conversion module 1030 is used to convert the lookup table on the key path to a carry chain if the actual number of entries of the lookup table on the key path is not greater than a preset threshold and at least one adjacent element on both ends of the reference path on the key path is a carry chain.

[0073] In some embodiments, the path module 1020 is used to utilize a static timing sequence analysis tool to perform timing sequence analysis on the aggregate network table to determine key paths in the aggregate network table.

[0074] In some embodiments, the conversion module 1030 is used to replace the lookup table on the key path with a carry chain, where the input pins of the carry chain replace the actual signal input pins of the lookup table on the key path, and the output pins of the carry chain replace the actual signal output pins of the lookup table on the key path.

[0075] In some embodiments, the logic synthesis tool is Design Compiler.

[0076] It should be noted that, since the device embodiment is basically similar to the method embodiment, the description thereof is simpler, and the relevant points can be referred to the description of part of the method embodiment. Any processing manner described in the method embodiment can be realized by the corresponding processing module in the device embodiment, and will not be further described in the device embodiment.

[0077] All or part of each module in the above-mentioned FPGA carry chain based circuit structure optimization system can be realized by software, hardware, or a combination thereof. Each of the above-mentioned modules can be built into the processor in the computer device in the form of hardware, or can be independent, or can be stored in the memory of the computer device in the form of software, so that the processor can easily call and execute the operation corresponding to each of the above-mentioned modules.

[0078] In some embodiments, FIG. 11 is a schematic diagram showing the structure of a computer device provided by an embodiment of the present invention. The computer device can be a server, and its internal structure is as shown in FIG. 11. The computer device includes a processor, a memory, a network interface, and a database connected via a system bus. The processor of the computer device is used to provide calculation and control capabilities. The memory of the computer device includes a computer storage medium and an internal memory. The computer storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the execution of the operating system and the computer program in the computer storage medium. The database of the computer device is used to store data generated or obtained during the execution of the circuit structure optimization method based on the FPGA carry chain. The network interface of the computer device is used to communicate with an external terminal via a network connection. The computer program is executed by the processor to realize the circuit structure optimization method based on the FPGA carry chain.

[0079] In one embodiment, a computer device is provided, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the steps of the circuit structure optimization method based on the FPGA carry chain in the above-mentioned embodiment are realized. Alternatively, when the processor executes the computer program, the functions of each module / unit in the embodiment of the circuit structure optimization system based on the FPGA carry chain are realized, and will not be described here to avoid duplication.

[0080] In one embodiment, a computer storage medium is provided that stores a computer program. When the computer program is executed by a processor, the steps of the circuit structure optimization method based on FPGA carry chain in the above-mentioned embodiment are realized. Alternatively, when the processor executes the computer program, the functions of each module / unit in the embodiment of the circuit structure optimization system based on FPGA carry chain are realized, and will not be described here to avoid duplication.

[0081] Those skilled in the art can understand that all or part of the processes in the above-mentioned method embodiments can be completed by instructing related hardware by a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, the processes of the above-mentioned method embodiments can be performed. Here, any reference to memory, storage, database, or other medium used in the embodiments provided herein may include non-volatile and / or volatile memory. The non-volatile memory may include read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory may include random access memory (RAM) or external high-speed cache memory. By way of illustrative, but non-limiting example, various RAMs are available, such as static random access memory (static RAM, SRAM), dynamic random access memory (dynamic RAM, DRAM), synchronous dynamic random access memory (synchronous DRAM, SDRAM), double data rate synchronous dynamic random access memory (double data rate SDRAM, DDRSDRAM), enhanced synchronous dynamic random access memory (enhanced SDRAM, ESDRAM), synchronous link dynamic random access memory (synch-link DRAM, SLDRAM), Rambus Direct Random Access Memory (Rambus Direct RAM, RDRAM), Direct Rambus Dynamic Random Access Memory (Direct Rambus DRAM, DRDRAM), Rambus Dynamic Random Access Memory (Rambus DRAM, RDRAM), and the like.

[0082] For convenience and conciseness of explanation, only the division of each of the above-mentioned functional units and modules is described as an example. Those skilled in the art can clearly understand that in actual applications, the distribution of the above-mentioned functions can be performed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the above-mentioned functions.

[0083] The above embodiments are only used to describe the technical solutions of the present invention, and are not limited thereto. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that the technical solutions described in the above embodiments can still be modified or some of the technical features can be replaced with equivalents, and these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention, and all should be included in the protection scope of the present invention.

Claims

1. A circuit structure optimization method based on an FPGA carry chain, comprising: logically integrating the target logical operations by a logical integration tool to obtain an integrated network table; obtaining a key path in the integrated network table; If the number of actual inputs of the lookup table on the key path is not greater than a preset threshold value and the adjacent elements at both ends of the reference path on the key path are carry chains, convert the lookup table on the key path into a carry chain, and the reference path is a path consisting of consecutive adjacent lookup tables; Including, A circuit structure optimization method based on an FPGA carry chain, comprising:

2. The preset threshold value is determined based on a target FPGA chip for realizing the target logical operation.

2. The method for optimizing a circuit structure based on an FPGA carry chain as claimed in claim 1.

3. The preset threshold is the number of theoretical inputs of the lookup table in the target FPGA chip carry chain plus the number of cin pins; 3. The method for optimizing a circuit structure based on an FPGA carry chain as claimed in claim 2.

4. The preset threshold is the theoretical number of inputs of the lookup table in the target FPGA chip carry chain plus one; 3. The method for optimizing a circuit structure based on an FPGA carry chain as claimed in claim 2.

5. The key path may be one or more. The method for optimizing a circuit structure based on an FPGA carry chain according to any one of claims 1 to 4.

6. The key paths are multiple, When the number of actual entries of the lookup table on the key path is not greater than a preset threshold and the adjacent elements at both ends of the reference path on the key path are carry chains, converting the lookup table on the key path into a carry chain includes: separately checking whether a lookup table exists on each of said key paths; If a lookup table exists on the key path, calculating the number of signals actually input to the lookup table; converting the lookup table on the key path into a carry chain when the number of actually input signals is not greater than a preset threshold and the adjacent elements at both ends of the reference path in which the lookup table is located are carry chains; Including, 6. The method for optimizing a circuit structure based on an FPGA carry chain as claimed in claim 5.

7. The key path includes a path in the integrated network table that has the greatest time delay. The method for optimizing a circuit structure based on an FPGA carry chain according to any one of claims 1 to 6.

8. the reference path includes one or more lookup tables; The method for optimizing a circuit structure based on an FPGA carry chain according to any one of claims 1 to 7.

9. the reference path includes a plurality of consecutive adjacent lookup tables; When the number of actual entries of the lookup table on the key path is not greater than a preset threshold and the adjacent elements at both ends of the reference path on the key path are carry chains, converting the lookup table on the key path into a carry chain includes: converting the lookup table on the key path into a carry chain when the number of actual entries of the lookup table on the key path is not greater than a preset threshold and at least one adjacent element on both ends of the reference path on the key path is a carry chain; The method for optimizing a circuit structure based on an FPGA carry chain according to any one of claims 1 to 5.

10. Obtaining a key path in the integrated network table includes: utilizing a static timing sequence analysis tool to perform a timing sequence analysis on the integrated network table to determine key paths in the integrated network table; The method for optimizing a circuit structure based on an FPGA carry chain according to any one of claims 1 to 9.

11. Transforming the lookup table on the key path into a carry chain, replacing the lookup table on the key path with the carry chain, an input pin of the carry chain replacing an actual signal input pin of the lookup table on the key path, and an output pin of the carry chain replacing an actual signal output pin of the lookup table on the key path; The method for optimizing a circuit structure based on an FPGA carry chain according to any one of claims 1 to 5.

12. The logic synthesis tool is Design Compiler. The method for optimizing a circuit structure based on an FPGA carry chain according to any one of claims 1 to 11.

13. A circuit structure optimization system based on an FPGA carry chain, comprising: The system includes an integration module, a path module, and a conversion module, The integration module is used to logically integrate the target logical operations through a logical integration tool to obtain an integrated network table; the path module is used to obtain a key path in the integrated network table; The conversion module is used to convert the lookup table on the key path into a carry chain when the actual number of inputs of the lookup table on the key path is not greater than a preset threshold and the adjacent elements at both ends of the reference path on the key path are carry chains, and the reference path is a path consisting of consecutive adjacent lookup tables. A circuit structure optimization system based on an FPGA carry chain, comprising:

14. The preset threshold value is determined based on a target FPGA chip for realizing the target logical operation. The FPGA carry chain based circuit structure optimization system according to claim 13.

15. The key paths are multiple, the conversion module separately checks whether a lookup table exists on each of the key paths, calculates the number of signals actually input on the lookup table if a lookup table exists on the key path, and converts the lookup table on the key path into a carry chain if the number of signals actually input is not greater than a preset threshold and the adjacent elements on both ends of the reference path where the lookup table exists are carry chains; The FPGA carry chain based circuit structure optimization system according to claim 13.

16. the reference path includes one or more lookup tables; The FPGA carry chain based circuit structure optimization system according to claim 13.

17. the reference path includes a plurality of consecutive adjacent lookup tables; The conversion module is used for converting the lookup table on the key path into a carry chain when the actual number of entries of the lookup table on the key path is not greater than a preset threshold and at least one adjacent element on both ends of the reference path on the key path is a carry chain. The FPGA carry chain based circuit structure optimization system according to claim 16.

18. The conversion module is used to convert the lookup table on the key path to the carry chain, and the input pin of the carry chain converts the actual signal input pin of the lookup table on the key path, and the output pin of the carry chain converts the actual signal output pin of the lookup table on the key path. The FPGA carry chain based circuit structure optimization system according to claim 13.

19. 1. A computing device comprising: A computer program comprising: a memory; a processor; and a computer program stored in the memory and executable on the processor; When the processor executes the computer program, the steps of the circuit structure optimization method based on an FPGA carry chain according to any one of claims 1 to 12 are realized. A computer apparatus comprising:

20. 1. A computer-readable storage medium, comprising: The computer-readable storage medium stores a computer program; When the computer program is executed by a processor, the computer program implements the steps of the FPGA carry chain based circuit structure optimization method according to any one of claims 1 to 12. A computer-readable storage medium comprising:

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