Gate Driver

Abstract

To accurately control a transient voltage in switching of a semiconductor switching element to a desired target value.SOLUTION: A gate drive device 1 is configured to control a transient voltage corresponding to voltage of a main terminal of a semiconductor switching element 5 in switching to a desired target value and comprises a calculation circuit 11, a drive circuit 12, a detection circuit 13 and a learning circuit 14. The calculation circuit 11 calculates an operation amount for operating a gate drive speed of the semiconductor switching element 5 according to a predetermined calculation method using the target value of the transient voltage. The drive circuit 12 drives a gate of the semiconductor switching element 5 based on the operation amount calculated by the calculation circuit 11. The detection circuit 13 detects the transient voltage. The learning circuit 14 executes learning processing capable of changing the calculation method based on the operation amount calculated by the calculation circuit 11 and a detection value of the transient voltage detected by the detection circuit 13.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present invention relates to a gate driver that drives the gate of a semiconductor switching element. [Background technology]

[0002] A gate driver that drives the gate of a semiconductor switching element controls a transient voltage corresponding to the voltage of the main terminal of the semiconductor switching element when the semiconductor switching element is switched to a desired target value for the purposes of reducing loss, reducing noise, preventing element failure, etc. The above-mentioned transient voltage includes the rate of change of the voltage of the main terminal when switching, that is, dV / dt, and the peak value of the voltage of the main terminal when switching, that is, the surge voltage.

[0003] Patent Document 1 discloses a technique for detecting dV / dt, which is the rate of change of the drain voltage of a semiconductor switching element that is a MOSFET, repeatedly adjusting the gate waveform so that the detected value does not exceed a target value, and terminating the adjustment at the stage when a gate waveform whose detected value does not exceed the target value is generated. Note that in the following description, the technique disclosed in Patent Document 1 will also be referred to simply as the prior art. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2019-57757 A Summary of the Invention [Problem to be solved by the invention]

[0005] In the conventional technology, it is necessary to operate the circuit to learn the optimal gate waveform profile, and it is difficult to obtain the optimal waveform during the trial and error period in such a learning process. Therefore, the conventional technology can only be applied to, for example, an adjustment process before shipping a product. In addition, in the conventional technology, since the gate signal that is considered to be optimal is generated after the learning is completed, if various characteristics change after the learning, it is not possible to correct the deviation caused by the change.

[0006] Although such conventional technology can cancel individual variations, it is not possible to make adjustments during actual operation, and so dV / dt gradually deviates from the target value due to aging fluctuations in the characteristics of the drive circuit, semiconductor switching elements, etc. In other words, conventional technology cannot accurately control dV / dt, which is the transient voltage when the semiconductor switching elements are switched, to the target value.

[0007] The present invention has been made in consideration of the above circumstances, and an object of the present invention is to provide a gate drive device that can precisely control the transient voltage during switching of a semiconductor switching element to a desired target value. [Means for solving the problem]

[0008] Claim 1 、2 The gate drive device described in the above drives the gates of semiconductor switching elements (5A, 5B, 5) and controls the voltage of the main terminal of the semiconductor switching element when the semiconductor switching element is switched. is the rate of change or peak value of The device controls a transient voltage to a desired target value, and includes a calculation circuit (11, 42, 52, 62, 82, 92), a drive circuit (12, 112), a detection circuit (13, 53, 63, 83, 93, 113) and a learning circuit (14, 43, 54, 64, 84, 94).

[0009] The calculation circuit calculates a manipulated variable for manipulating a gate drive speed of the semiconductor switching element by a predetermined calculation method using a target value of the transient voltage. The drive circuit drives the gate of the semiconductor switching element based on the manipulated variable calculated by the calculation circuit. The detection circuit detects the transient voltage. The learning circuit executes a learning process that can change the calculation method based on the manipulated variable calculated by the calculation circuit and a detection value of the transient voltage detected by the detection circuit. The calculation circuit is configured to acquire in advance a target value of the transient voltage and relationship information representing the relationship between the operation amount and the transient voltage, and calculate the operation amount based on the acquired target value of the transient voltage and the relationship information. The calculation circuit (11, 62) according to claim 1 is configured to acquire in advance a model parameter as the relationship information, and calculate the operation amount by a model formula using the target value of the transient voltage and the model parameter. The learning circuit (14, 64) according to claim 1 is configured to calculate a learning value that is a value corresponding to the model parameter based on the operation amount calculated by the calculation circuit and the detection value of the transient voltage detected by the detection circuit, and update the model parameter based on the calculated learning value. The calculation circuit (42, 52, 82, 92) according to claim 2 is configured to acquire in advance map data that is a map representing the relationship between the operation amount and the transient voltage, as the relationship information, and calculate the operation amount based on the target value of the transient voltage and the map data. The learning circuit (43, 54, 84, 94) according to claim 2 is configured to update the map data based on the operation amount calculated by the calculation circuit and the detection value of the transient voltage detected by the detection circuit.

[0010] In the above configuration, the learning process is executed, and the calculation method used by the calculation circuit to calculate the manipulated variable is optimized so as to correspond to the transient voltage actually generated in the semiconductor switching element to be driven by the gate drive device. In this way, according to the above configuration, since the calculation method is optimized according to the individual product variations, even if there are individual variations, it is possible to control the gate drive speed to a desired speed, and therefore the transient voltage to a desired target value.

[0011] In addition, in the above configuration, the learning process by the learning circuit can be performed while the gate drive device is actually operating, that is, during actual operation. In this way, with the above configuration, it is possible to execute the learning process even during actual operation, that is, to optimize the calculation method, so that the transient voltage can be controlled to a desired target value even when characteristics change over time or when load changes occur due to temperature or power supply voltage. Therefore, with the above configuration, it is possible to obtain the excellent effect of accurately controlling the transient voltage during switching of the semiconductor switching element to a desired target value. [Brief description of the drawings]

[0012] [Figure 1] FIG. 1 is a diagram showing a schematic configuration of a gate drive device and a half-bridge circuit according to a first embodiment; [Diagram 2] FIG. 4 is a diagram showing waveforms at various points when the semiconductor switching element according to the first embodiment is turned off; [Diagram 3]FIG. 1 is a diagram illustrating main functions of a gate driving device according to a first embodiment; [Figure 4] FIG. 1 is a diagram showing an example of a specific configuration of a gate driving device according to a first embodiment; [Diagram 5] FIG. 4 is a diagram showing a schematic flow of an operation performed by the gate driving device according to the first embodiment; [Figure 6] FIG. 11 is a diagram illustrating the main functions of a gate driving device according to a second embodiment. [Figure 7] FIG. 13 is a diagram showing an example of a specific configuration of a gate driving device according to a second embodiment; [Figure 8] FIG. 13 is a diagram showing an example of map data according to the second embodiment; [Figure 9] FIG. 13 is a diagram showing an example of updated map data created by an update process according to the second embodiment; [Figure 10] FIG. 11 is a diagram illustrating a flow of operations performed by the gate driving device according to the second embodiment. [Figure 11] FIG. 13 is a diagram showing an example of updated map data created by an update process of a first modified example according to the second embodiment; [Figure 12] FIG. 13 is a diagram showing an example of updated map data created by an update process of a second modified example according to the second embodiment; [Figure 13] FIG. 11 is a diagram illustrating main functions of a gate driving device according to a third embodiment. [Figure 14] FIG. 13 is a diagram showing an example of a specific configuration of a gate driving device according to a third embodiment; [Figure 15] FIG. 13 is a diagram showing an example of map data according to the third embodiment; [Figure 16] FIG. 11 is a diagram illustrating a flow of operations performed by a gate driving device according to a third embodiment. [Figure 17] FIG. 13 is a diagram illustrating main functions of a gate driving device according to a fourth embodiment. [Figure 18] FIG. 13 is a diagram showing an example of a specific configuration of a gate driving device according to a fourth embodiment. [Figure 19] FIG. 13 is a diagram illustrating a flow of operations performed by a gate driving device according to a fourth embodiment. [Figure 20]FIG. 13 is a diagram illustrating main functions of a gate driving device according to a fifth embodiment. [Figure 21] FIG. 13 is a diagram showing an example of a specific configuration of a gate driving device according to a fifth embodiment. [Figure 22] FIG. 13 is a diagram showing an example of map data according to the fifth embodiment; [Figure 23] FIG. 13 is a diagram showing an example of updated map data created by an update process according to the fifth embodiment; [Figure 24] FIG. 13 is a diagram illustrating a flow of operations performed by a gate driving device according to a fifth embodiment. [Diagram 25] FIG. 13 is a diagram illustrating main functions of a gate driving device according to a sixth embodiment. [Figure 26] FIG. 13 is a diagram showing an example of a specific configuration of a gate driving device according to a sixth embodiment. [Figure 27] FIG. 23 is a diagram showing an example of map data according to the sixth embodiment; [Figure 28] FIG. 13 is a diagram illustrating a flow of operations performed by a gate driving device according to a sixth embodiment. [Figure 29] FIG. 13 is a diagram illustrating main functions of a gate driving device according to a seventh embodiment. [Diagram 30] FIG. 13 is a diagram showing an example of a specific configuration of a gate driving device according to a seventh embodiment. [Diagram 31] FIG. 23 is a diagram illustrating a flow of operations performed by the gate driving device according to the seventh embodiment. [Diagram 32] A schematic diagram showing the relationship between the rate of change of the drain-source voltage and the gate voltage. [Diagram 33] A diagram showing the relationship between surge voltage and gate voltage [Diagram 34] Schematic diagram showing the relationship between the rate of change of drain-source voltage and gate resistance [Diagram 35] A schematic diagram showing the relationship between surge voltage and gate resistance DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Hereinafter, a number of embodiments will be described with reference to the drawings. Note that the same reference numerals are used to designate substantially the same components in the respective embodiments, and the description thereof will be omitted. (First embodiment) The first embodiment will be described below with reference to FIGS.

[0014] <Outline of the gate drive device> As shown in Fig. 1, a gate drive device 1A of this embodiment drives a semiconductor switching element 5A that constitutes the upper arm of a half-bridge circuit 4 connected between a pair of DC power supply lines 2 and 3. A gate drive device 1B of this embodiment drives a semiconductor switching element 5B that constitutes the lower arm of the half-bridge circuit 4. In this case, the gate drive devices 1A and 1B have the same configuration, and the semiconductor switching elements 5A and 5B have the same configuration. Therefore, in this specification, when it is not necessary to distinguish between the gate drive devices 1A and 1B and the semiconductor switching elements 5A and 5B, they will be referred to collectively with the alphabets at the end omitted.

[0015] The half-bridge circuit 4 is included in an inverter that drives a motor (not shown). A power supply voltage Va is supplied to the half-bridge circuit 4 from a DC power supply (not shown), such as a battery, via DC power supply lines 2 and 3. In this case, it is assumed that the gate drive device 1 is used in an automobile or other vehicle, and the power supply voltage Va applied to the semiconductor switching element 5 is a relatively high voltage, such as several hundred volts.

[0016] The semiconductor switching element 5 is a power element, and in this case includes an N-channel MOSFET and a freewheeling diode connected between the drain and source of the MOSFET with the source side as the anode, that is, connected in anti-parallel to the MOSFET. In this case, the freewheeling diode is provided as an element separate from the MOSFET, but the body diode of the MOSFET may be used as the freewheeling diode.

[0017] The drain of the semiconductor switching element 5A is connected to the high-potential side DC power supply line 2. The source of the semiconductor switching element 5A is connected to the drain of the semiconductor switching element 5B. The source of the semiconductor switching element 5B is connected to the low-potential side DC power supply line 3. A node N1 which is an interconnection node between the semiconductor switching elements 5A and 5B is connected to the motor (not shown). As a result, a load current IL which is an output current of the half-bridge circuit 4 is supplied to the motor. The controller 6 includes, for example, a microcomputer, and controls the operation of the half-bridge circuit 4 which constitutes the inverter, thereby controlling the drive of the motor.

[0018] The controller 6 is provided with a detection signal Sc indicating a detection value of the load current IL output from a current detection unit (not shown). The controller 6 generates and outputs a command signal Sa for commanding the operation of the gate drive device 1A and a command signal Sb for commanding the operation of the gate drive device 1B so that the load current IL coincides with a desired target current based on the detection signal Sc. The gate drive device 1A performs PWM control of the drive of the semiconductor switching element 5A based on the command signal Sa provided by the controller 6. Note that PWM is an abbreviation for Pulse Width Modulation. The gate drive device 1B performs PWM control of the drive of the semiconductor switching element 5B based on the command signal Sb provided by the controller 6.

[0019] In this case, the semiconductor switching element 5A and the semiconductor switching element 5B are turned on and off complementarily. Therefore, during the period when the semiconductor switching element 5A is on, the semiconductor switching element 5B is turned off, and during the period when the semiconductor switching element 5B is on, the semiconductor switching element 5A is turned off. In the above configuration, during the period when the load current IL flows from the node N1 to the motor, the semiconductor switching element 5A is driven to pass a current in the forward direction from the drain to the source, and the semiconductor switching element 5B is driven to pass a current in the reverse direction from the source to the drain.

[0020] In addition, in the above configuration, during the period when the load current IL flows from the motor to the node N1, the semiconductor switching element 5B is driven to pass a current in the forward direction from the drain to the source, and the semiconductor switching element 5A is driven to pass a current in the reverse direction from the source to the drain.

[0021] In the above configuration, the drain-source voltage Vds of the semiconductor switching element 5 is the voltage at the main terminals of the semiconductor switching element 5 and corresponds to the element voltage. Also, in the above configuration, the drain current Id is the current flowing between the main terminals of the semiconductor switching element 5 and corresponds to the element current. Note that in this specification, the drain current Id and the drain-source voltage Vds may be simply referred to as the current Id and the voltage Vds, respectively.

[0022] When the semiconductor switching element 5 is switched, specifically when the semiconductor switching element 5 is turned off, the waveforms of the various parts are as shown in Fig. 2. Note that Fig. 2 illustrates the waveforms of the various parts corresponding to the semiconductor switching element 5B, but the same waveforms are also obtained for the semiconductor switching element 5A. When the semiconductor switching element 5B is off, the off voltage Vds_off is approximately equal to the power supply voltage Va.

[0023] The peak value Vds_p of the voltage Vds at the time of turn-off corresponds to the peak value of the voltage at the main terminal at the time of switching of the semiconductor switching element 5. The peak value Vds_p is the off voltage Vds_off plus the voltage ΔVds, and is equal to the surge voltage superimposed on the semiconductor switching element 5B. Therefore, in the following description, the peak value Vds_p is also referred to as the surge voltage Vsrg. In this case, the gradient of the fluctuation of the voltage Vds at the time of turn-off, that is, the slew rate, corresponds to the rate of change of the voltage at the main terminal at the time of switching of the semiconductor switching element 5. In this specification, the gradient of the fluctuation of the voltage Vds may be referred to as the rate of change dV / dt.

[0024] The surge voltage Vsrg and the rate of change dV / dt described above both correspond to a transient voltage corresponding to the voltage at the main terminal of the semiconductor switching element 5 when the semiconductor switching element 5 is switched. The gate drive device 1 of this embodiment has various functions described below, and is therefore capable of controlling such a transient voltage to a desired target value. The transient voltage that is the object of control by the gate drive device 1 of this embodiment has a rate of change dV / dt.

[0025] <Major functions of gate drive unit> Next, the main functions of the gate driving device 1 will be described with reference to FIG. 3. In FIG. 3 and other figures, the main functions of the gate driving device 1 are shown in the form of functional blocks. A specific method for realizing each function will be described later. In the following description, of the two semiconductor switching elements 5, the one that is the driving target of the own device will be referred to as the semiconductor switching element 5 of the own arm, and the one that is the driving target of a gate driving device 1 other than the own device will be referred to as the semiconductor switching element 5 of the opposing arm. Note that when simply referring to a semiconductor switching element 5, it refers to the semiconductor switching element 5 of the own arm.

[0026] The calculation circuit 11 calculates an operation amount for operating the gate drive speed of the semiconductor switching element 5 by a predetermined calculation method using a target value of the change rate dV / dt. Examples of the operation amount include the gate current, gate voltage, and gate resistance of the semiconductor switching element 5. The drive circuit 12 drives the gate of the semiconductor switching element 5 based on the operation amount calculated by the calculation circuit 11. The detection circuit 13 detects the change rate dV / dt of the semiconductor switching element 5 of its own arm. The learning circuit 14 executes a learning process that can change the calculation method based on the operation amount calculated by the calculation circuit 11 and the detection value of the change rate dV / dt detected by the detection circuit 13.

[0027] In this case, the calculation circuit 11 is adapted to acquire in advance a target value of the rate of change dV / dt and relationship information representing the relationship between the manipulated variable and the rate of change dV / dt, and calculate the manipulated variable based on the acquired target value of the rate of change dV / dt and relationship information. Specifically, the calculation circuit 11 is adapted to acquire in advance model parameters as relationship information, and calculate the manipulated variable by a model formula using the target value of the rate of change dV / dt and the model parameters. In addition, as the above-mentioned learning process, the learning circuit 14 is adapted to calculate a learning value that is a value corresponding to the model parameter based on the manipulated variable calculated by the calculation circuit 11 and the detection value of the rate of change dV / dt detected by the detection circuit 13, and to change the calculation method of the manipulated variable by updating the model parameter based on the calculated learning value.

[0028] In this case, the drive circuit 12 is configured to drive the gate of the semiconductor switching element 5 with a constant current. Therefore, the calculation circuit 11 is configured to calculate the gate current Ig of the semiconductor switching element 5 as the manipulated variable. The calculation circuit 11 is configured to calculate the gate current Ig using the following formula (1) as a model formula, where K is a model parameter, dV / dt* is a target value of the rate of change dV / dt, and Ig is the gate current which is the manipulated variable. Ig = K × dV / dt … (1)

[0029] In addition, the learning circuit 14 calculates the learning value Ka using the following equation (2) as an inverse model equation, where the learning value is Ka, the gate current calculated by the calculation circuit 11 is Iga, and the detection value of the rate of change dV / dt detected by the detection circuit 13 is directly dV / dt. Ka = Iga ÷ dV / dt … (2)

[0030] The storage unit 15 can store the model parameter K updated by the learning circuit 14. The learning circuit 14 stores the updated model parameter K in the storage unit 15 before power is cut off to the gate drive device 1. The calculation circuit 11 is configured to calculate the operation amount using the model parameter K stored in the storage unit 15 at the start of the next operation to be performed after power is cut off to the gate drive device 1. In this case, when executing the learning process, the learning circuit 14 is configured to change the calculation method based on the past operation amount calculated by the calculation circuit 11 and the past detection value of the change rate dV / dt detected by the detection circuit 13 in addition to the present operation amount calculated by the calculation circuit 11 and the present detection value of the change rate dV / dt detected by the detection circuit 13.

[0031] <Specific configuration of the gate driving device> As a specific configuration of the gate driving device 1 having the above-mentioned functions, for example, a configuration example as shown in Fig. 4 can be adopted. Note that Fig. 4 shows a specific configuration of the gate driving device 1 using the gate driving device 1B as an example, but a similar configuration can also be adopted for the gate driving device 1A. The gate driving device 1B shown in Fig. 4 includes a calculation circuit 11, a driving circuit 12, a detection circuit 13, a learning circuit 14, a memory unit 15, etc.

[0032] The storage unit 15 is, for example, a non-volatile memory, and stores in advance a target value dV / dt* of the rate of change dV / dt, a value of the model parameter K, etc. If the system is one in which power is constantly supplied to the gate driver 1, a volatile memory can also be used as the storage unit 15. In this specification, the target value dV / dt* of the rate of change dV / dt may be referred to as a target rate of change dV / dt*, and the value of the model parameter K may be referred to as a K value.

[0033] The target rate of change dV / dt* is transmitted as a command from a higher-level control device, and can be obtained in advance by this. The K value can be obtained in advance, for example, by performing various simulations. When the calculation circuit 11 requests the storage unit 15 to read out the target rate of change dV / dt*, the storage unit 15 outputs a signal representing the target rate of change dV / dt*. When the calculation circuit 11 requests the storage unit 15 to read out the model parameter K, the storage unit 15 outputs a signal representing the model parameter K. In FIG. 4 and other figures, each signal is indicated by the same symbol as the value represented by each signal.

[0034] The voltage of node N1, i.e., the drain voltage of semiconductor switching element 5B, is input to detection circuit 13. Detection circuit 13 is configured as a circuit that inputs the drain voltage of semiconductor switching element 5B when the potential of the source of semiconductor switching element 5B is used as a reference, i.e., voltage Vds, and monitors the waveform of voltage Vds. Detection circuit 13 detects the rate of change dV / dt of voltage Vds by monitoring the waveform of voltage Vds. Detection circuit 13 outputs a signal indicating the detected value of the rate of change dV / dt.

[0035] At the start of operation, calculation circuit 11 requests storage unit 15 to read out target rate of change dV / dt* and model parameter K. As a result, signal dV / dt* and signal K output from storage unit 15 are input to calculation circuit 11. Calculation circuit 11 includes a register 21 that stores the target rate of change dV / dt* represented by signal dV / dt*, a register 22 that stores the K value represented by signal K, and an arithmetic circuit 23. Calculation circuit 11 stores the target rate of change dV / dt* and model parameter K read out from storage unit 15 in registers 21 and 22.

[0036] The arithmetic circuit 23 reads out the target rate of change dV / dt* stored in the register 21 and the K value stored in the register 22, and multiplies them together. The value obtained as a result of such arithmetic operation by the arithmetic circuit 23 corresponds to the gate current Ig described above. The arithmetic circuit 23 outputs a signal representing the gate current Ig. In this case, the K value stored in the register 22 is updated by the operation of the learning circuit 14 described later. Before the power supply to the gate driving device 1B is cut off, the register 22 outputs a signal representing the stored K value to the storage unit 15. As a result, the K value stored in the storage unit 15 is updated by being overwritten by the K value stored in the register 22.

[0037] The learning circuit 14 receives the signal dV / dt output from the detection circuit 13 and the signal Ig output from the calculation circuit 11. The learning circuit 14 includes an arithmetic circuit 24 and a filter processing circuit 25. The arithmetic circuit 24 divides the value of the gate current Ig represented by the signal Ig by the detection value of the rate of change dV / dt represented by the signal dV / dt. The value obtained as a result of such calculation by the arithmetic circuit 24 corresponds to the learning value Ka described above. The arithmetic circuit 24 outputs a signal representing the learning value Ka.

[0038] The filter processing circuit 25 is configured as, for example, a digital filter. The filter processing circuit 25 performs the following filter processing using the learning value Ka represented by the signal Ka output from the arithmetic circuit 24 and the K value read from the register 22. That is, the filter processing circuit 25 determines a learning value Ka', which is a value obtained by smoothing the learning value Ka using the exponential moving average of the smoothing coefficient α based on the following formula (3). However, the smoothing coefficient α is a value greater than 0 and less than 1, that is, a value that satisfies "0<α<1". Ka' = Ka × α + K × (1-α) … (3)

[0039] The filter processing circuit 25 outputs a signal representing the learning value Ka' to the register 22 of the calculation circuit 11. As a result, the K value stored in the register 22 is updated by being overwritten with the learning value Ka'. The filter processing by the filter processing circuit 25 may be a low-pass filter or a band-pass filter other than the exponential moving average, may be a simple moving average that holds the most recent 10 values ​​and uses the average value, or may be another FIR filter or IIR filter.

[0040] The drive circuit 12 is configured to drive the gate of the semiconductor switching element 5 with a constant current. That is, the drive circuit 12 includes current sources 26, 27 and switches 28, 29. The upstream terminal of the current source 26 is connected to a power supply line 31 to which a power supply voltage Vb is supplied, and the downstream terminal of the current source 26 is connected to the gate of the semiconductor switching element 5B via the switch 28. The power supply voltage Vb is a voltage based on the potential of a power supply line 32 connected to the source of the semiconductor switching element 5B, and is a voltage sufficiently higher than the gate threshold voltage of the semiconductor switching element 5B.

[0041] The current source 26 is a constant current circuit that generates a constant current to be supplied to the gate of the semiconductor switching element 5B when it is turned on, that is, a gate current Ig_on that turns on the gate of the semiconductor switching element 5B. Note that a resistor having a constant resistance value may be provided as a configuration on the turn-on side of the drive circuit 12 instead of the current source 26. In other words, the drive circuit 12 does not need to be configured to drive the turn-on side with a constant current. The switch 28 includes a semiconductor switching element such as a P-channel MOS transistor, and opens and closes between the current source 26 and the gate of the semiconductor switching element 5B.

[0042] The downstream terminal of the current source 27 is connected to the power supply line 32, and the upstream terminal is connected to the gate of the semiconductor switching element 5B via the switch 29. The current source 27 is a constant current circuit that generates a constant current to be drawn from the gate of the semiconductor switching element 5B when the element is turned off, that is, a gate current Ig_off for turning off the gate of the semiconductor switching element 5B. In this case, the current source 27 is configured to be able to change its current value based on the signal Ig output from the calculation circuit 11. The switch 29 includes a semiconductor switching element such as an N-channel MOS transistor, and opens and closes between the gate of the semiconductor switching element 5B and the current source 27.

[0043] A turn-on command ON, a turn-off command OFF, and a switching end command END are given to the driving circuit 12. In this case, the turn-on command ON and the turn-off command OFF are generated by a logic circuit (not shown) based on a command signal Sb, and the switching end command END is given from an external controller 6. The turn-on command ON and the turn-off command OFF can also be combined into one signal. In that case, for example, one signal can be made to indicate a turn-on command when it is at a high level and to indicate a turn-off command when it is at a low level. The switching end command END can also be generated inside the gate driving device 1B.

[0044] The operation of the drive circuit 12 is controlled by these commands. That is, during the period when the switching end command END is not given, the drive circuit 12 performs a switching operation to complementarily turn on and off the switches 28 and 29 based on the turn-on command ON and the turn-off command OFF. In this case, however, a period during which both the switches 28 and 29 are off, that is, a so-called dead time, is provided.

[0045] When a turn-on command ON is given, the drive circuit 12 turns on the switch 28. As a result, a gate current Ig_on is supplied to the gate of the semiconductor switching element 5B, and the semiconductor switching element 5B is turned on. When a turn-off command OFF is given, the drive circuit 12 turns on the switch 29. As a result, a gate current Ig_off is drawn from the gate of the semiconductor switching element 5B, and the semiconductor switching element 5B is turned off. When a switching end command END is given, the drive circuit 12 ends the switching operation.

[0046] <Flow of operation by the gate driver> Next, the flow of operations performed by the gate driving device 1 configured as above will be described with reference to Fig. 5. In the gate driving device 1, the process shown in Fig. 5 is executed from when the power is turned on to when the power is turned off. In step S101, which is executed first after the operation starts, the target change rate dV / dt* and the K value are read out from the storage unit 15 and stored in the registers 21 and 22 in the calculation circuit 11. That is, in step S101, the target change rate dV / dt* and the K value stored in the storage unit 15 are downloaded to the registers 21 and 22 in the calculation circuit 11.

[0047] After step S101 is executed, a loop start process of step S102 is executed. The loop start process of step S102 is a process of repeatedly executing the processes of steps S103 to S108 until a switching end command END is given, that is, with the giving of the switching end command END as the end condition, with step S109 as the loop end process. In step S103, a turn-on command ON is given, and the drive circuit 12 outputs a gate current Ig_on, thereby turning on the semiconductor switching element 5. The current value of the gate current Ig_on at this time is a predetermined current value.

[0048] In step S104, the arithmetic circuit 23 of the calculation circuit 11 calculates the gate current Ig based on the above-mentioned model formula (1). Note that step S104 can also be executed before step S103. That is, the execution order of steps S103 and S104 can be reversed. In step S105, a turn-off command OFF is given, and the drive circuit 12 outputs the gate current Ig_off, thereby turning off the semiconductor switching element 5. The current value of the gate current Ig_off at this time corresponds to the value of the gate current Ig calculated in step S104. In step S106, the detection circuit 13 detects the rate of change dV / dt of the voltage Vds generated at the time of turn-off.

[0049] In step S107, the arithmetic circuit 24 of the learning circuit 14 calculates the learning value Ka based on the inverse model equation (2). In step S108, the K value stored in the register 22 is updated by being overwritten with a learning value Ka' obtained by smoothing the learning value Ka obtained by performing a filter process by the filter processing circuit 25 of the learning circuit 14. These steps S107 and S108 correspond to the learning process executed by the learning circuit 14. In the gate driver 1, the processes of steps S102 to S109 as described above are repeatedly executed until a switching end command END is given.

[0050] That is, the loop process of steps S102 to S109 is repeatedly executed every time the semiconductor switching element 5 is switched. Then, when a switching end command END is given, the loop process of steps S102 to S109 ends and the process proceeds to step S110. In step S110, the K value stored in the storage unit 15 is updated by being overwritten with the K value stored in the register 22 of the calculation circuit 11. After step S110 is executed, the operation ends.

[0051] According to the gate driving device 1 of the present embodiment described above, the learning process is executed by the learning circuit 14, and the calculation method used by the calculation circuit 11 to calculate the gate current Ig, which is the manipulated variable for manipulating the gate driving speed when the semiconductor switching element 5 is turned off, is optimized so as to correspond to the rate of change dV / dt when the semiconductor switching element 5, which is the target of driving by the gate driving device 1, actually occurs in the semiconductor switching element 5 when it is turned off.

[0052] As described above, according to this embodiment, the calculation method is optimized in accordance with the individual variations of the products. Therefore, even if there are individual variations in the gate drive device 1 and the semiconductor switching element 5, it is possible to control the gate drive speed of the semiconductor switching element 5 to a desired speed, and ultimately to control the rate of change dV / dt at turn-off to a desired target value.

[0053] Furthermore, in the gate drive device 1, the learning process by the learning circuit 14 can be performed while the gate drive device 1 is actually operating, that is, during actual operation. As described above, according to this embodiment, since it is possible to execute the learning process even during actual operation, that is, to execute optimization of the calculation method, it is possible to control the rate of change dV / dt to a desired target value even when characteristics change due to aging or when load changes such as temperature or power supply voltage Va occur. Therefore, according to this embodiment, it is possible to obtain the excellent effect of accurately controlling the rate of change dV / dt at the time of switching of the semiconductor switching element 5, particularly at the time of turn-off, to a desired target value.

[0054] As described above, according to this embodiment, the rate of change dV / dt during switching of the semiconductor switching element 5 is set as the control target, and the rate of change dV / dt can be accurately controlled to a desired target value, so that it is possible to reduce both EMI and switching loss. Note that EMI is an abbreviation for Electromagnetic Interference.

[0055] In this case, the calculation circuit 11 is adapted to calculate the gate current Ig by a model equation using the model parameter K such as the above-mentioned equation (1). In addition, in this case, the learning circuit 14 is adapted to change the calculation method of the gate current Ig by calculating a learning value Ka corresponding to the model parameter K by an inverse model equation such as the above-mentioned equation (2) and updating the model parameter K based on the calculated learning value Ka. In this way, it is possible to realize optimization of the calculation method of the gate current Ig without requiring complex processing in the calculation circuit 11 and the learning circuit 14, so that the calculation circuit 11 and the learning circuit 14 can be configured relatively simply.

[0056] The gate drive device 1 includes a storage unit 15 capable of storing the model parameter K updated by the learning circuit 14. The learning circuit 14 stores the model parameter K updated before the gate drive device 1 is powered off in the storage unit 15, and the calculation circuit 11 calculates the gate current Ig using the model parameter K stored in the storage unit 15 at the start of the next operation executed after the gate drive device 1 is powered off. In this way, for the second and subsequent operations, the gate current Ig is calculated using the model parameter K learned in the previous operation from the start of the operation, so that the rate of change dV / dt can be stably and accurately controlled to the target value immediately after the start of the operation.

[0057] When the learning circuit 14 executes the learning process, in addition to the current gate current Ig calculated by the calculation circuit 11 and the detected value of the current rate of change dV / dt detected by the detection circuit 13, it changes the calculation method based on the past gate current Ig calculated by the calculation circuit 11 and the detected value of the past rate of change dV / dt detected by the detection circuit 13. Specifically, when the learning circuit 14 executes the learning process, it smoothes the learning value Ka obtained by performing filter processing using the current learning value Ka output from the arithmetic circuit 24 and the K value read from the register 22 of the calculation circuit 11, that is, the past learning value Ka, and updates the model parameter K based on the smoothed learning value Ka'. In this way, even when mislearning occurs in which the learning value Ka becomes an incorrect value due to the influence of noise, temporary abnormalities, etc., a situation in which the rate of change dV / dt deviates from the target value due to this influence can be suppressed.

[0058] <Modification Example Regarding Update of K Value> In this embodiment, the learning circuit 14 was configured to write and store the updated model parameter K in the storage unit 15 before the power supply of the gate drive device 1 was cut off, that is, to update the K value stored in the storage unit 15, but this can be modified as follows.

[0059] That is, the learning circuit 14 may store the updated model parameter K in the storage unit 15 after executing the learning process a specified number of times or more. Specifically, the learning circuit 14 may execute step S110 each time steps S107 and S108 are executed a specified number of times. That is, regarding the process shown in FIG. 5, it can be changed to execute step S110 during the loop process.

[0060] Furthermore, before the gate driver 1 is powered off or after the learning process has been executed a specified number of times (one or more), and the difference between the value of the model parameter K updated by the learning circuit 14 and the value of the model parameter K at the start of operation exceeds a preset allowable value, the learning circuit 14 may store the updated model parameter K in the storage unit 15. In this way, it is possible to maintain good stability in the control of the rate of change dV / dt immediately after the start of the second or subsequent operation, while suppressing the number of times of writing to the storage unit 15.

[0061] Furthermore, the learning circuit 14 does not need to store the updated model parameter K in the storage unit 15, that is, it does not need to update the K value stored in the storage unit 15. In this way, although the stability of control of the rate of change dV / dt immediately after the start of the second or subsequent operations decreases, it is possible to further reduce the number of times writing to the storage unit 15, which is preferable when the number of times writing to the storage unit 15 is limited. In this case, the gate driver 1 does not need to be equipped with the storage unit 15 in the first place, and the K value can use a previously fixed value as the initial value.

[0062] Second embodiment The second embodiment will be described below with reference to FIGS. <Major functions of gate drive unit> The main functions of the gate driving device 41 of this embodiment will be described with reference to Fig. 6. As shown in Fig. 6, the gate driving device 41 of this embodiment differs from the gate driving device 1 of the first embodiment in that it includes a calculation circuit 42 instead of the calculation circuit 11, a learning circuit 43 instead of the learning circuit 14, and a memory unit 44 instead of the memory unit 15.

[0063] The calculation circuit 42 is adapted to acquire map data in advance as relationship information, and calculate the gate current Ig, which is the manipulated variable, from the target value of the rate of change dV / dt and the map data. In this case, the map data is a one-dimensional map that indicates the relationship between the gate current Ig, which is the manipulated variable, and the rate of change dV / dt, which is the transient voltage, and specifically, is data such as that shown in FIG. 8. In the map data shown in FIG. 8, the unit of the rate of change dV / dt is [kV / μs], and the unit of the gate current Ig is [A]. In the following description, unless otherwise specified, the units of the rate of change dV / dt and the gate current Ig are the same as those shown in FIG. 8, and only the values ​​are described without the units.

[0064] As a learning process, the learning circuit 43 changes the calculation method of the manipulated variable by updating the map data based on the manipulated variable calculated by the calculation circuit 42 and the detection value of the rate of change dV / dt detected by the detection circuit 13. The memory unit 44 can store the map data updated by the learning circuit 43. The learning circuit 43 stores the updated map data in the memory unit 44 before the power supply to the gate drive device 41 is cut off and when the difference between the value of the map data updated by the learning circuit 43 and the value of the map data at the start of operation exceeds a preset allowable value.

[0065] The value of the map data MAP is the value of the gate current Ig which is the manipulated variable or the value of the rate of change dV / dt which is the transient voltage, and such a determination can be made for each value of the gate current Ig or each value of the rate of change dV / dt in the map data MAP. The calculation circuit 42 is adapted to calculate the manipulated variable using the map data stored in the memory unit 44 at the start of the next operation which is executed after the power supply to the gate drive device 1 is cut off.

[0066] <Specific configuration of the gate driving device> As a specific configuration of the gate driving device 41 having the above-mentioned functions, for example, a configuration example shown in Fig. 7 can be adopted. The gate driving device 41 shown in Fig. 7 differs from the gate driving device 1 shown in Fig. 4 in that it has a calculation circuit 42 instead of the calculation circuit 11, a learning circuit 43 instead of the learning circuit 14, and a memory unit 44 instead of the memory unit 15.

[0067] The storage unit 44 differs from the storage unit 15 in that the map data MAP, which is the one-dimensional map described above, is stored in advance instead of the value of the model parameter K. The map data MAP can be acquired in advance, for example, by performing various simulations. When a request to read out the map data MAP is received from the calculation circuit 42, the storage unit 44 outputs a signal representing the map data MAP.

[0068] The calculation circuit 42 differs from the calculation circuit 11 in that it includes a register 45 for storing map data MAP instead of the register 22, and a search processing circuit 46 instead of the arithmetic circuit 23. When starting operation, the calculation circuit 42 requests the memory unit 44 to read out the target change rate dV / dt* and the map data MAP. As a result, the signal dV / dt* and signal MAP output from the memory unit 44 are input to the calculation circuit 42. The calculation circuit 42 stores the target change rate dV / dt* and the map data MAP read from the memory unit 44 in the registers 21, 45.

[0069] The search processing circuit 46 reads out the target change rate dV / dt* stored in the register 21 and the map data MAP stored in the register 45. Then, the search processing circuit 46 executes a search process to search for a gate current Ig in the map data MAP corresponding to the value of the target change rate dV / dt* read out from the register 21, and to output a signal Ig representing the searched value of the gate current Ig. For example, if the value of the target change rate dV / dt* read out from the register 21 is "6", the search processing circuit 46 searches for a gate current Ig=0.15 in the map data MAP corresponding to the change rate dV / dt=6, and outputs a signal Ig representing the searched value of the gate current Ig, "0.15".

[0070] In this case, the map data MAP stored in the register 45 is updated by the operation of the learning circuit 43, which will be described later. Before the power supply to the gate drive device 41 is cut off and the difference between the map data value updated by the learning circuit 43 and the map data value at the start of operation exceeds a preset allowable value, the register 45 outputs a signal representing the stored map data MAP to the memory unit 44. As a result, the map data MAP stored in the memory unit 44 is updated by being overwritten by the map data MAP stored in the register 45.

[0071] The learning circuit 43 differs from the learning circuit 14 in that it includes an update processing circuit 47 instead of the arithmetic circuit 24 and the filter processing circuit 25. The learning circuit 43 receives the signal dV / dt output from the detection circuit 13 and the signals MAP and Ig output from the calculation circuit 42. The update processing circuit 47 searches for the gate current Ig in the map data MAP corresponding to the detection value of the rate of change dV / dt detected by the detection circuit 13, creates updated map data MAP' by changing the value of the gate current Ig in the map data MAP found to the value of the gate current Ig calculated by the calculation circuit 42, and executes an update process to output a signal representing the updated map data MAP'.

[0072] For example, if the detection value of the rate of change dV / dt detected by the detection circuit 13 is "7" and the value of the gate current Ig calculated by the calculation circuit 42 is "0.15", the update processing circuit 47 searches for the gate current Ig=0.20 in the map data MAP corresponding to the rate of change dV / dt=7. The update processing circuit 47 then creates update data MAP' in which the value of the gate current Ig corresponding to the rate of change dV / dt=7 in the searched map data MAP is changed to "0.15", which is the value of the gate current Ig calculated by the calculation circuit 42.

[0073] Specifically, the updated map data MAP' is data such as that shown in Fig. 9, for example. As shown in Fig. 9, in the updated map data MAP', the value of the gate current Ig corresponding to the rate of change dV / dt=7 is changed from "0.20" to "0.15". The update processing circuit 47 outputs a signal representing the updated map data MAP' created by such an update processing to the register 45 of the calculation circuit 42. As a result, the map data MAP stored in the register 45 is updated by being overwritten with the updated map data MAP'.

[0074] <Flow of operation by the gate driver> Next, the flow of operations performed by the gate drive device 41 having the above configuration will be described with reference to Fig. 10. In the gate drive device 41, the process shown in Fig. 10 is executed from when the power is turned on until when the power is turned off. In step S201, which is executed first after the operation starts, the target change rate dV / dt* and map data MAP are read out from the storage unit 44 and stored in the registers 21, 45 in the calculation circuit 42. That is, in step S201, the target change rate dV / dt* and map data MAP stored in the storage unit 44 are downloaded to the registers 21, 45 in the calculation circuit 42.

[0075] After step S201 is executed, a loop start process of step S202 is executed. The loop start process of step S202 is a process of repeatedly executing the processes of steps S203 to S207 until a switching end command END is given, that is, with the giving of the switching end command END as the end condition, with step S208 as the loop end process. In step S203, a turn-on command ON is given, and the drive circuit 12 outputs a gate current Ig_on, thereby turning on the semiconductor switching element 5. The current value of the gate current Ig_on at this time is a predetermined current value.

[0076] In step S204, the search processing circuit 46 of the calculation circuit 42 executes the above-mentioned search processing. That is, in step S204, the calculation circuit 42 searches for the gate current Ig from the map data MAP stored in the register 45 by using the target change rate dV / dt* stored in the register 21. Note that step S204 can also be executed before step S203. That is, the execution order of steps S203 and S204 can also be interchanged.

[0077] In step S205, a turn-off command OFF is given, and the drive circuit 12 outputs the gate current Ig_off, thereby turning off the semiconductor switching element 5. The current value of the gate current Ig_off at this time corresponds to the value of the gate current Ig found in step S204. In step S206, the detection circuit 13 detects the rate of change dV / dt of the voltage Vds generated at the time of turn-off.

[0078] In step S207, the update processing circuit 47 of the learning circuit 43 executes the above-mentioned update processing, thereby updating the map data MAP stored in the register 45 of the calculation circuit 42 by overwriting it with the updated map data MAP'. Step S207 corresponds to the learning processing executed by the learning circuit 43. In the gate driver 41, the processing of steps S202 to S208 as described above is repeatedly executed until a switching end command END is given.

[0079] That is, the loop process of steps S202 to S208 is repeatedly executed every time the semiconductor switching element 5 is switched. Then, when a switching end command END is given, the loop process of steps S202 to S208 ends and the process proceeds to step S209. In step S209, it is determined whether or not a difference between a current value, which is the value of the map data MAP stored in the register 45, and an initial value, which is the value of the map data MAP stored in the storage unit 44, i.e., the value of the map data MAP at the start of operation, exceeds a predetermined allowable value. Note that in this case, the value of the map data MAP refers to the value of the gate current Ig, which is the manipulated variable, and such a determination is made for each value of the gate current Ig in the map data MAP.

[0080] If the difference between the current value and the initial value is equal to or less than the allowable value, step S209 becomes "NO" and the operation ends without executing step S210. On the other hand, if the difference between the current value and the initial value exceeds the allowable value, step S209 becomes "YES" and the operation proceeds to step S210. In step S210, the map data MAP stored in the memory unit 44 is updated by being overwritten with the map data MAP stored in the register 45 of the calculation circuit 42. After step S210 is executed, the operation ends.

[0081] The gate drive device 41 of this embodiment described above also has the same effect as the first embodiment, that is, the excellent effect of being able to precisely control the rate of change dV / dt to a desired target value when the semiconductor switching element 5 is switched, particularly when it is turned off. In this case, the calculation circuit 42 calculates the value of the gate current Ig using map data MAP, which is a one-dimensional map showing the relationship between the gate current Ig and the rate of change dV / dt.

[0082] In this case, the learning circuit 43 changes the calculation method of the gate current Ig by updating the map data MAP based on the value of the gate current Ig calculated by the calculation circuit 42 and the detection value of the rate of change dV / dt detected by the detection circuit 13. In this way, the calculation error of the gate current Ig by the calculation circuit 42 is reduced, so that the rate of change dV / dt can be controlled to the target value with even greater accuracy.

[0083] The gate drive device 41 includes a storage unit 44 capable of storing map data MAP updated by the learning circuit 43. The learning circuit 43 stores the updated map data MAP in the storage unit 44 when the gate drive device 41 is before power is cut off and the difference between the value of the map data MAP updated by the learning circuit 43 and the value of the map data MAP at the start of the operation exceeds a preset allowable value, and the calculation circuit 42 calculates the gate current Ig using the map data MAP stored in the storage unit 44 at the start of the next operation executed after the power is cut off of the gate drive device 41. In this way, the number of times of writing to the storage unit 44 is suppressed, and the gate current Ig is calculated using the map data MAP learned in the previous operation from the start of the second or subsequent operation, so that the rate of change dV / dt can be stably and accurately controlled to the target value immediately after the start of the operation.

[0084] <Modifications regarding map data updates> In this embodiment, before power is cut off to the gate drive device 41 and if the difference between the value of the map data MAP updated by the learning circuit 43 and the value of the map data MAP at the start of operation exceeds a preset allowable value, the learning circuit 43 writes and stores the updated map data MAP in the memory unit 44, i.e., updates the map data MAP stored in the memory unit 44. However, this can be modified as follows.

[0085] That is, the learning circuit 43 may store the updated map data MAP in the storage unit 44 after the learning process has been executed a specified number of times (one or more) and the difference between the value of the map data MAP updated by the learning circuit 43 and the value of the map data MAP at the start of operation exceeds a preset allowable value. Specifically, the learning circuit 43 may execute steps S209 and S210 every time step S207 is executed a specified number of times. That is, the process shown in FIG. 10 can be modified so that steps S209 and S210 are executed during loop processing.

[0086] Furthermore, the learning circuit 43 may store the updated map data MAP in the storage unit 44 before the power supply to the gate drive device 41 is cut off or after the learning process has been executed a specified number of times or more. Specifically, the learning circuit 43 may execute step S210 without executing step S209 after the loop process ends. That is, the process shown in FIG. 10 can be modified so as to omit step S209. In this way, for the second or subsequent operations, the gate current Ig is calculated using the map data MAP learned in the previous operation from the start of the operation, so that the rate of change dV / dt can be stably and accurately controlled to the target value immediately after the start of the operation.

[0087] Furthermore, the learning circuit 43 does not need to store the updated map data MAP in the memory unit 44, i.e., it is not necessary to update the map data MAP stored in the memory unit 44. In this way, although the stability of control of the rate of change dV / dt immediately after the start of the second or subsequent operations decreases, it is possible to further reduce the number of times data is written to the memory unit 44, which is preferable when the number of times data is written to the memory unit 44 is limited. In this case, the gate drive device 41 does not need to be equipped with the memory unit 44 in the first place, and a previously fixed value may be used as the initial value of the map data MAP.

[0088] <Modifications regarding learning process> When executing the learning process, the learning circuit 43 can change the calculation method based on the past gate current Ig calculated by the calculation circuit 42 and the past detection value of the change rate dV / dt detected by the detection circuit 13, in addition to the present gate current Ig calculated by the calculation circuit 42 and the present detection value of the change rate dV / dt detected by the detection circuit 13. Specifically, when executing the learning process, the learning circuit 43 can update the map data by update map data obtained by smoothing the update map data MAP' obtained by performing a filter process using the present update map data MAP' output from the update processing circuit 47 and the map data MAP corresponding to the past update map data MAP' stored in the register 45 of the calculation circuit 42.

[0089] As the filtering process, for example, various processes described in the first embodiment can be adopted. In this way, even if erroneous learning occurs in which the value of the update map data MAP' becomes an erroneous value due to the influence of noise, temporary abnormality, etc., it is possible to suppress a situation in which the rate of change dV / dt becomes a value that deviates from the target value due to the influence.

[0090] <Modifications regarding update processing> The update process in which the update processing circuit 47 of the learning circuit 43 creates the updated map data MAP', that is, the process of updating the map data, can be modified as follows. [1] First variant The update processing circuit 47 of the learning circuit 43 can be modified to update the map data MAP by changing the value of the gate current Ig on the searched map data MAP by the difference between the value of the gate current Ig on the searched map data MAP and the value of the gate current Ig calculated by the calculation circuit 42, and by changing the value of the gate current Ig within a predetermined range centered on the gate current Ig on the searched map data MAP by the above-mentioned difference.

[0091] For example, if the detection value of the rate of change dV / dt detected by the detection circuit 13 is "7" and the value of the gate current Ig calculated by the calculation circuit 42 is "0.15", and the predetermined range is ±2 [kV / μs], the updated map data MAP' created by the update process of the first modified example described above will be data as shown in Fig. 11. As shown in Fig. 11, in this case, the value of the gate current Ig corresponding to the rate of change dV / dt=7 is changed from "0.20" to "0.15".

[0092] In this case, the values ​​of the gate current Ig corresponding to the data within the range of ±2 around the rate of change dV / dt=7, i.e., the rates of change dV / dt=5, dV / dt=6, dV / dt=8, and dV / dt=9, are all changed by "-0.05". "-0.05" is the difference between the searched value of the gate current Ig, "0.20", and the value of the gate current Ig calculated by the calculation circuit 42, "0.15".

[0093] In addition, the value of the gate current Ig corresponding to the rate of change dV / dt=5 has been changed to "0.07" which is smaller than the value of "0.09" of the gate current Ig corresponding to the rate of change dV / dt=4, and an inversion phenomenon occurs in the values ​​of the gate current Ig corresponding to the rates of change dV / dt=4 and dV / dt=5. Therefore, a predetermined limit may be imposed on the value of the gate current Ig after the change so that such an inversion phenomenon does not occur.

[0094] According to the update process of the first modified example, not only one value but also its surrounding values ​​are updated in one learning process, so that learning of the map data, i.e., optimization of the calculation method, can be realized more quickly. Therefore, according to the update process of the first modified example, the calculation error of the gate current Ig by the calculation circuit 42 is reduced, so that the rate of change dV / dt can be controlled to the target value with higher accuracy. Note that the predetermined range is not limited to the above-mentioned range, and can be, for example, the entire range of the map data MAP.

[0095] [2] Second variant The update processing circuit 47 of the learning circuit 43 can be modified to update the map data MAP by changing the value of the gate current Ig on the searched map data MAP by the difference between the value of the gate current Ig on the searched map data MAP and the value of the gate current Ig calculated by the calculation circuit 42, and by changing the value of the gate current Ig within a predetermined range centered on the gate current Ig on the searched map data MAP by a value obtained by multiplying the above-mentioned difference by a weighting coefficient that attenuates the value the more distant it is from the center.

[0096] For example, if the detection value of the rate of change dV / dt detected by the detection circuit 13 is "7" and the value of the gate current Ig calculated by the calculation circuit 42 is "0.15", and the predetermined range is ±2 [kV / μs], the updated map data MAP' created by the update process of the second modified example described above will be data as shown in Fig. 12. As shown in Fig. 12, in this case, the value of the gate current Ig corresponding to the rate of change dV / dt=7 is changed from "0.20" to "0.15".

[0097] In this case, the data within the range of ±2 around the rate of change dV / dt=7, that is, the gate current Ig values ​​corresponding to the rates of change dV / dt=5, dV / dt=6, dV / dt=8, and dV / dt=9, are all changed by "-0.05 x weighting coefficient." "-0.05" is the difference between the searched gate current Ig value of "0.20" and the gate current Ig value of "0.15" calculated by the calculation circuit 42. The weighting coefficient is set to "0.5" for the rate of change dV / dt=6 and the rate of change dV / dt=8, and to "0.25" for the rate of change dV / dt=5 and the rate of change dV / dt=9.

[0098] Specifically, the value of the gate current Ig corresponding to a rate of change dV / dt=5 has been changed from "0.12" to "0.11", the value of the gate current Ig corresponding to a rate of change dV / dt=6 has been changed from "0.15" to "0.13", the value of the gate current Ig corresponding to a rate of change dV / dt=8 has been changed from "0.25" to "0.23", and the value of the gate current Ig corresponding to a rate of change dV / dt=9 has been changed from "0.30" to "0.29".

[0099] According to the update process of the second modification, not only one value but also its surrounding values ​​are updated in one learning process, so that learning of the map data, that is, optimization of the calculation method, can be realized more quickly. Therefore, according to the update process of the second modification, the calculation error of the gate current Ig by the calculation circuit 42 is reduced, so that the rate of change dV / dt can be controlled to the target value with higher accuracy.

[0100] Furthermore, according to the update process of the second modification, the value of the gate current Ig within a predetermined range centered on the gate current Ig on the searched map data MAP is changed by a value obtained by multiplying the difference by a weighting coefficient that attenuates the value the farther away from the center it is, so that it is possible to reduce the possibility of the occurrence of the inversion phenomenon described in the update process of the first modification. Note that the predetermined range is not limited to the above range, and can be, for example, the entire range of the map data MAP.

[0101] Third embodiment The third embodiment will be described below with reference to FIGS. <Major functions of gate drive unit> The main functions of the gate drive device 51 of this embodiment will be described with reference to Fig. 13. As shown in Fig. 13, the gate drive device 51 of this embodiment differs from the gate drive device 41 of the second embodiment in that it includes a calculation circuit 52 instead of the calculation circuit 42, a detection circuit 53 instead of the detection circuit 13, a learning circuit 54 instead of the learning circuit 43, and a storage unit 55 instead of the storage unit 44.

[0102] The detection circuit 53 detects the element temperature, that is, the temperature Tj of the semiconductor switching element 5, in addition to the rate of change dV / dt. The calculation circuit 52, like the calculation circuit 42, acquires map data in advance as relational information. However, in this case, the map data is a multidimensional map that combines the rate of change dV / dt, which is a transient voltage, and the temperature Tj of the semiconductor switching element 5 to hold the gate current Ig, which is an operation amount, and is specifically data such as that shown in FIG. 15. In the map data shown in FIG. 15, the unit of the temperature Tj is "°C". In the following description, unless otherwise specified, the unit of the temperature Tj is the same as that shown in FIG. 15, and the unit will be omitted and only the value will be described.

[0103] The calculation circuit 52 is adapted to calculate the gate current Ig, which is the manipulated variable, based on the target value of the rate of change dV / dt, the detection value of the temperature Tj by the detection circuit 53, and the map data. The learning circuit 54 can execute a learning process similar to that of the learning circuit 43. The memory unit 55 can store the map data updated by the learning circuit 54. The learning circuit 54 stores the updated map data in the memory unit 55 before the power supply to the gate drive device 51 is cut off. The calculation circuit 52 is adapted to calculate the manipulated variable using the map data stored in the memory unit 55 at the start of the next operation to be executed after the power supply to the gate drive device 51 is cut off.

[0104] <Specific configuration of the gate driving device> As a specific configuration of the gate driving device 51 having the above-mentioned functions, for example, a configuration example shown in Fig. 14 can be adopted. The gate driving device 51 shown in Fig. 14 differs from the gate driving device 41 of the second embodiment shown in Fig. 7 in that it has a calculation circuit 52 instead of the calculation circuit 42, a detection circuit 53 instead of the detection circuit 13, a learning circuit 54 instead of the learning circuit 43, and a storage unit 55 instead of the storage unit 44.

[0105] The detection circuit 53 detects the rate of change dV / dt in the same manner as the detection circuit 13, and detects the temperature Tj as follows. In this case, a temperature sensor 56 is disposed near the semiconductor switching element 5. The temperature sensor 56 outputs temperature information corresponding to the detected temperature of the semiconductor switching element 5 as a voltage signal Vtj. The voltage signal Vtj output from the temperature sensor 56 is input to the detection circuit 53. The detection circuit 53 has a configuration for acquiring the temperature information represented by the voltage signal Vtj, thereby detecting the temperature Tj of the semiconductor switching element 5. The detection circuit 53 outputs a signal representing the detected value of the rate of change dV / dt and a signal representing the detected value of the temperature Tj.

[0106] The memory unit 55 differs from the memory unit 44 in that the map data MAP stored therein is the above-mentioned two-dimensional map. The calculation circuit 52 differs from the calculation circuit 42 in that a search processing circuit 57 is provided instead of the search processing circuit 46. The calculation circuit 42 performs substantially the same operations as the calculation circuit 42, except for the operations executed by the search processing circuit 57. The search processing circuit 57 reads out the target change rate dV / dt* stored in the register 21 and the map data MAP stored in the register 45. The search processing circuit 57 receives the signal Tj output from the detection circuit 53.

[0107] The search processing circuit 57 executes a search process to search for a gate current Ig on the map data MAP that corresponds to the value of the target rate of change dV / dt* read from the register 21 and that corresponds to the detected value of the temperature Tj of the semiconductor switching element 5 represented by the signal Tj, and to output a signal Ig that represents the searched value of the gate current Ig. For example, if the value of the target rate of change dV / dt* read from the register 21 is "3" and the detected value of the temperature Tj is "50", the search processing circuit 57 searches for a gate current Ig=0.09 on the map data MAP that corresponds to the rate of change dV / dt=3 and the temperature Tj=50, and outputs a signal Ig that represents the searched value of the gate current Ig, "0.09".

[0108] In this case, the map data MAP stored in the register 45 is updated by the operation of the learning circuit 54, which will be described later. Before the power supply to the gate drive device 51 is cut off, the register 45 outputs a signal representing the stored map data MAP to the memory unit 55. As a result, the map data MAP stored in the memory unit 55 is updated by being overwritten with the map data MAP stored in the register 45.

[0109] The learning circuit 54 differs from the learning circuit 43 in that it includes an update processing circuit 58 instead of the update processing circuit 47. The learning circuit 54 receives the signals dV / dt and Tj output from the detection circuit 53, and the signals MAP and Ig output from the calculation circuit 52. The update processing circuit 58 searches for the gate current Ig in the map data MAP that corresponds to the detection value of the rate of change dV / dt detected by the detection circuit 53 and that corresponds to the detection value of the temperature Tj detected by the detection circuit 53, creates updated map data MAP' by changing the value of the gate current Ig in the map data MAP found to the value of the gate current Ig calculated by the calculation circuit 52, and performs an update process to output a signal representing the updated map data MAP'.

[0110] For example, when the detection values ​​of the rate of change dV / dt and the temperature Tj detected by the detection circuit 53 are "4" and "50", respectively, and the value of the gate current Ig calculated by the calculation circuit 52 is "0.09", the update processing circuit 58 searches for the gate current Ig=0.10 in the map data MAP corresponding to the rate of change dV / dt=4 and the temperature Tj=50. Then, the update processing circuit 58 creates update data MAP' in which the value of the gate current Ig corresponding to the rate of change dV / dt=4 and the temperature Tj=50 in the searched map data MAP is changed to "0.09", which is the value of the gate current Ig calculated by the calculation circuit 52. The update processing circuit 58 outputs a signal representing the updated map data MAP' created by such an update process to the register 45 of the calculation circuit 52. As a result, the map data MAP stored in the register 45 is updated by being overwritten with the updated map data MAP'.

[0111] <Flow of operation by the gate driver> Next, the flow of operations performed by the gate drive device 51 having the above configuration will be described with reference to Fig. 16. In the gate drive device 51, the process shown in Fig. 16 is executed from when the power is turned on until when the power is turned off. In step S301, which is executed first after the operation starts, the target change rate dV / dt* and map data MAP are read out from the storage unit 55 and stored in the registers 21, 45 in the calculation circuit 52. That is, in step S301, the target change rate dV / dt* and map data MAP stored in the storage unit 55 are downloaded to the registers 21, 45 in the calculation circuit 52.

[0112] After step S301 is executed, a loop start process of step S302 is executed. The loop start process of step S302 is a process of repeatedly executing the processes of steps S303 to S308 until a switching end command END is given, that is, with the giving of the switching end command END as the end condition, with step S309 as the loop end process. In step S303, a turn-on command ON is given, and the drive circuit 12 outputs a gate current Ig_on, thereby turning on the semiconductor switching element 5. The current value of the gate current Ig_on at this time is a predetermined current value.

[0113] In step S304, the detection circuit 53 detects the temperature Tj of the semiconductor switching element 5, that is, the element temperature. In step S305, the search processing circuit 57 of the calculation circuit 52 executes the above-mentioned search processing. That is, in step S305, the calculation circuit 52 searches for the gate current Ig from the map data MAP stored in the register 45, using the target change rate dV / dt* stored in the register 21 and the temperature Tj detected in step S304. Note that steps S304 and S305 can also be executed before step S303. That is, the execution order of step S303 and steps S304 and S305 can also be interchanged.

[0114] In step S306, a turn-off command OFF is given, and the drive circuit 12 outputs the gate current Ig_off, thereby turning off the semiconductor switching element 5. The current value of the gate current Ig_off at this time corresponds to the value of the gate current Ig found in step S305. In step S307, the detection circuit 13 detects the rate of change dV / dt of the voltage Vds generated at the time of turn-off. In step S307, the detection circuit 53 may detect the temperature Tj in addition to the rate of change dV / dt.

[0115] In step S308, the update processing circuit 58 of the learning circuit 54 executes the above-mentioned update processing, thereby updating the map data MAP stored in the register 45 of the calculation circuit 52 by overwriting it with the updated map data MAP'. Step S308 corresponds to the learning processing executed by the learning circuit 54. In the gate driving device 51, the processing of steps S302 to S309 as described above is repeatedly executed until a switching end command END is given.

[0116] That is, the loop process of steps S302 to S309 is repeatedly executed every time the semiconductor switching element 5 is switched. Then, when a switching end command END is given, the loop process of steps S302 to S309 ends and the process proceeds to step S310. In step S310, the map data MAP stored in the storage unit 55 is updated by being overwritten with the map data MAP stored in the register 45 of the calculation circuit 52. After step S310 is executed, the operation ends.

[0117] The gate drive device 51 of this embodiment described above also provides the same effect as the first embodiment, that is, the excellent effect of being able to precisely control the rate of change dV / dt at the time of switching, particularly at the time of turn-off, of the semiconductor switching element 5 to a desired target value. Furthermore, the gate drive device 51 of this embodiment provides the following effect. That is, the rate of change dV / dt at the time of turn-off that actually occurs in the semiconductor switching element 5 that is the drive target of the gate drive device 51 may vary depending on the temperature Tj of the semiconductor switching element 5, etc.

[0118] Therefore, in this case, the calculation circuit 52 is adapted to calculate the value of the gate current Ig using map data MAP, which is a two-dimensional map that holds the gate current Ig by combining the rate of change dV / dt and the temperature Tj. Also, in this case, the learning circuit 54 is adapted to change the calculation method of the gate current Ig by updating the map data MAP based on the value of the gate current Ig calculated by the calculation circuit 52 and the detected values ​​of the rate of change dV / dt and the temperature Tj detected by the detection circuit 53. In this way, the calculation error of the gate current Ig by the calculation circuit 52 caused by the temperature Tj of the semiconductor switching element 5 is reduced, so that the rate of change dV / dt can be controlled to the target value with even greater accuracy.

[0119] The gate drive device 51 includes a storage unit 55 capable of storing map data MAP updated by the learning circuit 54. The learning circuit 54 stores the map data MAP updated before power is cut off to the gate drive device 51 in the storage unit 55, and the calculation circuit 52 calculates the gate current Ig using the map data MAP stored in the storage unit 55 at the start of the next operation executed after power is cut off to the gate drive device 51. In this way, for the second or subsequent operations, the gate current Ig is calculated using the map data MAP learned in the previous operation from the start of the operation, so that the rate of change dV / dt can be stably and accurately controlled to the target value immediately after the start of the operation.

[0120] <Modifications regarding map data> The rate of change dV / dt actually occurring in the semiconductor switching element 5 driven by the gate driver 51 at the time of turn-off can vary depending not only on the temperature Tj of the semiconductor switching element 5, but also on the temperature of the gate driver 51, the power supply voltage Va which is the voltage applied between the main terminals of the semiconductor switching element 5, i.e., between the drain and source, and the element current which is the current flowing between the main terminals of the semiconductor switching element 5, i.e., between the drain and source.

[0121] Therefore, the map data MAP can be a multidimensional map that holds the gate current Ig, which is the manipulated variable, by combining the rate of change dV / dt, which is the transient voltage, with at least one physical quantity among the temperature Tj of the semiconductor switching element 5, the temperature of the gate driver 51, the power supply voltage Va, and the element current. In this case, the detection circuit 53 needs to be configured to detect at least one physical quantity among the temperature Tj of the semiconductor switching element 5, the temperature of the gate driver 51, the power supply voltage Va, and the element current.

[0122] In this case, the calculation circuit 52 calculates the gate current Ig from the target value dV / dt* of the rate of change dV / dt, the detected values ​​of the physical quantities by the detection circuit 53, and the map data MAP. In this way, calculation errors in the gate current Ig caused by physical quantities such as the temperature Tj of the semiconductor switching element 5, the temperature of the gate driver 51, the power supply voltage Va, and the element current, that is, caused by various disturbance factors, are reduced, so that the rate of change dV / dt can be controlled to the target value with even greater accuracy.

[0123] <Modifications regarding map data updates> In this embodiment, the learning circuit 54 writes and stores the updated map data MAP in the memory unit 55 before power is cut off to the gate drive device 51, that is, updates the map data MAP stored in the memory unit 55. However, this can be modified as follows.

[0124] That is, the learning circuit 54 may execute the learning process a specified number of times, and then store the updated map data MAP in the storage unit 55. Specifically, the learning circuit 54 may execute step S310 every time step S308 is executed a specified number of times. That is, the process shown in FIG. 16 can be modified so that step S310 is executed during loop processing.

[0125] Moreover, the learning circuit 54 may store the updated map data MAP in the storage unit 55 before the power supply to the gate drive device 51 is cut off or after the learning process has been performed a specified number of times or more, and when the difference between the value of the map data MAP updated by the learning circuit 54 and the value of the map data MAP at the start of the operation exceeds a preset allowable value. Specifically, the learning circuit 54 may execute a process similar to step S209 in the process of the second embodiment shown in FIG. 10 after the loop process ends, and then execute step S310. That is, the process shown in FIG. 16 can be modified so that a process similar to step S209 is added between steps S309 and S310. In this way, the number of times data is written to the storage unit 55 can be reduced, while maintaining good stability in the control of the rate of change dV / dt immediately after the start of the second or subsequent operation.

[0126] Furthermore, the learning circuit 54 does not need to store the updated map data MAP in the memory unit 55, that is, it does not need to update the map data MAP stored in the memory unit 55. In this way, although the stability of control of the rate of change dV / dt immediately after the start of the second or subsequent operations decreases, it is possible to further reduce the number of times data is written to the memory unit 55, which is preferable when the number of times data is written to the memory unit 55 is limited. In this case, the gate drive device 51 does not need to be equipped with the memory unit 55 in the first place, and a previously fixed value may be used as the initial value of the map data MAP.

[0127] <Modifications regarding learning process> When executing the learning process, the learning circuit 54 can change the calculation method based on the past gate current Ig calculated by the calculation circuit 52 and the past detection values ​​of the change rate dV / dt and temperature Tj detected by the detection circuit 53, in addition to the present gate current Ig calculated by the calculation circuit 52 and the present detection values ​​of the change rate dV / dt and temperature Tj detected by the detection circuit 53. Specifically, when executing the learning process, the learning circuit 54 can update the map data by update map data obtained by smoothing the update map data MAP' obtained by performing a filter process using the present update map data MAP' output from the update processing circuit 58 and the map data MAP corresponding to the past update map data MAP' stored in the register 45 of the calculation circuit 52.

[0128] As the filtering process, for example, various processes described in the first embodiment can be adopted. In this way, even if erroneous learning occurs in which the value of the update map data MAP' becomes an erroneous value due to the influence of noise, temporary abnormality, etc., it is possible to suppress a situation in which the rate of change dV / dt becomes a value that deviates from the target value due to the influence.

[0129] <Modifications regarding update processing> The update process in which the update processing circuit 58 of the learning circuit 54 creates the updated map data MAP', that is, the process of updating the map data, can be modified in the same manner as the first and second modified examples of the update process described in the second embodiment.

[0130] (Fourth embodiment) The fourth embodiment will be described below with reference to FIGS. <Major functions of gate drive unit> The main functions of the gate drive device 61 of this embodiment will be described with reference to Fig. 17. As shown in Fig. 17, the gate drive device 61 of this embodiment differs from the gate drive device 1 of the first embodiment in that it includes a calculation circuit 62 instead of the calculation circuit 11, a detection circuit 63 instead of the detection circuit 13, a learning circuit 64 instead of the learning circuit 14, and a storage unit 65 instead of the storage unit 15.

[0131] The transient voltage to be controlled by the gate driver 61 of this embodiment is the surge voltage Vsrg of the semiconductor switching element 5 of the own arm. Each component of the gate driver 61 operates in a manner similar to each component of the gate driver 1, except that the control target is changed from the rate of change dV / dt to the surge voltage Vsrg. The detection circuit 63 detects the power supply voltage Va and the current Id in addition to the surge voltage Vsrg of the semiconductor switching element 5 of the own arm. The detection circuit 63 can also detect an off voltage Vds_off, which is a voltage approximately equal to the power supply voltage Va, instead of the power supply voltage Va. In this case, the power supply voltage Va in the following description may be replaced with the off voltage Vds_off.

[0132] The calculation circuit 62 is configured to calculate the gate current Ig using the following equation (4) as a model equation, where K is a model parameter, Vsrg* is a target value for the surge voltage Vsrg, Va is a power supply voltage that is the voltage applied between the main terminals of the semiconductor switching element 5, and Ig is a gate current that is an operating variable. Ig = (Vsrg * - Va) ÷ K … (4)

[0133] In addition, the learning circuit 64 calculates the learning value Ka using the following equation (5) as an inverse model equation, where the learning value is Ka, the gate current calculated by the calculation circuit 62 is Iga, and the detection value of the surge voltage Vsrg detected by the detection circuit 63 is Vsrg as it is. Ka = (Vsrg - Va) ÷ Iga … (5)

[0134] <Specific configuration of the gate driving device> As a specific configuration of a gate driving device 61 having the above-mentioned functions, for example, a configuration example as shown in Fig. 18 can be adopted. The gate driving device 61 shown in Fig. 18 differs from the gate driving device 1 of the first embodiment shown in Fig. 4 in that it has a calculation circuit 62 instead of the calculation circuit 11, a detection circuit 63 instead of the detection circuit 13, a learning circuit 64 instead of the learning circuit 14, and a storage unit 65 instead of the storage unit 15.

[0135] The storage unit 65 stores in advance the target value Vsrg* of the surge voltage Vsrg, a plurality of K values ​​determined for each current Id, and the like. In this specification, the target value Vsrg* of the surge voltage Vsrg may be referred to as the target surge voltage Vsrg*. The target surge voltage Vsrg* is transmitted as a command from a higher-level control device, and can be acquired in advance. For example, the target surge voltage Vsrg* can be acquired in advance by performing various simulations. When the calculation circuit 62 requests the storage unit 65 to read out the target surge voltage Vsrg*, the storage unit 65 outputs a signal representing the target surge voltage Vsrg*. When the calculation circuit 62 requests the storage unit 65 to read out the K value, the storage unit 65 outputs a signal representing the K value for each current Id.

[0136] The detection circuit 63 detects the surge voltage Vsrg and the off-voltage Vds_off by monitoring the waveform of the voltage Vds. As described above, the off-voltage Vds_off is approximately equal to the power supply voltage Va, so the detection circuit 63 detects the off-voltage Vds_off instead of the power supply voltage Va. The detection circuit 63 detects the current Id as follows. In this case, a shunt resistor 66 is connected between the source of the semiconductor switching element 5B and the DC power supply line 3.

[0137] The detection circuit 63 receives the terminal voltage of the shunt resistor 66, specifically, the voltage of the terminal of the shunt resistor 66 on the semiconductor switching element 5 side. The detection circuit 63 is configured to detect the current Id based on the voltage value of the terminal voltage of the shunt resistor 66. The detection circuit 63 outputs a signal representing the detection value of the rate of change dV / dt, a signal representing the detection value of the off-voltage Vds_off, and a signal representing the detection value of the current Id.

[0138] At the start of operation, the calculation circuit 62 requests the storage unit 65 to read out the target surge voltage Vsrg* and the K value. As a result, the signal Vsrg* and the signal K output from the storage unit 65 are input to the calculation circuit 62. The calculation circuit 62 includes a register 67 that stores the target surge voltage Vsrg* represented by the signal Vsrg*, a register 68 that stores the K value for each current Id represented by the signal K, a selector 69, and arithmetic circuits 70 and 71. The calculation circuit 62 stores the target surge voltage Vsrg* and the K value for each current Id read out from the storage unit 65 in the registers 67 and 68.

[0139] The selector 69 receives the signal Id output from the detection circuit 63. The selector 69 reads out a plurality of K values ​​stored in the register 68, and selects from the plurality of K values ​​a K value corresponding to the detection value of the current Id represented by the signal Id. The selector 69 outputs a signal representing the K value selected in this manner to the arithmetic circuit 71. The arithmetic circuit 70 receives the signal Vds_off output from the detection circuit 63. The arithmetic circuit 70 reads out the target surge voltage Vsrg* stored in the register 67, and subtracts the detection value of the off-voltage Vds_off represented by the signal Vds_off from the read target surge voltage Vsrg*.

[0140] The value obtained as a result of such calculation by the calculation circuit 70 corresponds to the target value ΔVds* of the voltage ΔVds described above. In this specification, the target value ΔVds* of the voltage ΔVds may be referred to as a target voltage ΔVds*. The calculation circuit 70 outputs a signal representing the voltage ΔVds* to the calculation circuit 71. The calculation circuit 71 divides the value of the target voltage ΔVds* represented by the signal ΔVds* by the K value represented by the signal K.

[0141] The value obtained as a result of such calculation by the calculation circuit 71 corresponds to the gate current Ig described above. The calculation circuit 71 outputs a signal representing the gate current Ig. In this case, the K value stored in the register 68 is updated by the operation of the learning circuit 64 described later. Before the power supply to the gate drive device 61 is cut off, the register 68 outputs a signal representing the stored K value to the storage unit 65. As a result, the K value stored in the storage unit 65 is updated by being overwritten by the K value stored in the register 68.

[0142] The learning circuit 64 receives the signals Vsrg and Vds_off output from the detection circuit 63, and the signal Ig output from the calculation circuit 62. The learning circuit 64 includes arithmetic circuits 72 and 73. The arithmetic circuit 72 subtracts the detection value of the off-voltage Vds_off represented by the signal Vds_off from the detection value of the surge voltage Vsrg represented by the signal Vsrg. The value obtained as the calculation result by the arithmetic circuit 72 corresponds to the detection value of the voltage ΔVds described above. The arithmetic circuit 72 outputs a signal representing the detection value of the voltage ΔVds to the arithmetic circuit 73.

[0143] The arithmetic circuit 73 divides the detection value of the voltage ΔVds represented by the signal ΔVds by the value of the gate current Ig represented by the signal Ig. The value obtained as a result of such calculation by the arithmetic circuit 73 corresponds to the learning value Ka described above. The arithmetic circuit 73 outputs a signal representing the learning value Ka to the register 68 of the calculation circuit 62. As a result, of the multiple K values ​​stored in the register 68, the K value corresponding to the detection value of the current Id represented by the signal Id is updated by being overwritten by the learning value Ka.

[0144] <Flow of operation by the gate driver> Next, the flow of operations performed by the gate driving device 61 having the above configuration will be described with reference to Fig. 19. In the gate driving device 61, the process shown in Fig. 19 is executed from when the power is turned on to when the power is turned off. In step S401, which is executed first after the operation starts, the target surge voltage Vsrg* and the K value for each current Id are read out from the storage unit 65, and these are stored in the registers 67 and 68 in the calculation circuit 62. That is, in step S401, the target surge voltage Vsrg* and the K value for each current Id stored in the storage unit 65 are downloaded to the registers 67 and 68 in the calculation circuit 62.

[0145] After step S401 is executed, a loop start process of step S402 is executed. The loop start process of step S402 is a process in which the processes of steps S403 to S410 are repeatedly executed until a switching end command END is given, that is, with the giving of the switching end command END as the end condition, with step S411 as the loop end process. In step S403, the semiconductor switching element 5 is in the off state, and in this state, the detection circuit 63 detects the off voltage Vds_off.

[0146] In step S404, a turn-on command ON is given, and the drive circuit 12 outputs a gate current Ig_on, thereby turning on the semiconductor switching element 5. The current value of the gate current Ig_on at this time is a predetermined current value. In step S405, the semiconductor switching element 5 is in an on state, and in this state, the detection circuit 63 detects the current Id. Also in step S405, the selector 69 of the calculation circuit 62 selects the K value corresponding to the detection value of the current Id.

[0147] In step S406, the calculation circuits 70 and 71 of the calculation circuit 62 perform respective calculations, and the calculation circuit 62 calculates the gate current Ig based on the above-mentioned model formula (4). In step S407, a turn-off command OFF is given, and the drive circuit 12 outputs the gate current Ig_off, thereby turning off the semiconductor switching element 5. The current value of the gate current Ig_off at this time corresponds to the value of the gate current Ig calculated in step S406.

[0148] In step S408, the detection circuit 63 detects the surge voltage Vsrg generated at the time of turn-off. In step S408, the detection circuit 63 may detect the off-voltage Vds_off in addition to the surge voltage Vsrg. In step S409, the arithmetic circuits 72 and 73 of the learning circuit 64 perform each calculation, and the learning circuit 64 calculates the learning value Ka based on the inverse model equation (5) described above. In step S410, the K value corresponding to the detection value of the current Id among the multiple K values ​​stored in the register 68 is updated by being overwritten with the learning value Ka.

[0149] These steps S409 and S410 correspond to the learning process executed by the learning circuit 14. Note that step S410 is executed after step S409, but instead of or in addition to this, it may be executed after step S405. However, when the loop process is executed for the first time, step S410 cannot be executed after step S405.

[0150] In the gate driving device 61, the processing of steps S402 to S411 as described above is repeatedly executed until the switching end command END is given. That is, the loop processing of steps S402 to S411 is repeatedly executed every time the semiconductor switching element 5 is switched. Then, when the switching end command END is given, the loop processing of steps S402 to S411 ends and the process proceeds to step S412. In step S412, the K value stored in the storage unit 65 is updated by being overwritten with the K value stored in the register 68 of the calculation circuit 62. After step S412 is executed, the operation ends.

[0151] According to the gate driving device 61 of the present embodiment described above, a learning process is executed by the learning circuit 64, and the calculation method used by the calculation circuit 62 to calculate the gate current Ig, which is the manipulation variable for manipulating the gate driving speed when the semiconductor switching element 5 is turned off, is optimized so as to correspond to the surge voltage Vsrg actually generated in the semiconductor switching element 5 that is the target of driving by the gate driving device 61, when it is turned off.

[0152] As described above, according to this embodiment, the calculation method is optimized in accordance with the individual variations of the products, so that even if there are individual variations in the gate drive device 61 and the semiconductor switching element 5, it is possible to control the gate drive speed of the semiconductor switching element 5 to a desired speed, and ultimately to control the surge voltage Vsrg at turn-off to a desired target value.

[0153] Furthermore, in the gate driver 61, the learning process by the learning circuit 64 can be performed while the gate driver 61 is actually operating, that is, during actual operation. As described above, according to this embodiment, since it is possible to execute the learning process even during actual operation, that is, to execute optimization of the calculation method, it is possible to control the surge voltage Vsrg to a desired target value even when characteristics change due to aging or when load changes such as temperature or power supply voltage Va occur. Therefore, according to this embodiment, it is possible to obtain an excellent effect of accurately controlling the surge voltage Vsrg to a desired target value when the semiconductor switching element 5 is switched, particularly when it is turned off.

[0154] As described above, according to this embodiment, the surge voltage Vsrg generated when the semiconductor switching element 5 is switched is targeted for control, and the surge voltage Vsrg can be precisely controlled to a desired target value. This makes it possible to prevent failures caused by the surge voltage Vsrg applied to the main terminal of the semiconductor switching element 5 exceeding the element withstand voltage, and to reduce switching losses at the same time.

[0155] In this case, the calculation circuit 62 calculates the gate current Ig by a model equation using the model parameter K such as the above-mentioned equation (4). In addition, in this case, the learning circuit 64 calculates a learning value Ka corresponding to the model parameter K by an inverse model equation such as the above-mentioned equation (5), and updates the model parameter K based on the calculated learning value Ka to change the calculation method of the gate current Ig. In this way, it is possible to realize optimization of the calculation method of the gate current Ig without requiring complex processing in the calculation circuit 62 and the learning circuit 64, so that the calculation circuit 62 and the learning circuit 64 can be configured relatively simply.

[0156] The gate drive device 61 includes a storage unit 65 that can store the model parameter K updated by the learning circuit 64. Then, the learning circuit 64 stores the model parameter K updated before the power supply of the gate drive device 61 is cut off in the storage unit 65, and the calculation circuit 62 calculates the gate current Ig using the model parameter K stored in the storage unit 65 at the start of the next operation executed after the power supply of the gate drive device 61 is cut off. In this way, for the second and subsequent operations, the gate current Ig is calculated using the model parameter K learned in the previous operation from the start of the operation, so that it is possible to accurately control the surge voltage Vsrg to the target value stably immediately after the start of the operation.

[0157] <Modification Example Regarding Update of K Value> In the present embodiment, the learning circuit 64 writes and stores the updated model parameter K in the storage unit 65 before the power supply of the gate drive device 61 is cut off, that is, updates the K value stored in the storage unit 65. However, this can be modified as follows.

[0158] That is, the learning circuit 64 may store the updated model parameter K in the storage unit 65 after executing the learning process a specified number of times or more. Specifically, the learning circuit 64 may execute step S412 each time steps S409 and S410 are executed a specified number of times. That is, regarding the process shown in FIG. 19, step S412 can be changed to be executed during the loop process.

[0159] Further, the learning circuit 64 stores the updated model parameter K in the storage unit 65 when it is before the power supply of the gate drive device 61 is cut off or after the learning process is executed a specified number of times or more and the difference between the value of the model parameter K updated by the learning circuit 64 and the value of the model parameter K at the start of the operation exceeds a preset allowable value. In this way, it is possible to maintain good stability in controlling the surge voltage Vsrg immediately after the start of the second and subsequent operations while suppressing the number of write operations to the storage unit 65.

[0160] Furthermore, the learning circuit 64 may store the updated model parameter K in the storage unit 65, that is, it is not necessary to update the K value stored in the storage unit 65. In this way, although the stability of the control of the surge voltage Vsrg immediately after the start of the second and subsequent operations decreases, the number of write operations to the storage unit 65 can be suppressed lower, so it is suitable when there is a limit on the number of write operations to the storage unit 65. In this case, originally, the gate driver device 61 does not necessarily need to include the storage unit 65, and a fixed value may be used as the initial value for the K value in advance.

[0161] <Modification example regarding K value> In this embodiment, considering the characteristic that the surge voltage Vsrg depends on the current Id, the calculation of the gate current Ig, the learning process, etc. are executed using the K value for each current Id. However, it is also possible to execute the calculation of the gate current Ig, the learning process, etc. using one K value. In this way, since the current Id dependence of the surge voltage Vsrg is ignored, although the stability of the control of the surge voltage Vsrg slightly decreases, for each circuit constituting the gate driver device 61, the processing load can be reduced, the configuration can be simplified, etc.

[0162] <Modification example regarding learning process> When the learning circuit 64 executes the learning process, in addition to the detection values of the current gate current Ig calculated by the calculation circuit 62 and the current surge voltage Vsrg detected by the detection circuit 63, the calculation method can be changed based on the detection values of the past gate current Ig calculated by the calculation circuit 62 and the past surge voltage Vsrg detected by the detection circuit 63.

[0163] Specifically, when the learning circuit 64 executes the learning process, the learning circuit 64 can update the model parameter K based on a learning value obtained by smoothing the learning value Ka obtained by performing a filter process using the current learning value Ka output from the arithmetic circuit 73 and the K value read from the register 68 of the calculation circuit 62, i.e., the past learning value Ka. Note that, as the filter process, for example, various processes described in the first embodiment can be adopted. In this way, even if erroneous learning occurs in which the learning value Ka becomes an erroneous value due to the influence of noise, temporary abnormality, etc., it is possible to suppress a situation in which the surge voltage Vsrg becomes a value deviating from the target value due to the influence.

[0164] Fifth embodiment The fifth embodiment will be described below with reference to FIGS. <Major functions of gate drive unit> The main functions of the gate driving device 81 of this embodiment will be described with reference to Fig. 20. As shown in Fig. 20, the gate driving device 81 of this embodiment differs from the gate driving device 61 of the fourth embodiment in that it includes a calculation circuit 82 instead of the calculation circuit 62, a detection circuit 83 instead of the detection circuit 63, a learning circuit 84 instead of the learning circuit 64, and a storage unit 85 instead of the storage unit 65.

[0165] The calculation circuit 82 is configured to acquire map data in advance as relationship information, and calculate the gate current Ig, which is an operation amount, based on the target value of the surge voltage Vsrg and the map data. In this case, the map data is a one-dimensional map that shows the relationship between the gate current Ig, which is an operation amount, and the surge voltage Vsrg, which is a transient voltage, and specifically, is data such as that shown in FIG. 22. In the map data shown in FIG. 22, the unit of the surge voltage Vsrg is [V]. In the following description, unless otherwise specified, the unit of the surge voltage Vsrg is the same as that shown in FIG. 22, and these units will be omitted and only the value will be described.

[0166] The detection circuit 83 is adapted to detect the surge voltage Vsrg. The learning circuit 84 is adapted to change the calculation method of the manipulated variable by updating the map data based on the manipulated variable calculated by the calculation circuit 82 and the detection value of the surge voltage Vsrg detected by the detection circuit 83 as a learning process. The storage unit 85 can store the map data updated by the learning circuit 84. The learning circuit 84 stores the updated map data in the storage unit 85 before the power supply to the gate drive device 81 is cut off. The calculation circuit 82 is adapted to calculate the manipulated variable using the map data stored in the storage unit 85 at the start of the next operation to be executed after the power supply to the gate drive device 81 is cut off.

[0167] <Specific configuration of the gate driving device> As a specific configuration of a gate driving device 81 having the functions described above, for example, a configuration example shown in Fig. 21 can be adopted. The gate driving device 81 shown in Fig. 21 differs from the gate driving device 61 shown in Fig. 18 in that it has a calculation circuit 82 instead of the calculation circuit 62, a detection circuit 83 instead of the detection circuit 63, a learning circuit 84 instead of the learning circuit 64, and a storage unit 85 instead of the storage unit 65.

[0168] The storage unit 85 differs from the storage unit 65 in that the map data MAP, which is the one-dimensional map described above, is stored in advance instead of the value of the model parameter K. The map data MAP can be acquired in advance, for example, by performing various simulations. When a request to read out the map data MAP is received from the calculation circuit 82, the storage unit 85 outputs a signal representing the map data MAP. The detection circuit 83 detects the surge voltage Vsrg in the same manner as the detection circuit 63.

[0169] The calculation circuit 82 differs from the calculation circuit 62 in that it includes a register 86 that stores map data MAP instead of the register 68, and in that it includes a search processing circuit 87 instead of the selector 69 and the arithmetic circuits 70 and 71. When starting operation, the calculation circuit 82 requests the memory unit 85 to read out the target surge voltage Vsrg* and the map data MAP. As a result, the signal Vsrg* and the signal MAP output from the memory unit 85 are input to the calculation circuit 82. The calculation circuit 82 stores the target surge voltage Vsrg* and the map data MAP read out from the memory unit 85 in the registers 67 and 86.

[0170] The search processing circuit 87 reads out the target surge voltage Vsrg* stored in the register 67 and the map data MAP stored in the register 86. Then, the search processing circuit 87 executes a search process to search for a gate current Ig on the map data MAP corresponding to the value of the target surge voltage Vsrg* read out from the register 67, and to output a signal Ig representing the searched value of the gate current Ig. For example, when the value of the target surge voltage Vsrg* read out from the register 67 is "360", the search processing circuit 87 searches for a gate current Ig=0.15 on the map data MAP corresponding to the surge voltage Vsrg=360, and outputs a signal Ig representing the searched value of the gate current Ig, "0.15".

[0171] In this case, the map data MAP stored in the register 86 is updated by the operation of the learning circuit 84, which will be described later. Before the power supply to the gate drive device 61 is cut off, the register 86 outputs a signal representing the stored map data MAP to the storage unit 85. As a result, the map data MAP stored in the storage unit 85 is updated by being overwritten by the map data MAP stored in the register 86.

[0172] The learning circuit 84 differs from the learning circuit 64 in that it includes an update processing circuit 88 instead of the arithmetic circuits 72, 73. The learning circuit 84 receives the signal Vsrg output from the detection circuit 83 and the signals MAP and Ig output from the calculation circuit 82. The update processing circuit 88 searches for the gate current Ig in the map data MAP corresponding to the detection value of the surge voltage Vsrg detected by the detection circuit 83, creates updated map data MAP' by changing the value of the gate current Ig in the map data MAP found to the value of the gate current Ig calculated by the calculation circuit 82, and executes an update process to output a signal representing the updated map data MAP'.

[0173] For example, if the detection value of the surge voltage Vsrg detected by the detection circuit 83 is "370" and the value of the gate current Ig calculated by the calculation circuit 82 is "0.15", the update processing circuit 88 searches for the gate current Ig=0.20 in the map data MAP corresponding to the surge voltage Vsrg=370. Then, the update processing circuit 88 creates update data MAP' in which the value of the gate current Ig corresponding to the surge voltage Vsrg=370 on the map data MAP found is changed to "0.15", which is the value of the gate current Ig calculated by the calculation circuit 82.

[0174] Specifically, the updated map data MAP' is data such as that shown in Fig. 23, for example. As shown in Fig. 23, in the updated map data MAP', the value of the gate current Ig corresponding to the surge voltage Vsrg=370 is changed from "0.20" to "0.15". The update processing circuit 88 outputs a signal representing the updated map data MAP' created by such an update processing to the register 86 of the calculation circuit 82. As a result, the map data MAP stored in the register 86 is updated by being overwritten with the updated map data MAP'.

[0175] <Flow of operation by the gate driver> Next, the flow of operations performed by the gate drive device 81 having the above configuration will be described with reference to Fig. 24. In the gate drive device 81, the process shown in Fig. 24 is executed from when the power is turned on to when the power is turned off. In step S501, which is executed first after the operation starts, the target surge voltage Vsrg* and map data MAP are read out from the storage unit 85 and stored in the registers 67, 86 in the calculation circuit 82. That is, in step S501, the target surge voltage Vsrg* and map data MAP stored in the storage unit 85 are downloaded to the registers 67, 86 in the calculation circuit 82.

[0176] After step S501 is executed, a loop start process of step S502 is executed. The loop start process of step S502 is a process of repeatedly executing the processes of steps S503 to S507 until a switching end command END is given, that is, with the giving of the switching end command END as the end condition, with step S508 as the loop end process. In step S503, a turn-on command ON is given, and the drive circuit 12 outputs a gate current Ig_on, thereby turning on the semiconductor switching element 5. The current value of the gate current Ig_on at this time is a predetermined current value.

[0177] In step S504, the search processing circuit 87 of the calculation circuit 82 executes the above-mentioned search processing. That is, in step S504, the calculation circuit 82 searches for the gate current Ig from the map data MAP stored in the register 86 by using the target surge voltage Vsrg* stored in the register 67. Note that step S504 can also be executed before step S503. That is, the execution order of steps S503 and S504 can also be switched.

[0178] In step S505, a turn-off command OFF is given, and the drive circuit 12 outputs the gate current Ig_off, thereby turning off the semiconductor switching element 5. The current value of the gate current Ig_off at this time corresponds to the value of the gate current Ig found in step S504. In step S506, the detection circuit 83 detects the surge voltage Vsrg generated at the time of turn-off.

[0179] In step S507, the update processing circuit 88 of the learning circuit 84 executes the above-mentioned update processing, thereby updating the map data MAP stored in the register 86 of the calculation circuit 82 by overwriting it with the updated map data MAP'. Step S507 corresponds to the learning processing executed by the learning circuit 84. In the gate driver 81, the processing of steps S502 to S508 as described above is repeatedly executed until a switching end command END is given.

[0180] That is, the loop process of steps S502 to S508 is repeatedly executed every time the semiconductor switching element 5 is switched. Then, when a switching end command END is given, the loop process of steps S502 to S508 ends and the process proceeds to step S509. In step S509, the map data MAP stored in the storage unit 85 is updated by being overwritten with the map data MAP stored in the register 86 of the calculation circuit 82. After step S509 is executed, the operation ends.

[0181] The gate drive device 81 of this embodiment described above also has the same effect as the fourth embodiment, that is, the excellent effect of being able to accurately control the surge voltage Vsrg to a desired target value when the semiconductor switching element 5 is switched, particularly when it is turned off. In this case, the calculation circuit 82 calculates the value of the gate current Ig using map data MAP, which is a one-dimensional map showing the relationship between the gate current Ig and the surge voltage Vsrg.

[0182] In this case, the learning circuit 84 changes the calculation method of the gate current Ig by updating the map data MAP based on the value of the gate current Ig calculated by the calculation circuit 82 and the detection value of the surge voltage Vsrg detected by the detection circuit 83. In this way, the calculation error of the gate current Ig by the calculation circuit 82 is reduced, so that the surge voltage Vsrg can be controlled to the target value with even greater accuracy.

[0183] The gate drive device 81 includes a storage unit 85 capable of storing map data MAP updated by the learning circuit 84. The learning circuit 84 stores the map data MAP updated before power is cut off to the gate drive device 81 in the storage unit 85, and the calculation circuit 82 calculates the gate current Ig using the map data MAP stored in the storage unit 85 at the start of the next operation executed after power is cut off to the gate drive device 81. In this way, for the second or subsequent operations, the gate current Ig is calculated using the map data MAP learned in the previous operation from the start of the operation, so that the surge voltage Vsrg can be stably and accurately controlled to the target value immediately after the start of the operation.

[0184] <Modifications regarding map data updates> In this embodiment, the learning circuit 84 writes and stores the updated map data MAP in the memory unit 85 before power is cut off to the gate drive device 81, that is, updates the map data MAP stored in the memory unit 85. However, this can be modified as follows.

[0185] That is, the learning circuit 84 may execute the learning process a specified number of times, and then store the updated map data MAP in the storage unit 85. Specifically, the learning circuit 84 may execute step S509 every time step S507 is executed a specified number of times. That is, the process shown in FIG. 24 can be modified so that step S509 is executed during loop processing.

[0186] Furthermore, the learning circuit 84 may store the updated map data MAP in the memory unit 85 before the gate driver 81 is powered off or after the learning process has been executed a specified number of times or more and when the difference between the value of the map data MAP updated by the learning circuit 84 and the value of the map data MAP at the start of operation exceeds a preset allowable value. In this way, the number of times writing to the memory unit 85 can be reduced, while maintaining good stability in the control of the surge voltage Vsrg immediately after the start of the second or subsequent operation.

[0187] The value of the map data MAP is the value of the gate current Ig, which is an manipulated variable, or the value of the surge voltage Vsrg, which is a transient voltage, and the determination of whether or not the above-mentioned difference exceeds the allowable value can be made for each value of the gate current Ig or each value of the surge voltage Vsrg in the map data MAP.

[0188] Furthermore, the learning circuit 84 does not need to store the updated map data MAP in the memory unit 85, i.e., it is not necessary to update the map data MAP stored in the memory unit 85. In this way, although the stability of control of the surge voltage Vsrg immediately after the start of the second or subsequent operations decreases, it is possible to further reduce the number of times data is written to the memory unit 85, which is preferable when the number of times data is written to the memory unit 85 is limited. In this case, the gate drive device 81 does not need to be equipped with the memory unit 85 in the first place, and a previously fixed value may be used as the initial value of the map data MAP.

[0189] <Modifications regarding learning process> When executing the learning process, the learning circuit 84 can change the calculation method based on the past gate current Ig calculated by the calculation circuit 82 and the past detection value of the surge voltage Vsrg detected by the detection circuit 83, in addition to the present gate current Ig calculated by the calculation circuit 82 and the present detection value of the surge voltage Vsrg detected by the detection circuit 83. Specifically, when executing the learning process, the learning circuit 84 can update the map data by update map data obtained by smoothing update map data MAP' obtained by performing a filter process using present update map data MAP' output from the update processing circuit 88 and map data MAP corresponding to the past update map data MAP' stored in the register 86 of the calculation circuit 82.

[0190] As the filtering process, for example, various processes described in the first embodiment can be adopted. In this way, even if erroneous learning occurs in which the value of the updated map data MAP' becomes an erroneous value due to the influence of noise, temporary abnormality, etc., it is possible to suppress a situation in which the surge voltage Vsrg becomes a value that deviates from the target value due to the influence.

[0191] <Modifications regarding update processing> The update process in which the update processing circuit 88 of the learning circuit 84 creates the updated map data MAP', i.e., the process of updating the map data, can be modified in the same manner as the first and second modified examples of the update process described in the second embodiment.

[0192] Sixth embodiment The sixth embodiment will be described below with reference to FIGS. <Major functions of gate drive unit> The main functions of the gate drive device 91 of this embodiment will be described with reference to Fig. 25. As shown in Fig. 25, the gate drive device 91 of this embodiment differs from the gate drive device 81 of the fifth embodiment in that it includes a calculation circuit 92 instead of the calculation circuit 82, a detection circuit 93 instead of the detection circuit 53, a learning circuit 94 instead of the learning circuit 84, and a storage unit 95 instead of the storage unit 85.

[0193] The detection circuit 93 detects the power supply voltage Va and the current Id in addition to the surge voltage Vsrg. Note that the detection circuit 93 can also detect an off-voltage Vds_off, which is a voltage substantially equal to the power supply voltage Va, instead of the power supply voltage Va. In this case, the power supply voltage Va in the following description can be replaced with the off-voltage Vds_off.

[0194] The calculation circuit 92, like the calculation circuit 82, acquires map data in advance as relationship information. However, in this case, the map data is a multidimensional map that holds the gate current Ig, which is an operation amount, by combining a voltage ΔVds and a current Id that are correlated with the surge voltage Vsrg, which is a transient voltage, and specifically, is data such as that shown in FIG. 27. In the map data shown in FIG. 27, the unit of the voltage ΔVds is "V". In the following description, unless otherwise specified, the unit of the voltage ΔVds is the same as that shown in FIG. 27, and the unit will be omitted and only the value will be described.

[0195] The calculation circuit 92 is adapted to calculate the gate current Ig, which is an operation amount, based on the target value of the voltage ΔVds corresponding to the target value of the transient voltage, the detection value of the current Id by the detection circuit 83, and the map data. The learning circuit 94 is adapted to change the calculation method of the operation amount by updating the map data based on the operation amount calculated by the calculation circuit 92 and each detection value by the detection circuit 93 as a learning process. The storage unit 95 can store the map data updated by the learning circuit 94. The learning circuit 94 stores the updated map data in the storage unit 95 before the power supply to the gate drive device 91 is cut off. The calculation circuit 92 is adapted to calculate the operation amount using the map data stored in the storage unit 95 at the start of the next operation to be executed after the power supply to the gate drive device 91 is cut off.

[0196] <Specific configuration of the gate driving device> As a specific configuration of a gate driving device 91 having the above-mentioned functions, for example, a configuration example shown in Fig. 26 can be adopted. The gate driving device 91 shown in Fig. 26 differs from the gate driving device 81 of the fifth embodiment shown in Fig. 21 in that it has a calculation circuit 92 instead of the calculation circuit 82, a detection circuit 93 instead of the detection circuit 53, a learning circuit 94 instead of the learning circuit 84, and a storage unit 95 instead of the storage unit 85.

[0197] 18, the detection circuit 93 detects the surge voltage Vsrg and the off-voltage Vds_off. The detection circuit 93 also detects the current Id based on a current detection signal output from a current sensor 96 provided in a path through which the current Id of the semiconductor switching element 5B flows. The detection circuit 93 outputs a signal representing the detection value of the surge voltage Vsrg, a signal representing the detection value of the off-voltage Vds_off, and a signal representing the detection value of the current Id.

[0198] The memory unit 95 differs from the memory unit 85 in that the stored map data MAP is the above-mentioned two-dimensional map. The calculation circuit 92 differs from the calculation circuit 82 in that an arithmetic circuit 97 is added and that a search processing circuit 98 is provided instead of the search processing circuit 87. The calculation circuit 92 performs substantially the same operations as the calculation circuit 82, except for the operations executed by the arithmetic circuit 97 and the search processing circuit 98.

[0199] The calculation circuit 97 receives the signal Vds_off output from the detection circuit 93. The calculation circuit 97 reads out the target surge voltage Vsrg* stored in the register 67, and subtracts the detection value of the off-voltage Vds_off represented by the signal Vds_off from the read out target surge voltage Vsrg*. The value obtained as the result of such calculation by the calculation circuit 97 corresponds to the target value ΔVds* of the voltage ΔVds described above. The calculation circuit 97 outputs a signal representing the voltage ΔVds*.

[0200] The search processing circuit 98 reads out the map data MAP stored in the register 86. The search processing circuit 98 receives the signal ΔVds* output from the calculation circuit 97 and the signal Id output from the detection circuit 93. The search processing circuit 98 executes a search process to search for a gate current Ig on the map data MAP that corresponds to the value of the target voltage ΔVds* represented by the signal ΔVds* and the detected value of the current Id represented by the signal Id, and to output a signal Ig representing the searched value of the gate current Ig. For example, when the value of the target voltage ΔVds* is "30" and the detected value of the current Id is "20", the search processing circuit 98 searches for a gate current Ig=0.08 on the map data MAP that corresponds to the voltage ΔVds=30 and the current Id=20, and outputs a signal Ig representing the searched value of the gate current Ig, "0.08".

[0201] In this case, the map data MAP stored in the register 86 is updated by the operation of a learning circuit 94, which will be described later. Before the power supply to the gate drive device 91 is cut off, the register 86 outputs a signal representing the stored map data MAP to the memory unit 95. As a result, the map data MAP stored in the memory unit 95 is updated by being overwritten with the map data MAP stored in the register 86.

[0202] The learning circuit 94 differs from the learning circuit 84 in that a calculation circuit 99 is added and that an update processing circuit 100 is provided instead of the update processing circuit 88. The learning circuit 94 receives the signals Vsrg, Vds_off, and Id output from the detection circuit 93, and the signal Ig output from the calculation circuit 92. The calculation circuit 99 subtracts the detection value of the off-voltage Vds_off represented by the signal Vds_off from the detection value of the surge voltage Vsrg represented by the signal Vsrg. The value obtained as the calculation result by the calculation circuit 99 corresponds to the detection value of the voltage ΔVds. The calculation circuit 99 outputs a signal representing the detection value of the voltage ΔVds to the update processing circuit 100.

[0203] The update processing circuit 100 searches for the gate current Ig in the map data MAP which corresponds to the detection value of the voltage ΔVds represented by the signal ΔVds and which corresponds to the detection value of the current Id detected by the detection circuit 93, creates updated map data MAP' in which the value of the gate current Ig found in the map data MAP is changed to the value of the gate current Ig calculated by the calculation circuit 92, and performs an update process to output a signal representing the updated map data MAP'.

[0204] For example, when the detected values ​​of the voltage ΔVds and the current Id are "40" and "20", respectively, and the value of the gate current Ig calculated by the calculation circuit 92 is "0.08", the update processing circuit 100 searches for a gate current Ig of 0.09 in the map data MAP corresponding to the voltage ΔVds=40 and the current Id=20. Then, the update processing circuit 100 creates update data MAP' in which the value of the gate current Ig corresponding to the voltage ΔVds=40 and the current Id=20 in the map data MAP that was searched for is changed to "0.08", which is the value of the gate current Ig calculated by the calculation circuit 92. The update processing circuit 100 outputs a signal representing the updated map data MAP' created by such an update process to the register 86 of the calculation circuit 92. As a result, the map data MAP stored in the register 86 is updated by being overwritten with the updated map data MAP'.

[0205] <Flow of operation by the gate driver> Next, the flow of operations performed by the gate drive device 91 having the above configuration will be described with reference to Fig. 28. In the gate drive device 91, the process shown in Fig. 28 is executed from when the power is turned on until when the power is turned off. In step S601, which is executed first after the operation starts, the target surge voltage Vsrg* and map data MAP are read out from the storage unit 95 and stored in the registers 67, 86 in the calculation circuit 92. That is, in step S601, the target surge voltage Vsrg* and map data MAP stored in the storage unit 95 are downloaded to the registers 67, 86 in the calculation circuit 92.

[0206] After step S601 is executed, a loop start process of step S602 is executed. The loop start process of step S602 is a process of repeatedly executing the processes of steps S603 to S609 until a switching end command END is given, that is, with the giving of the switching end command END as the end condition, with step S610 as the loop end process. In step S603, the semiconductor switching element 5 is in the off state, and in this state, the detection circuit 93 detects the off voltage Vds_off.

[0207] In step S604, a turn-on command ON is given, and the drive circuit 12 outputs a gate current Ig_on, thereby turning on the semiconductor switching element 5. The current value of the gate current Ig_on at this time is a predetermined current value. In step S605, the semiconductor switching element 5 is in an on state, and in this state, the detection circuit 93 detects the current Id.

[0208] In step S606, the search processing circuit 98 of the calculation circuit 92 executes the above-mentioned search processing. That is, in step S606, the calculation circuit 92 searches for the gate current Ig from the map data MAP stored in the register 86 using the target voltage ΔVds* and the detection value of the current Id detected in step S605. In step S607, a turn-off command OFF is given, causing the drive circuit 12 to output the gate current Ig_off, thereby turning off the semiconductor switching element 5. The current value of the gate current Ig_off at this time corresponds to the value of the gate current Ig searched for in step S606.

[0209] In step S608, the detection circuit 93 detects a surge voltage Vsrg that occurs at the time of turn-off. Also in step S608, a calculation is performed by the calculation circuit 99 of the learning circuit 94 to detect a voltage ΔVds. Note that in step S608, the detection circuit 93 may detect an off-voltage Vds_off in addition to the surge voltage Vsrg.

[0210] In step S609, the update processing circuit 100 of the learning circuit 94 executes the above-mentioned update processing, thereby updating the map data MAP stored in the register 86 of the calculation circuit 92 by overwriting it with the updated map data MAP'. Step S609 corresponds to the learning processing executed by the learning circuit 94. In the gate driver 91, the processing of steps S602 to S610 as described above is repeatedly executed until a switching end command END is given.

[0211] That is, the loop process of steps S602 to S610 is repeatedly executed every time the semiconductor switching element 5 is switched. When the switching end command END is given, the loop process of steps S602 to S610 ends and the process proceeds to step S611.

[0212] In step S611, the map data MAP stored in the storage unit 95 is updated by being overwritten with the map data MAP stored in the register 86 of the calculation circuit 92. After step S611 is executed, the operation ends.

[0213] The gate drive device 51 of this embodiment described above also provides the same effect as the fourth embodiment, that is, the excellent effect of being able to precisely control the surge voltage Vsrg at the time of switching, particularly at the time of turn-off, of the semiconductor switching element 5 to a desired target value. Furthermore, the gate drive device 91 of this embodiment provides the following effect. That is, the surge voltage Vsrg actually generated at the time of turn-off in the semiconductor switching element 5 that is the drive target of the gate drive device 91 may vary depending on the current Id of the semiconductor switching element 5, etc.

[0214] Therefore, in this case, the calculation circuit 92 calculates the value of the gate current Ig using map data MAP, which is a two-dimensional map that holds the gate current Ig by combining the voltage ΔVds correlated with the surge voltage Vsrg and the current Id. Also, in this case, the learning circuit 94 changes the calculation method of the gate current Ig by updating the map data MAP based on the value of the gate current Ig calculated by the calculation circuit 92 and the detected values ​​of the surge voltage Vsrg, the off-voltage Vds_off, and the current Id detected by the detection circuit 93. In this way, the calculation error of the gate current Ig by the calculation circuit 92 caused by the current Id dependency of the surge voltage Vsrg is reduced, so that the surge voltage Vsrg can be controlled to the target value with even greater accuracy.

[0215] The gate drive device 91 includes a storage unit 95 capable of storing map data MAP updated by a learning circuit 94. The learning circuit 94 stores the map data MAP updated before power is cut off to the gate drive device 91 in the storage unit 95, and the calculation circuit 92 calculates the gate current Ig using the map data MAP stored in the storage unit 95 at the start of the next operation executed after power is cut off to the gate drive device 91. In this way, for the second or subsequent operations, the gate current Ig is calculated using the map data MAP learned in the previous operation from the start of the operation, so that the surge voltage Vsrg can be stably and accurately controlled to the target value immediately after the start of the operation.

[0216] <Modifications regarding map data> The surge voltage Vsrg that actually occurs in the semiconductor switching element 5 that is the target of the gate driver 91 when the element is turned off may vary depending not only on the current Id of the semiconductor switching element 5, but also on the temperature of the semiconductor switching element 5, the temperature of the gate driver 51, and the power supply voltage Va.

[0217] Therefore, the map data MAP can be a multidimensional map that holds the gate current Ig, which is the manipulated variable, by combining the surge voltage Vsrg, which is a transient voltage, or a voltage ΔVds correlated therewith, with at least one physical quantity among the temperature of the semiconductor switching element 5, the temperature of the gate drive device 91, the power supply voltage Va, and the current Id. In this case, the detection circuit 93 needs to be configured to detect at least one physical quantity among the temperature of the semiconductor switching element 5, the temperature of the gate drive device 91, the power supply voltage Va, and the current Id.

[0218] In this case, the calculation circuit 92 calculates the gate current Ig from the target value Vsrg* of the surge voltage Vsrg, the physical quantity detected by the detection circuit 93, and the map data MAP. This reduces calculation errors in the gate current Ig caused by physical quantities such as the temperature of the semiconductor switching element 5, the temperature of the gate driver 91, the power supply voltage Va, and the current Id, that is, caused by various disturbance factors, and therefore makes it possible to control the surge voltage Vsrg to the target value with even greater accuracy.

[0219] <Modifications regarding map data updates> In this embodiment, the learning circuit 94 writes and stores the updated map data MAP in the memory unit 95 before power is cut off to the gate drive device 91, that is, updates the map data MAP stored in the memory unit 95. However, this can be modified as follows.

[0220] That is, the learning circuit 94 may execute the learning process a specified number of times, which is equal to or greater than one, and then store the updated map data MAP in the storage unit 95. Specifically, the learning circuit 94 may execute step S611 every time step S609 is executed a specified number of times. That is, the process shown in Fig. 28 can be modified so that step S611 is executed during loop processing.

[0221] Furthermore, the learning circuit 94 may store the updated map data MAP in the memory unit 95 before power is cut off to the gate drive device 91 or after the learning process has been executed a specified number of times (one or more) and the difference between the value of the map data MAP updated by the learning circuit 94 and the value of the map data MAP at the start of operation exceeds a preset allowable value.

[0222] Specifically, after the loop process ends, the learning circuit 94 may execute a process similar to step S209 in the process of the second embodiment shown in Fig. 10, and then execute step S611. That is, the process shown in Fig. 28 can be modified so that a process similar to step S209 is added between steps S610 and S611. In this way, it is possible to suppress the number of times data is written to the storage unit 95, while maintaining good stability in the control of the surge voltage Vsrg immediately after the start of the second or subsequent operation.

[0223] Furthermore, the learning circuit 94 does not need to save the updated map data MAP in the memory unit 95, i.e., it is not necessary to update the map data MAP stored in the memory unit 95. In this way, although the stability of control of the surge voltage Vsrg immediately after the start of the second or subsequent operations decreases, it is possible to further reduce the number of times data is written to the memory unit 95, which is preferable when the number of times data is written to the memory unit 95 is limited. In this case, the gate drive device 91 does not need to be equipped with the memory unit 95 in the first place, and a previously fixed value may be used as the initial value of the map data MAP.

[0224] <Modifications regarding learning process> When executing the learning process, the learning circuit 94 can change the calculation method based on the past gate current Ig calculated by the calculation circuit 92 and each past detection value detected by the detection circuit 93, in addition to the present gate current Ig calculated by the calculation circuit 92 and each present detection value detected by the detection circuit 93. Specifically, when executing the learning process, the learning circuit 94 can update the map data by update map data obtained by smoothing update map data MAP' obtained by performing a filter process using present update map data MAP' output from the update processing circuit 100 and map data MAP corresponding to the past update map data MAP' stored in the register 86 of the calculation circuit 92.

[0225] As the filtering process, for example, various processes described in the first embodiment can be adopted. In this way, even if erroneous learning occurs in which the value of the updated map data MAP' becomes an erroneous value due to the influence of noise, temporary abnormality, etc., it is possible to suppress a situation in which the surge voltage Vsrg becomes a value that deviates from the target value due to the influence.

[0226] <Modifications regarding update processing> The update process in which the update processing circuit 100 of the learning circuit 94 creates the updated map data MAP', that is, the process of updating the map data, can be modified in the same manner as the first and second modified examples of the update process described in the second embodiment.

[0227] Seventh embodiment The seventh embodiment will be described below with reference to FIGS. <Major functions of gate drive unit> The main functions of the gate drive device 111 of this embodiment will be described with reference to FIG. 29. As shown in FIG. 29, the gate drive device 111 of this embodiment differs from the gate drive device 41 of the second embodiment in that it includes a drive circuit 112 instead of the drive circuit 12, and a detection circuit 113 instead of the detection circuit 53. The transient voltage controlled by the gate drive device 111 of this embodiment is the rate of change dV / dt of the semiconductor switching element 5 of the opposing arm. The drive circuit 112 drives the gate of the semiconductor switching element 5 based on the operation amount calculated by the calculation circuit 11, similar to the drive circuit 12. The detection circuit 113 detects the rate of change dV / dt of the semiconductor switching element 5 of the opposing arm.

[0228] <Specific configuration of the gate driving device> As a specific configuration of the gate driving device 111 having the above-mentioned functions, for example, a configuration example shown in Fig. 30 can be adopted. The gate driving device 111 shown in Fig. 30 differs from the gate driving device 41 shown in Fig. 7 in that it has a driving circuit 112 instead of the driving circuit 12, and a detection circuit 113 instead of the detection circuit 53.

[0229] The detection circuit 113 detects the rate of change dV / dt of the voltage Vds of the semiconductor switching element 5 on the opposing arm side, and outputs a signal representing the detection value. The drive circuit 112 differs from the drive circuit 12 in the following respects. That is, in this case, the current source 26 is configured to be able to change its current value based on the signal Ig output from the calculation circuit 42. In this case, a resistor having a constant resistance value may be provided as a configuration on the turn-off side of the drive circuit 112 instead of the current source 27. That is, the drive circuit 112 does not need to be configured to drive with a constant current on the turn-off side.

[0230] <Flow of operation by the gate driver> Next, the flow of operations performed by the gate driving device 111 configured as described above will be described with reference to Fig. 31. In the gate driving device 111, the process shown in Fig. 31 is executed from when the power is turned on until when the power is turned off. In step S701, which is executed first after the operation starts, the target change rate dV / dt* and map data MAP are read out from the storage unit 44 and stored in the registers 21, 45 in the calculation circuit 42. That is, in step S701, the target change rate dV / dt* and map data MAP stored in the storage unit 44 are downloaded to the registers 21, 45 in the calculation circuit 42.

[0231] After step S701 is executed, a loop start process of step S702 is executed. The loop start process of step S702 is a process of repeatedly executing the processes of steps S703 to S707 until a switching end command END is given, that is, with the giving of the switching end command END as the end condition, with step S708 being the loop end process.

[0232] In step S703, the search processing circuit 46 of the calculation circuit 42 executes the above-mentioned search processing. That is, in step S703, the calculation circuit 42 searches for the gate current Ig using the target change rate dV / dt* stored in the register 21 from the map data MAP stored in the register 45. In step S704, a turn-on command ON is given, and the drive circuit 112 outputs the gate current Ig_on, thereby turning on the semiconductor switching element 5. The current value of the gate current Ig_off at this time corresponds to the value of the gate current Ig searched for in step S703.

[0233] In step S705, the detection circuit 113 detects the rate of change dV / dt of the semiconductor switching element 5 on the opposing arm side when turned on. In step S706, the update processing circuit 47 of the learning circuit 43 executes the above-mentioned update processing, thereby updating the map data MAP stored in the register 45 of the calculation circuit 42 by overwriting it with the updated map data MAP'. Step S706 corresponds to the learning processing executed by the learning circuit 43.

[0234] In step S707, a turn-off command OFF is given, and the drive circuit 112 outputs the gate current Ig_off, thereby turning off the semiconductor switching element 5. The current value of the gate current Ig_on at this time is a predetermined current value. In the gate drive device 111, the processes of steps S702 to S708 as described above are repeatedly executed until a switching end command END is given.

[0235] That is, the loop process of steps S702 to S708 is repeatedly executed every time the semiconductor switching element 5 is switched. Then, when a switching end command END is given, the loop process of steps S702 to S708 ends and the process proceeds to step S709. In step S709, it is determined whether or not the difference between the current value, which is the value of the map data MAP stored in the register 45, and the initial value, which is the value of the map data MAP stored in the storage unit 44, i.e., the value of the map data MAP at the start of operation, exceeds a predetermined allowable value. Note that in this case, the value of the map data MAP refers to the value of the gate current Ig, which is the manipulated variable, and such a determination is made for each value of the gate current Ig in the map data MAP.

[0236] If the difference between the current value and the initial value is equal to or less than the allowable value, step S709 becomes "NO" and the operation ends without executing step S710. On the other hand, if the difference between the current value and the initial value exceeds the allowable value, step S709 becomes "YES" and the operation proceeds to step S710. In step S710, the map data MAP stored in the memory unit 44 is updated by being overwritten with the map data MAP stored in the register 45 of the calculation circuit 42. After execution of step S710, the operation ends.

[0237] According to the gate driving device 111 of the present embodiment described above, the learning process is executed by the learning circuit 43, and thereby the calculation method used by the calculation circuit 42 to calculate the gate current Ig, which is the manipulated variable for manipulating the gate driving speed when the semiconductor switching element 5 is turned on, is optimized so as to correspond to the rate of change dV / dt actually occurring in the semiconductor switching element 5 on the opposing arm side when the semiconductor switching element 5 on the own arm side is turned on.

[0238] As described above, according to this embodiment, since the calculation method is optimized according to the individual product variations, even if there are individual variations in the gate drive device 111 and the semiconductor switching element 5, it is possible to control the gate drive speed of the semiconductor switching element 5 to a desired speed, and further to control the rate of change dV / dt of the semiconductor switching element 5 on the opposing arm side at turn-on to a desired target value. As described above, according to this embodiment, the same effects as those of the second embodiment can be obtained, except that the transient voltage to be controlled is the rate of change dV / dt of the semiconductor switching element 5 of the opposing arm.

[0239] (Other embodiments) The present invention is not limited to the embodiments described above and illustrated in the drawings, and can be modified, combined, or expanded in any manner without departing from the spirit and scope of the present invention. The numerical values ​​and the like shown in the above embodiments are merely examples and are not intended to be limiting.

[0240] The gate driver in each of the above embodiments is not limited to driving an N-channel MOSFET, but can drive various types of semiconductor switching elements such as a P-channel MOSFET or an IGBT.

[0241] The manipulated variable for manipulating the gate drive speed of the semiconductor switching element 5 is not limited to the gate current Ig, but may also be the gate voltage Vg or gate resistance Rg of the semiconductor switching element 5. The rate of change dV / dt and the gate voltage Vg have a relationship as shown in Fig. 32, for example, and the surge voltage Vsrg and the gate voltage Vg have a relationship as shown in Fig. 33, for example. Therefore, when the manipulated variable is the gate voltage Vg, it is sufficient to set an optimal model formula and inverse model formula taking into consideration the relationships as shown in Figs. 32 and 33.

[0242] 32 and 33, the gate threshold voltage of semiconductor switching element 5 is designated as Vth. In addition, in Fig. 32 and 33, the ON side shows characteristics corresponding to a positive gate voltage Vg for turning on the gate of semiconductor switching element 5, and the OFF side shows characteristics corresponding to a negative gate voltage Vg for turning off the gate of semiconductor switching element 5.

[0243] Furthermore, the rate of change dV / dt and the gate resistance Rg have a relationship as shown in Fig. 34, and the surge voltage Vsrg and the gate resistance Rg have a relationship as shown in Fig. 35. Therefore, when the manipulated variable is the gate resistance Rg, it is only necessary to set the optimal model equation and inverse model equation taking into consideration the relationships as shown in Figs.

[0244] Although the present disclosure has been described based on the embodiment, it is understood that the present disclosure is not limited to the embodiment or structure. The present disclosure also includes various modifications and modifications within the equivalent range. In addition, various combinations and forms, and other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and concept of the present disclosure. [Explanation of symbols]

[0245] 1A, 1B, 1, 41, 51, 61, 81, 91, 111A, 111B, 111...gate driving device, 4...half-bridge circuit, 5A, 5B, 5...semiconductor switching element, 11, 42, 52, 62, 82, 92...calculation circuit, 12, 112...driving circuit, 13, 53, 63, 83, 93, 113...detection circuit, 14, 43, 54, 64, 84, 94...learning circuit, 15, 44, 55, 65, 85, 95...memory unit.

Claims

1. A gate drive device that drives a gate of a semiconductor switching element (5A, 5B, 5) and controls a transient voltage, which is a rate of change or peak value of a voltage of a main terminal of the semiconductor switching element when the semiconductor switching element is switched, to a desired target value, a calculation circuit (11, 62) that calculates an amount of operation for operating a gate drive speed of the semiconductor switching element by a predetermined calculation method using a target value of the transient voltage; a drive circuit (12, 112) that drives a gate of the semiconductor switching element based on the operation amount calculated by the calculation circuit; A detection circuit (13, 53, 63, 83, 93, 113) for detecting the transient voltage; a learning circuit (14, 64) that executes a learning process that can change the calculation method based on the manipulated variable calculated by the calculation circuit and the detected value of the transient voltage detected by the detection circuit; Equipped with The calculation circuit includes: A target value of the transient voltage and relationship information representing a relationship between the manipulated variable and the transient voltage are acquired in advance; The control unit calculates the manipulated variable based on the acquired target value of the transient voltage and the relationship information, the calculation circuit (11, 62) acquires model parameters as the relationship information in advance, and calculates the manipulated variable by a model formula using the target value of the transient voltage and the model parameters; The learning circuit (14, 64) calculates a learning value, which is a value corresponding to the model parameter, based on the operation amount calculated by the calculation circuit and the detection value of the transient voltage detected by the detection circuit, and updates the model parameter based on the calculated learning value.

2. A gate drive device that drives a gate of a semiconductor switching element (5A, 5B, 5) and controls a transient voltage, which is a rate of change or peak value of a voltage of a main terminal of the semiconductor switching element when the semiconductor switching element is switched, to a desired target value, a calculation circuit (42, 52, 82, 92) that calculates an amount of operation for controlling a gate drive speed of the semiconductor switching element by a predetermined calculation method using a target value of the transient voltage; a drive circuit (12, 112) that drives a gate of the semiconductor switching element based on the operation amount calculated by the calculation circuit; A detection circuit (13, 53, 63, 83, 93, 113) for detecting the transient voltage; a learning circuit (43, 54, 84, 94) that executes a learning process that can change the calculation method based on the manipulated variable calculated by the calculation circuit and the detected value of the transient voltage detected by the detection circuit; Equipped with The calculation circuit includes: A target value of the transient voltage and relationship information representing a relationship between the manipulated variable and the transient voltage are acquired in advance; The control unit calculates the manipulated variable based on the acquired target value of the transient voltage and the relationship information, the calculation circuit (42, 52, 82, 92) acquires map data in advance, which is a map showing a relationship between the manipulated variable and the transient voltage, as the relationship information, and calculates the manipulated variable based on the target value of the transient voltage and the map data; The learning circuit (43, 54, 84, 94) updates the map data based on the manipulated variable calculated by the calculation circuit and the detected value of the transient voltage detected by the detection circuit.

3. The learning circuit includes:

3. The gate drive device according to claim 2, wherein the map data is updated so as to search for the manipulated variable on the map data corresponding to the detection value of the transient voltage detected by the detection circuit, change the manipulated variable on the searched map data by a difference between the manipulated variable on the searched map data and the manipulated variable calculated by the calculation circuit, and change the manipulated variable within a predetermined range centered on the manipulated variable on the searched map data by the difference.

4. The learning circuit includes:

3. The gate drive device according to claim 2, wherein the map data is updated in such a way that the manipulated variable on the map data corresponding to the detection value of the transient voltage detected by the detection circuit is searched for, and the manipulated variable on the searched map data is changed by a difference between the manipulated variable on the searched map data and the manipulated variable calculated by the calculation circuit, and the manipulated variable within a predetermined range centered on the manipulated variable on the searched map data is changed by a value obtained by multiplying the difference by a weighting coefficient that attenuates the value the more distant it is from the center.

5. the map data is a multidimensional map that holds the manipulated variable by combining the transient voltage with at least one physical quantity selected from the group consisting of a temperature of the semiconductor switching element, a temperature of the gate drive device, a power supply voltage that is a voltage applied between main terminals of the semiconductor switching element, and an element current that is a current flowing between main terminals of the semiconductor switching element; The detection circuit (53, 93) is further configured to detect at least one physical quantity among a temperature of the semiconductor switching element, a temperature of the gate driver, the power supply voltage, and the element current; 5. The gate drive device according to claim 2, wherein the calculation circuit (52, 92) is configured to calculate the manipulated variable based on a target value of the transient voltage, a detection value of the physical variable by the detection circuit, and the map data.

6. 6. The gate driver according to claim 1, wherein the transient voltage is a rate of change of a voltage at a main terminal when the semiconductor switching element is switched.

7. 6. The gate driver according to claim 1, wherein the transient voltage is a peak value of a voltage at a main terminal when the semiconductor switching element is switched.

8. the drive circuit is configured to drive a gate of the semiconductor switching element with a constant current, 8. The gate drive device according to claim 1, wherein the calculation circuit calculates a gate current of the semiconductor switching element as the manipulated variable.

9. the transient voltage is a rate of change of a voltage at a main terminal when the semiconductor switching element is switched, the drive circuit is configured to drive a gate of the semiconductor switching element with a constant current, The calculation circuit (11) A gate current of the semiconductor switching element is calculated as the manipulated variable, When the model parameter is K, the target value of the rate of change which is the transient voltage is dV / dt*, and the gate current which is the manipulated variable is Ig, the following equation is obtained: Ig = K x dV / dt The gate current is calculated using the model formula, The learning circuit (14) The learned value is Ka, the gate current, which is the manipulated variable calculated by the calculation circuit, is Iga, and the detected value of the rate of change, which is the transient voltage detected by the detection circuit, is dV / dt, then Ka=Iga÷dV / dt 2. The gate drive device according to claim 1, wherein the learned value Ka is calculated by:

10. the transient voltage is a peak value of a voltage at a main terminal when the semiconductor switching element is switched, the drive circuit is configured to drive a gate of the semiconductor switching element with a constant current, The calculation circuit (62) A gate current of the semiconductor switching element is calculated as the manipulated variable, The model parameter is K, the target value of the peak value which is the transient voltage is Vsrg*, the power supply voltage which is the voltage applied between the main terminals of the semiconductor switching element is Va, and the gate current which is the manipulated variable is Ig, then Ig=(Vsrg*-Va)÷K The gate current Ig is calculated using the model formula, The learning circuit (64) Let Ka be the learned value, Iga be the gate current that is the manipulated variable calculated by the calculation circuit, and Vsrg be the detected value of the peak value that is the transient voltage detected by the detection circuit. Then, Ka=(Vsrg-Va)÷Iga 2. The gate drive device according to claim 1, wherein the learned value Ka is calculated by:

11. Further, a storage unit (15, 65) capable of storing the model parameters updated by the learning circuit, the learning circuit stores the updated model parameters in the storage unit before power is cut off for the gate drive device or after the learning process is executed one or more specified times; 11. The gate drive device according to claim 1, wherein the calculation circuit is configured to calculate the manipulated variable using the model parameters stored in the memory unit at the start of a next operation performed after a power cut-off of the gate drive device.

12. Further, a storage unit (44, 55, 85, 95) capable of storing the map data updated by the learning circuit is provided, the learning circuit stores the updated map data in the storage unit before power is cut off from the gate drive device or after the learning process is executed one or more specified times; 6. The gate drive device according to claim 2, wherein the calculation circuit is configured to calculate the manipulated variable by using the map data stored in the memory unit at the start of a next operation performed after a power cut of the gate drive device.

13. Further, a storage unit (15, 65) capable of storing the model parameters updated by the learning circuit, the learning circuit stores the updated model parameters in the storage unit before power is cut off for the gate drive device or after the learning process has been performed one or more specified times and when a difference between the value of the model parameter updated by the learning circuit and the value of the model parameter at the start of operation exceeds a preset allowable value; 11. The gate drive device according to claim 1, wherein the calculation circuit is configured to calculate the manipulated variable using the model parameters stored in the memory unit at the start of a next operation performed after a power cut-off of the gate drive device.

14. Further, a storage unit (44, 55, 85, 95) capable of storing the map data updated by the learning circuit is provided, the learning circuit stores the updated map data in the storage unit when a difference between a value of the map data updated by the learning circuit and a value of the map data at the start of operation exceeds a preset allowable value before a power supply to the gate drive device is cut off or after the learning process has been performed one or more specified times, and 6. The gate drive device according to claim 2, wherein the calculation circuit is configured to calculate the manipulated variable by using the map data stored in the memory unit at the start of a next operation performed after a power cut of the gate drive device.

15. 15. The gate drive device according to claim 1, wherein, when executing the learning process, the learning circuit changes the calculation method based on the past operation amount calculated by the calculation circuit and the past detection value of the transient voltage detected by the detection circuit, in addition to the present operation amount calculated by the calculation circuit and the present detection value of the transient voltage detected by the detection circuit.

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