Analog Circuits

Abstract

An analog circuit is provided, comprising: a plurality of analog functions divided into at least two groups; and an interconnect structure configured to interconnect the plurality of analog functions to enable transmission of both voltage and current signals between analog functions in the plurality of analog functions, the interconnect structure having at least two hierarchical levels of interconnection, a local bus hierarchical level configured to interconnect the analog functions of each group, and a global bus hierarchical level configured to interconnect the analog functions of the plurality of groups, the local bus hierarchical level having voltage signal lines for transmitting voltage signals and / or current signal lines for transmitting current signals, and the global bus hierarchical level having voltage signal lines for transmitting voltage signals and / or current signal lines for transmitting current signals.

Description

[Technical field]

[0001] The subject matter disclosed herein relates to analog circuits, and more particularly to (the design and operation of) analog circuits having multiple analog functions, and in particular to the interconnection of multiple analog functions.

[0002] Essentially, the subject matter disclosed herein (hereinafter referred to as the present disclosure) relates to the interconnection of multiple analog functions of an analog circuit, in other words, the transmission (or routing) of signals between multiple analog functions of an analog circuit. The phrase "analog circuit" may refer to an analog or hybrid computer, an analog or hybrid computing circuit, an analog or hybrid filter, an analog or hybrid signal conditioner, etc.

[0003] Distributed analog computers, integrated analog computers, and digital field programmable gate arrays (FPGAs) all share similar challenges in terms of interconnecting components and transmitting (or routing) signals between them. Therefore, a brief overview of the prior art for such circuits is presented below.

[0004] In classical analog computers, the individual computing elements, such as integrators, multipliers, adders, etc., are connected via a so-called patch panel, which is a matrix of sockets to which the inputs and outputs of the individual computing elements are connected. These computing elements are interconnected via patch cables. The advantage of a patch panel is that any element can be connected to any other element, with an unlimited number of signal lines. The disadvantage of a patch panel is that the interconnections must be done manually. For each new program, i.e. for each new mathematical problem that the analog computer has to solve, the interconnections must be changed manually. Even with patch panels where the programs (which are the form of the interconnections of the elements) can be exchanged, the disadvantage of the need for manual implementation of the programs remains.

[0005] For this reason, patch panels were replaced by electronic switching matrices. However, the problem with such switching matrices is that the number of switches becomes very large. For example, if there are 100 computing elements, a switching matrix of at least 100 x 100 = 10,000 switches is required. Since computing elements usually have more than one input and output, in practice many more switches are required. In addition to the large number of switches, the parasitic capacitance of the signal lines and the switches themselves also represents a drawback of such switching matrices. The number of switches can be reduced by designing the switching matrix in multiple stages. Such switching networks are called Clos networks and have been used since early times in the field of communication engineering. Multistage Clos networks have a small overall number of switches and can be designed so that each input node can always be connected to each output node. If it is possible to reconfigure the entire network when a different connection is required, the overhead of the network (i.e. the circuit) can be reduced. This is because in an analog computer, a new connection corresponds to a new program, i.e. a new configuration. The effort can be further reduced if it is not necessary to implement a small number of desired connections. This is acceptable in telephone networks but not in analog computers. A Clos network has at least three stages, and therefore at least three switches in series, which reduces the signal bandwidth due to parasitic capacitance and, if transistors are used as switches, the combined bandwidth of the capacitance and on-resistance of the switches.

[0006] In FPGAs (Field Programmable Gate Arrays), the interconnects and signal transmission (or routing) between components called CLBs (Configurable Logic Blocks) are designed to reduce the probability of blocking, the area used for signal lines (or routing channels), the overall effort of signal transmission (or routing), and the ratio of the parasitic capacitance to the on-resistance of the transmission gates to shorten the propagation time and phase shift, respectively, and reduce dynamic power consumption. These requirements are realized by the (combined) concept of local and global routing. Specifically, there are short lines that connect only adjacent CLBs, and long lines that connect clusters of CLBs. The short and long lines divide the routing into local and global routing. By dividing the routing into local and global routing, the lengths of the lines can be adjusted, and as a result, effort-optimized routing can be realized.

[0007] FIG. 1 is a schematic diagram showing the configuration of local and global routing in a conventional FPGA. As shown in FIG. 1, a local interconnect is provided for local signal transmission (or routing) within a cluster (or group) of CLBs, and a global interconnect is provided for global signal transmission (or routing) between clusters (or groups) of CLBs. In either one of the local interconnect and global interconnect, signal transmission (or routing) between corresponding CLBs is realized by switches (at the crossing points) of signal lines. These switches are shown diagrammatically by at least some black dots on the global interconnect. (Note that this is drawn for illustrative purposes.)

[0008] A Configurable Logic Block (CLB) is a general purpose digital block that contains at least one look-up table or logic function and an edge-controlled D flip-flop. The logic function may have a multiplexer. Some CLBs contain full adders, additional flip-flops, clock gating, and local feedback from the flip-flop output to the logic input.

[0009] The universality of CLBs is different from the application challenges in analog circuits such as analog computers. Frequently used analog functions such as integrators, adders, and multipliers have different circuit configurations, so the circuit overhead is too large for universal analog blocks, and the performance is suboptimal due to the circuit overhead. An integrator can be converted to an adder by replacing the capacitor in the negative feedback (loop) with a resistor. However, the integrator still has circuitry to set the initial conditions, which becomes unused overhead in an adder. Also, multipliers are implemented very differently from adders and integrators. Therefore, the concept of local routing and global routing in FPGAs mentioned above cannot be directly transferred to analog circuits such as analog computers.

[0010] However, it does make sense to place analog functions in clusters (or groups) similar to the CLB groups in an FPGA, as shown in Figure 1. This is because in analog circuits, the core element, the integrator, is typically connected directly to the adder and multiplier, so it seems reasonable to organize the clusters (or groups) with integrators, adders, and multipliers.

[0011] Analog computers have similar challenges to FPGAs in interconnecting individual elements, but this is primarily due to finite routing resources, and not every element can be arbitrarily interconnected with any other element, so clustering (or grouping) can also be used to solve the limited routability problem in analog computers.

[0012] FIG. 2 is a schematic diagram showing the configuration of a macrocell in a conventional analog computer, and FIG. 3 is a schematic diagram showing the configuration of an array of four macrocells in the conventional analog computer.

[0013] As shown in Figure 2, any analog function can be connected to any other analog function without blockage. The inputs of the analog functions are fixedly connected to horizontal lines. The outputs of the analog functions and the connections at the crossbar are flexibly configured and connected with switches such as CMOS transfer gates. This is different from an FPGA crossbar because at the crosspoints, not only are connections made but also the interruption of signal lines can be programmed or the routing is done at right angles.

[0014] To mitigate the problem of errors due to parasitic capacitances and on-resistance of the switches, currents are used as signals. Currents have the advantage that they can be summed directly at the inputs of the op-amp circuit. The use of currents is beneficial in terms of fan-in. However, the disadvantage of currents is that if the output signal needs to be distributed to several inputs, a current mirror circuit is required. The use of currents is disadvantageous in terms of fan-out. In Figure 2, the function f1(x) represents a so-called fan-out circuit with several current outputs, which requires a current mirror circuit.

[0015] One might expect that the routing effort would be less if analog functions were mixed (since the routing distance is statistically shorter on average), but this is almost impossible because functions f1(x), f2(x), and f3(x,y) have different physical layout dimensions. In addition, each analog function requires special signals such as reference voltages and bias currents, which require additional interconnect lines and make it difficult to place the functions arbitrarily.

[0016] The macrocells are interconnected at a high hierarchical level, as shown in Figure 3. Within a macrocell, all functions can be freely connected, but non-blocking connections are not guaranteed at higher hierarchical levels.

[0017] For example, the top left macrocell in Figure 3 has a bundle of output lines m1-m4, i.e. a total of 18 output lines for the 16 function cells, which exit the macrocell at the bottom. The reason there are more output lines than function cells is that the 8 functions on the left have a smaller area and are fan-out functions for branched output signals. Thus, the 16 functions of the macrocell have a total of 20 inputs, with 4 functions having 2 inputs each. The bundle of input lines n1-n4 is located on the right side of the macrocell. The inputs of the macrocell go to the vertical bus N of the array, and the outputs go to the horizontal bus M. When multiple macrocells are interconnected, it is not possible to provide an arbitrary number of buses so that every analog function of one macrocell can be interconnected with every analog function of every other macrocell. Thus, blocking can occur in some situations.

[0018] Analog signal transmission or distribution (routing) can be either current (based) or voltage (based) signals. In other words, signal transmission (or routing) in analog circuits, such as analog computers, can be in current mode or voltage mode.

[0019] When analog signals are distributed, static and dynamic errors must be considered. In the case of voltage-based signal transmission (or routing), the on-resistance of switches, such as crossbar switches, connected in series with the input resistance of analog functions such as integrators and adders becomes important. The switches require small on-resistance, which results in large gate areas and large parasitic capacitances. These capacitances, combined with the finite output resistance of each functional circuit and the on-resistance of upstream switches, narrow the signal bandwidth. In the case of current-based signal transmission (or routing), the voltage drop across the switches is not an issue, so the switches can be made smaller.

[0020] Fan-out and fan-in also make a difference between voltage (based) signaling (or routing) and current (based) signaling (or routing). In the case of current (based) signaling (or routing), the fan-in is simply a matter of connecting signal lines, while the fan-out (such as f1(x) in Figure 2) requires a special function. In the case of voltage (based) signaling (or routing), each analog function must have a number of resistors equal to the required fan-in, and if the fan-in is not enough, another summing stage must be connected before it.

[0021] A circuit diagram showing an implementation of an integrator for current-mode operation in a conventional analog computer is shown in Figure 4. Note that the fully differential circuit principle is applied in this integrator, but for simplicity, the fully differential circuit configuration is not depicted in Figure 4.

[0022] As shown in Figure 4, an integrator for current mode operation has a current input (i.e., fan-in circuit), a voltage-to-current conversion circuit (i.e., VI converter), and a current output (i.e., fan-out circuit). The fan-out circuit is a circuit for copying current when the output of the integrator must be switched to multiple subsequent inputs. In this example, the fan-out circuit has three current outputs; if a larger fan-out, i.e., more current outputs, is required, multiple fan-out circuits must be cascaded.

[0023] Taking into account fan-in and fan-out and bandwidth limitations due to on-resistance of (crossbar) switches, traditionally, transmission (or routing) of analog signals in analog computers such as the designs / implementations described above is typically accomplished by current (based) signals, i.e., in analog computers such as the designs / implementations described above, analog signals are typically transmitted or routed as currents.

[0024] Regarding the integrator implementation of FIG. 4, which shows an example of an implementation of an analog function in an analog circuit, using current (based) signal transmission / routing exhibits the following properties:

[0025] Regarding fan-in: The Vcn and Vcp input transistors must have low input impedance, which corresponds to high transconductance (gm). This requires high currents as well as short channel lengths, which, combined with matching errors in the upper and lower current mirrors (shown as X:Y in Figure 4), leads to offset errors.

[0026] Regarding VI conversion: Dynamically, this circuit has high stability because it integrates the current on an integral capacitance without negative feedback, where the integral capacitance represents the summing point of the integrator. That is, no integral capacitance is needed for the negative feedback of the op-amp. However, the bandwidth is limited by the finite transconductance of the fan-in circuit. The input node of the op-amp is in some sense isolated from the external signal bus, which is advantageous in case of interfering signals. The dual current output from the transconductance amplifier, realized by matching the current mirror, keeps the parasitic capacitance of the negative feedback loop small, which is good for dynamic stability. However, the matching error of the current mirror needs to be considered. Due to the fully differential circuit principle of the integrator, an additional transconductance amplifier is required for common-mode adjustment of the voltage on the integrating capacitance (not shown in Figure 4).

[0027] Regarding fanout: In fan-out circuits, the matching error between the upper and lower current mirrors (shown as X:Y in Figure 4) is important. Therefore, a current-steering DAC such as a 6-bit DAC (5 bits + sign) is required for correction / compensation. However, this can only correct the offset error, not the gain error.

[0028] In distributed analog computers, potentiometers are used to set the scaling and factor precisely. In integrated analog computers, digital potentiometers can be easily realized, for example, by R-2-R networks. However, in current mode, it is difficult to realize the appropriate coefficients for current-based signals. For example, in the implementation of Figure 4, the coefficients of all output currents can only be adjusted in the same way (generally) by changing the resistance value of resistor RV-I in the VI conversion circuit. To adjust the coefficients of each output current individually, a multiplying DAC is required. A multiplying DAC is a current-type DAC in which a current reference is used as the signal input. Current-type DACs can switch very instantaneously, but the signal bandwidth when changing the reference current is low and the area consumption is quite large.

[0029] From the above, it can be recognized that there is room for improvement in the design and operation of analog circuits that include multiple analog functions, and in particular in the interconnection of the multiple analog functions. In particular, there is room for improvement in the interconnection of the multiple analog functions of an analog circuit, in other words, in the signal transmission (or routing) between the multiple analog functions of an analog circuit.

[0030] Various embodiments disclosed herein aim to address at least some of the issues and / or problems and drawbacks described above.

[0031] More specifically, it is an object of the present disclosure to provide analog circuits that provide efficient interconnection or signal transmission (or routing) between multiple analog functions, and to provide methods of operating and / or designing such analog circuits.

[0032] Various aspects of the embodiments of the present disclosure are set forth in the following claims.

[0033] According to one exemplary aspect of the present disclosure, there is provided an analog circuit comprising: a plurality of analog functions divided into at least two groups; and an interconnect structure configured to interconnect the plurality of analog functions to enable transmission of both voltage and current signals between analog functions in the plurality of analog functions, the interconnect structure having at least two hierarchical levels of interconnection, a local bus hierarchical level configured to interconnect a group of analog functions and a global bus hierarchical level configured to interconnect a plurality of groups of analog functions, the local bus hierarchical level having voltage signal lines for transmitting voltage signals and / or current signal lines for transmitting current signals, and the global bus hierarchical level having voltage signal lines for transmitting voltage signals and / or current signal lines for transmitting current signals.

[0034] In the above configuration, the local bus hierarchy level may include at least one local bus for each group configured to interconnect the analog functions included in the group, and the global bus hierarchy level may include at least one global bus configured to interconnect the analog functions of the groups. In this case, the at least one local bus for each group may include a voltage signal line for transmitting a voltage signal, and the at least one global bus may include a current signal line for transmitting a current signal. And, the at least one local bus for at least one group may include a current signal line for transmitting a current signal, and / or the at least one global bus may include a voltage signal line for transmitting a voltage signal. Additionally or alternatively, any analog function may be connected to the local bus for its group and / or to the at least one global bus.

[0035] In any of the above configurations, the current input or current output of the analog function may be connected to a current signal line, and the voltage input or voltage output of the analog function may be connected to a voltage signal line.

[0036] In any of the above configurations, a first analog function connected to a voltage signal line in a group and a second analog function connected to a current signal line in the group may be interconnected via a voltage-to-current converter or a current-to-voltage converter as a third analog function in the group.

[0037] In any of the above configurations, at least one group may have a plurality of voltage-to-current converters as analog functions, the plurality of voltage-to-current converters being configured to extend the fan-in characteristics of the analog functions in that the current outputs of at least two voltage-to-current converters, each of which has its voltage input connected to a separate voltage signal line, are connected to a single current signal line that is connected to a current input of the analog function, and / or the plurality of voltage-to-current converters being configured to extend the fan-out characteristics of the analog functions in that the voltage output of the analog function is connected to a single voltage signal line that is connected to both voltage inputs of at least two voltage-to-current converters, each of which has its current output connected to a separate current signal line.

[0038] In any of the above configurations, at least one group may have one or more voltage-to-current converters as analog functions, where these converters are configured to extend signal bandwidth and / or reduce the effects of parasitic resistance in signal transmission in that one or more voltage signals are converted to one or more current signals and the one or more current signals are transmitted between the analog functions of the different groups via at least one global bus.

[0039] In any of the above configurations, at least one group may have a voltage-to-current converter as an analog function configured to compensate for gain error and / or offset error of the analog function in that one or more adjustable resistors, such as one or more potentiometers, of the voltage-to-current converter are adjusted to calibrate an output signal of the analog function.

[0040] In any of the above configurations, at least one group may have a voltage-to-current converter as an analog function configured to compensate for parasitic resistance at the voltage input of the analog function in that a calibrated current signal and a sign-inverted version of the calibrated current signal are transmitted to a current input of the analog function and an output signal of the analog function is adjusted to zero.

[0041] In any of the above configurations, the local bus hierarchy level may include a first local bus and a second local bus for at least one group, where the first local bus is configured to interconnect a set of analog functions of the respective group and the second local bus is configured to interconnect another set of analog functions of the respective group, and in this case the first local bus may have voltage signal lines for carrying voltage signals and the second local bus may have current signal lines for carrying current signals.

[0042] In any of the above configurations, the interconnect structure may have at least further hierarchical levels of interconnection, with at least one intermediate bus hierarchical level configured to interconnect analog functions of a set of groups in the plurality of groups, the at least one intermediate bus hierarchical level having voltage signal lines for transmitting voltage signals and / or current signal lines for transmitting current signals, where each set of groups may include several groups arranged adjacent or proximate to each other. Additionally or alternatively, the at least one intermediate bus hierarchical level may have at least one intermediate bus for a set of groups, the intermediate bus configured to interconnect analog functions of the set. Additionally or alternatively, the at least one intermediate bus hierarchical level may have at least a first intermediate bus for a first group set and a second intermediate bus for a second group set, the first group set including a smaller number of groups and / or groups that are adjacent or closely located to each other compared to the second group set, the first intermediate bus having voltage signal lines for transmitting voltage signals, and the second intermediate bus having current signal lines for transmitting current signals.

[0043] In any of the above configurations, the analog functions may be divided into groups such that the number of links between the analog functions within a group is optimized, in which case the analog functions may constitute a mathematical problem to be solved by the analog circuit.

[0044] In any of the above configurations, the analog function may be or may include an integrator, an adder, a multiplier, a voltage-to-current converter, a comparator, an exponential function, a logarithmic function, a configurable arbitrary waveform function generator, or a current-to-voltage converter.

[0045] In any of the above configurations, any of the plurality of analog functions may have functional elements configured to achieve the respective function without including fan-in and / or fan-out circuitry.

[0046] In any of the above configurations, the analog circuit may be any one of an analog computer, an analog arithmetic circuit, an analog filter, and an analog signal conditioner, may be incorporated into any one of these, or may be dedicated to any one of these.

[0047] In any of the above configurations, the analog circuit may be any one of a hybrid computer, a hybrid arithmetic circuit, a hybrid filter, and a hybrid signal conditioner, may be incorporated into any one of these, or may be dedicated to any one of these.

[0048] In any of the above configurations, the analog circuitry may be implemented as an integrated circuit such as a system-on-chip integrated circuit, a microchip, a microprocessor, or as a discrete circuit.

[0049] In any of the above configurations, it is possible to provide analog circuitry that provides efficient interconnection or signal transmission (or routing) between multiple analog functions.

[0050] Hereafter, further developments and / or modifications of the aforementioned exemplary embodiments are also disclosed. [Brief description of the drawings]

[0051] The disclosure of the present application will now be explained in more detail, by way of non-limiting examples, with reference to the accompanying drawings, in which: [Figure 1] FIG. 1 is a schematic diagram showing a configuration of local routing and global routing in a conventional FPGA. [Diagram 2] FIG. 1 is a schematic diagram showing a configuration of a macrocell in a conventional analog computer. [Diagram 3] FIG. 1 is a schematic diagram showing the configuration of an array of four macrocells in a conventional analog computer. [Figure 4] FIG. 1 is a circuit diagram showing an implementation of an integrator using current mode operation in a conventional analog computer. [Diagram 5] FIG. 2 is a schematic diagram showing an example of a configuration of local routing and global routing in an analog circuit according to an embodiment. [Figure 6] FIG. 2 is a schematic diagram showing an example of a configuration of local routing and global routing in an analog circuit according to an embodiment. [Figure 7] FIG. 2 is a schematic diagram showing an example of a configuration of local routing and global routing in an analog circuit according to an embodiment. [Figure 8] FIG. 2 is a schematic diagram showing an example of a configuration of local routing and global routing in an analog circuit according to an embodiment. [Figure 9] FIG. 2 is a circuit diagram illustrating an implementation of a cluster of analog circuits according to an embodiment. [Figure 10] FIG. 2 is a schematic diagram showing an example of a configuration of local routing, global routing, and intermediate routing in an analog circuit according to an embodiment. [Figure 11] FIG. 2 is a schematic diagram showing an example of a configuration of local routing, global routing, and intermediate routing in an analog circuit according to an embodiment. [Figure 12] 1 is a flowchart illustrating an example of a method for designing an analog circuit according to an embodiment. [Figure 13] 1 is a flowchart illustrating an example of a method for designing an analog circuit according to an embodiment. Detailed explanation

[0052] The disclosure of the present application will now be described with reference to certain non-limiting examples of currently contemplated embodiments, but those skilled in the art will understand that the disclosure is in no way limited to these examples and embodiments, but may be more broadly applicable.

[0053] Please note that the following description mainly focuses on the specifications used as non-limiting examples and embodiments of certain exemplary circuit structures, implementations, and technologies. These descriptions are used only in the context of the presented non-limiting examples and embodiments and are not intended to limit the present disclosure in any way. Rather, any other circuit structures, implementations, and technologies may be used as well, so long as the contents described herein and / or the embodiments described herein are applicable.

[0054] Various examples and embodiments of some aspects disclosed herein are described below with some variations and / or alternatives. In general, all of the various forms and / or alternatives described may be provided alone or in any possible combination (including combinations of individual features of the various forms and / or alternatives) according to specific needs and constraints. In this specification, the words "comprise", "have", and "include" should be understood not to limit the described examples and embodiments to only the mentioned features. Such examples and embodiments may also include structures, units, modules, networks, etc. that are not mentioned.

[0055] It should be noted that in the drawings, lines and arrows interconnecting individual blocks or entities are generally meant to illustrate an operational coupling therebetween, which may be a physical and / or logical coupling, on the one hand, that is independent of the implementation, and on the other hand, that may consist of any number of intermediate functional blocks or entities not shown.

[0056] In accordance with embodiments of the present disclosure, there is generally provided an analog circuit, and a method of operating and / or designing an analog circuit, that provides efficient interconnection or signal transmission (or routing) between multiple analog functions. In the present disclosure, an analog function may be or include any analog function, such as an integrator, an adder (including a subtractor), a multiplier, a voltage-to-current (VI) converter, a current-to-voltage (IV) converter, a comparator, an exponential function, a logarithmic function, a configurable arbitrary waveform function generator, etc.

[0057] Here, "analog circuitry" may refer to an analog or hybrid computer, an analog or hybrid computing circuit, an analog or hybrid filter, an analog or hybrid signal conditioner, and the like. More specifically, an analog circuitry according to the present disclosure may be an analog computer, an analog computing circuit, an analog filter, an analog signal conditioner, and the like, or may be included in or dedicated to any of these. More specifically, an analog circuitry according to the present disclosure may be a hybrid computer, a hybrid computing circuit, a hybrid filter, a hybrid signal conditioner, and the like, or may be included in or dedicated to any of these. Thus, the present disclosure encompasses analog or hybrid computers, analog or hybrid computing circuits, analog or hybrid filters, analog or hybrid signal conditioners, and the like, that include or are included in analog circuits as disclosed herein.

[0058] Additionally, analog circuitry according to the present disclosure may be implemented in any manner, for example as an integrated circuit, such as a system-on-a-chip integrated circuit, a microchip or a microprocessor, or as discrete circuitry, and thus the present disclosure encompasses integrated circuits, system-on-a-chip integrated circuits, microchips, microprocessors, discrete circuits, etc., in which or by which analog circuitry as disclosed herein is implemented.

[0059] Furthermore, in this specification, a bus is intended to represent any medium capable of transmitting / carrying any kind of signal. More specifically, a bus may represent a shared transmission medium that allows the transmission / carrying of signals between different components depending on their configuration, operation or control.

[0060] According to the present disclosure and / or embodiments thereof, an analog circuit comprises a plurality of analog functions divided into at least two groups, and an interconnect structure configured to interconnect the plurality of analog functions to enable transmission of both voltage and current signals between analog functions in the plurality of analog functions, the interconnect structure having at least two hierarchical levels of interconnection, a local bus hierarchical level configured to interconnect the analog functions of each group, and a global bus hierarchical level configured to interconnect the analog functions of the plurality of groups, the local bus hierarchical level having voltage signal lines for transmitting voltage signals and / or current signal lines for transmitting current signals, and the global bus hierarchical level having voltage signal lines for transmitting voltage signals and / or current signal lines for transmitting current signals.

[0061] Thus, analog circuits according to the present disclosure and / or embodiments thereof provide a (combination) of local and global routing and can use different (types) of signals, i.e., voltage signals and current signals, for local and global routing, thereby beneficially combining the advantages of each method of signal transmission (or routing), i.e., current mode operation and voltage mode operation, as will be explained in more detail below.

[0062] In an exemplary variation of an analog circuit according to the present disclosure and / or embodiments thereof, a local bus hierarchy level is configured to transmit voltage signals by or through one or more voltage signal lines, i.e., the local routing is voltage-based, and a global bus hierarchy level is configured to transmit current signals by or through one or more current signal lines, i.e., the global routing is current-based.

[0063] In an exemplary variation of an analog circuit according to the present disclosure and / or embodiments thereof, the local bus hierarchy level is configured to transmit voltage signals by or through one or more voltage signal lines and current signals by or through one or more current signal lines, i.e. the local routing is both voltage-based and current-based, e.g. preferably voltage-based but additionally current-based; and / or the global bus hierarchy level is configured to transmit current signals by or through one or more current signal lines and voltage signals by or through one or more voltage signal lines, i.e. the global routing is both current-based and voltage-based, e.g. preferably current-based but additionally voltage-based.

[0064] In an exemplary variant of the analog circuit according to the present disclosure and / or embodiments thereof, the interconnect structure has at least further hierarchical levels of interconnection, and at least one intermediate bus hierarchical level is configured to interconnect the analog functions of a set of groups of the plurality of groups, the at least one intermediate bus hierarchical level having voltage signal lines for transmitting voltage signals and / or current signal lines for transmitting current signals, i.e., any intermediate bus hierarchical level, whether at a local bus hierarchical level or at a global bus hierarchical level, is configured to transmit voltage signals by / through one or more voltage signal lines and / or current signals by / through one or more current signal lines, i.e., the intermediate routing is configured to be voltage-based and / or current-based.

[0065] In describing the embodiments of the present disclosure, reference is made primarily to an analog computer as an analog circuit, but this is for purposes of illustration and explanation, not limitation of the scope of applicability, i.e., all features and characteristics exemplified by an analog computer are equally applicable to any type of analog circuit, where feasible, unless otherwise specified.

[0066] With reference to FIGS. 5-9, various examples and embodiments of analog circuits including two hierarchical levels of interconnection, a local bus hierarchical level and a global bus hierarchical level, are disclosed.

[0067] FIG. 5 is a schematic diagram showing an example of a configuration of local routing and global routing in an analog circuit according to an embodiment.

[0068] As shown in FIG. 5, an analog circuit according to an embodiment includes a plurality of analog functions (denoted as “func”) and an interconnect structure configured to interconnect the plurality of analog functions. The plurality of analog functions are divided into at least two analog function groups, each group being illustratively represented by a vertically arranged block of analog functions. As mentioned above, any of the analog functions may be or may include any analog function, such as an integrator, an adder (including a subtractor), a multiplier, a voltage-to-current (VI) converter, a current-to-voltage (IV) converter, a comparator, an exponential function, a logarithmic function, a configurable arbitrary waveform function generator, etc. The grouped plurality of analog functions need not be arranged linearly, but may be arranged in another manner, for example, depending on the shape, size, dimensions, etc. of the physical layout of the circuit of each function.

[0069] In some embodiments, the local bus hierarchy level has at least one local bus for each group configured to interconnect the analog functions contained in that group, and the global bus hierarchy level has at least one global bus configured to interconnect the analog functions of the groups. Any analog function may be connected to at least one local bus for its group and / or to at least one global bus. Regardless of the exemplary illustration of FIG. 5, depending on the (type and / or requirements of) the analog function, each analog function may be connected to a local bus, a global bus, or both a local bus and a global bus.

[0070] It should be noted that switches such as crossbar switches are not shown in the interconnect structure of FIG. 5. However, it would be clear to one skilled in the art where and how such switches should be provided to enable appropriate / necessary signal transmission (or routing) between the analog functions. Specifically, switches are provided at voltage connections (indicated by arrows marked with "V") between the analog functions (inputs or outputs) and the voltage lines of the bus, current connections (indicated by arrows marked with "I") between the analog functions (inputs or outputs) and the current lines of the bus, and at the intersections of the signal lines of the bus. For example, it would be clear that the connections at the crossbar are between the vertical current buses (lines) and the horizontal current buses (lines).

[0071] In some embodiments, the interconnect structure comprises a local bus (i.e., local interconnect) for each group configured to interconnect the analog functions of each group, and a global bus (i.e., global interconnect) configured to interconnect the analog functions of multiple groups. That is, the local bus is provided / configured to (enable) local routing of signals between the analog functions in each group, and the global bus is provided / configured to (enable) global routing of signals between the analog functions between the different groups. Thus, the interconnection between the analog functions in the analog circuit is configured in two hierarchical levels, with the local bus representing a first or lower hierarchical level and the global bus representing a second or higher hierarchical level. Both the local bus and the global bus are configured with an appropriate number of signal lines depending on the number of analog functions, their grouping, routing requirements, etc.

[0072] In some embodiments, each group of local buses has voltage signal lines for transmitting voltage signals, i.e., lines (dedicated) for transmitting voltage (based) signals or simply voltage, as indicated by a "V" on the respective bus or line, and at least one global bus has current signal lines for transmitting current signals, i.e., lines (dedicated) for transmitting current (based) signals or simply current, as indicated by an "I" on the respective bus or line.

[0073] Thus, the analog circuitry according to the present embodiment provides a (combination of) local and global routing, where the local routing is based on voltage and the global routing is based on current, thereby beneficially combining the advantages of each method of signal transmission (or routing), i.e., current-mode and voltage-mode operation, as will be explained in more detail below.

[0074] However, as will be demonstrated below, the present disclosure is not limited to structures or configurations in which the local routing (ie, any local buses) are purely voltage type and the global routing (ie, any global buses) are purely current type.

[0075] 5 exemplarily shows a single local bus for each group. However, a local bus hierarchy level may have multiple local buses for at least one group. A local bus hierarchy level may, for example, have a first local bus and a second local bus for at least one group, where the first local bus is configured to interconnect a set of analog functions of the respective group and the second local bus is configured to interconnect another set of analog functions of the respective group. In this case, for example, the first local bus may be configured to transmit voltage signals by or through one or more voltage signal lines and the second local bus may be configured to transmit current signals by or through one or more current signal lines.

[0076] FIG. 6 is a schematic diagram showing an example of a configuration of local routing and global routing in an analog circuit according to an embodiment.

[0077] As shown in Fig. 6, the analog circuit according to this embodiment has the same basic configuration or structure as that shown in Fig. 5. Therefore, the explanation of Fig. 5 applies mutatis mutandis to the basic structure or configuration, and differences will be explained below. As in Fig. 5, it will be clear that the connections in the crossbar are connections between vertical current buses (lines) and horizontal current buses (lines).

[0078] In some embodiments, at least one group of local buses further comprises a current signal line for transmitting a current signal. As shown in Fig. 6, each local bus has a current signal line for transmitting a current signal (denoted by "I") in addition to a voltage signal line for transmitting a voltage signal (denoted by "V"). Thus, a local bus has a combination or mixed configuration of one or more lines (dedicated to) transmitting a current (based) signal or simply a current, and one or more lines (dedicated to) transmitting a voltage (based) signal or simply a voltage.

[0079] Such an interconnect structure allowing combined voltage and current local routing is useful / beneficial in any group where there are multiple analog functions (e.g. multipliers, etc.) with current outputs in the group, i.e. it allows signal transmission (or routing) between such analog functions in the group to avoid having to detour to at least one global bus, thus saving signal lines on at least one global bus.

[0080] In addition to interconnecting analog functions within a group based on voltage, providing or allowing interconnection based on current as an additional method of signal distribution can have various advantages, for example, it can reduce the connection effort of analog functions that inherently have a current output, for example, parallel processing of voltage and current at the input of the analog function can allow calibration of parasitic resistances of switches.

[0081] Thus, the analog circuitry according to the present embodiment provides a (combination of) local and global routing, where the local routing is based on voltage and / or current, and the global routing is based on current, thereby more usefully combining the advantages of each method of signal transmission (or routing), i.e., current-mode and voltage-mode operation, as will be explained in more detail below.

[0082] FIG. 7 is a schematic diagram showing a configuration example of local routing and global routing in an analog circuit according to an embodiment.

[0083] As shown in Fig. 7, the analog circuit according to this embodiment has the same basic configuration or structure as that shown in Fig. 5. Therefore, the explanation of Fig. 5 applies mutatis mutandis to the basic structure or configuration, and differences will be explained below. As in Fig. 5, it is clear that the connections in the crossbar are between vertical current buses (lines) and horizontal current buses (lines), or between vertical voltage buses (lines) and horizontal voltage buses (lines).

[0084] In some embodiments, at least one global bus further comprises a voltage signal line for transmitting a voltage signal. As shown in Figure 7, each global bus has a voltage signal line for transmitting a voltage signal (denoted by "V") in addition to a current signal line for transmitting a current signal (denoted by "I"). Thus, a global bus has a combination or mixed configuration of one or more lines (dedicated to) transmitting a voltage (based) signal or simply a voltage, and one or more lines (dedicated to) transmitting a current (based) signal or simply a current.

[0085] Such an interconnect structure allows global routing of combined currents and voltages, which is useful when the connected analog functions have high input resistance, for example in the case of instrumentation amplifiers, or when a reference voltage must be distributed to several locations simultaneously, for initial conditioning of integrators, or for individual or global calibration of the system after power-up, thus reducing the number of signal lines required and allowing for more efficient operation.

[0086] In addition to providing or allowing current interconnections between analog functions between different groups, i.e. between analog functions at lower hierarchical levels and at higher hierarchical levels, providing or allowing voltage interconnections as an additional method of signal distribution can have various advantages, for example it is possible to calibrate errors in the case of high impedance inputs and low dynamic demands.

[0087] Thus, the analog circuitry according to the present embodiment provides a (combination of) local and global routing, where the local routing is based on voltage and the global routing is based on current and / or voltage, thereby more usefully combining the advantages of each method of signal transmission (or routing), i.e., current-mode and voltage-mode operation, as will be explained in more detail below.

[0088] In some embodiments, the structures or configurations of Figures 6 and 7 may be combined. Thus, an analog circuit according to an embodiment may comprise an interconnect structure in which at least one group of local buses further comprises current signal lines for transmitting current signals (as shown in Figure 6), and at least one global bus further comprises voltage signal lines for transmitting voltage signals (as shown in Figure 7). Thus, the respective advantages of these structures or configurations may be appropriately combined.

[0089] FIG. 8 is a schematic diagram showing a configuration example of local routing and global routing in an analog circuit according to an embodiment.

[0090] As shown in Fig. 8, the analog circuit according to this embodiment has the same basic configuration or structure as that shown in Fig. 5. Therefore, the explanation of Fig. 5 applies mutatis mutandis to the basic structure or configuration, and differences will be explained below. As in Fig. 5, it will be clear that the connections in the crossbar are connections between vertical current buses (lines) and horizontal current buses (lines).

[0091] In some embodiments, each analog function is connected to a local bus for its group and / or to at least one global bus. In the example shown in Figure 8, in each group, two functions are connected only to the local bus for that group, two functions are connected only to the global bus, and two functions designated V / I are connected to both the local bus and the global bus for that group. Of course, the structure or configuration need not be the same between different groups.

[0092] Thus, an analog function does not have to be connected to a local voltage bus and a global current bus simultaneously, but can also be connected to a local voltage bus or a global current bus, respectively, and the analog functions of the group connected to the local voltage bus and the analog functions of the group connected to the global current bus can be interconnected via one or more current-to-voltage converters or current-to-voltage converters (connected between the local voltage bus and the global current bus).

[0093] Such interconnections are equally applicable in the structures or configurations of Figures 6 and / or 7. For example, referring to Figure 6, a group of analog functions, some of which are connected to a local voltage bus and some to a local current bus, i.e., some of which are connected to one or more voltage lines of the local bus for that group and some of which are connected to one or more current lines of the local bus for that group, may be interconnected via one or more current-to-voltage converters or current-to-voltage converters (connected between the local voltage bus and the local current bus).

[0094] As will be apparent to those skilled in the art, depending on the characteristics of the inputs and outputs of the analog functions so interconnected, either a voltage-to-current converter or a current-to-voltage converter may be used for such an interconnection, i.e., the interconnection may be achieved through a voltage-to-current converter if the output of one analog function is a voltage output and the input of the other analog function (which may be the same as the one) is a current input, or through a current-to-voltage converter if the output of one analog function is a current output and the input of the other analog function (which may be the same as the one) is a voltage input.

[0095] Thus, a first analog function connected to a voltage signal line in a group and a second analog function connected to a current signal line in the group can be interconnected via a voltage-to-current converter or a current-to-voltage converter as a third analog function in the group.

[0096] However, although not shown in FIG. 8, at least one group may have one or more analog functions (func) connected to both the local bus and the global bus of that group.

[0097] In some embodiments, the current input or current output of an analog function may be connected to a current signal line, and the voltage input or voltage output of an analog function may be connected to a voltage signal line. That is, the input and output of an analog function may belong to / be associated with the same electrical signal or may belong to / be associated with different electrical signals. For example, as is clear from FIG. 9, a multiplier may have a voltage input and a current output, and an integrator or adder may have a voltage input, a current input, or both, and a voltage output.

[0098] FIG. 9 is a circuit diagram illustrating an implementation of a cluster of analog circuits according to one embodiment.

[0099] FIG. 9 shows an exemplary implementation combining voltage-based and current-based signal transmission (or routing) at two hierarchical levels of analog circuitry in accordance with the above embodiments for a cluster essentially corresponding to an analog function group as shown in any one of FIGS. 5 to 8.

[0100] As is clear from Figure 9, local routing is realized on a voltage basis via (interconnection by) a local voltage bus, while global routing is realized on a current basis via (interconnection by) a global current bus. This basically corresponds to the configuration or interconnection of Figure 5. This allows combining the advantages of each: voltage-based coupling is technically easier to implement, but has limitations in terms of fan-in characteristics; current-based coupling, on the other hand, requires a VI converter at the output of analog functions with voltage output, such as integrators, but unlike voltage-based coupling, the parasitic resistance of the switches is not significant.

[0101] In the exemplary implementation of FIG. 9, two integrators (denoted by “INT”) and two adders (denoted by “ADD”) are shown at the bottom, one multiplier (denoted by “MUL”) and two VI converters (denoted by “I / V”) are shown at the top, and all these analog functions are interconnected via a local voltage bus and a global current bus. The two integrators and the two adders have differential voltage outputs, which are switched to the local voltage bus. In principle, all the integrators and adders can be interconnected in any way, provided that the fan-in (2 in this example) is sufficient. The multipliers have a current output. Thus, like the VI converters, the multipliers are also not connected to the local voltage bus at the output side, but to the global current bus.

[0102] The multipliers, like the VI converters, can be connected to the summation node of one of the integrators and / or summers via paths in the global routing channels, i.e., the global current bus. Either the integrators and / or summers can be connected to either the multipliers and / or the VI converters via paths in the local routing channels, i.e., the local voltage bus.

[0103] In the exemplary embodiment of FIG. 9, the VI converter has various tasks or functions (operations), which are described below.

[0104] First, by converting the signals to currents and using internal summation nodes, the limited fan-in of, for example, integrators and / or adders can be extended, and therefore any fan-in can be realized for these integrators or adders. Additionally or alternatively, by using multiple VI converter inputs for voltage outputs, the limited fan-out (of the integrators and / or adders) can be extended, and therefore any fan-out can be realized for these integrators or adders. Thus, only the minimum or required fan-in and fan-out characteristics need to be provided or realized for each (circuit of) the analog functions, for example, for the integrators or adders.

[0105] Thus, if the group includes a voltage-to-current converter as an analog function, the voltage-to-current converter can be configured as follows: First, the fan-in property of the analog function can be extended such that the current outputs of at least two voltage-to-current converters, each of which has a voltage input connected to a different voltage signal line, are connected to a current signal line connected to a current input of the analog function. That is, the current outputs can be connected to a current signal line connected to a current input of the analog function. Additionally or alternatively, the voltage-to-current converter can be configured to extend the fan-out property of the analog function in that the voltage output of the analog function is connected to one voltage signal line connected to both voltage inputs of the at least two voltage-to-current converters, and each current output of the at least two voltage-to-current converters is connected to a separate current signal line. That is, the voltage output of the analog function can be connected to a voltage signal line connected to a voltage input of the at least two voltage-to-current converters.

[0106] Second, a VI converter can convert a voltage signal to a current and distribute it to any number of switches on a global current bus without the detrimental voltage drop of the on-resistance (of the switches that are on). That is, it can convert the voltage of an analog function to a current and distribute the converted current among groups of analog functions through multiple switches at higher hierarchical levels without the detrimental effects of parasitic resistance or resistors.

[0107] Thus, if a group has one or more voltage-to-current converters as analog functions, these converters can be configured to extend the signal bandwidth and / or reduce the effect of parasitic resistance in the signal transmission in that one or more voltage signals are converted into one or more current signals and the one or more current signals are transmitted over at least one global bus between the analog functions of different groups, i.e. one or more voltage signals can be converted into one or more current signals and the one or more current signals can be transmitted over at least one global bus.

[0108] Third, VI converters allow finer scale coefficients that would require a lot of effort in pure current-mode operation: adjustable resistors, such as (digitally finely divided) potentiometers, can be used to achieve the coefficients for current-based signals.

[0109] That is, if a group includes a voltage-to-current converter as an analog function, the voltage-to-current converter can be configured to compensate for gain and / or offset errors of the analog function in that one or more adjustable resistors, such as one or more potentiometers of the voltage-to-current converter, are adjusted to calibrate the output signal of the analog function, i.e., the adjustable resistor or resistors can be adjusted to calibrate the output signal of the analog function.

[0110] Fourth, the VI converter can calibrate the parasitic resistance at each voltage input by parallel processing of current and voltage in an analog function: by inputting a calibrated current signal in parallel to the summation point of an integrator or summer, and at the same time inputting the same signal with the sign inverted to the integrator or summer, the error due to the parasitic resistance of the switch connected in series with the input resistance of the integrator or summer can be compensated.

[0111] Thus, if a group includes a voltage-to-current converter as an analog function, this voltage-to-current converter can be configured to compensate for the parasitic resistance at the voltage input of the analog function in that a calibrated current signal and a sign-inverted version of the calibrated current signal are transmitted to the current input of the analog function and the output signal of the analog function is adjusted to zero, i.e. the calibrated current signal and a sign-inverted version of the calibrated current signal can be provided to the current input of the analog function and the output signal of the analog function can be adjusted to zero.

[0112] In the following, a description is provided of (a combination of) local and global routing, where the local routing is (mainly) voltage-based and the global routing is (mainly) current-based, i.e., the advantages of each method of signal transmission (or routing), i.e., current-mode operation and voltage-mode operation, and their combination according to the present disclosure.

[0113] Regarding the comparison of interconnection or signal transmission (or routing) in voltage mode and current mode with respect to fan-in / fan-out characteristics, the following considerations and findings underlie the above-described embodiments.

[0114] Considering the integrator as the main component of an analog computer, it should be noted that integration on a capacitor primarily generates a voltage. For the transmission (or routing) of a current signal, this voltage must be converted into a current. Such a conversion can be done in various ways. On the one hand, it is possible to use an integrator that stores the voltage in a logarithmically compressed form. When the logarithmically compressed voltage is converted into a current using the exponential function of bipolar transistors or MOSFETs in weak inversion operation, a current is implicitly generated. On the other hand, it is also possible to use an integrator circuit configuration as shown in Figure 4. In this case, the current is first directed to the integrating capacitance by means of a cascode and a current mirror. For the integration itself, no op-amp with a capacitance in the feedback is required, only a cascode circuit with an impedance converter, i.e. a fan-in circuit. However, the impedance converter places high demands on the accuracy, so it must be properly calibrated. The conversion of the voltage on the integrating capacitance to a current is realized by two transconductance amplifiers with unipolar outputs. These transconductance amplifiers each have a dual current output, one of which is fed to a resistor and used for the voltage feedback. (In Figure 4, only the single-ended configuration of the circuit is shown.) The second output goes to the crossbar switch, i.e. the switch of the crossbar. Because the transconductance amplifier is doubled to produce a fully differential output current, the transconductance amplifier does not need its own common-mode adjustment. However, the common-mode potential of the differential integrating capacitance must be adjusted to the common-mode reference potential by another transconductance amplifier. (In Figure 4, this transconductance amplifier for common-mode adjustment is not shown.)

[0115] Voltage mode is good for fan-out because you can spread the voltage as wide as you want. It is bad for fan-in because you have to have a lot of input resistors (corresponding to the fan-in you want). These input resistors may not be used, resulting in circuit overhead. But the resistor overhead is not high. Another problem is that the crossbar switches, i.e. the switches of the input crossbars, are connected in series with resistors because systematic errors occur due to the voltage drop across the switches.

[0116] Current mode is advantageous for fan-in because a subsequent analog function, i.e. its input, can easily be connected to multiple fan-outs of the previous analog function. However, current mode is disadvantageous for fan-out because of the need to use current mirrors in the fan-out circuits (instead of resistors at the summing points of the integrators or summers). From this perspective, the increased complexity can be seen because the multiplying current DACs required to calibrate the offset of the fan-out circuits (i.e. to compensate for the offset error) are much more complex than discrete or digital potentiometers where trimming or representing resistors is sufficient.

[0117] 10 and 11, various examples and embodiments are disclosed for analog circuits that include three hierarchical levels of interconnection: a local bus hierarchical level, a global bus hierarchical level, and an intermediate bus hierarchical level.

[0118] According to the embodiment of Figures 10 and 11, in addition to the local bus hierarchy level and the global bus hierarchy level (which may be configured as described above), the interconnect structure comprises an intermediate bus hierarchy level of interconnection configured to interconnect analog functions of a set of several groups included in the plurality of groups, and having voltage signal lines for transmitting voltage signals and / or current signal lines for transmitting current signals.

[0119] FIG. 10 is a schematic diagram showing an example of a configuration of local routing, global routing, and intermediate routing in an analog circuit according to an embodiment.

[0120] As shown in Figure 10, the analog circuit according to the present embodiment has a structure or configuration in which a set (or cluster) of analog function groups share a mid-level bus (or intermediate bus) in addition to a local bus for each group and at least one global bus. This mid-level bus is configured to interconnect the analog functions of the set (or cluster). In Figure 10, the dashed box indicates one of the sets (or clusters) of analog functions that share the mid-level bus. That is, the 2x2 analog function groups on the left share the mid-level bus.

[0121] Of course, the number and / or arrangement of analog function groups constituting a set or cluster is not limited to the embodiment of Fig. 10, and any number of analog function groups in close proximity (e.g., adjacent) to each other can constitute a set or cluster. Also, analog circuits may have sets or clusters of the same structure or configuration, or may have sets or clusters of different structures or configurations.

[0122] In some embodiments, the local buses of each group have voltage signal lines for transmitting voltage signals, i.e., lines (dedicated) for transmitting voltage (based) signals or simply voltages, as indicated by a "V" at the connections on the respective buses or lines. At least one global bus also has current signal lines for transmitting current signals, i.e., lines (dedicated) for transmitting current (based) signals or simply currents, as indicated by an "I" on the respective buses or lines. Additionally, the mid-level buses of each set or cluster have voltage signal lines for transmitting voltage signals, i.e., lines (dedicated) for transmitting voltage (based) signals or simply voltages, as indicated by a "V" on the respective buses or lines.

[0123] In Fig. 10, signal transmissions between local and mid-level voltage buses are represented by lines with arrows (indicated by "V"). Such connections can be realized by corresponding switches between these buses. It should also be clear that the connections in the crossbar are between vertical current buses (lines) and horizontal current buses (lines) or between vertical voltage buses (lines) and horizontal voltage buses (lines). At the intersections of mid-level voltage buses and global current buses, no crossbar switches are present (not allowed). Crossbar switches are present (allowed) only between intersecting voltage lines and / or intersecting current lines (i.e. buses of the same electrical type).

[0124] Although not shown in FIG. 10, at least some analog functions may be connected directly to the mid-level voltage bus without an (intermediate) connection via the local voltage bus.

[0125] FIG. 11 is a schematic diagram showing an example of the configuration of local routing, global routing, and intermediate routing in an analog circuit according to an embodiment.

[0126] As shown in Fig. 11, the analog circuit according to this embodiment has the same basic configuration or structure as that shown in Fig. 10. Therefore, the basic structure or configuration is explained mutatis mutandis with reference to Fig. 10, and only the differences will be explained below.

[0127] In some embodiments, the local buses of each group have voltage signal lines for transmitting voltage signals, i.e., lines (dedicated) for transmitting voltage (based) signals or simply voltage, as indicated by a "V" on the respective buses or lines. At least one global bus also has current signal lines for transmitting current signals, i.e., lines (dedicated) for transmitting current (based) signals or simply current, as indicated by an "I" on the respective buses or lines. Additionally, the mid-level buses of each set or cluster have current signal lines for transmitting current signals, i.e., lines (dedicated) for transmitting current (based) signals or simply current, as indicated by an "I" on the respective buses or lines.

[0128] It will be apparent that the crossbar connections connect vertical current buses (lines) with horizontal current buses (lines).

[0129] In Figure 11, signal transmission between the mid-level current buses and the global current buses is represented by lines with arrows (denoted by "I"). Such connections can be realized by corresponding switches between these buses, or by crossbar switches where the mid-level current buses cross the global current buses (since these buses are of the same electrical type).

[0130] Although not shown in FIG. 11, at least some analog functions may be connected directly to the global current buses without an (intermediate) connection via the intermediate level current buses.

[0131] In general, the structures or configurations shown in Figures 10 and 11 are not limited accordingly. It should be noted that these are for illustrative purposes. For example, any connection between each analog function and one or more of the local buses, mid-level buses, and global buses may be applicable, various arrangements of analog functions within each group may be applicable, various arrangements of sets or clusters may be applicable, and all variations as described above (with respect to Figures 5-9), respectively, may be applicable. For example, the local intermediate buses and global buses may have a combination or mixed configuration of one or more lines (dedicated) to carrying a current (based) signal or simply a current, and one or more lines (dedicated) to carrying a voltage (based) signal or simply a voltage.

[0132] As regards the use of different (types of) signals, i.e. (combinations of) voltage and current signals, for local, global and intermediate routing, the above explanations regarding (combinations of) local and global routing apply analogously.

[0133] It should be noted that although Figures 10 and 11 show an analog circuit with three hierarchical levels of interconnection, any number of hierarchical levels are applicable. That is, in some embodiments, an analog circuit may have four or more hierarchical levels of interconnection, such as a local bus hierarchical level, a global bus hierarchical level, and any number of intermediate bus hierarchical levels, where each intermediate bus hierarchical level is configured to interconnect analog functions of a different set (or cluster) of analog function groups. For example, with reference to the exemplary structure or configuration of Figures 10 and 11, the illustrated intermediate level bus may represent a third hierarchical level (for a set or cluster of 2x2 analog function groups) and a fourth hierarchical level (for a set or cluster of 4x2 analog function groups). In this case, two sets or clusters of the third hierarchical level in the embodiment of Figures 10 and 11 constitute another set or cluster of the fourth hierarchical level. For such additional hierarchical levels, the above description of the third hierarchical level applies as appropriate.

[0134] 10 and 11 exemplarily show a single mid-level bus for each set or cluster, an intermediate bus hierarchy level may have multiple mid-level buses for at least one set or cluster. For example, an intermediate bus hierarchy level may have at least a first mid-level bus for a first group set (or cluster) and a second mid-level bus for a second group set (or cluster). In this case, for example, the first group set (or cluster) may be composed of a smaller number of groups and / or groups that are more adjacent or closely located than the second group set. The first mid-level bus may also be configured to transmit voltage signals by or through one or more voltage signal lines. The second mid-level bus may also be configured to transmit current signals by or through one or more current signal lines.

[0135] According to the present disclosure, an efficient and compact analog circuit architecture can be provided by combining the advantages of voltage mode and current mode and eliminating the fan-in / fan-out problem.

[0136] In this regard, according to various embodiments, one or more of the following may be adopted. Integrators can provide current and voltage inputs simultaneously; the current input only requires another switch at the summation point. The on-resistance of the switch is not an issue. Integration can be done using a conventional opamp-based integrator, with a buffered voltage available at the output. The drawback of direct current injection in an opamp-based integrator or summer is that the input summing point is connected to the signal bus. Thus, interference can be reduced by using a fully differential circuit and, if necessary, a first order low pass filter on the input signal line, with a corner frequency below the second pole frequency of the integrator. The integrator eliminates the fan-out circuitry required for current mode. This is beneficial because offset errors are complex to correct and gain errors are almost impossible to correct. · If more than one fan-out is required, i.e. more than one output is required, this can be achieved in different ways. On the one hand, the voltage mode of one or more subsequent analog functions, such as integrators or adders, can be used, since a voltage output can provide any fan-out. If the current mode of one or more subsequent analog functions, such as integrators or adders, is used, i.e. a current needs to be conducted through the corresponding signal line or bus, several voltage-to-current converters (VI converters), each with one fan-out, can be used in parallel (and each of these can be connected to the current fan-in of one or more subsequent analog functions). If the on-resistance of the switches becomes an issue due to voltage fan-in, calibration can be done by feeding the integrator or summer with a positive reference signal once through the resistor and switch path and once with a negative reference signal as a current through the switch, and adjusting the summer or integrator result to zero. This can be done by designing some of the resistors as (digital) potentiometers, reducing their normal resistance to the point where their reduced resistance along with the on-resistance of the switches corresponds to the desired nominal resistance. Fan-out circuits for analog functions such as integrators and summers, which are required in current mode, can be omitted. This allows for correction of both gain and offset errors based on (digital) potentiometers without the need for complex current-mode DACs. Voltage mode can be used (preferably or as a first choice) for local routing to adjacent functions or elements, provided the connections are made with the shortest possible lines and are made with direct connections. For global routing, i.e. routing through multiple switches in a crossbar distributor to remote functions or elements, current mode can be used (preferably or as a first choice). Voltage mode and current mode can be combined in a fan-out, for example by driving an adjacent function or element directly with a voltage and transmitting the signal as a current to a remote function or element by a VI converter. One or more VI or IV converters can be used, for example in one or several groups. This overcomes the problem that with current signal distribution there is no easy way to fine-tune the coefficients, because the reference resistors in the converters can be implemented with digital potentiometers that allow fine adjustment.

[0137] According to various embodiments of the present invention, simplified and efficient circuit structures can be adopted for the implementation of integrators in analog circuits. For example, instead of the circuit structure shown in Figure 4, a circuit structure as shown in Figure 9 can be adopted. That is, the fan-out circuitry can be omitted, a classical op-amp-based implementation can be utilized, and the optimal fan-in concept can be applied, as explained above.

[0138] The configuration and functional characteristics of analog circuits according to various embodiments have been described. These descriptions constitute a disclosure of the analog circuits, their configurations, structures, and elements. They also constitute a disclosure of the manner in which the analog circuits operate, a disclosure of the methods for operating the analog circuits, and a disclosure of the processes and functions by which the analog circuits operate. When any interconnection or signal transmission (or routing) is mentioned in the above description, this relates to the corresponding structural and functional aspects as well. For example, when a signal transmission from one analog function to another is described, this includes both the structural connection by signal lines, switches, etc., and the functional operation including driving the analog functions involved, switching the required paths, etc.

[0139] A method for designing an analog circuit will now be described.

[0140] Essentially, a design method according to the present disclosure is any method or process of designing an analog circuit such that a structure or configuration is obtained that corresponds to, for example, a structure or configuration as shown in any of Figures 5-11. Such a design method may also be considered as a method or process of designing an analog circuit such that a desired or intended objective is achieved, for example such that a particular mathematical problem is solved or a mathematical task is implemented on an analog computer.

[0141] 12 is a flow chart illustrating an example of a method for designing an analog circuit according to an embodiment. The resulting analog circuit may have a structure or configuration such as that shown in any of FIGS.

[0142] As shown in Fig. 10, a design method according to an embodiment comprises the steps of dividing a plurality of analog functions into groups, i.e. grouping the plurality of analog functions, and providing an interconnect structure configured to interconnect the plurality of analog functions. The interconnect structure has at least two hierarchical levels of interconnection, i.e. a local bus hierarchical level and a global bus hierarchical level. The local bus hierarchical level is configured to interconnect, in each group, the analog functions of the group. In other words, in each group, it allows local routing of signals between the analog functions of the group. The global bus hierarchical level interconnects the analog functions between the groups. In other words, it allows global routing of signals between the analog functions between the groups, as already described. In other words, corresponding signal lines, connections and / or switches may be provided so that a current input or a current output of an analog function can be connected to a corresponding current signal line and / or a voltage input or a voltage output of an analog function can be connected to a corresponding voltage signal line.

[0143] In the dividing or grouping step, a set of required analog functions can be determined or set, i.e. a number of analog functions to be implemented can be determined (e.g. taking into account the mathematical problem to be solved).

[0144] Also, in the dividing or grouping step, the plurality of analog functions (or groups of analog functions) may additionally be divided into sets or clusters, and the interconnect structure providing step may provide an interconnect structure having at least one further hierarchical level as described above, including at least one intermediate bus hierarchical level configured to interconnect the sets of analog functions of some of the groups included in the plurality of groups (in other words, allowing intermediate (level) routing of signals).

[0145] 13 is a flow chart illustrating an example of a method for designing an analog circuit according to an embodiment. The resulting analog circuit may have a structure or configuration with two hierarchical levels of interconnection, such as shown in any one of FIGS. 5-9.

[0146] As shown in FIG. 13, a design method according to an embodiment comprises a first step in which the mathematical problem / task is decomposed, i.e. the system of equations is sorted. Here, the mathematical problem or task is decomposed in such a way that as many interconnections as possible are made within a group of analog functions and fewer interconnections are made between different groups. This effectively results in an optimized (e.g. maximized) grouping in terms of number or length of signal lines and / or routing requirements. In a second step, the inputs and outputs of the analog functions of the group are connected to the respective local buses as voltage signals (or current signals in the case shown in FIG. 7) if necessary. If the fan-in at one point, i.e. one or more analog functions, is not sufficient, in a third step one or more additional voltage-to-current and / or current-to-voltage converters are used and implemented within said group. In a fourth step, the outputs of any voltage-to-current converters and the outputs of analog functions only available as currents are routed as current signals through the global buses. In some embodiments, such as that shown in FIG. 8, in a fourth step, the outputs of any current-to-voltage converters and the outputs of analog functions that are only available as voltages are routed as voltage signals over the global bus.

[0147] A similar method for designing an analog circuit according to an embodiment also applies to analog circuits having structures or configurations with three or more hierarchical levels of interconnects, for example as shown in any one of Figures 10 and 11.

[0148] Various examples and embodiments have been disclosed for implementing analog circuits (and methods of operating and / or designing analog circuits) that provide efficient interconnection or signal transmission (or routing) between multiple analog functions. The disclosed examples and embodiments are intended to be illustrative and not limiting of the present disclosure.

[0149] Additionally, the present disclosure is directed to all possible combinations of the above described components or functional elements so long as the concepts of the above described methods and configurations are applicable.

[0150] As is evident from the above description, various examples and embodiments of the present disclosure present techniques that allow efficient interconnection of analog functions in analog circuits, such as analog computers. The interconnections are organized hierarchically. At a first or lower hierarchical level, voltages (preferably) are used for signaling, i.e., local routing, and at a second or higher hierarchical level, currents (preferably) are used for signaling, i.e., global routing, to interconnect the analog functions. This approach can enhance or optimize the advantages of signaling by voltage or current, respectively, avoid or at least reduce the respective limitations of fan-in and / or fan-out, and generally minimize the interconnection effort and thus space consumption.

[0151] In view of the above, an analog circuit is provided, comprising a plurality of analog functions divided into at least two groups, and an interconnect structure configured to interconnect the plurality of analog functions to enable transmission of both voltage and current signals between analog functions in the plurality of analog functions, the interconnect structure having at least two hierarchical levels of interconnection, a local bus hierarchical level configured to interconnect the analog functions of each group, and a global bus hierarchical level configured to interconnect the analog functions of the plurality of groups, the local bus hierarchical level having voltage signal lines for transmitting voltage signals and / or current signal lines for transmitting current signals, and the global bus hierarchical level having voltage signal lines for transmitting voltage signals and / or current signal lines for transmitting current signals.

[0152] Although the present disclosure has been described with reference to the embodiments illustrated in the accompanying drawings, the present disclosure is not limited to these embodiments, and it will be apparent to those skilled in the art that the disclosed embodiments can be modified in many ways without departing from the inventive concept disclosed.

Claims

1. A plurality of analog functions divided into at least two groups; an interconnect structure configured to interconnect the plurality of analog functions to enable transmission of both voltage and current signals between analog functions included in the plurality of analog functions; Equipped with the interconnect structure having at least two hierarchical levels of interconnection, a local bus hierarchical level configured to interconnect groups of analog functions and a global bus hierarchical level configured to interconnect multiple groups of analog functions; the local bus hierarchy level having voltage signal lines for transmitting voltage signals and / or current signal lines for transmitting current signals; the global bus hierarchy level having voltage signal lines for transmitting voltage signals and / or current signal lines for transmitting current signals; An analog circuit, At least one group includes a plurality of voltage-to-current converters as analog functions, the plurality of voltage-to-current converters including: and / or configured to extend the fan-in properties of the analog function in that the current outputs of at least two voltage-to-current converters, each having a voltage input connected to a different voltage signal line, are connected to a current signal line that is connected to a current input of the analog function; configured to enhance the fan-out characteristics of the analog function in that a voltage output of the analog function is connected to one voltage signal line which is connected to both voltage inputs of at least two voltage-to-current converters, and a current output of each of the at least two voltage-to-current converters is connected to a separate current signal line; Analog circuitry.

2. A plurality of analog functions divided into at least two groups; an interconnect structure configured to interconnect the plurality of analog functions to enable transmission of both voltage and current signals between analog functions included in the plurality of analog functions; Equipped with the interconnect structure having at least two hierarchical levels of interconnection, a local bus hierarchical level configured to interconnect groups of analog functions and a global bus hierarchical level configured to interconnect multiple groups of analog functions; the local bus hierarchy level having voltage signal lines for transmitting voltage signals and / or current signal lines for transmitting current signals; the global bus hierarchy level having voltage signal lines for transmitting voltage signals and / or current signal lines for transmitting current signals; An analog circuit, An analog circuit, wherein at least one group has one or more voltage-to-current converters as analog functions, the converters being configured to extend signal bandwidth and / or reduce the effects of parasitic resistance in signal transmission in that one or more voltage signals are converted to one or more current signals, and the one or more current signals are transmitted between the analog functions of different groups via at least one global bus.

3. A plurality of analog functions divided into at least two groups; an interconnect structure configured to interconnect the plurality of analog functions to enable transmission of both voltage and current signals between analog functions included in the plurality of analog functions; Equipped with the interconnect structure having at least two hierarchical levels of interconnection, a local bus hierarchical level configured to interconnect groups of analog functions and a global bus hierarchical level configured to interconnect multiple groups of analog functions; the local bus hierarchy level having voltage signal lines for transmitting voltage signals and / or current signal lines for transmitting current signals; the global bus hierarchy level having voltage signal lines for transmitting voltage signals and / or current signal lines for transmitting current signals; An analog circuit, At least one group has a voltage-to-current converter as an analog function, the voltage-to-current converter comprising: and / or is configured to compensate for gain and / or offset errors of an analog function in that one or more adjustable resistors, such as one or more potentiometers, of the voltage-to-current converter are adjusted to calibrate the output signal of the analog function; and / or a calibrated current signal and a sign-inverted version of the calibrated current signal are transmitted to a current input of an analog function, the output signal of which is adjusted to zero in order to compensate for parasitic resistances at a voltage input of the analog function; Analog circuitry.

4. the local bus hierarchy level having at least one local bus for each group, the local bus being configured to interconnect a plurality of analog functions of a corresponding group; the global bus hierarchy level having at least one global bus configured to interconnect the multiple groups of analog functions; 4. An analog circuit according to claim 1.

5. 5. The analog circuit of claim 4, wherein the at least one local bus of each group has a voltage signal line for transmitting a voltage signal, and the at least one global bus has a current signal line for transmitting a current signal.

6. 6. The analog circuit of claim 5, wherein the at least one local bus for at least one group has current signal lines for transmitting current signals and / or the at least one global bus has voltage signal lines for transmitting voltage signals.

7. 5. An analog circuit as claimed in claim 4, wherein each analog function is connected to the local bus of the group of analog functions and / or to the at least one global bus.

8. The current input or current output of the analog function is connected to a current signal line, and / or The voltage input or voltage output of the analog function is connected to a voltage signal line, and / or a first analog function connected to a voltage signal line in a group and a second analog function connected to a current signal line in the group are interconnected via a voltage-to-current converter or a current-to-voltage converter as a third analog function in the group; 4. An analog circuit according to claim 1.

9. The local bus hierarchy level includes, for at least one group: a first local bus configured to interconnect a set of analog functions of the group; a second local bus configured to interconnect another set of analog functions of the group; Equipped with 4. The analog circuit according to claim 1, wherein the first local bus has a voltage signal line for transmitting a voltage signal, and the second local bus has a current signal line for transmitting a current signal.

10. 4. The analog circuit of claim 1, wherein the interconnect structure has at least further hierarchical levels of interconnection, at least one intermediate bus hierarchical level configured to interconnect analog functions of a set of groups in the plurality of groups, the at least one intermediate bus hierarchical level having voltage signal lines for transmitting voltage signals and / or current signal lines for transmitting current signals.

11. Each set of groups includes several groups that are adjacent or proximate to one another; the at least one intermediate bus hierarchy level having at least one intermediate bus for a set of groups, the intermediate bus being configured to interconnect analog functions of the set; 11. The analog circuit of claim 10.

12. the at least one intermediate bus hierarchical level having at least a first intermediate bus for a first group set and a second intermediate bus for a second group set, the first group set including a smaller number of groups and / or groups that are adjacent or closely located to each other compared to the second group set; the first intermediate bus has a voltage signal line for transmitting a voltage signal, and the second intermediate bus has a current signal line for transmitting a current signal.

11. The analog circuit of claim 10.

13. the plurality of analog functions are divided into groups such that the number of links between the analog functions within a group is optimized, the plurality of analog functions constituting a mathematical problem to be solved by the analog circuit; and / or Any of the analog functions may be or include an integrator, an adder, a multiplier, a voltage-to-current converter, a comparator, an exponential function, a logarithmic function, a configurable arbitrary waveform function generator, a current-to-voltage converter, and / or any of the plurality of analog functions having functional elements configured to implement the respective function without including fan-in and / or fan-out circuitry; 13. An analog circuit according to any one of claims 1 to 12.

14. The analog circuit is, is incorporated in, or is dedicated to, one of an analog computer, an analog arithmetic circuit, an analog filter, or an analog signal conditioner; or the analog circuit is, is integrated into, or is dedicated to one of a hybrid computer, a hybrid arithmetic circuit, a hybrid filter, or a hybrid signal conditioner; and / or The analog circuit is implemented as an integrated circuit, such as a system-on-chip integrated circuit, a microchip, a microprocessor, or a discrete circuit.

13. An analog circuit according to any one of claims 1 to 12.

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