Multilayer Ceramic Capacitors

Abstract

This multilayer ceramic capacitor includes: a laminate including an active portion formed by laminating a dielectric layer and an internal electrode layer, and a first covered portion and a second covered portion respectively positioned at both ends of the active portion in the lamination direction, the laminate having a first surface and a second surface, a first end surface and a second end surface, and a first side surface and a second side surface; and an external electrode. The first covered portion includes a first dummy electrode and a second dummy electrode, and the second covered portion includes a third dummy electrode and a fourth dummy electrode. The first dummy electrode and the third dummy electrode are exposed to the first end surface, the second dummy electrode and the fourth dummy electrode are exposed to the second end surface, and at least one among the first to fourth dummy electrodes is thicker than the internal electrode layer.

Description

[Technical field]

[0001] The present disclosure relates to a multilayer ceramic capacitor. [Background technology]

[0002] A conventional technique for multilayer ceramic capacitors is described in, for example, Patent Document 1. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2014-212298 A Summary of the Invention

[0004] The multilayer ceramic capacitor of the present disclosure is a substantially rectangular parallelepiped laminate including an active section formed by alternately stacking dielectric layers and internal electrode layers, and a first covering section and a second covering section respectively located at both ends of the active section in a stacking direction of the dielectric layers and the internal electrode layers, the laminate having a first face and a second face opposing each other in the stacking direction, a first end face and a second end face opposing each other, and a first side face and a second side face opposing each other; a first external electrode located from the first end face to the first face, the second face, the first side face, and the second side face; a second external electrode located from the second end surface to the first surface, the second surface, the first side surface, and the second side surface, the first external electrode and the second external electrode are connected to different internal electrode layers of the internal electrode layer; the first covering portion has a first dielectric portion, and a first dummy electrode and a second dummy electrode located at both ends of the first dielectric portion in a first direction orthogonal to the first end face, the second covering portion has a second dielectric portion, and a third dummy electrode and a fourth dummy electrode located at both ends of the second dielectric portion in the first direction, the first dummy electrode and the third dummy electrode are exposed at the first end surface, and the second dummy electrode and the fourth dummy electrode are exposed at the second end surface, At least one of the first dummy electrode, the second dummy electrode, the third dummy electrode and the fourth dummy electrode is thicker than the internal electrode layer. [Brief description of the drawings]

[0005] The objects, features, and advantages of the present disclosure will become more apparent from the following detailed description and drawings. [Figure 1] 1 is a perspective view showing a multilayer ceramic capacitor according to an embodiment of the present invention. [Diagram 2] 2 is a perspective view showing a laminate of the multilayer ceramic capacitor of FIG. 1. [Diagram 3] FIG. 2 is a cross-sectional view taken along the line III-III in FIG. [Figure 4] FIG. 4 is a cross-sectional view taken along the line IV-IV in FIG. [Diagram 5] 1 is a cross-sectional view showing a multilayer ceramic capacitor according to an embodiment of the present invention. [Figure 6] FIG. 4 is a cross-sectional view showing another example of the multilayer ceramic capacitor according to the present embodiment. [Figure 7] FIG. 4 is a cross-sectional view showing another example of the multilayer ceramic capacitor according to the present embodiment. [Figure 8] FIG. 4 is a cross-sectional view showing another example of the multilayer ceramic capacitor according to the present embodiment. [Figure 9] FIG. 2 is a perspective view illustrating an example of a process for producing a base laminate. [Figure 10] FIG. 2 is a perspective view showing an example of a base laminate. [Figure 11] FIG. 2 is a perspective view showing an example of a laminate obtained by cutting a base laminate. [Figure 12] FIG. 11 is a perspective view illustrating another example of the process for producing the base laminate. [Figure 13] FIG. 11 is a perspective view showing another example of the base laminate. [Figure 14] FIG. 4 is a perspective view showing another example of a laminate obtained by cutting the base laminate. [Figure 15] FIG. 11 is a perspective view showing a multilayer ceramic capacitor according to another embodiment. [Figure 16] 16 is a perspective view showing a laminate of the multilayer ceramic capacitor of FIG. 15. [Figure 17] 17 is a cross-sectional view taken along the line XVII-XVII in FIG. 15. [Figure 18A] 18 is a cross-sectional view taken along the cutting line XVIIIA-XVIIIA in FIG. 17. [Figure 18B] 18 is a cross-sectional view taken along the cutting line XVIIIB-XVIIIB in FIG. 17. [Figure 19] FIG. 13 is a perspective view showing a multilayer ceramic capacitor according to still another embodiment. [Figure 20] 20 is a perspective view showing a laminate of the multilayer ceramic capacitor of FIG. 19. [Figure 21] 20 is a cross-sectional view taken along the line XXI-XXI in FIG. 19. [Figure 22A] FIG. 22 is a cross-sectional view taken along the line XXIIA-XXIIA in FIG. 21. [Figure 22B] 22 is a cross-sectional view taken along the line XXIIB-XXIIB in FIG. 21. [Diagram 23] FIG. 13 is a perspective view showing a multilayer ceramic capacitor according to still another embodiment. [Figure 24] FIG. 24 is a perspective view showing a laminate of the multilayer ceramic capacitor of FIG. 23. [Diagram 25] 25 is a cross-sectional view taken along the line XXV-XXV in FIG. 23. [Figure 26A] 26 is a cross-sectional view taken along the line XXVIA-XXVIA in FIG. 25. [Figure 26B] 26 is a cross-sectional view taken along the cutting line XXVIB-XXVIB of FIG. 25. [Figure 26C] 26 is a cross-sectional view taken along the line XXVIC-XXVIC of FIG. 25. [Figure 26D] 26 is a cross-sectional view taken along the cutting line XXVID-XXVID in FIG. 25. [Figure 27]FIG. 11 is a cross-sectional view showing a multilayer ceramic capacitor according to still another embodiment. [Figure 28] FIG. 11 is a cross-sectional view showing a multilayer ceramic capacitor according to still another embodiment. [Figure 29] FIG. 11 is a perspective view showing a laminate of a multilayer ceramic capacitor according to still another embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0006] A multilayer ceramic capacitor includes a laminate in which dielectric layers and internal electrode layers are alternately stacked, and external electrodes formed on the surface of the laminate and connected to the internal electrode layers. By using a plating film as the external electrode, the multilayer ceramic capacitor can be made smaller. However, the bonding strength between the laminate and the plating film is weak, and the plating film may peel off. The aforementioned Patent Document 1 discloses that the laminate is provided with multiple dummy electrode layers that are bonded to the plating film in order to increase the bonding strength between the laminate and the plating film.

[0007] The manufacturing process of a multilayer ceramic capacitor according to the prior art includes a process of firing an unfired laminate and then barrel polishing the laminate to fully expose the internal electrode layers on the surface of the laminate. The multilayer ceramic capacitor described in Patent Document 1 has many interfaces between the dielectric layers and the dummy electrode layers at the corners of the laminate, so that when the impact force between the polishing medium and other laminates applied to the corners of the laminate becomes excessive, delamination between the dielectric layers and the dummy electrode layers may occur. As a result, the reliability of the multilayer ceramic capacitor may be deteriorated.

[0008] Hereinafter, an embodiment of the multilayer ceramic capacitor of the present disclosure will be described with reference to the drawings. The drawings used in the following description are schematic, and the dimensional ratios and the like in the drawings do not necessarily correspond to the actual ones. In the multilayer ceramic electronic component according to the embodiment, any direction may be considered to be the upper or lower direction, but in this specification, for convenience, a Cartesian coordinate system xyz is defined in some drawings. In the following description, the positive side in the z-axis direction is considered to be the upper side, and terms such as the upper surface and the lower surface may be used. The x-axis direction is also referred to as the first direction or the length direction. The y-axis direction is also referred to as the second direction or the width direction. The z-axis direction is also referred to as the third direction, the height direction, or the stacking direction.

[0009] Fig. 1 is a perspective view showing a multilayer ceramic capacitor of this embodiment, and Fig. 2 is a perspective view showing a laminate of the multilayer ceramic capacitor of Fig. 1. Fig. 3 is a cross-sectional view taken along the line III-III in Fig. 1, and Fig. 4 is a cross-sectional view taken along the line IV-IV in Fig. 3. In Fig. 2, for ease of illustration, the internal electrode layers and the first to fourth dummy electrodes are shown hatched in their exposed portions on the surface of the laminate.

[0010] 1, the multilayer ceramic capacitor 1 of this embodiment includes a laminate 2, a first external electrode 10a, and a second external electrode 10b. Hereinafter, the first external electrode 10a and the second external electrode 10b may be collectively referred to as the external electrodes 10a, 10b.

[0011] As shown in FIG. 2, the laminate 2 is substantially rectangular. The laminate 2 has a first surface 7a and a second surface 7b facing each other, a first end surface 8a and a second end surface 8b facing each other, and a first side surface 9a and a second side surface 9b facing each other. The first end surface 8a and the second end surface 8b may be perpendicular to a first direction (x-axis direction). The first side surface 9a and the second side surface 9b may be perpendicular to a second direction (y-axis direction). The first surface 7a and the second surface 7b may be perpendicular to a third direction (z-axis direction). Hereinafter, the first surface 7a and the second surface 7b may be collectively referred to as the main surfaces 7a and 7b, the first end surface 8a and the second end surface 8b may be collectively referred to as the end surfaces 8a and 8b, and the first side surface 9a and the second side surface 9b may be collectively referred to as the side surfaces 9a and 9b.

[0012] The laminate 2 includes an active portion 3, a first covering portion 61, and a second covering portion 62. As shown in FIG. 3, the active portion 3 is configured by alternately stacking dielectric layers 4 and internal electrode layers 5. The dielectric layers 4 and the internal electrode layers 5 are stacked in the third direction (z-axis direction). The active portion 3 forms a capacitance. In FIG. 3, the boundaries between the active portion 3 and each of the first covering portion 61 and the second covering portion 62 are shown by two-dot chain lines, but the actual boundaries are not clearly visible.

[0013] The dielectric layer 4 is made of a dielectric material. The dielectric layer 4 may be made of a ceramic material containing, for example, barium titanate (BaTiO3), calcium titanate (CaTiO3), strontium titanate (SrTiO3), barium zirconate (BaZrO3), or the like as a main component. The dielectric layer 4 may have a thickness of, for example, 0.1 μm or more and 10 μm or less. In this specification, the term "main component" refers to the component that is contained in the highest proportion in the material or member of interest.

[0014] The internal electrode layer 5 is made of a conductive material. The internal electrode layer 5 may be made of a metal material mainly composed of metals such as Ni (nickel), Cu (copper), Sn (tin), Pt (platinum), Pd (palladium), Ag (silver), Au (gold), etc., or alloys thereof. The internal electrode layer 5 may have a thickness of, for example, 1.5 μm or less. In this case, internal defects caused by internal stress during firing of the laminate 2 or during application of voltage can be suppressed, and the reliability of the multilayer ceramic capacitor 1 can be improved.

[0015] The internal electrode layer 5 includes a first internal electrode layer 5a and a second internal electrode layer 5b having mutually opposite polarities. The active section 3 is configured by alternately laminating the first internal electrode layer 5a and the second internal electrode layer 5b with the dielectric layer 4 interposed therebetween.

[0016] As shown in FIG. 4, the first internal electrode layer 5a has a capacitance forming portion 5aa and a lead portion 5ab. The lead portion 5ab is exposed to the first end face 8a and the side faces 9a and 9b. It can also be said that the lead portion 5ab constitutes a part of the first end face 8a and the side faces 9a and 9b. As shown in FIG. 4, the second internal electrode layer 5b has a capacitance forming portion 5ba and a lead portion 5bb. The lead portion 5bb is exposed to the second end face 8b and the side faces 9a and 9b. It can also be said that the lead portion 5bb constitutes a part of the second end face 8b and the side faces 9a and 9b. The capacitance forming portion 5aa and the capacitance forming portion 5ba overlap each other in a plan view (i.e., when viewed from the third direction).

[0017] 3, the first covering portion 61 and the second covering portion 62 are located at both ends of the active portion 3 in the third direction (z-axis direction). Hereinafter, the first covering portion 61 and the second covering portion 62 may be collectively referred to as covering portions 61, 62.

[0018] The first covering portion 61 includes a first dummy electrode 61a, a second dummy electrode 61b, and a first dielectric portion 61c. The first dummy electrode 61a and the second dummy electrode 61b are located at both ends of the first dielectric portion 61c in the first direction (x-axis direction).

[0019] The first dummy electrode 61a is exposed at the first end surface 8a as shown in FIG. 3. It can be said that the first dummy electrode 61a constitutes a part of the first end surface 8a. The first dummy electrode 61a may have the same shape as the lead portion 5ab of the first internal electrode layer 5a in a plan view, or may have a different shape from the lead portion 5ab. The first dummy electrode 61a may be longer than the lead portion 5ab in the first direction (x-axis direction), or may be shorter than the lead portion 5ab. The second dummy electrode 61b is exposed at the second end surface 8b as shown in FIG. 3. It can be said that the second dummy electrode 61b constitutes a part of the second end surface 8b. The second dummy electrode 61b may have the same shape as the lead portion 5bb of the second internal electrode layer 5b in a plan view, or may have a different shape from the lead portion 5bb. The second dummy electrode 61b may be longer or shorter than the lead-out portion 5bb in the first direction.

[0020] The first dielectric portion 61c is made of a dielectric material and electrically insulates the first dummy electrode 61a from the second dummy electrode 61b. The first dielectric portion 61c may be made of the ceramic material that constitutes the dielectric layer 4.

[0021] The second covering portion 62 includes a third dummy electrode 62a, a fourth dummy electrode 62b, and a second dielectric portion 62c. The third dummy electrode 62a and the fourth dummy electrode 62b are located at both ends of the second dielectric portion 62c in the first direction (X-axis direction). Hereinafter, the first dielectric portion 61c and the second dielectric portion 62c may be collectively referred to as dielectric portions 61c, 62c.

[0022] The third dummy electrode 62a is exposed at the first end surface 8a as shown in FIGS. 2 and 3. It can be said that the third dummy electrode 62a constitutes a part of the first end surface 8a. The third dummy electrode 62a may have the same shape as the lead portion 5ab of the first internal electrode layer 5a in a plan view, or may have a different shape from the lead portion 5ab. The third dummy electrode 62a may be longer than the lead portion 5ab in the first direction (x-axis direction), or may be shorter than the lead portion 5ab. The fourth dummy electrode 62b is exposed at the second end surface 8b as shown in FIG. 3. It can be said that the fourth dummy electrode 62b constitutes a part of the second end surface 8b. The fourth dummy electrode 62b may have the same shape as the lead portion 5bb of the second internal electrode layer 5b in a plan view, or may have a different shape from the lead portion 5bb. The fourth dummy electrode 62b may be longer or shorter than the lead-out portion 5bb in the first direction.

[0023] The second dielectric portion 62c is made of a dielectric material and electrically insulates the third dummy electrode 62a from the fourth dummy electrode 62b. The second dielectric portion 62c may be made of the ceramic material that constitutes the dielectric layer 4.

[0024] Hereinafter, the first dummy electrode 61a, the second dummy electrode 61b, the third dummy electrode 62a and the fourth dummy electrode 62b may be collectively referred to as dummy electrodes 61a to 62b.

[0025] At least one of the dummy electrodes 61a-62b has a thickness in the third direction (z-axis direction) greater than that of one internal electrode layer 5, as shown in Figures 2 and 3. The thickness of the dummy electrodes 61a-62b may be three times or more, five times or more, or ten times or more, the thickness of one internal electrode layer 5. The dummy electrodes 61a-62b may have approximately the same dimensions as each other. In the following, unless otherwise specified, it is assumed that all of the dummy electrodes 61a-62b have a thickness in the third direction greater than that of the internal electrode layer 5, as shown in Figures 2 and 3.

[0026] The first external electrode 10a is located from the first end face 8a to the first face 7a, the second face 7b, the first side face 9a, and the second side face 9b. The first external electrode 10a is connected to a portion of the lead portion 5ab exposed on the surface of the laminate 2. The first external electrode 10a may completely cover the exposed portion of the lead portion 5ab. In this case, the first internal electrode layer 5a and the first external electrode 10a can be electrically connected well, and the active portion 3 can be protected from the external environment (e.g., moisture, etc.). The first external electrode 10a is connected to a portion of the first dummy electrode 61a and the third dummy electrode 62a exposed on the surface of the laminate 2. The first external electrode 10a may completely cover the exposed portions of the first dummy electrode 61a and the third dummy electrode 62a. In this case, the contact area between the laminate 2 and the first external electrode 10a can be increased, and the bonding strength between the laminate 2 and the first external electrode 10a can be improved.

[0027] The second external electrode 10b is located from the second end face 8b to the first face 7a, the second face 7b, the first side face 9a, and the second side face 9b. The second external electrode 10b is connected to a portion of the lead portion 5bb that is exposed on the surface of the laminate 2. The second external electrode 10b may completely cover the exposed portion of the lead portion 5bb. In this case, the second internal electrode layer 5b and the second external electrode 10b can be electrically connected well, and the active portion 3 can be protected from the external environment (e.g., moisture, etc.). The second external electrode 10b is connected to a portion of the second dummy electrode 61b and the fourth dummy electrode 62b that is exposed on the surface of the laminate 2. The second external electrode 10b may completely cover the exposed portions of the second dummy electrode 61b and the fourth dummy electrode 62b. In this case, the contact area between the laminate 2 and the second external electrode 10b can be increased, and the bonding strength between the laminate 2 and the second external electrode 10b can be improved.

[0028] As shown in FIGS. 3 and 4, the external electrodes 10a and 10b may include a first layer 11 in contact with the surface of the laminate 2 and a second layer 12 covering the first layer 11. The first layer 11 is also called an underlayer. The second layer 12 is also called an outer layer. By forming the external electrodes 10a and 10b into a multi-layer structure, it is possible to increase the bonding strength between the underlayer 11 and the laminate 2 and improve the wettability of the conductive bonding material (e.g., solder) to the outer layer 12. As a result, it is possible to improve the reliability of the multilayer ceramic capacitor 1 and the reliability of a mounting structure including the multilayer ceramic capacitor 1.

[0029] The underlayer 11 may be made of a metal material mainly composed of a metal such as Ni, Cu, Sn, Pt, Pd, Ag, or Au, or an alloy thereof. The underlayer 11 may be formed by using a thin film forming technique such as plating, sputtering, or vapor deposition. In this case, the volume of the underlayer 11 can be reduced, so that the multilayer ceramic capacitor 1 can be made smaller and the effective volume contributing to the capacitance can be increased. The technique for forming the underlayer 11 is not limited to a thin film forming technique. The underlayer 11 may be formed by using a thick film forming technique such as dipping, screen printing, or gravure printing. As shown in FIGS. 3 and 4, the underlayer 11 may completely cover the exposed portions of the lead portions 5ab and 5bb and the dummy electrodes 61a to 62b.

[0030] The outer layer 12 may be composed of a metal material mainly composed of a metal such as Ni, Cu, Sn, Pt, Pd, Ag, Au, or an alloy thereof. The outer layer 12 may be formed using a thin film formation technique such as an electroless plating method or an electrolytic plating method. As shown in Figs. 3 and 4, the outer layer 12 may completely cover (the surface of) the base layer 11. The outer layer 12 may extend to the center side of the laminate 2 beyond the end of the base layer 11 on the center side of the laminate 2. In other words, the inner end 10t of the external electrodes 10a and 10b on the center side of the laminate 2 may be composed of only the outer layer 12.

[0031] The multilayer ceramic capacitor 1 of this embodiment has a configuration in which dummy electrodes 61a-62b thicker than the internal electrode layers 5 are exposed at the end faces 8a, 8b, and the external electrodes 10a, 10b are connected to the exposed portions of the dummy electrodes 61a-62b. This increases the bonding strength between the laminate 2 and the external electrodes 10a, 10b, thereby improving the reliability of the multilayer ceramic capacitor 1.

[0032] In the conventional multilayer ceramic capacitor, the covering portion (corresponding to the covering portions 61 and 62) includes a dummy electrode portion formed by alternately laminating a plurality of dielectric layers and a plurality of dummy electrode layers. Compared to the conventional multilayer ceramic capacitor, the multilayer ceramic capacitor 1 of this embodiment has fewer interfaces of different materials in the covering portions 61 and 62, so that it is possible to reduce the occurrence of delamination in the covering portions 61 and 62 when the laminate 2 is (barrel) polished. Therefore, it is possible to improve the reliability of the multilayer ceramic capacitor 1.

[0033] Furthermore, according to the multilayer ceramic capacitor 1, the area of ​​the exposed portions of the dummy electrodes 61a-62b on the end faces 8a, 8b can be increased without increasing the number of interfaces between different materials in the covering portions 61, 62. Therefore, the reliability of the multilayer ceramic capacitor 1 can be effectively improved.

[0034] The first dummy electrode 61a and the second dummy electrode 61b may be further exposed on the first surface 7a, and the third dummy electrode 62a and the fourth dummy electrode 62b may be further exposed on the second surface 7b. In other words, the first dummy electrode 61a and the second dummy electrode 61b may form a part of the first surface 7a, and the third dummy electrode 62a and the fourth dummy electrode 62b may form a part of the second surface 7b. Since the first external electrode 10a is located from the first end surface 8a to the main surfaces 7a and 7b, and the second external electrode 10b is located from the second end surface 8b to the main surfaces 7a and 7b, the contact area between the dummy electrodes 61a to 62b and the external electrodes 10a and 10b can be increased by exposing the dummy electrodes 61a to 62b to the main surfaces 7a and 7b. As a result, the bonding strength between the laminate 2 and the external electrodes 10a, 10b can be further increased, and the reliability of the multilayer ceramic capacitor 1 can be further improved.

[0035] The upper surfaces of the first dummy electrode 61a and the second dummy electrode 61b may be flush with the upper surface of the first dielectric portion 61c, and the lower surfaces of the third dummy electrode 62a and the fourth dummy electrode 62b may be flush with the lower surface of the second dielectric portion 62c. In this case, in the manufacturing process of the multilayer ceramic capacitor 1, the thicknesses of the external electrodes 10a, 10b on the main surfaces 7a, 7b can be easily and accurately controlled, making it easier to manufacture the multilayer ceramic capacitor 1 with the designed dimensions.

[0036] The upper surfaces of the first dummy electrode 61a and the second dummy electrode 61b may protrude slightly upward from the upper surface of the first dielectric portion 61c, and the lower surfaces of the third dummy electrode 62a and the fourth dummy electrode 62b may protrude slightly downward from the lower surface of the second dielectric portion 62c. In this case, by forming the external electrodes 10a, 10b so as to wrap around the ends of the dummy electrodes 61a to 62b on the center side of the laminate 2, the contact area between the laminate 2 and the external electrodes 10a, 10b is increased, and the laminate 2 and the external electrodes 10a, 10b are less likely to peel off from each other. As a result, the reliability of the multilayer ceramic capacitor 1 can be improved.

[0037] The dummy electrodes 61a to 62b may be further exposed on the first side surface 9a and the second side surface 9b. In other words, the dummy electrodes 61a to 62b may constitute a part of the first side surface 9a and the second side surface 9b. Since the first external electrode 10a is located from the first end surface 8a to the side surfaces 9a and 9b, and the second external electrode 10b is located from the second end surface 8b to the side surfaces 9a and 9b, the dummy electrodes 61a to 62b are exposed on the side surfaces 9a and 9b, so that the dummy electrodes 61a to 62b As a result, the bonding strength between the laminate 2 and the external electrodes 10a, 10b can be further increased, and the reliability of the multilayer ceramic capacitor 1 can be further improved.

[0038] The side surfaces of the first dummy electrode 61a and the second dummy electrode 61b may be flush with the side surfaces of the first dielectric portion 61c, and the side surfaces of the third dummy electrode 62a and the fourth dummy electrode 62b may be flush with the side surfaces of the second dielectric portion 62c. In this case, in the manufacturing process of the multilayer ceramic capacitor 1, the thicknesses of the external electrodes 10a, 10b on the side surfaces 9a, 9b can be easily and accurately controlled, making it easier to manufacture the multilayer ceramic capacitor 1 with the designed dimensions.

[0039] The side surfaces of the first dummy electrode 61a and the second dummy electrode 61b may slightly protrude from the side surface of the first dielectric portion 61c in the second direction (y-axis direction), and the side surfaces of the third dummy electrode 62a and the fourth dummy electrode 62b may slightly protrude from the side surface of the second dielectric portion 62c in the second direction. In other words, the side surface of the first dielectric portion 61c may be recessed from the side surfaces of the first dummy electrode 61a and the second dummy electrode 61b, and the side surface of the second dielectric portion 62c may be recessed from the side surfaces of the third dummy electrode 62a and the fourth dummy electrode 62b. In this case, by forming the external electrodes 10a and 10b so as to wrap around the end portions of the dummy electrodes 61a to 62b on the center side of the laminate 2, the contact area between the laminate 2 and the external electrodes 10a and 10b is increased, and the laminate 2 and the external electrodes 10a and 10b are less likely to peel off from each other. As a result, the reliability of the multilayer ceramic capacitor 1 can be improved.

[0040] The multilayer ceramic capacitor 1 of this embodiment may have a configuration in which at least one of the dummy electrodes 61a to 62b is thicker than the internal electrode layer 5. As shown in FIG. 5, the multilayer ceramic capacitor 1 may have a configuration in which the first dummy electrode 61a is thicker than the internal electrode layer 5, and the second dummy electrode 61b, the third dummy electrode 62a, and the fourth dummy electrode 62b are the same thickness as the internal electrode layer 5 or thinner than the internal electrode layer 5. Compared with the multilayer ceramic capacitor of the conventional technology, the multilayer ceramic capacitor 1 can reduce the number of interfaces of different materials in the coating parts 61 and 62, and therefore can reduce the occurrence of delamination in the coating parts 61 and 62 when the laminate 2 is barrel polished. Therefore, the reliability of the multilayer ceramic capacitor 1 can be improved.

[0041] The laminate 2 may have an auxiliary electrode portion 61ba located inside (below) the second dummy electrode 61b in the third direction (z-axis direction) and formed by alternately stacking dielectric layers 65 and electrode layers 66. In this case, it is possible to provide the first dummy electrode 61a and the second dummy electrode 61b without forming a step on the first surface 7a of the laminate 2. The electrode layer 66 may be exposed on the second end surface 8b and the side surfaces 9a, 9b. In this case, it is possible to increase the bonding strength between the laminate 2 and the second external electrode 10b. The electrode layer 66 may have the same shape as the second dummy electrode 61b in a plan view, or may have a different shape from the second dummy electrode 61b.

[0042] The laminate 2 may have an auxiliary electrode portion 62aa located inside (above) the third dummy electrode 62a in the third direction (z-axis direction), and an auxiliary electrode portion 62ba located inside (above) the fourth dummy electrode 62b in the third direction. The auxiliary electrode portions 62aa and 62ba may be configured by alternately stacking dielectric layers 65 and electrode layers 66, similar to the auxiliary electrode portion 61ba. The electrode layer 66 of the auxiliary electrode portion 62aa may be exposed to the first end face 8a and the side faces 9a and 9b, and the electrode layer 66 of the auxiliary electrode portion 62ba may be exposed to the second end face 8b and the side faces 9a and 9b. In this case, the bonding strength between the laminate 2 and the external electrodes 10a and 10b can be increased. The electrode layer 66 of the auxiliary electrode portion 62aa may have the same shape as the third dummy electrode 62a in a plan view, or may have a different shape from the third dummy electrode 62a. The electrode layer 66 of the auxiliary electrode portion 62ba may have the same shape as the fourth dummy electrode 62b in a plan view, or may have a shape different from that of the fourth dummy electrode 62b.

[0043] The multilayer ceramic capacitor 1 may be configured such that two of the dummy electrodes 61a to 62b are thicker than the internal electrode layers 5, or may be configured such that three of the dummy electrodes 61a to 62b are thicker than the internal electrode layers 5.

[0044] Next, another example of the multilayer ceramic capacitor according to this embodiment will be described. Figures 6 to 8 are cross-sectional views showing another example of the multilayer ceramic capacitor according to this embodiment. The cross-sectional views shown in Figures 6 to 8 correspond to the cross-sectional view shown in Figure 3.

[0045] As shown in FIG. 6, the dummy electrodes 61a to 62b may be formed by stacking a plurality of dummy electrode layers 63. The plurality of dummy electrode layers 63 may be stacked in the third direction (z-axis direction). In this case, the dummy electrodes 61a to 62b having a large thickness can be formed by stacking the thin dummy electrode layers 63. The small thickness of the dummy electrode layers 63 allows the dimensions of the dummy electrode layers 63 to be controlled with high precision. Therefore, compared with the case where one dummy electrode 61a to 62b is formed, the dimensions of the dummy electrodes 61a to 62b can be controlled with high precision. As a result, even if the multilayer ceramic capacitor 1 is small, the dummy electrodes 61a to 62b having the designed dimensions can be formed, and the reliability of the multilayer ceramic capacitor 1 can be improved. In FIG. 6, the boundaries between the dummy electrode layers 63 are indicated by two-dot chain lines, but the actual boundaries are not clearly visible. This is the same for FIGS. 7 and 8.

[0046] The thickness of the dummy electrode layer 63 may be approximately the same as that of the internal electrode layer 5. Although details will be described later, in the manufacturing process of the multilayer ceramic capacitor 1, the active part 3 of the unfired laminate 2 is produced by a printing method such as screen printing or gravure printing using ceramic slurry and conductive paste. Therefore, when the thickness of the dummy electrode layer 63 is approximately the same as that of the internal electrode layer 5, the dummy electrode layer 63 can be printed using the same printing method as that used for printing the internal electrode layer 5. As a result, it becomes possible to efficiently form the dummy electrodes 61a to 62b having the designed dimensions.

[0047] When the dummy electrodes 61a to 62b are configured by stacking a plurality of dummy electrode layers 63, the first dielectric portion 61c and the second dielectric portion 62c may be configured by stacking a plurality of dielectric layers 64. The thickness of the dielectric layer 64 may be substantially the same as that of the dummy electrode layer 63. In this case, the dielectric layer 64 can be printed using a printing method similar to that used for printing the dummy electrode layer 63. As a result, it is possible to efficiently form the covering portions 61 and 62 having the designed dimensions. In FIG. 6, the boundaries between the dielectric layers 64 are shown by two-dot chain lines, but the actual boundaries are not clearly visible. The same applies to FIGS. 7 and 8.

[0048] The dummy electrode layer 63 may include a common material 63a made of a dielectric material. In this case, the bonding strength between the dummy electrode layers 63 can be increased, and therefore the occurrence of delamination between the dummy electrodes 61a to 62b can be suppressed. The dummy electrode layer 63 may include a common material made of a ceramic material constituting the dielectric layer 4 and the dielectric layer 64. In this case, the bonding strength between the dummy electrode layers 63 can be increased while the bonding strength between the dummy electrodes 61a to 62b and the active portion 3 can be increased. Furthermore, the bonding strength between the first dummy electrode 61a and the second dummy electrode 61b and the first dielectric portion 61c can be increased, and the bonding strength between the third dummy electrode 62a and the fourth dummy electrode 62b and the first dielectric portion 61c can be increased. As a result, the occurrence of delamination in the laminate 2 can be suppressed, and the reliability of the multilayer ceramic capacitor 1 can be improved.

[0049] An interface 61d between at least one of the first dummy electrode 61a and the second dummy electrode 61b and the first dielectric portion 61c may have an uneven structure. The multilayer ceramic capacitor 1 is used, for example, by being solder-mounted (reflow solder-mounted) on an external board. When mounting the multilayer ceramic capacitor 1 on an external board, cracks are likely to occur in a region (hereinafter also referred to as a "facing region") 2f near the inner end portion 10t of the external electrodes 10a, 10b on (the first surface 7a of) the laminate 2 due to contraction of the external electrodes 10a, 10b during cooling after heating. By having the uneven structure on the interface 61d of the first covering portion 61, even if a crack occurs in the facing region 2f of the first covering portion 61, it is possible to suppress the crack from extending to the active portion 3. As a result, it is possible to increase the moisture resistance of the multilayer ceramic capacitor 1 and improve its reliability.

[0050] When the first dummy electrode 61a and the second dummy electrode 61b are composed of a plurality of dummy electrode layers 63, the uneven structure of the interface 61d may be formed by regularly or irregularly changing the positions of the ends of the plurality of dummy electrode layers 63 on the first dielectric portion 61c side in the first direction (x-axis direction) as shown in Fig. 7. When the first dummy electrode 61a and the second dummy electrode 61b are one piece, the uneven structure of the interface 61d may be formed, for example, by providing unevenness at the interface between the electrode pattern to become the first dummy electrode 61a and the second dummy electrode 61b and the dielectric pattern to become the first dielectric portion 61c in the process of producing the base laminate (see Figs. 9 and 12).

[0051] An interface 62d between at least one of the third dummy electrode 62a and the fourth dummy electrode 62b and the second dielectric portion 62c may have an uneven structure. The effect of the uneven structure of the interface 62d is similar to that of the uneven structure of the interface 61d, and the method of making the interface 62d an uneven structure is similar to the method of making the interface 61d an uneven structure, so detailed description will be omitted.

[0052] 3 and 6 to 8, the lower surfaces of the first dummy electrode 61a and the second dummy electrode 61b may be in contact with the upper surface of the active portion 3. The laminate 2 may be configured such that an interface 61e between the active portion 3 and each of the first dummy electrode 61a and the second dummy electrode 61b has an uneven structure. In this case, the active portion 3 is less likely to peel off from the first dummy electrode 61a and the second dummy electrode 61b, and as a result, the reliability of the multilayer ceramic capacitor 1 can be improved.

[0053] The lower surfaces of the first dummy electrode 61a and the second dummy electrode 61b may not be in contact with the upper surface of the active portion 3. The first covering portion 61 may include an intermediate layer (not shown) located between the active portion 3 and the first dummy electrode 61a and between the active portion 3 and the second dummy electrode 61b. The intermediate layer may be made of the dielectric material that constitutes the first dielectric portion 61c. The first covering portion 61 may be configured such that the interfaces between the intermediate layer and each of the first dummy electrode 61a and the second dummy electrode 61b have an uneven structure. In this case, peeling in the first covering portion 61 can be suppressed, and the reliability of the multilayer ceramic capacitor 1 can be improved.

[0054] The upper surfaces of the third dummy electrode 62a and the fourth dummy electrode 62b may be in contact with the lower surface of the active portion 3. The laminate 2 may be configured such that an interface 62e between the active portion 3 and each of the third dummy electrode 62a and the fourth dummy electrode 62b has an uneven structure. In this case, the active portion 3 is less likely to peel off from the third dummy electrode 62a and the fourth dummy electrode 62b, and as a result, the reliability of the multilayer ceramic capacitor 1 can be improved.

[0055] The upper surfaces of the third dummy electrode 62a and the fourth dummy electrode 62b may not be in contact with the lower surface of the active portion 3. The second covering portion 62 may include a second intermediate layer (not shown) located between the active portion 3 and the third dummy electrode 62a and between the active portion 3 and the fourth dummy electrode 62b. The intermediate layer may be made of the dielectric material that constitutes the second dielectric portion 62c. The second covering portion 62 may be configured such that the interfaces between the third dummy electrode 62a and the fourth dummy electrode 62b and the second intermediate layer have an uneven structure. In this case, peeling in the second covering portion 62 can be suppressed, and the reliability of the multilayer ceramic capacitor 1 can be improved.

[0056] Next, a description will be given of an example of a manufacturing method for the multilayer ceramic capacitor 1 (hereinafter also referred to as "first manufacturing method"). Fig. 9 is a perspective view illustrating an example of a manufacturing process of a base laminate, Fig. 10 is a perspective view showing an example of a base laminate, and Fig. 11 is a perspective view showing an example of a laminate obtained by cutting the base laminate.

[0057] First, a raw material powder containing a dielectric material such as BaTiO3, CaTiO3, SrTiO3, BaZrO3, or a mixture thereof as a main component is prepared as a material for the dielectric layer 4. Then, an organic vehicle is mixed with the prepared raw material powder to prepare a ceramic slurry. The organic vehicle used to prepare the ceramic slurry may be, for example, a resin such as a butyral resin dissolved in a solvent containing ethyl alcohol and toluene. Then, a ceramic green sheet (hereinafter also referred to as "green sheet") 13 to be the dielectric layer 4 is formed by a sheet forming method such as a doctor blade method or a die coater method using the prepared ceramic slurry. The average thickness of the green sheet 13 may be, for example, about 0.5 to 10 μm. The above-mentioned ceramic slurry may be used for the dielectric parts 61c and 62c.

[0058] Next, a conductive paste is prepared by mixing an organic vehicle with a powder mainly composed of a metal such as Ni, Cu, Sn, Pt, Pd, Ag, Au, or an alloy thereof as a material for the internal electrode layer 5. The organic vehicle used for preparing the conductive paste may be, for example, a resin such as ethyl cellulose dissolved in a solvent mixed with a dihydroterpineol-based solvent and butyl cellosolve. The dispersant may be, for example, oleic acid, polyethylene glycol, or the like. The above-mentioned conductive paste may be used for the dummy electrodes 61a to 62b.

[0059] Next, a conductive paste is used to print an electrode pattern 14, which will become the internal electrode layer 5, on the main surface of the green sheet 13 to form a pattern sheet 15 (see FIG. 9). The electrode pattern 14 can be printed by a printing method such as screen printing or gravure printing.

[0060] Next, a temporary laminate, which is a precursor of the base laminate, is prepared. First, a first cover sheet 17, which will become the covering parts 61, 62, is formed on a support sheet 16 by a printing method such as screen printing or gravure printing using a ceramic slurry and a conductive paste. The first cover sheet 17 is composed of an electrode pattern 18, which will become the dummy electrodes 61a to 62b, and a dielectric pattern 19, which will become the dielectric parts 61c, 62c. The first cover sheet 17 may be formed by printing multiple times, or may be formed by printing once. FIG. 9 shows a case where the first cover sheet 17 is formed by printing multiple times, that is, the dummy electrodes 61a to 62b are formed by stacking multiple dummy electrode layers 63, and the dielectric parts 61c, 62c are formed by stacking multiple dielectric layers 64. In FIG. 9, the electrode pattern 14 and the electrode pattern 18 are shown hatched.

[0061] Next, as shown in FIG. 9, a predetermined number of pattern sheets 15 are laminated on the first cover sheet 17, and a second cover sheet 20 is formed thereon to produce a provisional laminate. The second cover sheet 20 can be formed in the same manner as the first cover sheet 17. Next, the provisional laminate is pressed in the lamination direction to obtain a base laminate 21 as shown in FIG. 10. In FIG. 10, the electrode patterns 14 and the electrode patterns 18 are hatched to show the exposed portions on the surface of the base laminate 21. The provisional laminate can be pressed using, for example, a hydrostatic press. Next, the base laminate 21 is cut along the virtual parting lines 22 to produce a plurality of unfired laminates 2 as shown in FIG. 11. The base laminate 21 can be cut using, for example, a press cutter, a dicing saw, or the like. Since the unsintered laminate 2 has the same structure as the laminate 2 after sintering, the terms and reference characters such as the internal electrode layer 5, main surfaces 7a, 7b, end surfaces 8a, 8b, and side surfaces 9a, 9b are hereinafter also used for the unsintered laminate 2. In Fig. 11, the portions of the internal electrode layer 5 and the dummy electrodes 61a to 62b exposed on the surface of the laminate 2 are shown with hatching.

[0062] Next, a degreasing treatment is performed in an air atmosphere, an inert gas atmosphere, or a reducing atmosphere on the unfired laminate 2. The degreasing treatment may be performed under atmospheric pressure or under reduced pressure.

[0063] Next, the degreased laminate 2 is fired in a reducing atmosphere. The atmospheric gas may be, for example, a mixed gas of hydrogen (H2) and nitrogen (N2). The firing temperature may be, for example, about 1100 to 1300° C. The fired laminate 2 may be subjected to a re-oxidation treatment in an oxidizing atmosphere.

[0064] Next, the fired laminate 2 is subjected to barrel polishing to fully expose the internal electrode layers 5 on the end faces 8a, 8b and side faces 9a, 9b, and to remove burrs from the surface of the laminate 2, thereby obtaining the laminate 2 as shown in Fig. 2. The external electrodes 10a, 10b are formed on the obtained laminate 2, thereby manufacturing the multilayer ceramic capacitor 1. The external electrodes 10a, 10b may be formed by applying a conductive paste to the unfired laminate 2 to become the external electrodes 10a, 10b, and then simultaneously firing the laminate 2 and the external electrodes 10a, 10b.

[0065] Next, another example of the manufacturing method of the multilayer ceramic capacitor 1 (hereinafter, also referred to as "second manufacturing method") will be described. The second manufacturing method is different from the first manufacturing method in that green sheets 13 are arranged on the uppermost layer and the lowermost layer of the base laminate, and the other steps are the same, so detailed description of the steps similar to those of the first manufacturing method will be omitted. FIG. 12 is a perspective view for explaining another example of the manufacturing steps of the base laminate, FIG. 13 is a perspective view showing another example of the base laminate, and FIG. 14 is a perspective view showing another example of the laminate obtained by cutting the base laminate. In FIG. 12, the electrode patterns 14 and the electrode patterns 18 are shown hatched. In FIG. 13, the parts of the electrode patterns 14 and the electrode patterns 18 exposed on the surface of the base laminate are shown hatched. In FIG. 14, the parts of the internal electrode layers 5 and the dummy electrodes 61a to 62b exposed on the surface of the laminate are shown hatched.

[0066] In the second manufacturing method, as shown in FIG. 12, one green sheet 13 is placed on a support sheet 16, and a first cover sheet 17 is formed thereon. Furthermore, a predetermined number of pattern sheets 15 are laminated on the first cover sheet 17, a second cover sheet 20 is formed thereon, and one green sheet 13 is placed thereon to produce a temporary laminate. The second cover sheet 20 can be formed in the same manner as the first cover sheet 17. The temporary laminate is pressed in the lamination direction to obtain a mother laminate 23 as shown in FIG. 13. The mother laminate 23 has the same configuration as the mother laminate 21, except that the green sheets 13 are located in the uppermost and lowermost layers in the lamination direction with respect to the above-mentioned mother laminate 21. Next, the mother laminate 23 is cut along the imaginary division lines 24 to produce a plurality of unfired laminates 2A as shown in FIG. 14. The laminate 2A has the same structure as the laminate 2 described above, except that parts of the green sheet 13 (reference numeral 13′ in FIG. 14) are positioned as the uppermost layer and the lowermost layer in the stacking direction. It can also be said that the laminate 2A is composed of the laminate 2 and a part of the green sheet 13.

[0067] Next, the unfired laminate 2A is subjected to a degreasing treatment. The degreasing treatment may be the same as the degreasing treatment in the first manufacturing method. Then, the laminate 2A that has been subjected to the degreasing treatment is fired. The firing atmosphere and firing temperature may be the same as the firing atmosphere and firing temperature in the first manufacturing method.

[0068] Next, the fired laminate 2A is subjected to barrel polishing to remove the dielectric layer formed by firing a portion of the green sheet 13, to fully expose the internal electrode layers 5 and dummy electrodes 61a to 62b on the surface of the laminate 2, and to remove burrs on the surface of the laminate 2, thereby obtaining the laminate 2 as shown in Fig. 2. The laminate 2 thus obtained is formed with external electrodes 10a, 10b, thereby manufacturing the multilayer ceramic capacitor 1.

[0069] In the second manufacturing method, the electrode patterns 18 that become the dummy electrodes 61a-62b contact the support sheet 16 via the green sheet 13, and do not contact the support sheet 16 directly. This makes it possible to prevent parts of the electrode patterns 18 from remaining on the support sheet 16 (hereinafter also referred to as "electrode erosion") when the laminate 2A obtained by cutting the base laminate 23 is peeled off from the support sheet 16. As a result, it is possible to prevent defective formation of the dummy electrodes 61a-62b due to electrode erosion, and ultimately improve the reliability of the multilayer ceramic capacitor 1.

[0070] In order to prevent electrode erosion by the support sheet 16, it is not necessary to place the green sheet 13 on the second cover sheet 20. However, by placing the green sheet 13 on the second cover sheet 20, the unsintered laminate 2A has a substantially vertically symmetrical configuration. Therefore, when the sintered laminate 2A is barrel polished, the upper and lower parts of the laminate 2A are uniformly polished, and the laminate 2A after barrel polishing (i.e., the laminate 2 shown in FIG. 2) has a substantially vertically symmetrical configuration. As a result, it is possible to prevent the bonding strength between the laminate 2 and the external electrodes 10a, 10b from becoming uneven, and ultimately the reliability of the multilayer ceramic capacitor 1 can be improved.

[0071] Hereinafter, a multilayer ceramic capacitor according to another embodiment of the present disclosure will be described.

[0072] Fig. 15, 16, 17, 18A, and 18B relate to a multilayer ceramic capacitor according to another embodiment. Fig. 15 is a perspective view showing a multilayer ceramic capacitor according to another embodiment, Fig. 16 is a perspective view showing a laminate of the multilayer ceramic capacitor shown in Fig. 15, Fig. 17 is a cross-sectional view taken along the line XVII-XVII in Fig. 15, Fig. 18A is a cross-sectional view taken along the line XVIIIA-XVIIIA in Fig. 17, and Fig. 18B is a cross-sectional view taken along the line XVIIIB-XVIIIB in Fig. 17. Fig. 18A shows an end surface cut along the line XVIIIA-XVIIIA in Fig. 17.

[0073] The multilayer ceramic capacitor 1A of this embodiment differs from the multilayer ceramic capacitor 1 in the configurations of the internal electrode layers 5 and the external electrodes 10a, 10b, but is otherwise similar to the multilayer ceramic capacitor 1, so detailed description of the similar configuration will be omitted.

[0074] In the multilayer ceramic capacitor 1A, as shown in Figs. 16, 17, and 18A, the lead-out portion 5ab of the first internal electrode layer 5a is exposed to the first end face 8a and the side faces 9a and 9b, and the lead-out portion 5bb of the second internal electrode layer 5b is exposed to the second end face 8b and the side faces 9a and 9b. As shown in Figs. 16, 17, and 18B, the first dummy electrode 61a is exposed to the first face 7a, the first end face 8a, and the side faces 9a and 9b, and the second dummy electrode 61b is exposed to the first face 7a, the second end face 8b, and the side faces 9a and 9b. In addition, the third dummy electrode 62a is exposed to the second face 7b, the first end face 8a, and the side faces 9a and 9b, and the fourth dummy electrode 62b is exposed to the second face 7b, the second end face 8b, and the side faces 9a and 9b.

[0075] 15, 17, 18A, and 18B, the first external electrode 10a is located from the first end face 8a to the main faces 7a, 7b and side faces 9a, 9b, and the second external electrode 10b is located from the second end face 8b to the main faces 7a, 7b and side faces 9a, 9b. The first external electrode 10a covers the portion of the first dummy electrode 61a exposed to the first face 7a and the portion of the third dummy electrode 62a exposed to the second face 7b. The first external electrode 10a covers the first dummy electrode 61a, the third dummy electrode 62a, and the portions of the lead-out portion 5ab of the first internal electrode layer 5a exposed to the first end face 8a and the side faces 9a, 9b. The second external electrode 10b covers the portion of the second dummy electrode 61b exposed on the first surface 7a, and covers the portion of the fourth dummy electrode 62b exposed on the second surface 7b. The second external electrode 10b covers the second dummy electrode 61b, the fourth dummy electrode 62b, and the portions of the second internal electrode layer 5b exposed on the second end surface 8b and the side surfaces 9a and 9b of the lead-out portion 5bb.

[0076] 16, 18A, and 18B, the portion of the lead-out portion 5ab exposed to the side surfaces 9a, 9b is shorter in length in the first direction (x-axis direction) than the portions of the first dummy electrode 61a and the third dummy electrode 62a exposed to the side surfaces 9a, 9b. The end of the portion of the lead-out portion 5ab exposed to the side surfaces 9a, 9b on the second end surface 8b side is located closer to the first end surface 8a than the end of the portion of the first dummy electrode 61a and the third dummy electrode 62a exposed to the side surfaces 9a, 9b on the second end surface 8b side. The portion of the lead-out portion 5bb exposed to the side surfaces 9a, 9b is shorter in length in the first direction (x-axis direction) than the portions of the second dummy electrode 61b and the fourth dummy electrode 62b exposed to the side surfaces 9a, 9b. The end portion of the lead portion 5bb on the first end face 8a side of the portion exposed on the side faces 9a, 9b is located closer to the second end face 8b than the end portions of the second dummy electrode 61b and the fourth dummy electrode 62b on the first end face 8a side of the portions exposed on the side faces 9a, 9b of the second dummy electrode 61b and the fourth dummy electrode 62b. The external electrodes 10a, 10b have a U-shape when viewed from the second direction (y-axis direction) as shown in FIG.

[0077] Since the multilayer ceramic capacitor 1A has dummy electrodes 61a-62b that are thicker than the internal electrode layers 5, it is possible to reduce the number of interfaces between different materials in the coating portions 61, 62 compared to multilayer ceramic capacitors of the prior art. As a result, it is possible to reduce the occurrence of delamination in the coating portions 61, 62 when the laminate 2 is barrel polished, thereby improving the reliability of the multilayer ceramic capacitor 1A.

[0078] The portions of the external electrodes 10a, 10b located on the principal surfaces 7a, 7b may be constituted only by the outer layer 12. In this case, the portions of the external electrodes 10a, 10b located on the principal surfaces 7a, 7b can be thinned, and as a result, the multilayer ceramic capacitor 1A can be made low-profile.

[0079] In the multilayer ceramic capacitor 1A, the side surfaces 9a, 9b, which have lower solder wettability than the surfaces of the external electrodes 10a, 10b, are largely exposed, so that solder is less likely to adhere to the side surfaces 9a, 9b when solder-mounted on an external board. As a result, even if the multilayer ceramic capacitor 1A is made low-profile, it is possible to reduce the risk of short-circuiting between the first external electrode 10a and the second external electrode 10b due to solder adhered to the side surfaces 9a, 9b.

[0080] The multilayer ceramic capacitor 1A may be configured such that all of the dummy electrodes 61a-62b are thicker than the internal electrode layer 5, as shown in Figures 16 and 17, or may be configured such that at least one of the dummy electrodes 61a-62b is thicker than the internal electrode layer 5, as in the multilayer ceramic capacitor 1 shown in Figure 5.

[0081] Fig. 19, 20, 21, 22A, and 22B relate to a multilayer ceramic capacitor according to still another embodiment. Fig. 19 is a perspective view showing a multilayer ceramic capacitor according to still another embodiment, Fig. 20 is a perspective view showing a laminate of the multilayer ceramic capacitor of Fig. 19, Fig. 21 is a cross-sectional view taken along the line XIX-XIX in Fig. 19, Fig. 22A is a cross-sectional view taken along the line XXIIA-XXIIA in Fig. 21, and Fig. 22B is a cross-sectional view taken along the line XXIIB-XXIIB in Fig. 21. Fig. 22A shows an end surface cut along the line XXIIA-XXIIA in Fig. 21.

[0082] The multilayer ceramic capacitor 1B of this embodiment differs from the multilayer ceramic capacitor 1 in the configurations of the internal electrode layers 5, dummy electrodes 61a to 62b, and external electrodes 10a, 10b, but is otherwise similar to the multilayer ceramic capacitor 1, so detailed description of the similar configuration will be omitted.

[0083] In the multilayer ceramic capacitor 1B, as shown in Figs. 20 and 22A, the lead-out portion 5ab of the first internal electrode layer 5a is exposed only to the first end face 8a, and is not exposed to the side faces 9a and 9b. The lead-out portion 5bb of the second internal electrode layer 5b is exposed only to the second end face 8b, and is not exposed to the side faces 9a and 9b. As shown in Figs. 20 and 21, the first dummy electrode 61a is exposed to the first face 7a, the first end face 8a, and the side faces 9a and 9b, and the second dummy electrode 61b is exposed to the first face 7a, the second end face 8b, and the side faces 9a and 9b. The third dummy electrode 62a is exposed to the second face 7b, the first end face 8a, and the side faces 9a and 9b, and the fourth dummy electrode 62b is exposed to the second face 7b, the second end face 8b, and the side faces 9a and 9b.

[0084] As shown in Figures 19, 21, and 22B, the first external electrode 10a is located from the first end face 8a to the main faces 7a, 7b and side faces 9a, 9b, and the second external electrode 10b is located from the second end face 8b to the main faces 7a, 7b and side faces 9a, 9b. As shown in Figures 21 and 22B, the first external electrode 10a covers the portion of the first dummy electrode 61a exposed to the first face 7a and side faces 9a, 9b, and also covers the portion of the third dummy electrode 62a exposed to the second face 7b and side faces 9a, 9b. The second external electrode 10b covers the portion of the second dummy electrode 61b exposed to the first face 7a and side faces 9a, 9b, and also covers the portion of the fourth dummy electrode 62b exposed to the second face 7b and side faces 9a, 9b. As shown in FIG. 19, the external electrodes 10a and 10b have a U-shape when viewed from the second direction (y-axis direction).

[0085] The multilayer ceramic capacitor 1B has dummy electrodes 61a-62b that are thicker than the internal electrode layers 5, and therefore can reduce the number of interfaces between different materials in the coating portions 61, 62 compared to conventional multilayer ceramic capacitors. As a result, it is possible to reduce the occurrence of delamination in the coating portions 61, 62 when the laminate 2 is barrel polished, thereby improving the reliability of the multilayer ceramic capacitor 1B.

[0086] The portions of the external electrodes 10a, 10b located on the principal surfaces 7a, 7b may be constituted only by the outer layer 12. In this case, the portions of the external electrodes 10a, 10b located on the principal surfaces 7a, 7b can be thinned, and as a result, the multilayer ceramic capacitor 1B can be made low-profile.

[0087] In the multilayer ceramic capacitor 1B, the side surfaces 9a, 9b, which have lower solder wettability than the surfaces of the external electrodes 10a, 10b, are largely exposed, so that solder is less likely to adhere to the side surfaces 9a, 9b when solder-mounted on an external board. As a result, even if the multilayer ceramic capacitor 1B is made low-profile, it is possible to reduce the risk of short-circuiting between the first external electrode 10a and the second external electrode 10b due to solder adhered to the side surfaces 9a, 9b.

[0088] The multilayer ceramic capacitor 1B may be configured such that all of the dummy electrodes 61a-62b are thicker than the internal electrode layer 5, as shown in Figures 20 and 21, or may be configured such that at least one of the dummy electrodes 61a-62b is thicker than the internal electrode layer 5, as in the multilayer ceramic capacitor 1 shown in Figure 5.

[0089] 23, 24, 25, 26A, 26B, 26C, and 26D relate to a multilayer ceramic capacitor according to still another embodiment. FIG. 23 is a perspective view showing a multilayer ceramic capacitor according to still another embodiment, FIG. 24 is a perspective view showing a laminate of the multilayer ceramic capacitor of FIG. 23, and FIG. 25 is a cross-sectional view taken along the line XXV-XXV in FIG. 23. FIG. 26A is a cross-sectional view taken along the line XXVIA-XXVIA in FIG. 25, FIG. 26B is a cross-sectional view taken along the line XXVIB-XXVIB in FIG. 25, FIG. 26C is a cross-sectional view taken along the line XXVIC-XXVIC in FIG. 25, and FIG. 26D is a cross-sectional view taken along the line XXVID-XXVID in FIG. 25. In FIG. 24, the portions of the internal electrode layer and the dummy electrode exposed on the surface of the laminate are shown with hatching.

[0090] 23, the multilayer ceramic capacitor 1C of this embodiment includes a laminate 25, a first external electrode 26a, a second external electrode 26b, a third external electrode 26c, and a fourth external electrode 26d. Hereinafter, the first external electrode 26a, the second external electrode 26b, the third external electrode 26c, and the fourth external electrode 26d may be collectively referred to as the external electrodes 26a to 26d.

[0091] As shown in FIG. 24, the laminate 25 has a substantially rectangular parallelepiped shape. The laminate 25 has a first surface 27a and a second surface 27b that face each other, a first end surface 28a and a second end surface 28b that face each other, and a first side surface 29a and a second side surface 29b that face each other. The first end surface 28a and the second end surface 28b may be perpendicular to a first direction (x-axis direction). The first side surface 29a and the second side surface 29b may be perpendicular to a second direction (y-axis direction). The first surface 27a and the second surface 27b may be perpendicular to a third direction (z-axis direction). The first surface 27a and the second surface 27b may be substantially square in a plan view.

[0092] As shown in FIG. 25, the laminate 25 includes an active section 30, a first covering section 33, and a second covering section 34. The active section 30 is configured by alternately stacking dielectric layers 31 and internal electrode layers 32. The dielectric layers 31 and the internal electrode layers 32 are stacked in the third direction (z-axis direction). The active section 30 forms a capacitance. In FIG. 25, the boundaries between the active section 30 and the first covering section and the second covering section are shown by two-dot chain lines, but the actual boundaries are not clearly visible. Hereinafter, the first covering section 33 and the second covering section 34 may be collectively referred to as covering sections 33, 34.

[0093] The dielectric layer 31 may be made of a ceramic material mainly composed of, for example, BaTiO3, CaTiO3, SrTiO3, BaZrO3, etc. The internal electrode layer 32 may be made of a metal material mainly composed of, for example, a metal such as Ni, Cu, Sn, Pt, Pd, Ag, Au, etc., or an alloy thereof.

[0094] The internal electrode layers 32 include a first internal electrode layer 32a and a second internal electrode layer 32b having mutually different polarities. The active section 30 is configured by alternately stacking the first internal electrode layers 32a and the second internal electrode layers 32b with a dielectric layer 31 interposed therebetween. Although an example in which the active section 30 has two internal electrode layers 32 is shown in Figs. 24 and 25, the active section 30 may have more than two internal electrode layers 32.

[0095] As shown in Fig. 26B, the first internal electrode layer 32a has a capacitance forming portion 32aa, a first lead portion 32ab, and a second lead portion 32ac. The first lead portion 32ab is exposed at the first end face 28a and the second side face 29b. The second lead portion 32ac is exposed at the second end face 28b and the first side face 29a. As shown in Fig. 26B, the first lead portion 32ab and the second lead portion 32ac are located at two diagonally opposite corners of the laminate 25 in a plan view.

[0096] As shown in Fig. 26C, the second internal electrode layer 32b has a capacitance forming portion 32ba, a third lead portion 32bb, and a fourth lead portion 32bc. The third lead portion 32bb is exposed at the first end face 28a and the first side face 29a. The fourth lead portion 32bc is exposed at the second end face 28b and the second side face 29b. The third lead portion 32bb and the fourth lead portion 32bc are located at two diagonally opposite corners of the laminate 25 in a plan view.

[0097] The capacitance generating portion 32aa and the capacitance generating portion 32ba overlap each other in a plan view. The first lead portion 32ab does not overlap the third lead portion 32bb and the fourth lead portion 32bc in a plan view. The second lead portion 32ac does not overlap the third lead portion 32bb and the fourth lead portion 32bc in a plan view.

[0098] As shown in FIG. 25, the first covering portion 33 and the second covering portion 34 are located at both ends of the active portion 30 in the third direction (z-axis direction).

[0099] As shown in FIG. 26A, the first covering portion 33 includes four dummy electrodes 33a, 33b, 33c, and 33d and a first dielectric portion 33e. The four dummy electrodes 33a, 33b, 33c, and 33d are located at the four corners of the laminate 25 in a plan view. The dummy electrodes 33a, 33b, 33c, and 33d are exposed on the first surface 27a. The dummy electrode 33a is further exposed on the first end surface 28a and the second side surface 29b. The dummy electrode 33b is further exposed on the second end surface 28b and the first side surface 29a. The dummy electrode 33c is further exposed on the first end surface 28a and the first side surface 29a. The dummy electrode 33d is further exposed on the second end surface 28b and the second side surface 29b. The dummy electrodes 33a, 33b, 33c, and 33d may be, for example, rectangular parallelepiped, cubic, triangular prism, or quadrant cylinder. The dummy electrodes 33a, 33b, 33c, and 33d may be made of the metal material that constitutes the internal electrode layer 32. The first dielectric portion 33e is made of a dielectric material and electrically insulates the dummy electrodes 33a, 33b, 33c, and 33d from each other. The first dielectric portion 33e may be made of the ceramic material that constitutes the dielectric layer 31.

[0100] As shown in FIG. 26D, the second covering portion 34 includes four dummy electrodes 34a, 34b, 34c, and 34d and a second dielectric portion 34e. The four dummy electrodes 34a, 34b, 34c, and 34d are located at the four corners of the laminate 25 in a plan view. The dummy electrodes 34a, 34b, 34c, and 34d are exposed to the second surface 27b. The dummy electrode 34a is further exposed to the first end surface 28a and the first side surface 29a. The dummy electrode 34b is further exposed to the second end surface 28b and the second side surface 29b. The dummy electrode 34c is further exposed to the first end surface 28a and the second side surface 29b. The dummy electrode 34d is further exposed to the second end surface 28b and the first side surface 29a. The dummy electrodes 34a, 34b, 34c, and 34d may be, for example, rectangular parallelepiped, cubic, triangular prism, or quadrant cylinder. The dummy electrodes 34a, 34b, 34c, and 34d may be made of the metal material that constitutes the internal electrode layer 32. The second dielectric portion 34e is made of a dielectric material and electrically insulates the dummy electrodes 34a, 34b, 34c, and 34d from each other. The second dielectric portion 34e may be made of the ceramic material that constitutes the dielectric layer 31. Hereinafter, the dummy electrodes 33a, 33b, 33c, and 33d and the dummy electrodes 34a, 34b, 34c, and 34d may be collectively referred to as dummy electrodes 33a to 34d.

[0101] The first external electrode 26a is located on the first surface 27a, the first end surface 28a, the second side surface 29b, and the second surface 27b. The first external electrode 26a is connected to a portion of the first lead portion 32ab exposed on the surface of the laminate 25, and portions of the dummy electrode 33a and the dummy electrode 34c exposed on the surface of the laminate 25. The first external electrode 26a may completely cover the portion of the first lead portion 32ab exposed on the surface of the laminate 25, and portions of the dummy electrode 33a and the dummy electrode 34c exposed on the surface of the laminate 25.

[0102] The second external electrode 26b is located on the first surface 27a, the second end surface 28b, the first side surface 29a, and the second surface 27b. The second external electrode 26b is connected to a portion of the second lead portion 32ac exposed on the surface of the laminate 25, and to portions of the dummy electrode 33b and the dummy electrode 34d exposed on the surface of the laminate 25. The second external electrode 26b may completely cover the portion of the second lead portion 32ac exposed on the surface of the laminate 25, and to portions of the dummy electrode 33b and the dummy electrode 34d exposed on the surface of the laminate 25.

[0103] The third external electrode 26c is located on the first surface 27a, the first end surface 28a, the first side surface 29a, and the second surface 27b. The third external electrode 26c is connected to a portion of the third lead portion 32bb exposed on the surface of the laminate 25, and portions of the dummy electrode 33c and the dummy electrode 34a exposed on the surface of the laminate 25. The third external electrode 26c may completely cover the portion of the third lead portion 32bb exposed on the surface of the laminate 25, and portions of the dummy electrode 33c and the dummy electrode 34a exposed on the surface of the laminate 25.

[0104] The fourth external electrode 26d is located on the first surface 27a, the second end surface 28b, the second side surface 29b, and the second surface 27b. The fourth external electrode 26d is connected to a portion of the fourth lead portion 32bc exposed on the surface of the laminate 25, and to portions of the dummy electrode 33d and the dummy electrode 34b exposed on the surface of the laminate 25. The fourth external electrode 26d may completely cover the portion of the fourth lead portion 32bc exposed on the surface of the laminate 25, and the portions of the dummy electrode 33d and the dummy electrode 34b exposed on the surface of the laminate 25.

[0105] The external electrodes 26a-26d may be made of a metal material mainly composed of a metal such as Ni, Cu, Sn, Pt, Pd, Ag, Au, or an alloy thereof. The external electrodes 26a-26d may be formed using a thick-film formation technique such as a dipping method, a screen printing method, or a gravure printing method. The external electrodes 26a-26d may be configured to include a base layer in contact with the surface of the laminate 25 and an outer layer covering the base layer, similar to the external electrodes 10a and 10b shown in Figs. 3 and 4.

[0106] The manufacturing method of the multilayer ceramic capacitor 1C is the same as that of the multilayer ceramic capacitor 1. First, a base laminate is produced, and then the base laminate is cut to produce a plurality of unfired laminates 25. Next, the unfired laminates 25 are degreased, and then the degreased laminates 25 are fired. Next, the fired laminates 2 are barrel polished to obtain the laminate 25 as shown in FIG. 24. External electrodes 26a to 26d are formed on the obtained laminates 25, thereby producing the multilayer ceramic capacitor 1C.

[0107] 24 and 25, the multilayer ceramic capacitor 1C is configured such that the dummy electrodes 33a-34d have a greater thickness in the third direction (z-axis direction) than one internal electrode layer 32. This allows the multilayer ceramic capacitor 1C to reduce the number of interfaces between different materials in the coating portions 33, 34 compared to conventional multilayer ceramic capacitors. As a result, it is possible to reduce the occurrence of interlayer peeling in the coating portions 33, 34 when the laminate 25 is barrel polished, thereby improving the reliability of the multilayer ceramic capacitor 1C.

[0108] The multilayer ceramic capacitor 1C may have a configuration in which at least one of the dummy electrodes 33a-34d is thicker than the internal electrode layer 32. The multilayer ceramic capacitor 1C may include dummy electrodes 33a-34d whose thickness is equal to or less than that of the internal electrode layer 32, such as the second dummy electrode 61b, the third dummy electrode 62a, and the fourth dummy electrode 62b shown in Fig. 5. For example, when the thickness of the dummy electrode 33b is equal to or less than that of the internal electrode layer 32, the laminate 25 may have auxiliary electrode portions similar to the auxiliary electrode portions 61ba, 62aa, and 62ba shown in Fig. 5 on the inner side (below) of the dummy electrode 33b in the third direction (z-axis direction).

[0109] The dummy electrodes 33a-34d may be one-piece dummy electrodes. The dummy electrodes 33a-34d may be configured by stacking a plurality of dummy electrode layers, like the dummy electrodes 61a-62b shown in Fig. 6. In this case, it becomes easy to form the dummy electrodes 33a-34d with the designed dimensions, and the reliability of the multilayer ceramic capacitor 1C can be improved.

[0110] An interface between at least one of the dummy electrodes 33a, 33b, 33c, and 33d and the first dielectric portion 33e may have an uneven structure, as shown in interfaces 61d and 62d in FIG. 7. In this case, even if a crack occurs in the first covering portion 33 when the multilayer ceramic capacitor 1C is solder-mounted on an external substrate, the crack can be prevented from extending to the active portion 30. As a result, the moisture resistance of the multilayer ceramic capacitor 1C can be improved, and the reliability can be improved. An interface between at least one of the dummy electrodes 34a, 34b, 34c, and 34d and the second dielectric portion 34e may have an uneven structure. In this case, the moisture resistance of the multilayer ceramic capacitor 1C can be improved, and the reliability can be improved, as described above.

[0111] Although the embodiments of the present disclosure have been described in detail above, the present disclosure is not limited to the above-described embodiments, and various modifications, improvements, etc. are possible without departing from the gist of the present disclosure.

[0112] FIG. 27 is a cross-sectional view showing a multilayer ceramic capacitor 1D according to still another embodiment of the present disclosure. This embodiment is similar to the embodiment of FIG. 3, and the corresponding parts are given the same reference numerals, and the overlapping description will be omitted. The multilayer ceramic capacitor 1D according to this embodiment may further include intermediate dummy electrodes 61a1, 61b1, 62a1, and 62b1. The intermediate dummy electrodes 61a1 and 61b1 may be configured such that the intermediate dummy electrodes 61f and 61g are provided between the electrode layers located inside (below) the first and second dummy electrodes 61a and 61b in the third direction (z-axis direction) and close to the lower sides of the first and second dummy electrodes 61a and 61b. The intermediate dummy electrodes 61a1 and 61b1 are electrically insulated by a dielectric layer made of the same dielectric material as the dielectric portion, and the dielectric layer may be made of a ceramic material. Furthermore, the intermediate dummy electrodes 62a1, 62b1 may be configured so that the intermediate dummy electrodes 61a1, 61b1 are provided inside (above) the third and fourth dummy electrodes 62a, 62b, respectively, and between the electrode layers close to the third and fourth dummy electrodes 62a, 62b. This can increase the area of ​​the exposed parts of the intermediate dummy electrodes 61a1, 61b1, 62a1, 62b1 on the end faces 8a, 8b and the side faces 9a, 9b. Therefore, the reliability of the multilayer ceramic capacitor 1D can be effectively improved. In addition, when the base layer 11 is formed by a plating method, for example, a plating film growing from the end of the first internal electrode layer 5a exposed from the first end face 8a as a starting point can easily reach the dummy electrode 61a via the intermediate dummy electrode 61a1, and the base layer 11 can be easily formed.

[0113] The intermediate dummy electrodes 61a1, 61b1, 62a1, and 62b1 may have the same shape as the dummy electrodes 61a, 61b, 62a, and 62b in a plan view, or may have a different shape from the dummy electrodes 61a, 61b, 62a, and 62b. The intermediate dummy electrodes 61f, 61g, 62f, and 62g may have a thickness in the third direction (z-axis direction) greater than that of the internal electrode layer 5. The intermediate dummy electrodes 61a1, 61b1, 62a1, and 62b1 may have approximately the same dimensions. The intermediate dummy electrodes 61a1, 61b1, 62a1, and 62b1 may be made of the same metal material as the metal material that makes up the dummy electrodes 61a, 61b, 62a, and 62b. By positioning the intermediate dummy electrodes 61a1, 61b1, 62a1, and 62b1 between the active portion 3 and the covering portions 61 and 62, a plating film is easily formed from the active portion 3 to the main surface side.

[0114] Fig. 28 is a cross-sectional view showing a multilayer ceramic capacitor 1E according to still another embodiment of the present disclosure. Since this embodiment is similar to the embodiment of Fig. 25, the same reference numerals are used for corresponding parts, and duplicated explanations are omitted. The multilayer ceramic capacitor 1E according to this embodiment may further include intermediate dummy electrodes 33a1, 33c1, 33b1, 33d1, 34a1, 34c1, 34b1, and 34d1. The intermediate dummy electrodes 33a1, 33c1, 33b1, 33d1 may be configured, for example, so that the intermediate dummy electrodes 33a1, 33c1, 33b1, 33d1 are provided inside (below) the dummy electrodes 33a, 33c, 33b, 33d, 34a, 34c, 34b, 34d in the third direction (z-axis direction) and between the intermediate dummy electrodes 33a1, 33c1, 33b1, 33d1 and electrode layers adjacent to the dummy electrodes 33a, 33c, 33b, 33d, 34a, 34c, 34b, 34d. The intermediate dummy electrodes 33a1, 33c1, 33b1, 33d1 are electrically insulated by a dielectric layer made of the same dielectric material as the dielectric portion, and the dielectric layer may be made of a ceramic material. Furthermore, the intermediate dummy electrodes 34a1, 34c1, 34b1, and 34d1 may be configured so that the intermediate dummy electrodes 34a1, 34c1, 34b1, and 34d1 are provided inside (above) the dummy electrodes 34a, 34c, 34b, and 34d, respectively, and between the electrode layers adjacent to the dummy electrodes 34a, 34c, 34b, and 34d.

[0115] The intermediate dummy electrodes 33a1, 33c1, 33b1, 33d1, 34a1, 34c1, 34b1, and 34d1 may have the same shape as the dummy electrodes 33a, 33c, 33b, 33d, 34a, 34c, 34b, and 34d in a plan view, or may have a different shape from the dummy electrodes 33a, 33c, 33b, 33d, 34a, 34c, 34b, and 34d. The intermediate dummy electrodes 33a1, 33c1, 33b1, 33d1, 34a1, 34c1, 34b1, and 34d1 may have a thickness in the third direction (z-axis direction) greater than that of the internal electrode layer 32. The dummy electrodes 33a, 33c, 33b, 33d, 34a, 34c, 34b, and 34d may have approximately the same dimensions as each other. The intermediate dummy electrodes 33a1, 33c1, 33b1, 33d1, 34a1, 34c1, 34b1, and 34d1 may be made of the same metal material as the dummy electrodes 33a, 33c, 33b, 33d, 34a, 34c, 34b, and 34d. The dummy electrodes 33a, 33c, 33b, 33d, 34a, 34c, 34b, and 34d may have a length in the y-axis direction shorter than that of the underlayer.

[0116] This makes it easier for a plating film to be formed from the active portion to the main surface side while maintaining the characteristic that solder is less likely to adhere to the side surfaces 9a and 9b.

[0117] Fig. 29 is a perspective view showing a laminate 2B of a laminated ceramic capacitor according to still another embodiment of the present disclosure. This embodiment is similar to the embodiment of Fig. 20, and the same reference numerals are used for corresponding parts, and duplicated explanations are omitted. The laminated ceramic capacitor of this embodiment may further include intermediate dummy electrodes 61a1, 61b1, 62a1, and 62b1 in addition to the four dummy electrodes 61a, 61b, 62c, and 62d included in the first covering portion 61. The intermediate dummy electrodes 61a1 and 61b1 may be configured to be provided, for example, on the inner side (below) of the first and second dummy electrodes 61a and 61b in the third direction (z-axis direction) and between the intermediate dummy electrodes 61a1 and 61b1 and electrode layers adjacent to the first and second dummy electrodes 61a and 61b. The intermediate dummy electrodes 62a1, 62b1 are electrically insulated by a dielectric layer made of the same dielectric material as the dielectric portion, and the dielectric layer may be made of a ceramic material. Furthermore, the intermediate dummy electrodes 62a1, 62b1 may be provided on the inner side (above) of each of the two dummy electrodes 34a, 34b, 34c, 34d included in the second covering portion 62, and between the electrode layers adjacent to the third and fourth dummy electrodes 62a, 62b. This increases the area of ​​the exposed portions of the dummy electrodes on the end faces and side faces, thereby effectively improving the reliability of the multilayer ceramic capacitor.

[0118] The intermediate dummy electrodes 61a1, 61b1, 62a1, and 62b1 may have the same shape as the dummy electrodes 61a, 61b, 62a, and 62b in a plan view, or may have a different shape from the dummy electrodes 61a, 61b, 62a, and 62b. The intermediate dummy electrodes 61a1, 61b1, 62a1, and 62b1 may have a larger thickness in the third direction (z-axis direction) than the dummy electrodes 61a, 61b, 62a, and 62b. The dummy electrodes 61a, 61b, 62a, and 62b may have approximately the same dimensions. The intermediate dummy electrodes 61a1, 61b1, 62a1, and 62b1 may be made of the same metal material as the dummy electrodes 61a, 61b, 62a, and 62b. By positioning the intermediate dummy electrodes 61a1, 61b1, 62a1, and 62b1 between the active portion 3 and the covering portions 61 and 62, a plating film is easily formed from the active portion to the main surface side.

[0119] The multilayer ceramic capacitor according to the present disclosure can suppress the occurrence of delamination in the coating while increasing the bonding strength between the laminate and the external electrodes, and therefore can provide a multilayer ceramic capacitor with improved reliability.

[0120] The multilayer ceramic capacitor of the present disclosure can be embodied in the following configurations (1) to (10).

[0121] (1) A laminate having a substantially rectangular parallelepiped shape including an active section formed by alternately stacking dielectric layers and internal electrode layers, and a first covering section and a second covering section located at both ends of the active section in a stacking direction of the dielectric layers and the internal electrode layers, the laminate having a first surface and a second surface opposed to each other in the stacking direction, a first end surface and a second end surface opposed to each other, and a first side surface and a second side surface opposed to each other; a first external electrode located from the first end face to the first face, the second face, the first side face, and the second side face; a second external electrode located from the second end surface to the first surface, the second surface, the first side surface, and the second side surface, the first external electrode and the second external electrode are connected to different internal electrode layers of the internal electrode layer; the first covering portion has a first dielectric portion, and a first dummy electrode and a second dummy electrode located at both ends of the first dielectric portion in a first direction orthogonal to the first end face, the second covering portion has a second dielectric portion, and a third dummy electrode and a fourth dummy electrode located at both ends of the second dielectric portion in the first direction, the first dummy electrode and the third dummy electrode are exposed at the first end surface, and the second dummy electrode and the fourth dummy electrode are exposed at the second end surface, At least one of the first dummy electrode, the second dummy electrode, the third dummy electrode, and the fourth dummy electrode is thicker than the internal electrode layer.

[0122] (2) the first dummy electrode and the second dummy electrode are further exposed on the first surface, The multilayer ceramic capacitor according to the above-mentioned configuration (1), wherein the third dummy electrode and the fourth dummy electrode are further exposed on the second surface.

[0123] (3) the first dummy electrode and the second dummy electrode are further exposed to the first side surface and the second side surface, The multilayer ceramic capacitor according to the above configuration (1) or (2), wherein the third dummy electrode and the fourth dummy electrode are further exposed on the first side surface and the second side surface.

[0124] (4) The multilayer ceramic capacitor according to any one of the above configurations (1) to (3), wherein at least one of the first dummy electrode, the second dummy electrode, the third dummy electrode, and the fourth dummy electrode includes a plurality of stacked dummy electrode layers.

[0125] (5) The multilayer ceramic capacitor according to the above-mentioned configuration (4), wherein the plurality of dummy electrode layers include a common material made of a dielectric material.

[0126] (6) an interface between at least one of the first dummy electrode and the second dummy electrode and the first dielectric portion has an uneven structure; The multilayer ceramic capacitor according to any one of the above configurations (1) to (5), wherein an interface between at least one of the third dummy electrode and the fourth dummy electrode and the second dielectric portion has an uneven structure.

[0127] (7) The first covering portion further includes a fifth dummy electrode and a sixth dummy electrode located at both ends of the first dielectric portion in the first direction, the second covering portion further includes a seventh dummy electrode and an eighth dummy electrode located at both ends of the second dielectric portion in the first direction, The multilayer ceramic capacitor according to any one of the above configurations (1) to (6), wherein the fifth dummy electrode and the seventh dummy electrode are exposed to the first end face, and the sixth dummy electrode and the eighth dummy electrode are exposed to the second end face.

[0128] (8) the first dummy electrode, the second dummy electrode, the fifth dummy electrode, and the sixth dummy electrode are further exposed on the first surface, The multilayer ceramic capacitor according to the above-mentioned configuration (7), wherein the third dummy electrode, the fourth dummy electrode, the seventh dummy electrode and the eighth dummy electrode are further exposed on the second surface.

[0129] (9) The first dummy electrode and the second dummy electrode are further exposed on the first side surface, the fifth dummy electrode and the sixth dummy electrode are further exposed to the second side surface, the third dummy electrode and the fourth dummy electrode are further exposed to the first side surface, The multilayer ceramic capacitor according to the above configuration (7) or (8), wherein the seventh dummy electrode and the eighth dummy electrode are further exposed on the second side surface.

[0130] (10) a first intermediate dummy electrode located between the first dummy electrode and the internal electrode layer in the lamination direction and having a thickness greater than that of the internal electrode layer; a second intermediate dummy electrode located between the second dummy electrode and the internal electrode layer in the stacking direction and having a thickness greater than that of the internal electrode layer; a third intermediate dummy electrode located between the third dummy electrode and the internal electrode layer in the stacking direction and having a thickness greater than that of the internal electrode layer; The multilayer ceramic capacitor according to any one of the above configurations (1) to (9), further comprising a fourth intermediate dummy electrode located between the fourth dummy electrode and the internal electrode layer in the stacking direction and having a thickness greater than that of the internal electrode layer.

[0131] Although the embodiments of the present disclosure have been described in detail above, the present disclosure is not limited to the above-mentioned embodiments, and various modifications and improvements are possible within the scope of the gist of the present disclosure. It goes without saying that all or part of the components of each of the above-mentioned embodiments can be appropriately combined within the scope of not contradicting each other. [Explanation of symbols]

[0132] 1,1A,1B,1C,1D,1E Multilayer Ceramic Capacitors 2,2A,2B laminate 2f Opposing area 3 Active part 4 Dielectric Layer 5 Internal electrode layer 5a 1st internal electrode layer 5aa capacitor formation part 5ab Drawer part 5b Second internal electrode layer 5ba capacity forming part 5bb drawer 61 First Covering Part 61a First dummy electrode 61b Second dummy electrode 61ba Auxiliary electrode part 61c First dielectric part 61d interface 61e Interface 62 Second Covering Section 62a Third dummy electrode 62aa auxiliary electrode part 62b 4th dummy electrode 62ba auxiliary electrode section 62c Second dielectric section 62d interface 63 Dummy electrode layer 63a Common material 64 Dielectric Layer 65 Dielectric Layer 66 Electrode layer 7a 1st page 7b 2nd side 8a 1st end face 8b 2nd end face 9a 1st side 9b Second side 10a 1st external electrode 10b 2nd external electrode 10t inner end 11 1st layer (base layer) 12 2nd layer (outer layer) 13,13' Ceramic green sheet (green sheet) 14 Electrode Pattern 15 Pattern Sheet 16 Support Sheet 17 First cover sheet 18 Electrode Pattern 19 Dielectric Pattern 20 Second cover sheet 21 Mother laminate 22 Virtual division line 23 Mother laminate 24 Virtual division line 25 Laminate 26a 1st external electrode 26b 2nd external electrode 26c 3rd external electrode 26d 4th external electrode 27a 1st page 27b 2nd side 28a 1st end face 28b 2nd end face 29a 1st side 29b Second side 30 Active part 31 Dielectric layer 32 Internal electrode layer 32a 1st internal electrode layer 32aa capacitor formation part 32ab 1st drawer 32ac 2nd drawer 32b Second internal electrode layer 32ba capacity forming part 32bb 3rd drawer 32bc 4th drawer 33 First Covering Section 33a, 33b, 33c, 33d Dummy electrodes 33e First dielectric section 34 Second Covering Section 34a, 34b, 34c, 34d Dummy electrodes 34e Second dielectric section

Claims

1. a substantially rectangular parallelepiped laminate including an active section formed by alternately stacking dielectric layers and internal electrode layers, and a first covering section and a second covering section located at both ends of the active section in a stacking direction of the dielectric layers and the internal electrode layers, the laminate having a first surface and a second surface opposed to each other in the stacking direction, a first end surface and a second end surface opposed to each other, and a first side surface and a second side surface opposed to each other; a first external electrode located from the first end surface to the first surface and the second surface; a second external electrode located from the second end surface to the first surface and the second surface, the first external electrode and the second external electrode are connected to different internal electrode layers of the internal electrode layer; the first covering portion has a first dielectric portion, and a first dummy electrode and a second dummy electrode located at both ends of the first dielectric portion in a first direction orthogonal to the first end surface, the second covering portion has a second dielectric portion, and a third dummy electrode and a fourth dummy electrode located at both ends of the second dielectric portion in the first direction, the first dummy electrode is continuously exposed from the first end surface to the first surface, the second dummy electrode is continuously exposed from the second end surface to the first surface, the third dummy electrode is continuously exposed from the first end surface to the second surface, the fourth dummy electrode is continuously exposed from the second end surface to the second surface, At least one of the first dummy electrode, the second dummy electrode, the third dummy electrode, and the fourth dummy electrode is thicker than the internal electrode layer, At least one of the first dummy electrode and the second dummy electrode includes a plurality of dummy electrode layers directly stacked on each other, and has an uneven structure at an interface with the first dielectric portion, At least one of the third dummy electrode and the fourth dummy electrode includes a plurality of dummy electrode layers directly stacked on each other, and an interface with the second dielectric portion has an uneven structure.

2. the first dummy electrode and the second dummy electrode are further exposed to the first side surface and the second side surface, The multilayer ceramic capacitor according to claim 1 , wherein the third dummy electrode and the fourth dummy electrode are further exposed to the first side surface and the second side surface.

3. The multilayer ceramic capacitor according to claim 1 , wherein the plurality of dummy electrode layers include a common material made of a dielectric material.

4. the first covering portion further includes a fifth dummy electrode and a sixth dummy electrode respectively positioned at both ends of the first dielectric portion in the first direction, the second covering portion further includes a seventh dummy electrode and an eighth dummy electrode located at both ends of the second dielectric portion in the first direction, 2 . The multilayer ceramic capacitor according to claim 1 , wherein the fifth dummy electrode and the seventh dummy electrode are exposed at the first end surface, and the sixth dummy electrode and the eighth dummy electrode are exposed at the second end surface.

5. the fifth dummy electrode and the sixth dummy electrode are further exposed to the first surface, The multilayer ceramic capacitor according to claim 4 , wherein the seventh dummy electrode and the eighth dummy electrode are further exposed on the second surface.

6. the first dummy electrode and the second dummy electrode are further exposed to the first side surface, the fifth dummy electrode and the sixth dummy electrode are further exposed to the second side surface, the third dummy electrode and the fourth dummy electrode are further exposed to the first side surface, The multilayer ceramic capacitor according to claim 4 , wherein the seventh dummy electrode and the eighth dummy electrode are further exposed at the second side surface.

7. a first intermediate dummy electrode located between the first dummy electrode and the internal electrode layer in the stacking direction and having a thickness greater than that of the internal electrode layer; a second intermediate dummy electrode located between the second dummy electrode and the internal electrode layer in the stacking direction and having a thickness greater than that of the internal electrode layer; a third intermediate dummy electrode located between the third dummy electrode and the internal electrode layer in the stacking direction and having a thickness greater than that of the internal electrode layer; 2. The multilayer ceramic capacitor according to claim 1, further comprising a fourth intermediate dummy electrode located between said fourth dummy electrode and said internal electrode layer in said lamination direction and having a thickness greater than that of said internal electrode layer.

8. a first intermediate dummy electrode located between the first dummy electrode and the internal electrode layer in the stacking direction; a second intermediate dummy electrode located between the second dummy electrode and the internal electrode layer in the stacking direction; a third intermediate dummy electrode located between the third dummy electrode and the internal electrode layer in the stacking direction; a fourth intermediate dummy electrode located between the fourth dummy electrode and the internal electrode layer in the stacking direction, 2. The multilayer ceramic capacitor according to claim 1, wherein each of the first intermediate dummy electrode, the second intermediate dummy electrode, the third intermediate dummy electrode, and the fourth intermediate dummy electrode is thinner than each of the first dummy electrode, the second dummy electrode, the third dummy electrode, and the fourth dummy electrode.

9. A multilayer ceramic capacitor as described in claim 1, wherein the first external electrode and the second external electrode are plating films having an area directly contacting the dielectric layer.

10. the first external electrode completely covers exposed portions of the first dummy electrode and the third dummy electrode, 2. The multilayer ceramic capacitor according to claim 1, wherein the second external electrode completely covers exposed portions of the second dummy electrode and the fourth dummy electrode.

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