Multiplication device, multiply-and-accumulate device, matrix calculation device and reservoir device

Abstract

To accurately execute arithmetic for a long time.SOLUTION: A multiplication device outputs an output value obtained by multiplying an input value by a weight value. The multiplication device includes a short-term memory circuit, a long-term memory circuit, a conversion circuit, and a control circuit. The short-term memory circuit generates first control voltage in accordance with the weight value by an electric charge. The long-term memory circuit generates second control voltage in accordance with the weight value by a circuit with a time constant larger than that of the short-term memory circuit. The first control voltage generated from the short-term memory circuit is applied to a control terminal, and the input voltage according to the input value is applied to an input terminal, by that, the conversion circuit outputs, from an output terminal, an output current obtained by multiplying input voltage by conductance as the output value. The control circuit executes calibration processing of matching the first control voltage generated from the short-term memory circuit with the second control voltage generated from the long-term memory circuit by transferring the electric charge from the long-term memory circuit to the short-term memory circuit.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The embodiments of the present invention relate to a multiplication device, a multiply-accumulate device, a matrix calculation device, and a reservoir device. [Background technology]

[0002] Artificial intelligence (AI) is being used for various automation and labor-saving purposes. Neural networks are known as a representative AI algorithm. Deep neural networks (DNNs), which are multi-layered neural networks, are used in deep learning algorithms. Recurrent neural networks (RNNs), which recursively connect neurons closer to the output to neurons closer to the input, are used for time-series data processing. Long-Short-Term Memory (LSTM) is also known as a neural network that has improved representation capabilities for short-term and long-term memory. LSTM has even greater applicability for time-series data processing.

[0003] RNNs and LSTMs used in time-series data processing are calculated using a general-purpose computing device called a CPU (Central Processing Unit). However, because RNNs and LSTMs require even more calculations than NNs and DNNs, they are often calculated using a GP-GPU (General Purpose Graphical Processing Unit). RNNs and LSTMs require even more calculations during training, and require a lot of time and power for training. Therefore, deep learning, RNNs, and LSTMs require precise parameter tuning during training to achieve high performance.

[0004] On the other hand, reservoir computing is known as an algorithm for time series data processing that requires a small amount of calculation during learning. Reservoir computing does not require learning of the reservoir unit. However, reservoir computing requires high accuracy of the weight between the reservoir unit and the output unit in order to output a desired signal. It is also known that the reservoir unit is not limited to an electronic circuit and is made using various media. Since the output signal from the reservoir unit is generally an analog signal, it is possible to realize the calculation of the weight between the reservoir unit and the output unit by a product-sum calculator using an analog circuit.

[0005] In general, and not just in reservoir computing, it is desirable to have high weight accuracy. However, it is technically difficult to realize a calculator that can perform high-speed calculations while maintaining sufficiently high weight accuracy. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] US Patent Application Publication No. 2019 / 0318239 [Patent Document 2] U.S. Patent No. 10340002 [Non-patent literature]

[0007] [Non-Patent Document 1] Seyoung Kim, Tayfun Gokmen, Hyung-Min Lee and Wilfried E. Haensch, "Analog CMOS-based Resistive Processing Unit for Deep Neural Network Training", 2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS), 6-9 Aug. 2017 [Non-Patent Document 2] Stefano Ambrogio, Pritish Narayanan, Hsinyu Tsai, Robert M. Shelby, Irem Boybat, Carmelo di Nolfo, Severin Sidler, Massimo Giordano1, Martina Bodini, Nathan CP Farinha, Benjamin Killeen, Christina Cheng, Yassine Jaoudi & Geoffrey W. Burr, "Equivalent-accuracy accelerated neuralnetwork training using analogue memory", Nature, vol. 558, 60-67, 6 June 2018 Summary of the Invention [Problem to be solved by the invention]

[0008] The problem to be solved by the present invention is to provide a multiplication device, a product-sum calculation device, a matrix calculation device, and a reservoir device that can set weight values ​​with high accuracy in a short period of time and perform calculations with high accuracy for a long period of time. [Means for solving the problem]

[0009] A multiplication device according to an embodiment outputs an output value obtained by multiplying an input value and a weight value. The multiplication device includes a short-term memory circuit, a long-term memory circuit, a conversion circuit, and a control circuit. The short-term memory circuit holds an electric charge and generates a first control voltage according to the weight value from the held electric charge. The long-term memory circuit generates a second control voltage according to the weight value by a circuit having a time constant larger than that of the short-term memory circuit. The conversion circuit changes its conductance according to a voltage applied to a control terminal, and outputs a current obtained by multiplying a voltage applied to an input terminal by the conductance from an output terminal. The conversion circuit applies the first control voltage generated by the short-term memory circuit to the control terminal and applies an input voltage according to the input value to the input terminal, thereby outputting an output current obtained by multiplying the input voltage and the conductance from the output terminal as the output value. The control circuit performs a calibration process to match the first control voltage generated from the short-term memory circuit to the second control voltage generated from the long-term memory circuit by transferring charge from the long-term memory circuit to the short-term memory circuit. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a diagram showing the configuration of a multiplication device according to a first embodiment. [Diagram 2] 4 is a flowchart showing a process flow of a control circuit. [Diagram 3] FIG. 13 is a diagram showing the configuration of a multiplication device according to a first modified example. [Figure 4] FIG. 13 is a diagram showing the configuration of a multiplication device according to a second modified example. [Diagram 5] FIG. 13 is a diagram showing the configuration of a multiplication device according to a third modified example. [Figure 6] FIG. 13 is a diagram showing the configuration of a multiplication device according to a fourth modified example. [Figure 7] FIG. 13 is a diagram showing the configuration of a signed multiplication device according to a second embodiment. [Figure 8] FIG. 13 is a diagram showing the configuration of a product-sum calculation device according to a third embodiment. [Figure 9] FIG. 13 is a diagram showing the configuration of a matrix calculation device according to a fourth embodiment. [Figure 10]FIG. 13 is a diagram showing the configuration of a reservoir device according to a fifth embodiment. [Figure 11] 10 is a flowchart showing a process flow of the reservoir device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, embodiments will be described with reference to the drawings.

[0012] (First embodiment) FIG. 1 is a diagram showing a configuration of a multiplication device 10 according to the first embodiment. The multiplication device 10 outputs an output value obtained by multiplying an input value by a weight value. In this embodiment, the input value, the weight value, and the output value are continuous values ​​within a predetermined range. For example, the input value, the weight value, and the output value may be continuous values ​​greater than or equal to 0 and less than or equal to 1. At least one of the input value and the weight value may be a binary value of 0 or 1, or may be a digital value of a predetermined number of bits.

[0013] The multiplication device 10 calculates an input voltage (V in ) is received. The multiplication device 10 is set to a conductance (G) according to the weight value. The conductance (G) is a voltage-current conversion coefficient. The multiplication device 10 receives the input voltage (V in ) multiplied by the conductance (G) to obtain the output current (I out = G × V in ) as the output value.

[0014] The multiplication device 10 includes a short-term memory circuit 12, a long-term memory circuit 14, a conversion circuit 16, a rectification circuit 18, a reference potential switch 20, an adjustment switch 22, a setting switch 24, a calibration switch 26, and a control circuit 30.

[0015] The short-term memory circuit 12 stores the electric charge. The short-term memory circuit 12 then generates a first control voltage (V W1 In this example, the short-term memory circuit 12 generates a first control voltage (V W1The short-term memory circuit 12 has a terminal opposite to the first terminal 12a connected to the ground potential via a reference potential switch 20.

[0016] The short-term memory circuit 12 is a circuit having a predetermined time constant, and reduces the charge it holds over time. The time constant of the short-term memory circuit 12 depends on the elements and circuit configuration that realize the short-term memory circuit 12. In other words, the voltage reduction curve in the short-term memory circuit 12 depends on the elements and circuit configuration that realize the short-term memory circuit 12. In this embodiment, the short-term memory circuit 12 includes a short-term memory capacitor 32, which is a capacitor with a predetermined capacitance.

[0017] It is preferable that the capacity of the short-term memory circuit 12 is small. This allows the short-term memory circuit 12 to accumulate a target amount of charge in a short time. However, the capacity of the short-term memory circuit 12 is at least larger than the parasitic capacitance of the wiring and the gate capacitance of the transistor. Furthermore, the short-term memory circuit 12 can easily and accurately control the amount of charge to be accumulated by the amount of current and the charge time or discharge time. In the short-term memory circuit 12, the relationship between the amount of accumulated charge and the generated voltage is linear due to the relationship Q=CV. This allows the short-term memory circuit 12 to easily and accurately control the generated voltage.

[0018] The long-term memory circuit 14 generates a second control voltage (V W2 In this example, the long-term memory circuit 14 generates a second control voltage (V W2 The long-term memory circuit 14 has a terminal opposite to the second terminal 14a connected to a ground potential.

[0019] The long-term memory circuit 14 is a circuit with a larger time constant than the short-term memory circuit 12, so the voltage decreases at a slower rate than the short-term memory circuit 12, or the voltage hardly decreases even over time. For example, the long-term memory circuit 14 holds charge by a circuit with a larger time constant than the short-term memory circuit 12. In this embodiment, the short-term memory circuit 12 includes a long-term memory capacitor 34, which is a capacitor with a predetermined capacity. The long-term memory capacitor 34 has a larger capacity than the short-term memory capacitor 32 included in the short-term memory circuit 12. The long-term memory capacitor 34 may be, for example, a capacitor with a large area, or may be configured by connecting multiple small-area capacitors in parallel.

[0020] Since the long-term memory circuit 14 is made of a capacitor, it can be mounted on a semiconductor device or the like by the same manufacturing method as the short-term memory circuit 12. Therefore, since the long-term memory circuit 14 is made of a capacitor, it is possible to improve the manufacturing efficiency of the multiplication device 10. Furthermore, since the long-term memory circuit 14 is made of a capacitor, the relationship between the amount of charge stored and the voltage generated becomes linear due to the relationship Q=CV, so that the generated voltage can be easily controlled with high precision.

[0021] The conversion circuit 16 has an input terminal 36, an output terminal 38, and a control terminal 40. The conversion circuit 16 changes the conductance (G) between the input terminal 36 and the output terminal 38 in response to the voltage applied to the control terminal 40. The conversion circuit 16 outputs a current obtained by multiplying the voltage applied to the input terminal 36 by the conductance (G) from the output terminal 38. In this embodiment, the conversion circuit 16 is a field effect transistor 42. The gate of the field effect transistor 42 corresponds to the control terminal 40. One of the drain or the source of the field effect transistor 42 corresponds to the input terminal 36, and the other of the drain or the source that is not the input terminal 36 corresponds to the output terminal 38.

[0022] The conversion circuit 16 can change the conductance (G) with a resolution that can express the weight value, which is a continuous value, with sufficient accuracy. For example, the conversion circuit 16 can change the conductance (G) in 256 steps (e.g., 8-bit accuracy).

[0023] During the calculation, the conversion circuit 16 inputs the first control voltage (V W1 During calculation, the conversion circuit 16 applies an input voltage (V in During calculation, the conversion circuit 16 outputs the input voltage (V in ) multiplied by the conductance (G) to obtain the output current (I out = G × V in That is, the conversion circuit 16 outputs an output current (I out ) to output.

[0024] Such a conversion circuit 16 can be configured using one field effect transistor 42, so that the area occupied by the conversion circuit 16 when implemented in a semiconductor device can be reduced. Therefore, the multiplication device 10 including such a conversion circuit 16 can be implemented in a semiconductor device at high density, and can be easily incorporated into a device that performs multiple multiplications in parallel.

[0025] The rectifier circuit 18 passes an output current in a first direction in the conversion circuit 16 and blocks a current in a direction opposite to the first direction. In this example, the rectifier circuit 18 passes a current in a direction from the input terminal 36 to the output terminal 38 and blocks a current in a direction from the output terminal 38 to the input terminal 36. The rectifier circuit 18 also passes a negative input voltage (V in ) is applied, and a negative output current (I out ), a current flows from the output terminal 38 to the input terminal 36, and a current flows from the input terminal 36 to the output terminal 38. The rectifier circuit 18 is, for example, a diode. Such a rectifier circuit 18 can prevent a current from flowing back from another circuit to the conversion circuit 16.

[0026] The reference potential switch 20 is connected to the first control voltage (V W1 The reference potential switch 20 shorts or disconnects the terminal opposite to the first terminal 12a that generates the reference potential signal 12a from the ground potential. The reference potential switch 20 is controlled by a control circuit 30. The reference potential switch 20 is shorted when the multiplication device 10 is in operation, and is disconnected when the multiplication device 10 is not in operation.

[0027] During adjustment, the adjustment switch 22 controls the first control voltage (V W1 ) is connected to ground potential or power supply potential to charge or discharge the short-term memory circuit 12. The adjustment switch 22 is controlled by the control circuit 30. When charging the short-term memory circuit 12, the adjustment switch 22 connects the first terminal 12a to the power supply potential under the control of the control circuit 30. When discharging the charge from the short-term memory circuit 12, the adjustment switch 22 connects the first terminal 12a to ground potential under the control of the control circuit 30. During periods other than the adjustment period, the adjustment switch 22 disconnects the first terminal 12a from both the power supply potential and the ground potential under the control of the control circuit 30.

[0028] The setting switch 24, when set, controls the second control voltage (V W2 ) is connected to the ground potential or the power supply potential to charge or discharge the long-term memory circuit 14. The setting switch 24 is controlled by the control circuit 30. When charging the long-term memory circuit 14, the setting switch 24 connects the second terminal 14a to the power supply potential under the control of the control circuit 30. When discharging the charge from the long-term memory circuit 14, the setting switch 24 connects the second terminal 14a to the ground potential under the control of the control circuit 30. During periods other than the setting time, the setting switch 24 disconnects the first terminal 12a from both the power supply potential and the ground potential under the control of the control circuit 30.

[0029] The calibration switch 26 connects the short-term memory circuit 12 to the long-term memory circuit 14 during calibration, allowing charge to be transferred from the long-term memory circuit 14 to the short-term memory circuit 12. The calibration switch 26 is controlled by the control circuit 30. For example, the calibration switch 26 connects the first terminal 12a of the short-term memory circuit 12 to the second terminal 14a of the long-term memory circuit 14 under the control of the control circuit 30 during calibration. The calibration switch 26 disconnects the short-term memory circuit 12 from the long-term memory circuit 14 under the control of the control circuit 30 during periods other than calibration.

[0030] The control circuit 30 controls the overall operation of the multiplication device 10. For example, the control circuit 30 is a processor or a field-programmable gate array (FPGA).

[0031] During adjustment, the control circuit 30 receives the weight value. Then, the control circuit 30 executes an adjustment process. In the adjustment process, the control circuit 30 controls the adjustment switch 22 to charge or discharge the short-term memory circuit 12, thereby causing the short-term memory circuit 12 to store a first control voltage (V W1 For example, the control circuit 30 stores a charge amount that generates a weight value and a first control voltage (V W1 ) and a function or table indicating a correspondence relationship between the weight value and the first control voltage (V W1 ) from the short-term memory circuit 12. The control circuit 30 generates a desired first control voltage (V W1 ) may be generated from the short-term memory circuit 12, or the desired first control voltage (V W1 ) may be generated.

[0032] Since the short-term memory circuit 12 has a relatively small time constant, the first control voltage (V W1 ) can be generated. Therefore, the control circuit 30 can generate the first control voltage (VW1 ) can be generated with high accuracy in a short time.

[0033] After the adjustment process, the control circuit 30 executes a setting process during the setting process. In the setting process, the control circuit 30 adjusts the second control voltage (V W2 ) is generated by the short-term memory circuit 12 as a first control voltage (V W1 ) according to the weighting value. W2 For example, the control circuit 30 may generate a first control voltage (V W1 The control circuit 30 then controls the setting switch 24 to charge or discharge the long-term memory circuit 14, thereby storing the detected first control voltage (V W1 ) and the second control voltage (V W2 ) is generated.

[0034] Since the long-term memory circuit 14 has a relatively large time constant, the amount of voltage drop per unit time is small. Therefore, the control circuit 30 controls the second control voltage (V W2 ) can be generated with high accuracy for a long period of time.

[0035] During the calculation, the control circuit 30 controls the first control voltage (V W1 ) to the control terminal 40 of the conversion circuit 16. That is, during calculation, the control circuit 30 sets the conductance (G) between the input terminal 36 and the output terminal 38 of the conversion circuit 16 according to the weight value. As a result, during calculation, the conversion circuit 16 applies an input voltage (V in ) and the output current (I out = G × V in ) can be output.

[0036] During the calibration, the control circuit 30 executes a calibration process. In the calibration process, the control circuit 30 controls the first control voltage (V W1 ) is generated by the long-term memory circuit 14 in response to a second control voltage (V W2 For example, the control circuit 30 controls the calibration switch 26 to connect the short-term memory circuit 12 and the long-term memory circuit 14, thereby transferring charge from the long-term memory circuit 14 to the short-term memory circuit 12. As a result, even if the accumulated charge in the short-term memory circuit 12 decreases, the charge is replenished from the long-term memory circuit 14, so that the first control voltage (V W1 ) can be generated with high accuracy for a long time. In addition, since the long-term memory circuit 14 has a larger time constant than the short-term memory circuit 12, the amount of voltage drop relative to the amount of charge reduction is very small. Therefore, the long-term memory circuit 14 can generate the second control voltage (V W2 ) can be generated with high accuracy.

[0037] The control circuit 30 executes the calibration process at predetermined time intervals or whenever a predetermined event occurs. The predetermined event may be, for example, a first control voltage (V W1 ) reaches a predetermined value or a predetermined rate or more. The predetermined event may be, for example, an event that occurs when the calculation operation of the multiplication device 10 is stopped, an event that occurs when a predetermined time is reached, or an event that receives an instruction to start calibration from an external device.

[0038] 2 is a flowchart showing a process flow of the control circuit 30. As an example, the control circuit 30 executes the process in the flow shown in FIG.

[0039] First, in S11, the control circuit 30 executes the adjustment process. Specifically, the control circuit 30 receives a weight value. Then, the control circuit 30 controls the adjustment switch 22 to supply the short-term memory circuit 12 with a first control voltage (V W1 ) is generated from the short-term memory circuit 12. In response to this, the control circuit 30 stores the first control voltage (V W1 ) can be generated.

[0040] Next, in S12, the control circuit 30 executes a setting process. Specifically, the control circuit 30 sets the second control voltage (V W2 ) is generated by the short-term memory circuit 12 as a first control voltage (V W1 For example, the control circuit 30 sets the first control voltage (V W1 ) and the voltage generated by the long-term memory circuit 14, the setting switch 24 is controlled to apply a first control voltage (V W1 ) and the second control voltage (V W2 ) is generated in response to the weighting value. In this way, the control circuit 30 stores the charge in the long-term memory circuit 14 in an amount that generates a second control voltage (V W2 ) can be generated.

[0041] Next, in S13, the control circuit 30 causes the conversion circuit 16 to execute arithmetic processing. Specifically, the control circuit 30 turns off all of the adjustment switch 22, the setting switch 24, and the calibration switch 26, and causes the first control voltage (V W1 ) to the control terminal 40 of the conversion circuit 16. As a result, the conversion circuit 16 has a conductance (G) between the input terminal 36 and the output terminal 38 that corresponds to the weight value. Then, the control circuit 30 applies an input voltage (V in ) is applied to the input terminal 36 of the conversion circuit 16. As a result, the conversion circuit 16 converts the input voltage (V in ) multiplied by the conductance (G) to obtain the output current (I out = G × V in) can be output from output terminal 38.

[0042] In addition, the control circuit 30 controls the first control voltage (V W1 ) is continuously applied to the control terminal 40 of the conversion circuit 16, and the input voltage (V in ) is applied, the output current (I out ) that represents the input value in a time series. in ) and the weighted value, and the time series output current (I out ) can be output.

[0043] Next, in S14, the control circuit 30 judges whether it is time for calibration. The calibration timing is, for example, every predetermined time interval or every time a predetermined event occurs. If it is not time for calibration (No in S14), the control circuit 30 returns the process to S13 and causes the conversion circuit 16 to continue the calculation process. If it is time for calibration (Yes in S14), the control circuit 30 advances the process to S15.

[0044] In S15, the control circuit 30 executes a calibration process. Specifically, the control circuit 30 calibrates the first control voltage (V W1 ) is generated by the long-term memory circuit 14 in response to a second control voltage (V W2 In this case, the control circuit 30 connects the long-term memory circuit 14 and the short-term memory circuit 12 by the calibration switch 26, and transfers charge from the long-term memory circuit 14 to the short-term memory circuit 12, thereby adjusting the first control voltage (V W1 ) is generated by the long-term memory circuit 14 as a second control voltage (V W2 ).

[0045] When the control circuit 30 finishes the process of S15, it returns the process to S13 and causes the conversion circuit 16 to continue the calculation process. The control circuit 30 may receive a new weight value during the execution of S13. In this case, the control circuit 30 returns the process to S11 and repeats the process from S11. Furthermore, when the control circuit 30 receives a new weight value during the execution of S13, it may proceed to the calculation process of S13 without executing the setting process of S12. In this case, the control circuit 30 executes the setting process of S12 after the calculation process is completed or interrupted. In this way, when the weight value is updated multiple times by a learning process or the like, the control circuit 30 can execute the setting process after the weight value is determined.

[0046] The multiplication device 10 as described above outputs a first control voltage (V W1 ) to the conversion circuit 16, an input voltage (V in ) is multiplied by the conductance (G) according to the weighting value to obtain the output current (I out ) can be output. This allows the multiplication device 10 to execute high-resolution, highly accurate multiplication processing with a very simple configuration.

[0047] In addition, the multiplication device 10 stores charges in the short-term memory circuit 12 and generates a first control voltage (V W1 Since the short-term memory circuit 12 has a relatively small time constant, it generates the first control voltage (V W1 ) can be generated. In this way, the multiplication device 10 can generate a first control voltage (V W1 ) can be generated with high accuracy in a short time. Therefore, the multiplication device 10 can change the weight values ​​efficiently in a short time.

[0048] In addition, the multiplication device 10 outputs a first control voltage (V W1 ), the long-term memory circuit 14 generates a second control voltage (V W2Since the long-term memory circuit 14 has a relatively large time constant, the amount of voltage drop per unit time is small. Therefore, the long-term memory circuit 14 generates the second control voltage (V W2 ) can be generated with high accuracy for a long period of time.

[0049] Furthermore, the multiplication device 10 couples the short-term memory circuit 12 to the long-term memory circuit 14 to transfer charge from the long-term memory circuit 14 to the short-term memory circuit 12, thereby generating a first control voltage (V W1 ) is generated by the long-term memory circuit 14 as a second control voltage (V W2 ) to the short-term memory circuit 12 in accordance with the weight value. W1 ) can be output with high accuracy for a long period of time.

[0050] In addition, the long-term memory circuit 14 with a large time constant has a small voltage reduction amount even when connected to the short-term memory circuit 12 with a small time constant. Therefore, the multiplication device 10 can obtain the first control voltage (V W1 Therefore, the multiplication device 10 can continue to generate the first control voltage (V W1 ) can be output.

[0051] (Modification of the first embodiment) The following describes modified examples of the first embodiment. In the description of the modified examples, members having substantially the same functions and configurations as those shown in Fig. 1 are designated by the same reference numerals, and detailed description thereof will be omitted except for the differences.

[0052] FIG. 3 is a diagram showing a configuration of a multiplication device 10 according to a first modified example of the first embodiment.

[0053] The long-term memory circuit 14 according to the first modification includes an electric storage element 46 instead of a capacitor. The electric storage element 46 has a larger time constant than the short-term memory circuit 12. The electric storage element 46 is, for example, a thin-film all-solid-state battery. For example, the electric storage element 46 includes lithium cobalt oxide in the positive electrode, lithium phosphate in the solid electrolyte, and copper in the negative electrode.

[0054] It is preferable that the relationship between the amount of charge transferred during charging and discharging and the electromotive force V of the storage element 46 be made linear by selecting the thin film material and devising the manufacturing method. W1 ) and the second control voltage (V W2 ), it is sufficient that storage element 46 has linearity to the extent that it can generate a target voltage, even if it is nonlinear.

[0055] The control circuit 30 according to the first modification controls the charging and discharging of the storage element 46 by, for example, a circuit similar to a charge / discharge control circuit for a lithium ion battery. However, in an all-solid-state battery, the voltage-capacity curve generally follows a different path when charging and discharging. Therefore, the control circuit 30 has a charge-only or discharge-only mode, and in the setting process, the first control voltage (V W1 ) and the second control voltage (V W2 For example, in the setting process, the control circuit 30 may control the storage element 46 to generate a desired second control voltage (V W2 Alternatively, for example, in the setting process, the control circuit 30 controls the storage element 46 to generate a target second control voltage (V W2 ) is generated.

[0056] The storage element 46 has a very large capacity as a battery. As a result, the multiplication device 10 according to the first modification includes the long-term memory circuit 14 with a small area and a large time constant, and can be made compact.

[0057] FIG. 4 is a diagram showing a configuration of a multiplication device 10 according to a second modified example of the first embodiment.

[0058] The long-term memory circuit 14 according to the second modification includes a variable resistance circuit 48 instead of a capacitor. The variable resistance circuit 48 has a time constant larger than that of the short-term memory circuit 12. The variable resistance circuit 48 has, for example, a fixed resistor 50 and a variable resistor 52 connected in series. The fixed resistor 50 and the variable resistor 52 connected in series are connected between a power supply potential and a ground potential. The variable resistance circuit 48 outputs a second control voltage (V W2 ) occurs.

[0059] The variable resistor 52 may be, for example, a memristor. A memristor can be set to any analog resistance value depending on the amount of charge passing through it. A memristor is made of a thin film of metal and metal oxide. A memristor is made of, for example, tungsten, tungsten oxide, titanium nitride, etc. By using a memristor as the variable resistor 52 in this way, the control circuit 30 can control the second control voltage (V W2 ) can be controlled.

[0060] Such a variable resistor circuit 48 controls the second control voltage (V W2 ) for a long period of time. Furthermore, even when the variable resistance circuit 48 is connected to the short-term memory circuit 12 during the calibration process, there is no voltage drop due to charge transfer. Therefore, the multiplication device 10 according to the second modification including such a variable resistance circuit 48 can generate the first control voltage (V W1 ) can be generated from the short-term memory circuit 12 with high accuracy for a long period of time, so that multiplication processing can be performed with high accuracy for a long period of time.

[0061] 5 is a diagram showing a configuration of a multiplication device 10 according to a third modification of the first embodiment. The conversion circuit 16 according to the third modification has a plurality of resistors 54 and a plurality of selection switches 56.

[0062] The multiple resistors 54 are connected in series between the input terminal 36 and the output terminal 38. Each of the multiple resistors 54 has a different resistance value from the other resistors 54. For example, the first resistor 54 after the multiple resistors 54 has a resistance value of 2 0 ×R (R is any positive real number). The second resistor 54 is set to a resistance of 2 1 ×R. The resistance value of the A-th resistor 54 (A is an integer equal to or greater than 2) is set to 2 (A-1) ×R is set.

[0063] The plurality of selection switches 56 are provided in a one-to-one correspondence with the plurality of resistors 54. Each of the plurality of selection switches 56 is, for example, an FET that operates as a switch.

[0064] Each of the multiple selection switches 56 connects or disconnects both ends of a corresponding resistor 54 among the multiple resistors 54. Therefore, when each of the multiple selection switches 56 is in a connected state, it allows a current flowing from the input terminal 36 to the output terminal 38 to bypass the corresponding resistor 54. Also, when each of the multiple selection switches 56 is in a disconnected state, it allows a current flowing from the input terminal 36 to the output terminal 38 to flow via the corresponding resistor 54.

[0065] Such a conversion circuit 16 can change the conductance (G) between the input terminal 36 and the output terminal 38 by switching between the connection and disconnection states of the multiple selection switches 56 .

[0066] The multiplication device 10 of the third modified example includes a plurality of short-term memory circuits 12, a plurality of long-term memory circuits 14, a plurality of reference potential switches 20, a plurality of adjustment switches 22, a plurality of setting switches 24, a plurality of calibration switches 26, and a control circuit 30.

[0067] The short-term memory circuits 12 correspond one-to-one to the selection switches 56. Each of the short-term memory circuits 12 controls a first binary control voltage (V W1 ) occurs.

[0068] The multiple long-term memory circuits 14 correspond one-to-one to the multiple short-term memory circuits 12. Each of the multiple long-term memory circuits 14 receives the first control voltage (V W1 ) and the second control voltage (V W2 ) occurs.

[0069] The reference potential switches 20 correspond one-to-one to the short-term memory circuits 12. Each of the reference potential switches 20 shorts or disconnects a terminal opposite to the first terminal 12a of the corresponding short-term memory circuit 12 from the ground potential.

[0070] The multiple adjustment switches 22 correspond one-to-one to the multiple short-term memory circuits 12. During adjustment, each of the multiple adjustment switches 22 connects the first terminal 12a of the corresponding short-term memory circuit 12 to the ground potential or the power supply potential, causing the corresponding short-term memory circuit 12 to charge or discharge an electric charge.

[0071] The multiple setting switches 24 correspond one-to-one to the multiple long-term memory circuits 14. When set, each of the multiple setting switches 24 connects the second terminal 14a of the corresponding long-term memory circuit 14 to the ground potential or the power supply potential, causing the long-term memory circuit 14 to charge or discharge an electric charge.

[0072] The calibration switches 26 correspond one-to-one to the short-term memory circuits 12. Each of the calibration switches 26 connects the corresponding short-term memory circuit 12 to the corresponding long-term memory circuit 14 during calibration, allowing charge to be transferred from the corresponding long-term memory circuit 14 to the corresponding short-term memory circuit 12.

[0073] In the third modification, the control circuit 30 selects one or more of the multiple short-term memory circuits 12 in response to the received weight value, and outputs a first control voltage (V W1 In addition, the control circuit 30 generates a first control voltage (V W1 The control circuit 30 may select one or more short-term memory circuits 12 based on, for example, a table or a function indicating the correspondence between the weight value and the one or more short-term memory circuits 12 to be selected.

[0074] During calculation, the control circuit 30 controls the first control voltage (V W1 ) to the corresponding selection switch 56. This allows the conversion circuit 16 to pass a current through one or more resistors 54 corresponding to the selected one or more short-term memory circuits 12 among the multiple resistors 54 connected in series. Therefore, the conversion circuit 16 can vary the conductance (G) according to the weight value, and can set the conductance (G) between the input terminal 36 and the output terminal 38 to a value according to the weight value. As a result, during calculation, the conversion circuit 16 outputs the input voltage (V in ) multiplied by the conductance (G) to obtain the output current (I out = G × V in ) can be output.

[0075] The multiplication device 10 according to the third modification can change the conductance (G) by switching the resistors 54, and therefore can accurately represent the conductance (G) and perform multiplication with high accuracy. Furthermore, the multiplication device 10 according to the third modification requires only that each of the short-term memory circuits 12 generate a two-value voltage, which simplifies the control for generating a target voltage during adjustment. Furthermore, the multiplication device 10 according to the third modification requires only that each of the long-term memory circuits 14 generate a two-value voltage, which simplifies the control for generating a target voltage during setting.

[0076] 6 is a diagram showing the configuration of a multiplication device 10 according to a fourth modified example of the first embodiment. The multiplication device 10 according to the fourth modified example has the same configuration as that of the third modified example, except for the conversion circuit 16.

[0077] The conversion circuit 16 according to the fourth modification includes a plurality of Schottky barrier diodes 58 and a plurality of selection switches 56.

[0078] Each of the multiple Schottky barrier diodes 58 has a reverse voltage-current characteristic that allows a constant current (reverse current) to flow regardless of the voltage. For example, the reverse current of each of the multiple Schottky barrier diodes 58 is different from that of the other Schottky barrier diodes 58. For example, the first Schottky barrier diode 58 of the multiple Schottky barrier diodes 58 has a reverse current of 2 0 × I (I is any positive real number). The second Schottky barrier diode 58 flows a reverse current of 2 1 × I flows through the A-th Schottky barrier diode 58. (A-1) ×Pour I.

[0079] The selection switches 56 are provided in a one-to-one correspondence with the Schottky barrier diodes 58. Each of the selection switches 56 is, for example, an FET that operates as a switch.

[0080] Each of the plurality of Schottky barrier diodes 58 is connected in series with a corresponding selection switch 56. The series-connected Schottky barrier diodes 58 and selection switches 56 are connected between the input terminal 36 and the output terminal 38.

[0081] Each of the multiple selection switches 56 is connected or disconnected. Therefore, when each of the multiple selection switches 56 is in a connected state, it is possible for a current to flow from the input terminal 36 to the output terminal 38 via the corresponding Schottky barrier diode 58. When each of the multiple selection switches 56 is in a disconnected state, it is possible for a current not to flow from the input terminal 36 to the output terminal 38 via the corresponding Schottky barrier diode 58.

[0082] Such a conversion circuit 16 can change the conductance (G) between the input terminal 36 and the output terminal 38 by switching between the connection and disconnection states of the multiple selection switches 56 .

[0083] The multiplication device 10 according to the fourth modification can change the conductance (G) by switching the multiple Schottky barrier diodes 58, and can therefore accurately represent the conductance (G) and perform multiplication with high accuracy. in ) is no longer dependent on the input voltage (V in However, the multiplication device 10 according to the fourth modification cannot perform a multiplication and accumulation operation using an input voltage (V in When Io is 0, a constant current is output regardless of the voltage error, so a stable output current (Io ut ) can be output.

[0084] Moreover, the Schottky barrier diode 58 can reduce the reverse current to the order of nA and operates stably. Therefore, the multiplication device 10 according to the fourth modification can achieve low power consumption. However, the multiplication device 10 according to the fourth modification must include a rectifier circuit 18 and perform rectification so that no forward current flows through the Schottky barrier diode 58. In the fourth modification, the rectifier circuit 18 has a conductance sufficiently larger than the reverse voltage-current characteristics of the Schottky barrier diode 58, and suppresses the amount of current to a sufficiently low level when a reverse voltage is applied.

[0085] Second embodiment FIG. 7 is a diagram showing a configuration of a signed multiplication device 60 according to the second embodiment.

[0086] The signed multiplication device 60 according to the second embodiment outputs an output value obtained by multiplying an input value with a positive or negative sign by a weight value with a positive or negative sign.

[0087] The signed multiplication device 60 multiplies the positive and negative input voltages (V in ) is received. The signed multiplication device 60 is set with a positive or negative conductance (G) according to the weight value. The signed multiplication device 60 receives an input voltage (V in ) and conductance (G) multiplied to obtain the output voltage (V out = G × V in ) is output as the output value. out ) is a given common voltage (e.g., 1 / 2×V DD ) is set to 0, and the common voltage is set to 0 and is expressed as positive or negative.

[0088] The signed multiplication device 60 includes an absolute value circuit 62, an encoding circuit 64, a selector 66, a first multiplication circuit 10-pp, a second multiplication circuit 10-pn, a third multiplication circuit 10-np, a fourth multiplication circuit 10-nn, a first current mirror circuit 68-pp, a second current mirror circuit 68-pn, a third current mirror circuit 68-np, a fourth current mirror circuit 68-nn, an output capacitor 70, an output current mirror circuit 72, and a main control circuit 74.

[0089] The absolute value circuit 62 converts the input voltage (V in ) and the input voltage (V in ) is converted to an absolute value, in The encoding circuit 64 outputs the input voltage (V in ) and the input voltage (V in ) is encoded into a code signal (sing(V in For example, the encoding circuit 64 outputs an input voltage (V in ) is 0 or greater, it represents 1, and the input voltage (V in If V is negative, the sign signal (sing(V in )).

[0090] The selector 66 selects the absolute input voltage (|V in |), and the sign signal (sing(V in The selector 66 receives the sign signal (sing(V in ) is 1, i.e., when the input voltage (V in ) is greater than or equal to 0, the absolute input voltage (|V in The selector 66 outputs the sign signal (sing(V in ) is 0, i.e., when the input voltage (V in ) is negative, the absolute input voltage (|V in |) is output from the second output terminal 66-2.

[0091] The first multiplier circuit 10-pp, the second multiplier circuit 10-pn, the third multiplier circuit 10-np and the fourth multiplier circuit 10-nn have the same configurations as those in the first embodiment and the respective modifications of the first embodiment.

[0092] The first multiplier circuit 10-pp and the second multiplier circuit 10-pn multiply the absolute input voltage (|V in |) to the input voltage (V in ) and the output current (I outThe third multiplier circuit 10-np and the fourth multiplier circuit 10-nn output the absolute input voltage (|V in |) to the input voltage (V in ) and the output current (I out ) to output.

[0093] The first current mirror circuit 68-pp mirrors the output current (I out ) and the received output current (I out The second current mirror circuit 68-pn outputs a first reference current that is the same as the output current (I out ) and the received output current (I out ) outputs a second reference current that is the same as

[0094] The third current mirror circuit 68-np mirrors the output current (I out ) and the received output current (I out The fourth current mirror circuit 68-nn outputs a third reference current that is the same as the output current (I out ) and the received output current (I out ) outputs a fourth reference current that is the same as

[0095] The output current mirror circuit 72 receives a current obtained by adding the first reference current output from the first current mirror circuit 68-pp and the fourth reference current output from the fourth current mirror circuit 68-nn. The output current mirror circuit 72 then outputs a positive-side combined current (I outp ) to output.

[0096] The output capacitor 70 is provided between the voltage output terminal 76 and the ground potential.

[0097] The output capacitor 70 outputs a positive combined current (I outp) and the positive combined current (I outp ) is stored in the second current mirror circuit 68-pn and the third current mirror circuit 68-np. The second current mirror circuit 68-pn and the third current mirror circuit 68-np output a negative combined current (I outn ) is sucked out.

[0098] Such an output capacitor 70 reduces the output current (I out ), and the second multiplier circuit 10-pn and the third multiplier circuit 10-np output currents (I out ) the charge is discharged according to

[0099] The main control circuit 74 receives the weight values ​​from an external device.

[0100] When the weighting value is 0 or more, the main control circuit 74 provides the absolute value of the weighting value to the first multiplier circuit 10-pp and the third multiplier circuit 10-np, and makes the first multiplier circuit 10-pp and the third multiplier circuit 10-np set the conductance (G) according to the absolute value of the weighting value. When the weighting value is 0 or more, the main control circuit 74 provides the second multiplier circuit 10-pn and the fourth multiplier circuit 10-nn with a weighting value of 0, and makes them set the conductance (G) to 0.

[0101] When the weighting value is negative, the main control circuit 74 provides the absolute value of the weighting value to the second multiplier circuit 10-pn and the fourth multiplier circuit 10-nn, causing the second multiplier circuit 10-pn and the fourth multiplier circuit 10-nn to set the conductance (G) according to the absolute value of the weighting value. When the weighting value is negative, the main control circuit 74 provides the first multiplier circuit 10-pp and the third multiplier circuit 10-np with a weighting value of 0, causing the conductance (G) to be set to 0.

[0102] The signed multiplication device 60 configured as above operates as follows.

[0103] First, the output capacitor 70 is connected to a predetermined common voltage (for example, 1 / 2×V DD The amount of charge to be stored is adjusted so that the signed multiplication device 60 generates an input voltage (V in ) and perform the multiplication operation.

[0104] When the input value is equal to or greater than 0 and the weight value is equal to or greater than 0, the first multiplier circuit 10-pp multiplies the absolute value of the input value by the absolute value of the weight value to produce an output current (I out In this case, the output capacitor 70 outputs the output current (I out ) is charged, and the voltage corresponding to the multiplication value is output as the output voltage (V out ) to increase

[0105] When the input value is equal to or greater than 0 and the weight value is negative, the second multiplier circuit 10-pn multiplies the absolute value of the input value by the absolute value of the weight value to produce an output current (I out In this case, the output capacitor 70 outputs the output current (I out ) is discharged, and the voltage corresponding to the multiplication value is output as the output voltage (V out ) to reduce

[0106] When the input value is negative and the weight value is equal to or greater than 0, the third multiplier circuit 10-np multiplies the absolute value of the input value by the absolute value of the weight value to produce an output current (I out In this case, the output capacitor 70 outputs the output current (I out ) is discharged, and the voltage corresponding to the multiplication value is output as the output voltage (V out ) to reduce

[0107] When the input value is negative and the weight value is negative, the fourth multiplier circuit 10-nn multiplies the absolute value of the input value by the absolute value of the weight value to produce an output current (I outIn this case, the output capacitor 70 outputs the output current (I out ) is charged, and the voltage corresponding to the multiplication value is output as the output voltage (V out ) to increase

[0108] Then, the signed multiplication device 60 calculates a voltage according to the charge stored in the output capacitor 70 as the output voltage (V out ) from the voltage output terminal 76. In this way, the signed multiplication device 60 multiplies the output value obtained by multiplying the input value with a positive or negative sign by the weight value with a positive or negative sign, and outputs the output voltage (V out ) can be output.

[0109] Third embodiment FIG. 8 is a diagram showing the configuration of a product-sum calculation device 80 according to the third embodiment. The product-sum calculation device 80 according to the third embodiment outputs a product-sum calculation value obtained by performing a product-sum calculation on M input values ​​(M is an integer equal to or greater than 2) and M weight values. The product-sum calculation device 80 outputs M input voltages (V in_1 ~V in_M ) is received. The product-sum calculation device 80 then calculates the product-sum current (I acc ) is output as the sum of products.

[0110] The product-sum calculation device 80 includes M multiplication devices 10 (10-1 to 10-M) and an output line 82. Each of the M multiplication devices 10 has the same configuration as the first embodiment and each modified example of the first embodiment.

[0111] The M multiplication devices 10 correspond one-to-one to the M weight values. An m-th multiplication device 10-m (m is an integer between 1 and M) among the M multiplication devices 10 outputs an output value obtained by multiplying an m-th input value among the M input values ​​by an m-th weight value among the M weight values. In other words, the m-th multiplication device 10-m outputs an input voltage (V in_m ) The m-th multiplier 10-m receives the m-th conductance (G_m ) is set. Then, the m-th multiplication device 10-m receives the m-th input voltage (V in ) and the mth conductance (G _m ) and the output current (I out =G _m ×V in_m ) as the output value.

[0112] Each of the M multipliers 10 outputs an output current (I out ) to the output line 82. The output current (I out ) are summed on output line 82. Thus, output line 82 represents the output current (I out ) is added to the sum of the current (I acc ) is output as a product-sum operation value obtained by performing a product-sum operation on M input values ​​and M weight values.

[0113] The above-described product-sum calculation device 80 performs product-sum calculations using M multiplication devices 10, and therefore can execute high-resolution, highly accurate product-sum calculation processing with a very simple configuration.

[0114] (Fourth embodiment) FIG. 9 is a diagram showing the configuration of a matrix calculation device 90 according to the fourth embodiment. The matrix calculation device 90 according to the fourth embodiment performs a matrix calculation on M column input values ​​and M row×N column weight values ​​(N is an integer equal to or greater than 1) and outputs N column product-sum calculation values. The matrix calculation device 90 generates M input voltages (V in_1 ~V in_M ) is received. The matrix calculation device 90 then calculates N product-sum currents (I acc_1 ~I acc_N ) is output as the sum of products of N columns.

[0115] The matrix calculation device 90 includes M×N multiplication devices 10 (10-1, 1 to 10-M, N) and N output lines 82 (82-1 to 82-N). Each of the M multiplication devices 10 has the same configuration as the first embodiment and each modified example of the first embodiment.

[0116] The M×N multiplication devices 10 correspond one-to-one to the weight values ​​of the M rows×N columns. A multiplication device 10-m,n corresponding to the nth column in the mth row (n is an integer between 1 and N) among the M×N multiplication devices 10 outputs an output value obtained by multiplying an input value in the mth column among the input values ​​in the M columns by a weight value in the nth column in the mth row among the weight values ​​of the M rows×N columns.

[0117] That is, the multiplication device 10-m,n corresponding to the n-th column in the m-th row outputs an input voltage (V in_m ) is received. Also, the multiplication device 10-m,n corresponding to the n-th column in the m-th row receives a conductance (G _m,n ) is set. The multiplication device 10-m,n corresponding to the n-th column in the m-th row outputs an input voltage (V in_m ) and the conductance of the nth column in the mth row (G _m,n ) and the output current (I out =G _m,n ×V in_m ) as the output value.

[0118] Each of the M multipliers 10-1,m to 10-M,m corresponding to the n-th column among the M×N multipliers 10 outputs an output current (I out ) to the n-th output line 82 among the N output lines 82. The output current (I out ) are added in the n-th output line 82. Therefore, the n-th output line 82 receives the output currents (I out ) is added together to obtain the sum of M currents (I acc_1 ~I acc_N ) the nth product sum current (I acc_n) as a result of which the N output lines 82 output N sum-of-product currents (I acc_1 ~I acc_N ) can be output as the sum of products of N columns.

[0119] The above-described matrix calculation device 90 performs matrix calculations using M×N multiplication devices 10 (10-1, 1 to 10-M, N), and therefore can execute high-resolution, highly accurate product-sum calculation processing with a very simple configuration.

[0120] Fifth embodiment 10 is a diagram showing a configuration of a reservoir device 110 according to the fifth embodiment. The reservoir device 110 is one of recurrent neural networks. The reservoir device 110 according to this embodiment is realized using an analog circuit.

[0121] The reservoir device 110 receives a time-series input signal. The time-series input signal is a signal whose value changes in the time direction. In this embodiment, the time-series input signal is a voltage signal whose value is represented by an analog voltage. The time-series input signal may be a time-series digital signal.

[0122] Then, the reservoir device 110 outputs one or more time series inference signals. Each of the one or more time series inference signals is a signal whose value changes in the time direction. In this embodiment, each of the one or more time series inference signals is a voltage signal whose value is represented by an analog voltage. Each of the one or more time series inference signals may be a time-series digital signal.

[0123] Each of the one or more time series inference signals may be, for example, a signal representing a feature of the time series input signal. For example, each of the one or more time series inference signals may be the same signal as the time series input signal, or may be a signal obtained by inferring the time series input signal after a predetermined time. Furthermore, each of the one or more time series inference signals may be a signal representing an abnormality in the time series input signal at present or after a predetermined time, or may be a signal representing a feature component obtained by removing noise, etc. from the time series input signal.

[0124] The reservoir device 110 includes an input circuit 112 , a reservoir circuit 114 , an output circuit 116 , and a learning control circuit 118 .

[0125] The input circuit 112 receives a time-series input signal, and outputs a time-series pre-processed signal obtained by performing a predetermined process on the time-series input signal. For example, the input circuit 112 obtains a reference signal representing a reference waveform, and outputs a time-series pre-processed signal representing the difference between the time-series signal and the reference signal. Alternatively, the input circuit 112 may output the time-series input signal as it is as the time-series pre-processed signal.

[0126] The reservoir circuit 114 includes a plurality of synapse circuits 122 and a plurality of neuron circuits 124. In this embodiment, each of the plurality of synapse circuits 122 and each of the plurality of neuron circuits 124 are realized by analog circuits.

[0127] A synapse weight is set for each of the plurality of synapse circuits 122. Each of the plurality of synapse circuits 122 receives an ignition signal from any one of the plurality of neuron circuits 124. Each of the plurality of synapse circuits 122 supplies a signal, which is the received ignition signal and is influenced by the set synapse weight, to any one of the plurality of neuron circuits 124. For example, the synapse weight may be expressed by two values, 1 and -1, or may be expressed by three values, such as 1, -1, and 0. The synapse weight may be expressed by a multi-value of three or more values, or a continuous value. Each of the plurality of synapse circuits 122 may delay the ignition signal according to the set synapse weight. Each of the plurality of synapse circuits 122 may change the level of the ignition signal according to the set synapse weight. Each of the plurality of synapse circuits 122 may be configured to receive an ignition signal but not output a signal when the set synapse weight is set to 0 among the three values, 1, -1, and 0.

[0128] Each of the multiple neuron circuits 124 receives a signal from one or more of the multiple synapse circuits 122. Some of the multiple neuron circuits 124 receive a time-series pre-processed signal from the input circuit 112. The neuron circuit 124 that receives the time-series pre-processed signal may further receive a signal from one or more of the synapse circuits 122 in addition to the time-series pre-processed signal.

[0129] Each of the neuron circuits 124 accumulates one or more received signals, performs activation function processing on the accumulated value, and outputs an ignition signal. Each of the neuron circuits 124 may perform threshold processing on the accumulated value, or may output an ignition signal probabilistically for the accumulated value. The ignition signal is, for example, a pulse waveform that becomes H logic at the timing of ignition and becomes L logic a certain time after becoming H logic.

[0130] Here, at least one of the neuron circuits 124 has an ignition signal outputted from itself fed back via one or more synapse circuits 122. For example, the neuron circuit 124 may have an ignition signal outputted from itself fed back via the synapse circuit 122 directly to itself. Also, the neuron circuit 124 may have an ignition signal outputted from itself fed back via the multiple synapse circuits 122 and one or more other neuron circuits 124. In this way, the reservoir circuit 114 can configure a recurrent neural network.

[0131] The reservoir circuit 114 may be capable of arbitrarily switching the connection relationship between the plurality of synapse circuits 122 and the plurality of neuron circuits 124. For example, the reservoir circuit 114 may have a module circuit in which the output terminals of the plurality of neuron circuits 124 are connected to all the input terminals of the plurality of neuron circuits 124 via different synapse circuits 122. In this case, the module circuit is capable of switching between enabling and disabling each of the plurality of synapse circuits 122 from the learning control circuit 118. The enabled synapse circuit 122 outputs a signal that is the result of adding the influence of a synapse weight to the received firing signal. The disabled synapse circuit 122 does not output a signal even if it receives a firing signal. The reservoir circuit 114 may include a plurality of such module circuits, and the connection between the modules may be configurable.

[0132] The reservoir circuit 114 outputs M firing signals output from M neuron circuits 124 among the plurality of neuron circuits 124 as M time-series intermediate signals. The reservoir circuit 114 may be capable of arbitrarily selecting M neuron circuits 124 that output M time-series intermediate signals from among all the plurality of neuron circuits 124.

[0133] The output circuit 116 includes a matrix calculation device 90 and N voltage conversion circuits 132 .

[0134] The matrix calculation device 90 is the same as the circuit described in the fourth embodiment. The matrix calculation device 90 receives M time-series intermediate signals from the reservoir circuit 114 as M input values. Then, the matrix calculation device 90 calculates N product-sum currents (I acc ) to output.

[0135] The N voltage conversion circuits 132 generate N product-sum currents (I acc Each of the N voltage conversion circuits 132 outputs N product-sum currents (I acc ) corresponding product sum current (I acc ) into a voltage signal and output as the corresponding time series inference signal among the N time series inference signals.

[0136] Such an output circuit 116 can output N time series inference signals. Note that the output circuit 116 may be configured to include only a portion of the N voltage conversion circuits 132. In this case, the output circuit 116 outputs one or more time series inference signals, the number of which is less than N. Also, such an output circuit 116 may binarize the time series inference signal and output a digital time series inference signal.

[0137] In the learning process, the learning control circuit 118 sets synapse weights to be set in the plurality of synapse circuits 122 included in the reservoir circuit 114 and weight values ​​for the M×N multiplication devices 10 included in the matrix calculation device 90.

[0138] 11 is a flowchart showing the flow of processing of the reservoir device 110. The reservoir device 110 executes processing according to the flow shown in FIG.

[0139] First, in S21, the learning control circuit 118 sets the connection relationships and the synapse weights of each of the plurality of synapse circuits 122 and the plurality of neuron circuits 124 in the reservoir circuit 114. The learning control circuit 118 may set the connection relationships and the synapse weights based on information defined by a user or the like. The learning control circuit 118 may also set the connection relationships and the synapse weights randomly.

[0140] Next, in S22, the learning control circuit 118 executes a learning process. In the learning process, the learning control circuit 118, for example, supplies a predetermined learning input signal to the input circuit 112 as a time-series input signal. Next, the learning control circuit 118 compares a time-series inference signal output from the output circuit 116 in response to the input of the learning input signal with a predetermined teacher signal. Then, the learning control circuit 118 changes the weight values ​​set for each of the M×N multiplication devices 10 included in the matrix calculation device 90, for example, so that the time-series inference signal matches the teacher signal.

[0141] In the learning process, the learning control circuit 118 charges and discharges the short-term memory circuit 12 in each of the M×N multiplication devices 10 included in the matrix calculation device 90, and controls the first control voltage (V W1 That is, in the learning process, the learning control circuit 118 adjusts the second control voltage (V W2 ) is not changed. As a result, the learning control circuit 118 causes each of the M×N multiplication devices 10 to charge and discharge the short-term memory circuit 12 with a relatively small time constant, thereby enabling the weight values ​​to be updated at high speed.

[0142] When the weight values ​​of the M×N multiplication devices 10 included in the matrix calculation device 90 are set so that the time-series inference signal coincides with the teacher signal, the learning control circuit 118 ends the learning process. After the learning process, the learning control circuit 118 advances the process to S23.

[0143] In S23, the learning control circuit 118 executes the setting process for each of the M×N multiplication devices 10. That is, after the learning process, the learning control circuit 118 controls the second control voltage (V W2 ) is generated by the short-term memory circuit 12 as a first control voltage (V W1 ) to match the weight values. This allows the learning control circuit 118 to store the weight values ​​with high accuracy for a long period of time in each of the M×N multiplication devices 10. After the setting process, the learning control circuit 118 advances the process to S24.

[0144] In S24, the learning control circuit 118 causes the input circuit 112, the reservoir circuit 114, and the output circuit 116 to execute an inference process. That is, after the setting process, the learning control circuit 118 inputs a time-series input signal and outputs a time-series inference signal.

[0145] Next, in S25, the learning control circuit 118 judges whether it is time for calibration. The calibration timing is, for example, every predetermined time interval or every time a predetermined event occurs. If it is not time for calibration (No in S25), the learning control circuit 118 returns the process to S24 and continues the inference process. If it is time for calibration (Yes in S25), the learning control circuit 118 advances the process to S26.

[0146] In S26, the learning control circuit 118 executes a calibration process for each of the M×N multiplication devices 10. Specifically, the learning control circuit 118 causes the first control voltage (V W1 ) is generated by the long-term memory circuit 14 in response to a second control voltage (V W2 ) to match.

[0147] When the learning control circuit 118 finishes the process of S26, it returns the process to S24 and continues the inference process. The reservoir device 110 as described above uses M×N multiplication devices 10 to learn and infer weight values, and therefore can execute high-resolution, highly accurate product-sum calculation processing with a very simple configuration.

[0148] Furthermore, in the learning process, the reservoir device 110 updates the weights by charging and discharging electric charges to the short-term memory circuits 12 included in each of the M×N multiplication devices 10. This allows the reservoir device 110 to update the weight values ​​quickly and accurately.

[0149] Furthermore, after the learning process is completed, the reservoir device 110 stores the weight values ​​in the long-term memory circuits 14 included in each of the M×N multiplication devices 10. This allows the reservoir device 110 to store the weight values ​​with high accuracy for a long period of time.

[0150] Furthermore, at the calibration timing, the reservoir device 110 causes each of the M×N multiplication devices 10 to transfer electric charges from the long-term memory circuit 14 to the short-term memory circuit 12 to execute a calibration process. This allows the reservoir device 110 to continue storing weight values ​​in the short-term memory circuit 12 with high accuracy for a long period of time.

[0151] As described above, the reservoir device 110 can update the weight values ​​with high accuracy in a short time and store the weight values ​​with high accuracy for a long period of time, thereby enabling the reservoir device 110 to output a high-accuracy inference signal for a long period of time.

[0152] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0153] 10 Multiplication Device 12 Short-term memory circuit 14 Long-term memory circuit 16 Conversion circuit 18 Rectifier circuit 20 Reference potential switch 22 Adjustment switch 24 Setting Switch 26 Calibration Switch 30 Control circuit 32 Short-term Memory Capacitor 34 Long-term memory capacitor 36 Input terminals 38 Output terminal 40 Control terminal 42 Field-effect transistor 46 Energy storage element 48 Variable Resistor Circuit 50 fixed resistor 52 Variable resistor 54 Resistance 56 Selection switch 58 Schottky Barrier Diode 60 Signed Multiplication Unit 80 Multiply-and-accumulate unit 82 Output line 110 Reservoir device 112 Input circuit 114 Reservoir Circuit 116 Output circuit 118 Learning control circuit 122 Synapse Circuit 124 Neuronal Circuits 132 Voltage conversion circuit

Claims

1. A multiplication device that outputs an output value obtained by multiplying an input value by a weighting value, a short-term memory circuit that holds charges and generates a first control voltage according to the weight value based on the held charges; a long-term memory circuit that generates a second control voltage according to the weighting value by using a circuit having a larger time constant than the short-term memory circuit; a conversion circuit whose conductance is changed in response to a voltage applied to a control terminal, and which outputs from an output terminal a current obtained by multiplying the voltage applied to an input terminal by the conductance; A control circuit; Equipped with the conversion circuit applies the first control voltage generated from the short-term memory circuit to the control terminal and applies an input voltage corresponding to the input value to the input terminal, thereby outputting an output current obtained by multiplying the input voltage and the conductance from the output terminal as the output value; The control circuit performs a calibration process to match the first control voltage generated from the short-term memory circuit to the second control voltage generated from the long-term memory circuit by transferring charges from the long-term memory circuit to the short-term memory circuit. Multiplication device.

2. the control circuit performs an adjustment process of storing, in the short-term memory circuit, an amount of charge for generating the first control voltage according to the weight value, by charging or discharging the short-term memory circuit; After the adjustment process, the control circuit executes a setting process to make the second control voltage generated from the long-term memory circuit coincide with the first control voltage generated from the short-term memory circuit.

2. The multiplication device according to claim 1.

3. The control circuit executes the calibration process at predetermined time intervals or whenever a predetermined event occurs.

3. The multiplication device according to claim 1 or 2.

4. The conversion circuit is a field effect transistor. A multiplication device according to any one of claims 1 to 3.

5. The short-term memory circuit includes a capacitor. A multiplication device according to any one of claims 1 to 4.

6. The long-term memory circuit holds charge using a circuit with a larger time constant than the short-term memory circuit, and generates the second control voltage according to the weight value using the held charge. A multiplication device according to any one of claims 1 to 5.

7. The long-term memory circuit includes a capacitor.

7. The multiplication device according to claim 6.

8. The long-term memory circuit includes a storage element.

7. The multiplication device according to claim 6.

9. The long-term memory circuit is a variable resistor. A multiplication device according to any one of claims 1 to 5.

10. A multiply-and-accumulate device that outputs a multiply-and-accumulate value obtained by multiplying and accumulating M input values ​​(M is an integer equal to or greater than 2) and M weight values, M multiplication devices corresponding to the M weight values; An output line; A control circuit; Equipped with an m-th multiplication device (m is an integer between 1 and M) among the M multiplication devices outputs an output value obtained by multiplying an m-th input value among the M input values ​​by an m-th weight value among the M weight values; The mth multiplication device a short-term memory circuit that holds charges and generates a first control voltage according to the m-th weight value based on the held charges; a long-term memory circuit that generates a second control voltage according to the m-th weighting value by using a circuit having a larger time constant than that of the short-term memory circuit; a conversion circuit whose conductance is changed in response to a voltage applied to a control terminal, and which outputs from an output terminal a current obtained by multiplying the voltage applied to an input terminal by the conductance; having the conversion circuit outputs an output current corresponding to the output value from the output terminal to the output line by applying the first control voltage generated from the short-term memory circuit to the control terminal and applying an input voltage corresponding to the m-th input value to the input terminal; the output line outputs a product-sum current obtained by adding up the output currents output from the M multiplication devices as the product-sum operation value; The control circuit performs a calibration process for each of the M multiplication devices to match the first control voltage generated from the short-term memory circuit with the second control voltage generated from the long-term memory circuit. Multiply-and-accumulate unit.

11. The m-th multiplication device further includes a rectifier circuit that causes the output current to flow in a predetermined first direction from the output terminal and blocks a current in a direction opposite to the first direction. The multiply-add operation device according to claim 10.

12. 1. A matrix calculation device that performs a matrix calculation on M column input values ​​(M is an integer of 2 or more) and M row by N column weight values ​​(N is an integer of 1 or more) to output N column product-sum calculation values, M×N multiplication devices corresponding to the weight values ​​of the M rows by N columns; N output lines corresponding to the N columns of product-sum values; A control circuit; Equipped with a multiplication device corresponding to an n-th column (n is an integer between 1 and N) in an m-th row (m is an integer between 1 and M) among the M×N multiplication devices outputs an output value obtained by multiplying an input value in an m-th column among the input values ​​in the M columns by a weight value in an n-th column in an m-th row among the weight values ​​of the M rows×N columns; A multiplication unit corresponding to the n-th column in the m-th row is a short-term memory circuit that holds charges and generates a first control voltage according to the weight value of the n-th column in the m-th row based on the held charges; a long-term memory circuit that generates a second control voltage according to the weight value of the n-th column in the m-th row by using a circuit with a larger time constant than that of the short-term memory circuit; a conversion circuit whose conductance is changed in response to a voltage applied to a control terminal, and which outputs from an output terminal a current obtained by multiplying the voltage applied to an input terminal by the conductance; having the conversion circuit outputs an output current corresponding to the output value from the output terminal to an n-th output line among the N output lines by applying to the control terminal the first control voltage generated from the short-term memory circuit and applying to the input terminal an input voltage corresponding to the m-th input value among the M input values; the n-th output line outputs a product-sum current obtained by adding up the output currents output from M multipliers corresponding to the n-th column among the M×N multipliers as a product-sum value of the n-th column among the product-sum values ​​of the N columns; The control circuit performs a calibration process for each of the M×N multiplication devices to match the first control voltage generated from the short-term memory circuit to the second control voltage generated from the long-term memory circuit. Matrix calculation device.

13. The multiplication device corresponding to the n-th column in the m-th row further includes a rectifier circuit that causes the output current to flow in a predetermined first direction from the output terminal and blocks a current in a direction opposite to the first direction. The matrix calculation device according to claim 12.

14. A reservoir device including the matrix calculation device according to claim 13, receiving a time series input signal and outputting one or more time series inference signals, an input circuit that outputs a time-series pre-processed signal corresponding to the time-series input signal; a reservoir circuit, which is a recurrent neural network, that receives the time-series pre-processed signal and outputs M time-series intermediate signals (M is an integer equal to or greater than 2); an output circuit for receiving the M time-series intermediate signals and outputting a time-series inference signal; Equipped with The output circuit includes: The matrix calculation device; A voltage conversion circuit; having the matrix calculation device receives the M time-series intermediate signals as the M column input values, and outputs N product-sum currents; The voltage conversion circuit converts a predetermined one of the N product-sum currents into a voltage signal and outputs the voltage signal as the time-series inference signal. Reservoir device.

15. the reservoir circuit includes a plurality of synapse circuits and a plurality of neuron circuits; Each of the plurality of synapse circuits has a synapse weight set, receives an ignition signal from any one of the plurality of neuron circuits, and supplies a signal that is the ignition signal that has been influenced by the set synapse weight to any one of the plurality of neuron circuits; Each of the plurality of neuron circuits outputs the firing signal according to an accumulated value of received signals; At least one of the plurality of neuron circuits has the firing signal outputted from the neuron circuit fed back via one or more synapse circuits.

15. The reservoir device of claim 14.

16. A learning control circuit is further provided, The learning control circuit includes: In a learning process, a predetermined learning input signal is supplied to the input circuit as the time series input signal, the time series inference signal is compared with a teacher signal, the weight values ​​to be given to each of the M×N multiplication devices are updated, and each of the M×N multiplication devices is caused to adjust the first control voltage generated from the short-term memory circuit; After the learning process, a setting process is performed for each of the M×N multiplication devices to make the second control voltage generated from the long-term memory circuit coincide with the first control voltage generated from the short-term memory circuit; After the setting process, an inference process is executed to input the time-series input signal and output the time-series inference signal; After the learning process is completed, the calibration process is executed at predetermined time intervals or whenever a predetermined event occurs.

16. The reservoir device of claim 15.

17. Prior to the learning process, the learning control circuit randomly sets the synapse weights of the plurality of synapse circuits and the neuron circuits connected to the plurality of synapse circuits.

17. The reservoir device of claim 16.

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