Display device

Abstract

To provide a metal oxide film including a crystal part and also to provide the metal oxide film having high stability of physical properties.SOLUTION: Provided is a metal oxide film having a new structure in which a plurality of spots circumferentially arranged together with a halo pattern showing an amorphous state are observed in an electron diffraction pattern using nanobeam electron diffraction. Each of the plurality of spots is unlike a spot having regularity indicating a crystalline state oriented in a particular plane and does not have directionality. Moreover, in the metal oxide film, the plurality of spots is not observed in a selected visual field electron diffraction pattern.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One embodiment of the present invention is, for example, a semiconductor device, a display device, a light-emitting device, a driving method thereof, or a In particular, one aspect of the present invention relates to a metal oxide film and a method for producing the same. The present invention relates to a method for forming a film, and also to a semiconductor device using the metal oxide film.

[0002] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This refers to devices in general, and electro-optical devices, semiconductor circuits, and electronic equipment are all classified as semiconductor devices. [Background technology]

[0003] The technology of constructing transistors using semiconductor films formed on substrates with insulating surfaces is attracting attention. The transistor is used in integrated circuits (ICs) and image display devices (also called simply display devices). Semiconductors that can be used in transistors are widely used in electronic devices such as Silicon-based semiconductor materials are widely known as films, but other materials with semiconductor properties are also available. Metal oxides (oxide semiconductors) exhibiting the above properties have been attracting attention.

[0004] For example, amorphous oxides containing In, Zn, Ga, Sn, etc. are used as oxide semiconductors. A technique for fabricating a transistor is disclosed in Patent Document 1. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2006-165529 A Summary of the Invention [Problem to be solved by the invention]

[0006] An object of one embodiment of the present invention is to provide a metal oxide film including crystal parts.

[0007] Another object of one embodiment of the present invention is to provide a metal oxide film having highly stable physical properties. Let us assume that.

[0008] Another embodiment of the present invention provides a highly reliable semiconductor device using the above-described metal oxide film or the like. The objective of the project is to provide

[0009] Another object of one embodiment of the present invention is to provide a novel semiconductor device. The description of these problems does not preclude the existence of other problems. It is not necessary to solve all of these problems. Problems other than these may be solved by the specification. The above will become apparent from the description, drawings, claims, etc. From descriptions such as these, it is possible to extract other issues. [Means for solving the problem]

[0010] One embodiment of the disclosed invention is a method for manufacturing a semiconductor device in which the atomic arrangement is not periodic when viewed macroscopically, or The metal oxide film includes extremely fine crystal parts to the extent that no long-range order is observed. The metal oxide film of the present embodiment has a halide film showing an amorphous state in the selected area electron diffraction pattern of the film plane. A low pattern was observed, and a halo pattern was observed in the cross-sectional nanobeam electron diffraction pattern. The spots are not observed, and have a specific orientation, which is different from the regular spots that indicate crystals oriented in a specific plane. More specifically, for example, the following configuration is included: It is a metal oxide film.

[0011] In one aspect of the present invention, a nanobeam electron diffraction pattern of a cross section shows multiple circularly distributed particles. The metal oxide film is characterized by including an area in which a number of spots are observed.

[0012] In addition, one aspect of the present invention is a method for producing a nanobeam electron diffraction pattern of a cross section of a circumferentially distributed A number of spots were observed, and the selected area electron diffraction pattern of the planar structure showed The metal oxide film is characterized by including an area in which a row pattern is observed.

[0013] In the above, the measurement range in the selected area electron diffraction pattern is 300 nmφ or more. It is preferred.

[0014] In the above, the measurement range of nanobeam electron diffraction is set to 5 nmφ or more and 10 nmφ or less. It is preferable to irradiate the electron beam with a beam diameter of 1 nmφ. A nanobeam electron diffraction pattern is obtained with a measurement range of 5 nmφ to 10 nmφ. This can be done.

[0015] In addition, the above nanobeam electron diffraction pattern shows that the thickness of the film is greater than 10 nm and less than 50 nm. It is preferable that the pattern is a nanobeam electron diffraction pattern of a cross section of a thin sliced ​​sample.

[0016] In the above, the metal oxide film includes a crystal portion, and the size of the crystal portion is 10 nm or less. Alternatively, it is preferably 1 nm or more and 10 nm or less.

[0017] In addition, one aspect of the present invention is a metal oxide film including a crystalline portion, the crystalline portion being within a measurement range of 5 In nanobeam electron diffraction with a diameter of 10 nm or more and 10 nm or less, the metal oxide film is In the cross-sectional diffraction pattern of a slice with a thickness of greater than m and less than 50 nm, Several spots were observed, and the cross-section of the metal oxide film sliced ​​to a thickness of 10 nm or less was In the folding pattern, areas with regular spots showing crystals oriented in a specific plane were observed. The metal oxide film is characterized by including a region.

[0018] In any one of the above metal oxide films, the metal oxide film is at least indium. It is preferable that the material contains aluminum, gallium or zinc.

[0019] In another aspect of the present invention, an oxide target is heated at room temperature in an atmosphere containing oxygen. By using this material for sputtering, the nanobeam electron diffraction pattern in the cross-sectional direction was A metal oxide film including an area where a plurality of spots distributed in a circumferential shape are observed is formed. The present invention relates to a method for forming a metal oxide film.

[0020] In the above-mentioned method for forming a metal oxide film, the partial pressure of oxygen is 33% or more in an atmosphere. It is preferable to form a film. Effect of the Invention

[0021] According to one embodiment of the present invention, a metal oxide film including a crystal part can be provided.

[0022] According to one embodiment of the present invention, a metal oxide film having highly stable physical properties can be provided. In addition, by applying the metal oxide film to a semiconductor device, a highly reliable semiconductor device can be provided. It can be provided. [Brief description of the drawings]

[0023] [Figure 1]1 shows a cross-sectional TEM image and a nanobeam electron diffraction pattern of a metal oxide film according to one embodiment of the present invention. [Diagram 2] 1 shows a planar TEM image and a selected area electron diffraction pattern of a metal oxide film according to one embodiment of the present invention. [Diagram 3] Schematic diagram of electron beam diffraction intensity distribution. [Figure 4] Nanobeam electron diffraction pattern of a quartz glass substrate. [Diagram 5] 1 is a cross-sectional TEM image of a metal oxide film according to one embodiment of the present invention. [Figure 6] 1 shows the results of X-ray diffraction analysis of a metal oxide film according to one embodiment of the present invention. [Figure 7] 1 is a nanobeam electron diffraction pattern of a metal oxide film according to one embodiment of the present invention. [Figure 8] 1 is a nanobeam electron diffraction pattern of a metal oxide film according to one embodiment of the present invention. [Figure 9] 1A to 1C illustrate examples of the structure of a transistor according to an embodiment. [Figure 10] 1A to 1C illustrate an example of a method for manufacturing a transistor according to an embodiment. [Figure 11] 1A to 1C illustrate examples of the structure of a transistor according to an embodiment. [Figure 12] 1A to 1C illustrate a structure of a display panel according to an embodiment. [Figure 13] 1A to 1C are block diagrams illustrating electronic devices according to an embodiment. [Figure 14] 1A to 1C are diagrams illustrating external views of electronic devices according to an embodiment. [Figure 15] 1 shows a cross-sectional TEM image and a nanobeam electron diffraction pattern of a metal oxide film according to one embodiment of the present invention. [Figure 16] A conceptual diagram showing a method for thinning a sample using ion milling. [Figure 17] 1 is a nanobeam electron diffraction pattern of a metal oxide film according to one embodiment of the present invention. [Figure 18] SIMS analysis results of metal oxide films according to a comparative example and an embodiment. [Figure 19] X-ray diffraction analysis results of a sample prepared by the liquid phase method. [Figure 20] 4 is a cross-sectional TEM image of a comparative sample. [Figure 21] 1 shows nanobeam electron diffraction patterns of a metal oxide film according to one embodiment of the present invention and a comparative sample. [Figure 22] 1A and 1B show crystal structures of oxide semiconductor layers used in calculation. [Diagram 23] Calculation results showing the effect of hydrogen addition on the crystal state. [Figure 24] 1 shows the results of bond energy measurement by XPS for a metal oxide film according to one embodiment of the present invention and a comparative sample. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0024] Hereinafter, the embodiment of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following description, and it is understood by those skilled in the art that the present invention may be modified in various ways. Therefore, the present invention should not be construed as being limited to the following description of the embodiments. It is not something that can be achieved.

[0025] (Embodiment 1) In this embodiment, a metal oxide film of one embodiment of the present invention will be described with reference to FIGS. This will be explained with reference to 21.

[0026] <Crystalline part of metal oxide film> The metal oxide film of the present embodiment has an atomic arrangement that is not periodic when viewed macroscopically, or It is a metal oxide film that contains extremely fine crystals to the extent that no long-range order can be observed visually. Therefore, in a measurement range larger (wider) than the crystal part contained in the metal oxide film of this embodiment, In some cases, electron diffraction does not reveal regular spots that indicate a crystalline state. do.

[0027] <Cross-sectional TEM image and ultrafine electron diffraction pattern> FIG. 1(A) shows a cross-sectional TEM (Transmission Emission Microscopy) image of the metal oxide film of this embodiment. The image of the ion beam taken by a transmission electron microscope (TEM) is shown in Fig. 1. B) Electron beam diffraction measured by nanobeam electron diffraction at point 1 in Fig. 1(A). The folding pattern is shown in Fig. 1(C) by nanobeam electron diffraction at point 2 in Fig. 1(A). The electron diffraction pattern measured at point 3 in Figure 1(A) is shown in Figure 1(D). Electron beam diffraction patterns measured using a beam electron diffraction are shown.

[0028] As an example of a metal oxide film, an In-Ga-Zn oxide film was formed on a quartz glass substrate with a thickness of 50 mm. The deposition conditions for the metal oxide film were In:Ga:Zn=1:1: Using an oxide target with an atomic ratio of 1, under an oxygen atmosphere (flow rate 45 sccm), The pressure was 0.4 Pa, the direct current (DC) power was 0.5 kW, and the substrate temperature was room temperature. The metal oxide film is sliced ​​to a thickness of about 50 nm (for example, 40 nm ± 10 nm) and cut. Area TEM images and nanobeam electron diffraction patterns were obtained.

[0029] Cross-sectional observation of metal oxide films was performed using a transmission electron microscope (Hitachi High-Technologies Corporation, H-900 The experiment was carried out using a nanobeam microscope (NARA) with an acceleration voltage of 300 kV and a magnification of 2 million times. Electron diffraction was performed using a transmission electron microscope (Hitachi High-Technologies Corporation, "HF-2000"). The acceleration voltage was 200 kV and the beam diameter was about 1 nmφ. The measurement range for diffraction is from 5 nmφ to 10 nmφ.

[0030] As shown in FIG. 1(B), the metal oxide film of the present embodiment is a nano-beam electron diffraction pattern. In the image, multiple spots (bright points) arranged in a circular pattern are observed. In the metal oxide film of the embodiment, a plurality of spots distributed in a circumferential shape are observed. Or, It can also be said that the multiple spots distributed circumferentially form multiple concentric circles.

[0031] In addition, in the vicinity of the interface with the quartz glass substrate (FIG. 1(D)), and in the center of the thickness direction of the metal oxide film (FIG. 1(C)), In Fig. 1(C) of the portion, multiple spots distributed in a circumferential shape were observed, similar to Fig. 1(B). In FIG. 1(C), the radius of the first circumference (the distance from the main spot) is 3.8 The interplanar spacing was 0.8 / nm to 4.93 / nm. It is 57nm.

[0032] The nanobeam electron diffraction pattern in Figure 1 shows a halo pattern that indicates an amorphous state. Therefore, the metal oxide film of the present embodiment has a crystal portion. However, the nanobeam electron diffraction pattern in Figure 1 shows that The spots are not regular, which indicates crystals oriented on the plane, but random spots. From the observation, it can be seen that the metal oxide film of the present embodiment has irregular plane orientation and large It is presumed that the film is a mixture of multiple crystal parts with different sizes.

[0033] FIG. 5 shows a partially enlarged view of the cross-sectional TEM image shown in FIG. 1(A). Cross-sectional TEM image of the vicinity of point 1 in (A) (metal oxide film surface) observed at 8 million times magnification. FIG. 5B shows the vicinity of point 2 in FIG. 1A (in the thickness direction of the metal oxide film). This is a cross-sectional TEM image of the sample (center) observed at 8 million times magnification.

[0034] In addition, the crystal structure of the metal oxide film of this embodiment is clearly visible from the cross-sectional TEM image shown in FIG. cannot be confirmed.

[0035] <Plane TEM image and selected area electron diffraction pattern> Next, FIG. 2(A) shows a planar TEM image of the metal oxide film of the present embodiment. B) The electron beam of the circled area in Fig. 2(A) measured by selected area electron diffraction. Diffraction patterns are shown.

[0036] As an example of a metal oxide film, an In-Ga-Zn oxide film was formed on a quartz glass substrate to a thickness of 30 mm. The deposition conditions for the metal oxide film were In:Ga:Zn=1:1: Using an oxide target with an atomic ratio of 1, under an oxygen atmosphere (flow rate 45 sccm), The pressure was 0.4 Pa, the direct current (DC) power was 0.5 kW, and the substrate temperature was room temperature. The sample was sliced ​​so that the metal oxide film remained, and planar TEM images and selected area electron diffraction patterns were obtained. Got a turn.

[0037] The image in Figure 2 was taken using a transmission electron microscope (Hitachi High-Technologies Corporation's H-9000NAR The image was taken at an accelerating voltage of 300 kV using a 300-kV microscope. Figure 2(A) shows the image of a metal oxide at a magnification of 500,000 times. The results were obtained by plane observation of the film. Also, Fig. 2(B) shows the area within the circle shown in Fig. 2(A) using a selected-area electron microscope. The pattern in Figure 2(B) is the result of measurement using X-ray diffraction. The electron diffraction was performed by taking into account the spread of the electron beam (approximately several nm). The measurement range is 300 nmφ or more.

[0038] As shown in FIG. 2B, in the metal oxide film of the present embodiment, the measurement In the electron diffraction pattern using the wide range selected area electron diffraction, The multiple spots observed in the previous experiment were not observed, and a halo pattern was observed. The metal oxide film in the form of is such that no periodicity is observed in the atomic arrangement, or no long-range order is observed macroscopically. It can be said that the metal oxide film contains extremely fine crystal parts.

[0039] <Conceptual diagram of electron diffraction intensity distribution> FIG. 3 conceptually shows the distribution of diffraction intensity in the electron beam diffraction patterns of FIGS. 1 and 2. 3(A) is the diffraction intensity in the electron microbeam diffraction patterns shown in FIG. 1(B) to FIG. 1(D). FIG. 3(B) is a schematic diagram of the distribution of the selected area electron beam diffraction pattern shown in FIG. Fig. 3(C) shows the distribution of diffraction intensity in the ideal polycrystalline structure. FIG. 2 is a conceptual diagram of the distribution of diffraction intensity in an electron beam diffraction pattern.

[0040] In Fig. 3, the vertical axis represents the electron diffraction intensity (arbitrary unit) and the horizontal axis represents the distance from the main spot. show.

[0041] In the ideal polycrystalline structure shown in FIG. 3(C), the spacing (d value) of the planes along which the crystals are oriented is A peak appears at a specific distance from the main spot depending on the electron diffraction. In the pattern, a narrow ring is clearly visible at a certain distance from the main spot. It is suspected.

[0042] On the other hand, as shown in FIG. 1, the nanobeam electron diffraction pattern of the metal oxide film of the present embodiment The circumferential area formed by the observed spots has a relatively large width. Therefore, as shown in FIG. 3(A), the electron beam diffraction intensity is a band-like distribution of peaks (peak The nanobeam electron diffraction pattern shows a discrete intensity distribution with multiple bands. In this case, since there are a few spots between the concentric regions, as shown in FIG. It can be seen that there is a diffraction peak between the two peak bands.

[0043] On the other hand, as shown in FIG. 3(B), the selected area electron diffraction pattern of the metal oxide film of the present embodiment The electron diffraction intensity distribution in the image shows a continuous intensity distribution. ) can be approximated by the results of observing the electron beam diffraction intensity distribution over a wide area, as shown in Figure 3(A). It can be considered that the peak band shown in is integrated to obtain a continuous intensity distribution.

[0044] As shown in FIG. 3(A) to FIG. 3(C), the metal oxide film of this embodiment has irregular plane orientation. The film has a plurality of crystal parts of different sizes, and the crystal parts are controlled by the The particles are so fine that no spots are observed in the limited-field electron diffraction pattern. is suggested.

[0045] In the nanobeam electron diffraction pattern, multiple spots are observed, as shown in Figure 1. The oxide film is thinned to a thickness of about 50 nm. The electron beam diameter is 1 nmφ. Since the beam is converged, the measurement range is 5 nm to 10 nm. The size of the crystal part contained in the metal oxide film of the form is at least 50 nm or less, for example For example, it is estimated to be 10 nm or less, or 5 nm or less.

[0046] <Nanobeam electron diffraction pattern of ultra-thin sample> The size of the crystal part contained in the metal oxide film of the present embodiment is 10 nm or less, or 5 nm or less. In this case, the measurement in the depth direction is difficult for a sample in which the metal oxide film is sliced ​​to a thickness of about 50 nm. Since the measurement range is larger than the size of the crystal part, multiple crystal parts are included in the measurement range. Therefore, the metal oxide film is sliced ​​to a thickness of 10 nm or less, and its cross section is nano-sized. The crystals were observed by electron diffraction.

[0047] The sample preparation method is as follows. An In-Ga-Zn oxide film with a thickness of 5 mm was formed on a quartz glass substrate. The deposition conditions were In:Ga:Zn=1:1:1 (atomic ratio). Using an oxide target, under oxygen atmosphere (flow rate 45sccm), pressure 0.4Pa, direct current The DC power supply was 0.5 kW, and the substrate temperature was room temperature. After the metal oxide film was formed, A first heat treatment at 0° C. under nitrogen atmosphere for 1 hour, and a second heat treatment at 450° C. under nitrogen and oxygen atmosphere for 1 hour. A second heat treatment was carried out at 40° C. for 1 hour.

[0048] The metal oxide film after the second heat treatment was cut into thin slices by ion milling using Ar ions. First, a quartz glass substrate with a metal oxide film formed on it to reinforce the thinning process was After bonding the substrate, it was cut and polished to a thickness of about 50 μm. Thereafter, as shown in FIG. 16, the quartz glass substrate 200 on which the metal oxide film 204 is provided and The dummy substrate 202 is irradiated with argon ions from a low angle (approximately 3°) to form ions. The area 21 is thinned to a thickness of about 50 nm (40 nm ± 10 nm) by milling. 0a, and a region 210b thinned to a thickness of 10 nm or less, for example, 5 to 10 nm. The cross sections of each were observed.

[0049] FIG. 15A shows a cross section of a sample sliced ​​to a thickness of about 50 nm, which corresponds to region 210a. The TEM image is shown. The cross section shown in FIG. 15(A) was also measured by nanobeam electron diffraction. The electron beam diffraction patterns are shown in Fig. 15(B) to Fig. 15(E). FIG. 15(C) shows an electron beam diffraction pattern using an electron beam focused to a diameter of 1 nmφ. The electron beam diffraction pattern was obtained by using an electron beam focused to a beam diameter of 10 nmφ. D) is an electron beam diffraction pattern using an electron beam focused to a beam diameter of 20 nmφ. FIG. 15(E) shows the electron beam diffraction using an electron beam focused to a beam diameter of 30 nmφ. It's a pattern.

[0050] As shown in FIG. 15(B), the metal oxide film after the heat treatment also has a circumferential distribution similar to that shown in FIG. In addition, from Fig. 15(C) to Fig. 15(E), it is clear that the When the beam diameter of the sagittal beam is increased to expand the measurement range, the multiple spots gradually become broader. It is confirmed that the following occurs:

[0051] 17(A) to 17(D), a thin film having a thickness of 10 nm or less, which corresponds to the region 210b, is shown. Four arbitrary points on the fragmented sample were measured using an electron beam focused to a beam diameter of 1 nmφ. The nanobeam electron diffraction pattern is shown.

[0052] In Fig. 17(A) and Fig. 17(B), regular spots showing crystals oriented in a specific plane are shown. From this, it is clear that the metal oxide film according to the present embodiment certainly has crystal parts. On the other hand, in Fig. 17(C) and Fig. 17(D), the complex distribution Several spots (bright points) are observed.

[0053] As described above, the size of the crystal portion contained in the metal oxide film of the present embodiment is at least It is 50 nm or less, for example, 10 nm or less, or 5 nm or less, which is extremely fine. For example, the sample is sliced ​​to a thickness of 10 nm or less, and the electron beam is focused to 1 nmφ. If the measurement range is reduced to an area smaller than the size of a single crystal, for example, In some areas, it is possible to observe regular spots that indicate crystals oriented in specific planes. In addition, if the area to be measured contains multiple crystalline parts, the electron beam that passes through the crystalline parts may In some cases, the nanobeams may be directed at other crystals in the depth direction. In this case, multiple nanobeams It can be assumed that an electron diffraction pattern is observed.

[0054] <Microelectron diffraction pattern of quartz substrate> Figure 4 shows the nanobeam electron diffraction pattern of the quartz glass substrate. The measurement conditions were as shown in Figure 1. The thickness of the metal oxide film was determined to be the same as that of the metal oxide film.

[0055] As shown in Figure 4, the amorphous quartz glass substrate does not diffract light to a specific spot, but rather focuses it on the main A halo pattern with a continuously changing brightness is observed from the spot. In the case of a film having a structure, even if electron beam diffraction is performed on a very small area, In contrast, multiple spots arranged in a circular pattern, as observed in the metal oxide film of the above-mentioned embodiment, are not observed. Therefore, the multiple spots arranged in a circular pattern observed in Figs. 1(B) to 1(D) are It is confirmed that this is unique to the metal oxide film of this embodiment.

[0056] <Electron diffraction pattern after continuous irradiation with ultrafine electron beam> In Fig. 8, an electron beam focused to a beam diameter of about 1 nmφ was applied to point 2 shown in Fig. 1(A) for one minute. The electron diffraction pattern measured after irradiation is shown.

[0057] The electron diffraction pattern shown in FIG. 8 is similar to the electron diffraction pattern shown in FIG. 1(C). Multiple spots were observed, and no significant differences were observed between the two measurement results. This means that the crystal parts confirmed in FIG. 1(C) were formed during the deposition of the metal oxide film of this embodiment. This means that the crystals are formed by irradiating the material with a focused electron beam. This means that the information has not been

[0058] <X-ray diffraction analysis> The test piece shown in FIG. 1 and FIG. 2 has a metal oxide film formed on a quartz glass substrate according to the present embodiment. The samples were analyzed using X-ray diffraction (XRD). The results of measuring the XRD spectrum using the out-of-plane method are shown in Figure 1.

[0059] In FIG. 6, the vertical axis represents the X-ray diffraction intensity (arbitrary unit), and the horizontal axis represents the diffraction angle 2θ (deg.). The XRD spectrum was measured using a Bruker AXS X-ray diffractometer D- 8 ADVANCE was used.

[0060] As shown in Figure 6, a peak due to quartz is observed in the vicinity of 2θ = 20 to 23°. However, no peaks due to crystal parts contained in the metal oxide film can be confirmed.

[0061] From the results of FIG. 6, it can be seen that the crystal parts contained in the metal oxide film of the present embodiment are extremely fine crystal parts. This suggests that there is.

[0062] As described above, the metal oxide film of the present embodiment is formed by agglomerating crystal parts with irregular plane orientation. It can be assumed that a membrane has formed.

[0063] The size of the crystal part contained in the metal oxide film of this embodiment is, for example, 10 nm or less. It is estimated that the thickness of the metal oxide film of the present embodiment is, for example, Contains crystalline parts (nanocrystals (nc)) with a size of 1 nm to 10 nm It is a metal oxide film.

[0064] <Metal oxide film formation method> The method for forming a metal oxide film according to the present embodiment will be described below. The metal oxide film of the embodiment is formed by sputtering at room temperature in an oxygen-containing atmosphere. By forming the film in an oxygen-containing atmosphere, the metal oxide film is This reduces oxygen vacancies in the film and makes it possible to form a film containing crystal parts.

[0065] <Reduction of oxygen deficiency> In the metal oxide film of this embodiment, the reduction of oxygen vacancies results in a film with stable physical properties. In particular, when an oxide semiconductor film is used as the metal oxide film in this embodiment, In manufacturing a semiconductor device, oxygen vacancies in an oxide semiconductor film are a cause of carrier generation. As a result, the electrical characteristics of the semiconductor device are changed. By manufacturing a semiconductor device using a reduced oxide semiconductor film, a highly reliable semiconductor device can be obtained. It can be placed.

[0066] In addition, in the metal oxide film of the present embodiment, when the oxygen partial pressure in the film formation atmosphere is increased, oxygen deficiency is increased. For example, the oxygen partial pressure in the film formation atmosphere is set to 33% or more. It is preferred.

[0067] FIG. 7 shows the nanobeam electron micrographs of the metal oxide film of this embodiment formed at an oxygen partial pressure of 33%. The X-ray diffraction pattern of the metal oxide film of the present embodiment shown in FIG. The atmosphere was a mixture of argon and oxygen (Ar:O2 = 30sccm:15sccm), and the other conditions were the same as in Fig. 1. The metal oxide film was prepared under the same conditions as those shown in Fig. 1. Nanobeam electron diffraction measurements were performed using the The measurements were performed in the same manner as described in Figs. 1(B) to 1(D).

[0068] As shown in FIG. 7, the metal oxide film of this embodiment formed with an oxygen partial pressure of 33% also exhibited nano- In the open-beam electron diffraction pattern, multiple spots arranged in a circular pattern were observed. It is confirmed that a metal oxide film containing crystal parts is formed.

[0069] <<Film formation by sputtering method>> As an oxide target that can be used for forming the metal oxide film of this embodiment, I Not limited to n-Ga-Zn oxides, for example, In-M-Zn oxides (where M is Al, T i, Ga, Y, Zr, La, Ce, Nd or Hf) can be applied.

[0070] In addition, the present invention uses a sputtering target containing a polycrystalline oxide having a plurality of crystal grains. It is preferable to form a metal oxide film including crystal parts, which is the metal oxide film of the embodiment. The sputtering target has a plurality of crystal grains, and the bonds between the crystal grains are weak. When an interface that is easily cleaved exists, the sputtering target is bombarded with ions to form a By this, the crystal grains may be cleaved, and flat sputtered particles may be obtained. The plate-like sputtered particles are deposited on the substrate to form metal oxides containing nanocrystals. However, the metal oxide film according to the present embodiment may be formed. It should be noted that the above film formation mechanism is merely one consideration.

[0071] The metal oxide film of the present embodiment has irregular plane orientations and different sizes. A film containing a plurality of crystal parts, and the crystal parts are In some cases, the size is so small that no spots are observed.

[0072] In addition, the metal oxide film of the present embodiment has a region containing a crystal part, and is a film with stable physical properties. Therefore, by applying the metal oxide film of this embodiment to a semiconductor device, the reliability can be improved. It is therefore possible to provide a high quality semiconductor device.

[0073] (Comparative Example) In this comparative example, the crystallinity of a metal oxide film produced by a liquid phase method will be described with reference to the drawings. explain.

[0074] The method for forming the metal oxide film in this comparative example will be described below.

[0075] First, In2O3 (5wt%), Ga2O3 (3wt%), ZnO (5wt%) and The coating agent was mixed in a ratio of In:Ga:Zn=1:1:1 and spin-coated on a glass substrate. The coating was performed by spin coating at 900 rpm to 2 000 rpm in stages.

[0076] After coating, a first heat treatment was performed at 150°C for 2 minutes in an air atmosphere using a hot plate. I did.

[0077] Next, a second heat treatment was performed in an air atmosphere at 450° C. for 1 hour. After the second heat treatment The metal oxide film of this comparative example (film formed by liquid phase method) and the metal oxide film shown in FIG. For each of the metal oxide films (films formed by sputtering) of the present embodiment, X X-ray Photoelectron Spectros (XPS) The bonding state was evaluated using a 3D copy of the 3D printed circuit board. The evaluation results are shown in Figure 24.

[0078] In the XPS analysis, a measuring device, Quantera SXM manufactured by PHI Corporation, was used. For each metal oxide film, the In 3d(5 / 2) orbital (see Figure 24(A)), G a 3d orbital (see FIG. 24(B)), Zn 3p orbital (see FIG. 24(C)), and O 1 The spectrum of the region corresponding to the s orbital (see Figure 24(D)) is shown. 24 shows the results of evaluation of an In-Ga-Zn oxide film formed by a liquid phase method according to a comparative example. The dashed line indicates the In-Ga-Zn film formed by the sputtering method according to the present embodiment. 13 shows the evaluation results of the oxide film.

[0079] From Figure 24(A) to (D), a slight shift in the binding energy is observed, but this comparison A metal oxide film formed by a liquid phase method shown in the example and a sputtering method according to the present embodiment The metal oxide film formed in the above-mentioned comparative example had a spectrum shape similar to that of the above-mentioned comparative example. The metal oxide film prepared by the liquid phase method shown here is indeed an In-Ga-Zn oxide film. It was identified that:

[0080] Next, the sample of this comparative example was analyzed by XRD. The results of analysis using the plane method are shown below.

[0081] For the XRD analysis, after the first heat treatment, the samples were heated at 350℃, 450℃, and 600℃ in air. The In-Ga-Zn oxide film sample was subjected to a second heat treatment at 550° C. for 1 hour.

[0082] In FIG. 19, the vertical axis represents the X-ray diffraction intensity (arbitrary unit), and the horizontal axis represents the diffraction angle 2θ (deg. The XRD measurements were performed using a Bruker AXS X-ray diffractometer D-8 ADVANC E was used.

[0083] FIG. 19(A) shows the measurement results of the sample prepared by the liquid phase method in this comparative example. The XRD pattern of the sample that was not heat-treated is the pattern shown as-depo. In addition, in Fig. 19(B), (C), and (D), the film is formed by the liquid phase method and then cooled in an air atmosphere. Indium oxide was heat-treated at 350℃, 450℃, or 550℃ for 1 hour under atmospheric pressure. The measurement results for a gallium oxide film, a gallium oxide film, and a zinc oxide film are shown.

[0084] As shown in Fig. 19, the XRD pattern of the indium oxide film after heat treatment shows that the crystal peaks of In2O3 In addition, the XRD pattern of the zinc oxide film after heat treatment showed a peak that matched the peak of the In the sample of this comparative example, a peak corresponding to the crystal peak of ZnO was confirmed. Unlike the indium oxide and zinc oxide films, the samples after heat treatment under any temperature conditions No crystalline peak was observed.

[0085] In addition, the samples that were subjected to the second heat treatment at 450°C for 1 hour in air were analyzed by X-ray reflection. The film density was measured by X-Ray Reflection (XRR).

[0086] In addition, XRR measurement involves irradiating X-rays to a measurement sample and measuring the critical angle, amplitude, and By measuring the change in shape, etc., and performing theoretical analysis using the measured critical angle, amplitude waveform, etc., This is a method for measuring the density of the formed thin film.

[0087] The measured film densities are shown in Table 1.

[0088] [Table 1]

[0089] From Table 1, the film obtained by the liquid phase method has a non-linearity compared to the theoretical value calculated from the single crystal structure. It was confirmed that the density was always low. However, the film formed by the liquid phase method had a high degree of roughness. It should be noted that it is difficult to measure the film density with high accuracy due to its large size.

[0090] Next, the metal oxide film of the comparative example and the metal oxide film of the present embodiment were examined to determine whether the metal oxide film contained The impurity concentration was measured by SIMS (Secondary Ion Mass Spectrometer) The results were measured by try analysis.

[0091] FIG. 18(A) shows the hydrogen ( 1 FIG. 18(B) shows the concentration profile of the metal oxide film of the comparative example and the present embodiment. The carbon ( 12 C) Concentration profile. The axis represents the depth (nm), and the vertical axis represents the hydrogen or carbon concentration (atoms / cm 3 ) is doing.

[0092] In FIG. 18, the metal oxide film of the comparative example was prepared by the liquid phase method under the same conditions as described above. However, the sample was filtered through a membrane filter (0.2 μm) before spin coating. The second heat treatment was performed under air at 450°C and 500°C. Or 550 °C for 1 hour. The other conditions were the same as those for the metal oxide film by the liquid phase method described above. The metal oxide film of this embodiment was formed under the same conditions as the metal oxide film shown in FIG. It was prepared by sputtering.

[0093] As shown in FIG. 18(A) and FIG. 18(B), the metal oxide film of the comparative example was different from the metal oxide film of the present embodiment. It was confirmed that larger amounts of hydrogen and carbon were uniformly present in the film than in the oxide film.

[0094] The carbon concentration of the metal oxide film of this embodiment shown in FIG. 18(B) gradually increases from the surface to the inside of the film. Therefore, the carbon contained in the metal oxide film of the present embodiment is the carbon derived from surface contamination. This suggests that the sides are strong.

[0095] On the other hand, in the metal oxide film of the comparative example, hydrogen was 1×10 22 (atoms / cm 3 ) or more, carbon is 4×10 21 (atoms / cm 3 ) or higher It can be seen that carbon is uniformly present in the film. It is believed to be derived from organic acid salts, which are the raw materials for the coating material.

[0096] Next, a second heat treatment was performed at 450° C. for 1 hour in an air atmosphere. The surface TEM image is shown in Figure 20. Cross-sectional observation was performed using a transmission electron microscope (Hitachi High-Technologies Corporation). The experiment was performed with an accelerating voltage of 300 kV using a microscope (H-9000NAR). FIG. 20(B) is a cross-sectional observation image at a magnification of 2,000,000 times, and FIG. 20(C) is a cross-sectional observation image at a magnification of 2,000,000 times. (C) is a cross-sectional image observed at 8 million times magnification.

[0097] As shown in Fig. 20(A) and Fig. 20(B), the sample prepared by the liquid phase method in this comparative example has an amorphous region. It can be seen that the majority of the area is covered by the shading (high and low brightness) due to the difference in film density. ) is found to exist.

[0098] In the region a in FIG. 20(C), the brightness of the cross-sectional TEM image is high, and the film density is low. In region b in FIG. 20(C), the brightness of the cross-sectional TEM image is low, and the film It can be said that this is an area of ​​high density.

[0099] Regions a and b in FIG. 20(C) were observed using nanobeam electron diffraction. 21(A) to (C) show the nanobeam electron diffraction patterns.

[0100] Electron diffraction was performed using a transmission electron microscope (Hitachi High-Technologies Corporation, "HF-2000"). The acceleration voltage was 200 kV and the beam diameter was about 1 nmφ. 21(B) and 21(C) are nanobeam electron diffraction patterns of region a in FIG. 21(B) and FIG. 21(C). Both are nanobeam electron diffraction patterns of region b in FIG. 20(C), and are from two different locations. These are the observation results of (denoted as b1 and b2).

[0101] FIG. 21(D) shows a nanobeam electron diffraction pattern of the metal oxide film according to one embodiment of the present invention. The electron diffraction pattern was prepared and observed under the same conditions as those shown in Figure 7. be.

[0102] As shown in FIG. 21, in the metal oxide film prepared by the liquid phase method in this comparative example, However, the metal oxide film of one embodiment of the present invention shown in FIG. 21D is arranged in a circular shape. A different pattern was confirmed from the multiple spots (bright points) seen in the image.

[0103] As shown in FIG. 21(A), the nanobeam electron diffraction pattern of region a shows a halo indicating an amorphous structure. The presence of such low crystallinity regions is due to the low density of the film, It can be assumed that this is due to the high impurity concentration.

[0104] In addition, from FIGS. 21B and 21C, the nanobeam electron diffraction pattern of region b shows that The spots have regularity, indicating crystals oriented in the same plane (1 in Fig. 21(B) and (C)). The diffraction pattern of this spot was analyzed and the results are shown in Fig. , as shown in Table 2 below.

[0105] [Table 2]

[0106] From Table 2, the actual measurement of d value derived from the spot observed in FIG. 21(B) or FIG. 21(C) The values ​​are almost the same as the theoretical values ​​for multiple plane orientations of InGaZnO4, and the film was formed by the liquid phase method. The In-Ga-Zn oxide film of this comparative example partially contains crystals due to InZnGaO4. The existence of the area was confirmed.

[0107] From the above, it was found that the In-Ga-Zn oxide film prepared by the liquid phase method contains impurities, but In the figure, there are regions with periodic atomic arrangements due to InZnGaO4 crystals, and regions with very high crystallinity. It can be said that there is a mixture of low and nearly amorphous regions.

[0108] Next, impurities such as hydrogen and carbon present in the metal oxide film of the comparative example are removed by The effect on the crystallinity of the film was evaluated by calculation.

[0109] In the calculations shown below, the effect of hydrogen on the crystallization of metal oxide films is investigated using first-principles calculations. Specifically, the InGaZnO4 was investigated in two cases: when it does not contain hydrogen and when it contains hydrogen at 6.67a. The energy difference between the amorphous state and the crystalline state was investigated for each of the In -The atomic density of Ga-Zn-O crystal is 8.54×10 22 atoms / cm 3 To be From the SIMS analysis results shown in FIG. 18, it can be seen that this hydrogen concentration is contained in the metal oxide film of this comparative example. The hydrogen concentration is equivalent to that of the metal oxide film. An In-Ga-Zn oxide film with an atomic ratio of Zn=1:1:1 was used.

[0110] Figure 22 shows the lattice structure of the In-Ga-Zn-O crystal with 112 atoms used in the calculation. vinegar.

[0111] In the calculation, a structure without H and a structure with eight H atoms added to the structure shown in Figure 22 were We created and optimized each structure and calculated the energy. Based on this, an amorphous structure was created using the following process.

[0112] (1) Molecular dynamics calculations in the NVT ensemble at a temperature of 3000K. (2) Molecular dynamics calculations in the NVT ensemble at a temperature of 1000 K and a time of 2 psec. (3) Structural optimization.

[0113] However, in the calculation of (1) above, the structures after 5 psec, 5.5 psec, and 6 psec Then, we take out the amorphous structure, perform the calculations from (2) onwards, and create three amorphous structures. The calculation was performed using the first-principles calculation software "VASP (Vienna The calculation conditions were As shown in Table 3.

[0114] [Table 3]

[0115] Figure 23 shows some of the structures obtained by calculation, and Table 4 shows the calculation results of the energy difference. 23(A) shows the structure of a single-crystal In-Ga-Zn oxide film without H addition (0 atom%). FIG. 23(B) shows the structure of a single-crystal In-Ga-Z alloy doped with eight H atoms (6.67 atom%). The structure of the n-oxide film is shown in Fig. 23(C). The structure of the In-Ga-Zn oxide film is shown in FIG. 23(D). The structure of an amorphous In-Ga-Zn oxide film (100 atom%) is shown.

[0116] [Table 4]

[0117] From Table 4, the energy of the In-Ga-Zn oxide film is greatly reduced by crystallization. On the other hand, the stabilization energy due to crystallization increases with the addition of H. From the above, it is clear that the metal oxide film produced by the liquid phase method of this comparative example has a periodic atomic arrangement. The nanobeam electron diffraction patterns were similar to the halo pattern, along with a pattern containing spots showing The reason for this is believed to be the destabilization of the crystal structure by hydrogen.

[0118] As described above, the inclusion of hydrogen as an impurity in the metal oxide film improves the stability of the crystal. The calculation results show that the nanobeam electron diffraction pattern is close to the halo pattern. In the metal oxide film of the comparative example, the content of hydrogen and carbon as impurities was 100% of that of the present embodiment. This is also consistent with the fact that the resistivity of the metal oxide film is higher than that of the metal oxide film in the solid-state.

[0119] As described above, this embodiment may be implemented in appropriate combination with other embodiments described in this specification. It is possible.

[0120] (Embodiment 2) In this embodiment, the metal oxide film exemplified in the first embodiment and having semiconductor properties is used. A configuration example of a transistor using an oxide film (oxide semiconductor film) will be described with reference to the drawings. explain.

[0121] <Example of transistor configuration> FIG. 9A is a schematic cross-sectional view of a transistor 100, which will be described below as an example. Transistor 1 00 is a bottom gate type transistor.

[0122] The transistor 100 includes a gate electrode 102 provided on a substrate 101 and a An insulating layer 103 is provided on the gate electrode 102, and the gate electrode 102 is provided on the insulating layer 103. The oxide semiconductor layer 104 provided so as to overlap with the oxide semiconductor layer 104 The insulating layer 103 and the oxide semiconductor layer 104 are disposed on the insulating layer 103. An insulating layer 106 covers the pair of electrodes 105a and 105b, and an insulating layer 107 is formed on the insulating layer 106. is provided.

[0123] The oxide semiconductor film of one embodiment of the present invention is applied to the oxide semiconductor layer 104 of the transistor 100. It is possible.

[0124] "PCB 101" There is no particular restriction on the material of the substrate 101, but it should be strong enough to withstand the subsequent heat treatment. Use heat-resistant materials. For example, glass substrate, ceramic substrate, quartz substrate, safa A ceramic substrate, a YSZ (yttria stabilized zirconia) substrate, etc. may be used as the substrate 101. In addition, a single crystal semiconductor substrate such as silicon or silicon carbide, a polycrystalline semiconductor substrate, a silicon It is also possible to use a compound semiconductor substrate such as congermanium, an SOI substrate, or the like. Moreover, a substrate having a semiconductor element formed thereon may be used as the substrate 101. .

[0125] In addition, a flexible substrate such as plastic is used as the substrate 101, and the substrate is directly formed on the flexible substrate. Alternatively, the transistor 100 may be formed between the substrate 101 and the transistor 100. A peeling layer may be provided on the upper layer of the transistor. After that, it can be separated from the substrate 101 and used for transfer to another substrate. Therefore, the transistor 100 can be mounted on a substrate having low heat resistance or a flexible substrate.

[0126] Gate electrode 102 The gate electrode 102 may be made of any of a variety of materials including aluminum, chromium, copper, tantalum, titanium, molybdenum, and titanium. A metal selected from the group consisting of tin, tin, tin alloys, and tin alloys containing the above-mentioned metals. In addition, it can be formed by using an alloy of manganese and zirconium. The gate electrode 102 may be a single layer. For example, a silicon-containing aluminum film may be used. Single layer structure, two-layer structure with titanium layer laminated on aluminum layer, titanium layer on titanium nitride layer a two-layer structure in which a tungsten film is laminated on a titanium nitride film; A two-layer structure in which a tungsten film is laminated on a titanium film or a tungsten nitride film, and a titanium film and A three-layer structure in which an aluminum film is laminated on a titanium film, and a titanium film is further formed on the aluminum film. In addition, titanium, tantalum, tungsten, molybdenum, chromium, , neodymium, and scandium, or an alloy film made by combining one or more metals selected from the group consisting of Alternatively, a nitride film of these may be used.

[0127] The gate electrode 102 is made of indium tin oxide or indium oxide containing tungsten oxide. oxide, indium zinc oxide with tungsten oxide, indium oxide with titanium oxide Indium tin oxide, indium zinc oxide, silicon oxide with titanium oxide A light-transmitting conductive material such as indium tin oxide can also be used. A laminated structure of the above-mentioned light-transmitting conductive material and the above-mentioned metal may also be used.

[0128] In addition, an In-Ga-Zn-based oxynitride semiconductor film is provided between the gate electrode 102 and the insulating layer 103. , In-Sn-based oxynitride semiconductor film, In-Ga-based oxynitride semiconductor film, In-Zn-based oxynitride Semiconductor film, Sn-based oxynitride semiconductor film, In-based oxynitride semiconductor film, metal nitride film (InN, These films have a work energy of 5 eV or more, or 5.5 eV or more. function, which is larger than the electron affinity of an oxide semiconductor. The threshold voltage of the transistor can be shifted to the positive side, and the so-called normally-off characteristic can be improved. For example, a switching element having a conductivity at least higher than that of the oxide semiconductor layer 104 can be realized. In-Ga-Zn-based oxynitride semiconductor having a nitrogen concentration of 7 atomic % or more Uses body membrane.

[0129] Insulating layer 103 The insulating layer 103 functions as a gate insulating film. The edge layer 103 is preferably an amorphous film.

[0130] The insulating layer 103 is made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon nitride. Copper, aluminum oxide, hafnium oxide, gallium oxide or Ga-Zn-based metal oxide , silicon nitride, or the like may be used, and the insulating film 11 is provided as a laminated layer or a single layer.

[0131] The insulating layer 103 is made of hafnium silicate (HfSiO x ), nitrogen added Hafnium Silicate (HfSi x O y N z ), nitrogen-doped hafnium aluminate HfAl x O y N z ), high-k materials such as hafnium oxide and yttrium oxide By using this, the gate leakage of the transistor can be reduced.

[0132] <<Pair of electrodes 105a, 105b>> The pair of electrodes 105a and 105b serve as source and drain electrodes of a transistor. It works like this.

[0133] The pair of electrodes 105a and 105b are made of a conductive material such as aluminum, titanium, chromium, or nickel. Nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten A metal consisting of tin or an alloy containing it can be used as a single layer structure or a laminate structure. For example, a single layer structure of an aluminum film containing silicon, titanium on an aluminum film, Two-layer structure with a titanium film laminated on a tungsten film, two-layer structure with a copper-magnesium film laminated on a tungsten film A two-layer structure in which a copper film is laminated on a copper-aluminum alloy film, a titanium film or a titanium nitride film, An aluminum film or a copper film is laminated on the titanium film or the titanium nitride film, and further A three-layer structure in which a titanium film or titanium nitride film is formed on the top of the molybdenum film or molybdenum nitride film A molybdenum film and an aluminum film or The copper film is laminated on top of which a molybdenum film or molybdenum nitride film is formed. In addition, transparent conductive materials containing indium oxide, tin oxide, or zinc oxide are used. Good too.

[0134] Insulating layers 106 and 107 The insulating layer 106 is made of an oxide insulating film containing more oxygen than the oxygen required for the stoichiometric composition. It is preferable that such an oxide insulating film has oxygen partially released by heating. For example, when such an oxide insulating film is heated at a temperature equal to or higher than the heat treatment temperature in the manufacturing process of a transistor, When heated, thermal desorption spectroscopy (TDS) The amount of oxygen released was 1.0×10 18 atoms / cm 3 More than 3.0×10 20 atoms / cm 3That's all. do.

[0135] The insulating layer 106 can be made of silicon oxide, silicon oxynitride, or the like.

[0136] The insulating layer 106 is formed on the oxide semiconductor layer 10 when the insulating layer 107 is formed later. It also functions as a damage mitigation membrane for 4.

[0137] Alternatively, an oxide film that transmits oxygen may be provided between the insulating layer 106 and the oxide semiconductor layer 104. good.

[0138] As the oxide film that transmits oxygen, silicon oxide, silicon oxynitride, etc. can be used. In this specification, the silicon oxynitride film is a film containing less than or equal to nitrogen. A silicon nitride film is a film that contains more oxygen than silicon dioxide. This refers to a film with a high nitrogen content.

[0139] The insulating layer 107 can be made of an insulating film having a blocking effect against oxygen, hydrogen, water, etc. By providing the insulating layer 107 over the insulating layer 106, oxygen from the oxide semiconductor layer 104 can be prevented. Therefore, the diffusion of hydrogen, water, and the like to the outside and the intrusion of hydrogen, water, and the like into the oxide semiconductor layer 104 from the outside can be prevented. Such insulating films include silicon nitride, silicon oxynitride, and aluminum oxide. , aluminum oxide, gallium oxide, gallium oxide, yttrium oxide, nitric oxide Examples of such oxides include yttrium nitride, hafnium oxide, and hafnium oxynitride.

[0140] <Example of transistor manufacturing method> Next, an example of a method for manufacturing the transistor 100 illustrated in FIGS.

[0141] First, as shown in FIG. 10(A), a gate electrode 102 is formed on a substrate 101. An insulating layer 103 is formed on the electrode 102 .

[0142] Here, a glass substrate is used as the substrate 101 .

[0143] <<Formation of Gate Electrode>> The method of forming the gate electrode 102 will be described below. First, the sputtering method, the CVD method, and the evaporation method are used. A conductive film is formed by deposition or the like, and a first photomask is used to perform photolithography on the conductive film. A resist mask is formed by a deposition process. Next, a part of the conductive film is The resist mask is then etched to form the gate electrode 102. After that, the resist mask is removed.

[0144] The gate electrode 102 may be formed by electrolytic plating, printing, inkjet printing, or the like instead of the above-mentioned method. It may be formed by a jet method or the like.

[0145] <<Formation of gate insulating layer>> The insulating layer 103 is formed by a method such as sputtering, CVD, or vapor deposition.

[0146] The insulating layer 103 is a silicon oxide film, a silicon oxynitride film, or a silicon nitride oxide film. In the case of forming the silicon-containing film, a deposition gas containing silicon and an oxidizing gas are used as the source gas. Representative examples of deposition gases containing silicon include silane, disilane, trisilane, and Examples of oxidizing gases include oxygen, ozone, nitrous oxide, and dioxygen. Examples include nitrogen oxides.

[0147] In addition, when forming a silicon nitride film as the insulating layer 103, a two-stage formation method is used. First, a mixture of silane, nitrogen, and ammonia is used as a raw material gas. A first silicon nitride film with few defects is formed by the plasma CVD method using the same material. The fuel gas was changed to a mixture of silane and nitrogen, and the hydrogen concentration was low and hydrogen was not blown. A second silicon nitride film capable of being coated is formed. As the insulating layer 103, a silicon nitride film having few defects and a hydrogen blocking property is used. can be formed.

[0148] In addition, when a gallium oxide film is formed as the insulating layer 103, MOCVD (Metal O Formed using the organic chemical vapor deposition (OCVD) method It is possible.

[0149] <<Formation of oxide semiconductor layer>> Next, as shown in FIG. 10B, the oxide semiconductor layer 104 is formed over the insulating layer 103.

[0150] A method for forming the oxide semiconductor layer 104 will be described below. First, the method described in Embodiment 1 will be described. Then, a second photomask is applied to the oxide semiconductor film. A resist mask is formed by a photolithography process using the resist mask. The oxide semiconductor film is partly etched using a etchant to form the oxide semiconductor layer 104. Thereafter, the resist mask is removed.

[0151] After this, a heat treatment may be performed. When the heat treatment is performed, it is performed in an atmosphere containing oxygen. It is preferred.

[0152] <<Formation of a pair of electrodes>> Next, as shown in FIG. 10(C), a pair of electrodes 105a and 105b are formed.

[0153] The method for forming the pair of electrodes 105a and 105b will be described below. First, a sputtering method is used. A conductive film is formed by a CVD method, a vapor deposition method, or the like. Next, a third photomask is used on the conductive film. A resist mask is formed by a photolithography process. The conductive film is partially etched using the etching solution to form a pair of electrodes 105a and 105b. Thereafter, the resist mask is removed.

[0154] Note that as shown in FIG. 10B, when the conductive film is etched, the top of the oxide semiconductor layer 104 is Therefore, a part of the oxide semiconductor layer 104 may be etched and thinned. When the oxide semiconductor film is formed, the thickness of the oxide semiconductor film is preferably set to be large in advance.

[0155] <<Formation of insulating layer>> Next, as shown in FIG. 10D, the oxide semiconductor layer 104 and the pair of electrodes 105a and 10 An insulating layer 106 is formed on 5b, and then an insulating layer 107 is formed on insulating layer 106.

[0156] When a silicon oxide film or a silicon oxynitride film is formed as the insulating layer 106, the source gas As the gas, a deposition gas containing silicon and an oxidizing gas are preferably used. Representative examples of deposition gases containing silane include silane, disilane, trisilane, and fluorosilane. Oxidizing gases include oxygen, ozone, nitrous oxide, and nitrogen dioxide.

[0157] For example, a substrate placed in a vacuum-evacuated processing chamber of a plasma CVD device is heated to 180° C. or higher. The temperature is kept at 260° C. or less, more preferably at 200° C. or more and 240° C. or less, and the raw material gas is introduced into the processing chamber. By introducing the gas, the pressure in the processing chamber is adjusted to 100 Pa or more and 250 Pa or less, more preferably 1 00 Pa to 200 Pa, and 0.17 W / cm2 to the electrode installed in the treatment chamber 2 End 0.5W / cm 2 Less than or equal to 0.25 W / cm 2 More than 0.35W / cm 2 Below Silicon oxide film or silicon oxynitride film is formed by supplying high frequency power under the following conditions. do.

[0158] Supplying high-frequency power increases the efficiency of decomposing the source gas in the plasma, resulting in oxygen radicals. As a result, the oxygen content in the oxide insulating film becomes smaller than the stoichiometric ratio. However, in the film formed at the above substrate temperature, Heating causes some of the oxygen in the film to be desorbed. As a result, the oxygen content is less than the stoichiometric composition. It is possible to form an oxide insulating film that contains a large amount of oxygen and from which part of the oxygen is released by heating. do.

[0159] In addition, when an oxide insulating film is provided between the oxide semiconductor layer 104 and the insulating layer 106, In the step of forming the layer 106 , the oxide insulating film serves as a protective film for the oxide semiconductor layer 104 . As a result, damage to the oxide semiconductor layer 104 is reduced, and high-frequency power density is reduced. A force may be used to form the insulating layer 106 .

[0160] For example, a substrate placed in a vacuum-evacuated processing chamber of a plasma CVD device is heated to 180° C. or higher. The temperature is kept at 400° C. or less, more preferably 200° C. to 370° C., and the raw material gas is introduced into the processing chamber. By introducing the gas, the pressure in the processing chamber is adjusted to 20 Pa or more and 250 Pa or less, more preferably 10 The pressure is between 0 Pa and 250 Pa, and high-frequency power is supplied to the electrode installed in the processing chamber. As a result, a silicon oxide film or a silicon oxynitride film can be formed as the oxide insulating film. In addition, by setting the pressure in the processing chamber to 100 Pa or more and 250 Pa or less, the oxide insulation can be improved. When the insulating layer is formed, damage to the oxide semiconductor layer 104 can be reduced.

[0161] As the source gas for the oxide insulating film, a deposition gas containing silicon and an oxidizing gas are used. Representative examples of deposition gases containing silicon include silane, disilane, trisilane, and Examples of oxidizing gases include oxygen, ozone, nitrous oxide, and dioxygen. Examples include nitrogen oxides.

[0162] The insulating layer 107 can be formed by a sputtering method, a CVD method, or the like.

[0163] When a silicon nitride film or a silicon nitride oxide film is formed as the insulating layer 107, the raw material gas The gas used may be a deposition gas containing silicon, an oxidizing gas, or a gas containing nitrogen. Representative examples of deposition gases containing silicon include silane, disilane, trisilane, and Examples of oxidizing gases include oxygen, ozone, nitrous oxide, and fluorinated silane. Nitrogen, etc. Nitrogen-containing gases include nitrogen and ammonia.

[0164] Through the above steps, the transistor 100 can be formed.

[0165] <Modifications of the Transistor 100> An example of the structure of a transistor that is partially different from the transistor 100 will be described below.

[0166] Variation 1 FIG. 9B is a schematic cross-sectional view of a transistor 110, which will be described below as an example. Transistor 1 The transistor 10 differs from the transistor 100 in the structure of the oxide semiconductor layer. In the following, in the case of components having the same configuration or the same function as other configuration examples, The same reference numerals are used and duplicated explanations are omitted.

[0167] The oxide semiconductor layer 114 of the transistor 110 is a semiconductor layer including an oxide semiconductor layer 114a and an oxide The semiconductor layer 114b is laminated thereon.

[0168] Note that the boundary between the oxide semiconductor layer 114a and the oxide semiconductor layer 114b may be unclear. Therefore, in the drawings such as FIG. 9(B), these boundaries are shown by dashed lines.

[0169] Either or both of the oxide semiconductor layer 114a and the oxide semiconductor layer 114b may be In this case, the oxide semiconductor film of one embodiment of the present invention can be used.

[0170] For example, the oxide semiconductor layer 114a is typically made of In-Ga oxide, In-Zn oxide, In-M-Zn oxide (M is Al, Ti, Ga, Y, Zr, La, Ce, Nd, or H When the oxide semiconductor layer 114a is an In-M-Zn oxide, Zn The atomic ratio of In and M excluding oxygen is 100 atomic % in total. In this case, preferably, In is 25 atomic % or more and M is less than 75 atomic %. More preferably, In is 34 atomic % or more and M is less than 66 atomic %. For example, the oxide semiconductor layer 114a has an energy gap of 2 eV or more, preferably 2 Materials with a polarization of .5 eV or more, more preferably 3 eV or more, are used.

[0171] For example, the oxide semiconductor layer 114b contains In or Ga, typically, In-Ga oxide. In-Zn oxide, In-M-Zn oxide (where M is Al, Ti, Ga, Y, Zr, La, Ce, Nd or Hf) and has a conduction band smaller than that of the oxide semiconductor layer 114a. The energy level at the bottom of the oxide semiconductor layer 114b is close to the vacuum level. and the energy level of the conduction band of the oxide semiconductor layer 114a. The difference between the or more, and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less is preferred.

[0172] For example, when the oxide semiconductor layer 114b is an In-M-Zn oxide, Zn and oxygen are The atomic ratio of In and M, excluding the above, is preferably 100 atomic %. Preferably, In is less than 50 atomic % and M is 50 atomic % or more, and more preferably In general, In is less than 25 atomic % and M is 75 atomic % or more.

[0173] For example, the oxide semiconductor layer 114a may have a composition of In:Ga:Zn=1:1:1 or 3:1:2. In addition, a target having an atomic ratio of I Targets with atomic ratios of n:Ga:Zn=1:3:2, 1:6:4, or 1:9:6 Note that the oxide semiconductor layers 114a and 114b can be formed using The atomic ratio may differ from that of the target used, within a range of ±20%. There may be differences.

[0174] The oxide semiconductor layer 114b provided on the upper layer has a content of Ga that functions as a stabilizer. By using an oxide having a high content of fluorine, the oxide semiconductor layer 114a and the oxide semiconductor layer 114 It is possible to suppress the release of oxygen from b.

[0175] In addition, the semiconductor characteristics and electrical characteristics (field effect The appropriate composition should be used depending on the required properties (mobility, threshold voltage, etc.). In order to obtain semiconductor characteristics of a transistor, the oxide semiconductor layer 114a and the oxide semiconductor layer 11 4b Carrier density, impurity concentration, defect density, atomic ratio of metal elements to oxygen, interatomic distance, It is preferable to make the density etc. appropriate.

[0176] Note that in the above description, the oxide semiconductor layer 114 has a structure in which two oxide semiconductor layers are stacked. Although this is illustrated as an example, a structure in which three or more oxide semiconductor layers are stacked may be used.

[0177] Variation 2 FIG. 9C is a schematic cross-sectional view of a transistor 120, which will be described below as an example. Transistor 1 The transistor 20 is different from the transistor 100 in the structure of the oxide semiconductor layer. is different from 0.

[0178] The oxide semiconductor layer 124 of the transistor 120 includes an oxide semiconductor layer 124a, an oxide The semiconductor layer 124b and the oxide semiconductor layer 124c are laminated in this order.

[0179] The oxide semiconductor layer 124a and the oxide semiconductor layer 124b are stacked over the insulating layer 103. The oxide semiconductor layer 124c is formed on the top surface of the oxide semiconductor layer 124b and on a pair of The electrodes 105a and 105b are provided in contact with the upper and side surfaces thereof.

[0180] Among the oxide semiconductor layer 124a, the oxide semiconductor layer 124b, and the oxide semiconductor layer 124c, The oxide semiconductor film of one embodiment of the present invention is applied to any one, any two, or all of the above. It is possible.

[0181] For example, the oxide semiconductor layer 124b may be the oxide semiconductor layer 114 shown in the first modification. For example, the oxide semiconductor layers 124a and 124c may have a similar structure to that of the oxide semiconductor layers 124a and 124c. As the oxide semiconductor layer 114b, a structure similar to that of the oxide semiconductor layer 114b illustrated in the first modification can be used. Cut.

[0182] For example, the oxide semiconductor layer 124a and the oxide semiconductor layer 124c may be provided with a layer having a function as a stabilizer. By using an oxide having a high Ga content, the oxide semiconductor layer 124a and the oxide The release of oxygen from the semiconductor layer 124b and the oxide semiconductor layer 124c can be suppressed. do.

[0183] In addition, when a channel is mainly formed in the oxide semiconductor layer 124b, for example, The conductor layer 124b is made of an oxide containing a large amount of In. By providing the pair of electrodes 105a and 105b, the on-current of the transistor 120 is increased. It can be done.

[0184] <Other examples of transistor configurations> A top-gate transistor to which the oxide semiconductor film of one embodiment of the present invention can be applied will be described below. A configuration example of the data recorder will be described below.

[0185] Example of configuration FIG. 11A is a schematic cross-sectional view of a top-gate transistor 150, which will be described below. vinegar.

[0186] The transistor 150 is an oxide semiconductor provided on a substrate 101 having an insulating layer 151 provided thereon. a pair of electrodes 105a and 105b in contact with an upper surface of the oxide semiconductor layer 104; an insulating layer 103 provided over an oxide semiconductor layer 104 and a pair of electrodes 105a and 105b; A gate electrode 102 is provided on the insulating layer 103 so as to overlap with the oxide semiconductor layer 104. In addition, an insulating layer 152 is provided to cover the insulating layer 103 and the gate electrode 102. do.

[0187] The oxide semiconductor film of one embodiment of the present invention is applied to the oxide semiconductor layer 104 of the transistor 150. It is possible.

[0188] The insulating layer 151 has a function of suppressing diffusion of impurities from the substrate 101 to the oxide semiconductor layer 104. For example, the insulating layer 107 may have the same structure as the insulating layer 107. 151 does not have to be provided if it is not necessary.

[0189] The insulating layer 152 has a blocking effect against oxygen, hydrogen, water, etc., similar to the insulating layer 107. Note that the insulating layer 107 may not be provided if it is not necessary. stomach.

[0190] <<Variation>> An example of the structure of a transistor that is partially different from the transistor 150 will be described below.

[0191] FIG. 11B is a schematic cross-sectional view of a transistor 160, which will be described below as an example. The transistor 160 differs from the transistor 150 in the structure of the oxide semiconductor layer.

[0192] The oxide semiconductor layer 164 included in the transistor 160 includes an oxide semiconductor layer 164a and an oxide The semiconductor layer 164b and the oxide semiconductor layer 164c are stacked in this order.

[0193] Among the oxide semiconductor layer 164a, the oxide semiconductor layer 164b, and the oxide semiconductor layer 164c, The oxide semiconductor film of one embodiment of the present invention is applied to any one, any two, or all of the above. It is possible.

[0194] For example, the oxide semiconductor layer 164b may be the oxide semiconductor layer 114 shown in the first modification. For example, the oxide semiconductor layers 164a and 164c may have a similar structure to that of the oxide semiconductor layers 164a and 164c. As the oxide semiconductor layer 114b, a structure similar to that of the oxide semiconductor layer 114b illustrated in the first modification can be used. Cut.

[0195] For example, the oxide semiconductor layer 164a and the oxide semiconductor layer 164c may be provided with a layer having a function as a stabilizer. By using an oxide having a high Ga content, the oxide semiconductor layer 164a and the oxide This can suppress release of oxygen from the semiconductor layer 164b and the oxide semiconductor layer 164c.

[0196] When the oxide semiconductor layer 164 is formed, the oxide semiconductor layer 164c and the oxide semiconductor The oxide semiconductor layer 164b is processed by etching to form an oxide semiconductor film that is to be the oxide semiconductor layer 164a. The oxide semiconductor film is then processed by a dry etching method to form an oxide semiconductor film. When the oxide semiconductor layer 164a is formed, the reaction product of the oxide semiconductor film is The oxide semiconductor layer 164c is then reattached to the side surfaces of the oxide semiconductor layer 164b and the oxide semiconductor layer 164c, forming a sidewall protective layer (also called a rabbit ear). The reaction product may be formed by the sputtering phenomenon. In addition to redeposition, redeposition may occur during dry etching.

[0197] FIG. 11C shows a sidewall protective layer 164d formed on the side surface of the oxide semiconductor layer 164 as described above. 1 shows a schematic cross-sectional view of a transistor 161 when The other configurations of the transistor 1 are the same as those of the transistor 160.

[0198] The sidewall protection layer 164d mainly contains the same material as the oxide semiconductor layer 164a. The wall protection layer 164d is formed by a layer (here, an insulating layer) provided under the oxide semiconductor layer 164a. 151) (e.g., silicon).

[0199] As shown in FIG. 11C, the side surface of the oxide semiconductor layer 164b is covered with a sidewall protective layer 164d. By covering the pair of electrodes 105a and 105b with a material that does not contact the pair of electrodes 105a and 105b, When a channel is formed mainly in the conductor layer 164b, the transistor is turned off as intended. This makes it possible to realize a transistor having excellent off-state characteristics by suppressing unwanted leakage current. The wall protection layer 164d is made of a material having a high Ga content that functions as a stabilizer. As a result, the desorption of oxygen from the side surface of the oxide semiconductor layer 164b is effectively suppressed, and the electrical characteristics are improved. This makes it possible to realize a transistor with excellent stability.

[0200] This embodiment may be implemented in appropriate combination with other embodiments described in this specification. can be done.

[0201] (Embodiment 3) In this embodiment, a structure of a display panel according to one embodiment of the present invention will be described with reference to FIG. explain.

[0202] FIG. 12A is a top view of a display panel according to one embodiment of the present invention, and FIG. A pixel circuit that can be used when a liquid crystal element is applied to a pixel of a display panel according to one embodiment of the present invention. FIG. 12C is a circuit diagram for explaining a display panel according to one embodiment of the present invention. A circuit diagram for explaining a pixel circuit that can be used when an organic EL element is used as a substrate. It is.

[0203] The transistor disposed in the pixel portion can be formed according to the embodiment 2. Since the transistor can be easily made into an n-channel type, the n-channel A part of the driver circuit can be made of type transistors on the same substrate as the transistors in the pixel section. In this manner, the transistor described in Embodiment 2 is used in the pixel portion and the driver circuit. This makes it possible to provide a highly reliable display device.

[0204] An example of a block diagram of an active matrix display device is shown in FIG. On a substrate 500, a pixel section 501, a first scanning line driving circuit 502, a second scanning line driving circuit The pixel portion 501 includes a signal line driver circuit 503 and a signal line driver circuit 504. A first scanning line driving circuit 502 and a second scanning line driving circuit 504 are arranged to extend from the first scanning line driving circuit 502 and a second scanning line driving circuit 504. The scanning line driving circuit 503 is extended and arranged. , each of which has a pixel having a display element arranged in a matrix. 500 is connected via a flexible printed circuit (FPC) or other connection part. It is connected to a timing control circuit (also called a controller or control IC).

[0205] In FIG. 12A, a first scanning line driver circuit 502, a second scanning line driver circuit 503, a signal line The driver circuit 504 is formed on the same substrate 500 as the pixel portion 501. This reduces the number of components, such as the drive circuits, and thus reduces costs. In addition, when a driving circuit is provided outside the substrate 500, it is necessary to extend the wiring. However, by providing a driving circuit on the same substrate 500, the number of connections between the wirings can be reduced. Therefore, it is possible to improve the reliability of the semiconductor device and to improve the yield. This can be done.

[0206] <Liquid crystal panel> An example of the circuit configuration of a pixel is shown in FIG. 12(B). 4 shows a pixel circuit that can be applied to the pixel.

[0207] This pixel circuit can be applied to a configuration in which one pixel has multiple pixel electrode layers. The pixel electrode layer is connected to different transistors, and each transistor is driven by a different gate signal. This allows individual pixels of a multi-domain pixel to be The signals applied to the electrode layers can be controlled independently.

[0208] The gate wiring 512 of the transistor 516 and the gate wiring 513 of the transistor 517 are , are separated so that different gate signals can be applied. On the other hand, The functioning source or drain electrode layer 514 is a transistor 516 and a transistor The transistors 516 and 517 are used in common. The transistors described in 2 can be appropriately used. This makes it possible to realize a highly reliable liquid crystal display. A display panel can be provided.

[0209] A first pixel electrode layer electrically connected to the transistor 516 and a second pixel electrode layer electrically connected to the transistor 517 The shape of the second pixel electrode layer that is electrically connected to the first pixel electrode layer will be described. The shape of the electrode layer is separated by slits. The first pixel electrode layer spreads in a V-shape. The second pixel electrode layer is formed so as to surround the outside of the first pixel electrode layer.

[0210] The gate electrode of the transistor 516 is connected to the gate wiring 512. The gate electrode is connected to the gate wiring 513. By applying different gate signals to the transistors 516 and 517, the operation timing of the transistors 516 and 517 is By varying the polarity, the alignment of the liquid crystal can be controlled.

[0211] In addition, the capacitance wiring 510, the gate insulating film functioning as a dielectric, and the first pixel electrode layer or A storage capacitor may be formed by a capacitor electrode electrically connected to the second pixel electrode layer.

[0212] The multi-domain structure includes a first liquid crystal element 518 and a second liquid crystal element 519 in one pixel. The first liquid crystal element 518 is composed of a first pixel electrode layer, a counter electrode layer, and a liquid crystal layer therebetween. The second liquid crystal element 519 is composed of a second pixel electrode layer, a counter electrode layer, and a liquid crystal layer therebetween. do.

[0213] Note that the pixel circuit shown in FIG. 12B is not limited to this. The pixels are now equipped with new switches, resistors, capacitors, transistors, sensors, logic circuits, etc. Any of the above may be added.

[0214] <Organic EL panel> Another example of the circuit configuration of a pixel is shown in FIG. 12(C). 4 shows the pixel structure of the display panel.

[0215] In an organic EL element, when a voltage is applied to the light-emitting element, electrons are emitted from one of a pair of electrodes. Holes are injected from the other side into the layer containing the light-emitting organic compound, causing a current to flow. The electrons and holes recombine to form an excited state in the light-emitting organic compound, which When the excited state of the electron returns to the ground state, light is emitted. The element is called a current-excited light-emitting element.

[0216] FIG. 12C is a diagram showing an example of an applicable pixel circuit. An example in which two transistors are used in one pixel is shown. The film can be used for the channel formation region of an n-channel transistor. The pixel circuit can apply digital time gray scale driving.

[0217] Regarding the configuration of an applicable pixel circuit and the operation of a pixel when digital time gray scale driving is applied, He explains.

[0218] The pixel 520 includes a switching transistor 521, a driving transistor 522, and a light-emitting element The switching transistor 521 has a gate electrode 524 and a capacitance element 523. The first electrode layer is connected to the scanning line 526, and the second electrode (one of the source electrode layer and the drain electrode layer) is connected to the scanning line 526. ) is connected to a signal line 525, and the second electrode (the other of the source electrode layer and the drain electrode layer) is The driving transistor 522 is connected to the gate electrode layer of the driving transistor 522. The gate electrode layer is connected to a power supply line 527 via a capacitance element 523, and the first electrode is connected to the power supply line 527. 27, and the second electrode is connected to the first electrode (pixel electrode) of the light emitting element 524. The second electrode of the light emitting element 524 corresponds to a common electrode 528. The common electrode 528 is formed on the same substrate. The common potential line is electrically connected to the common potential line formed in the

[0219] The switching transistor 521 and the driving transistor 522 are the same as those described in the second embodiment. This allows the use of transistors that illuminate the display, making it possible to achieve highly reliable organic EL displays. A panel can be provided.

[0220] The potential of the second electrode (common electrode 528) of the light emitting element 524 is set to a low power supply potential. The power supply potential is a potential lower than the high power supply potential set on the power supply line 527, for example, GND The low power supply potential can be set to 0 V or the like. The high power supply potential and the low power supply potential are set so that the potential difference is equal to or greater than the threshold voltage. By applying a voltage to the light emitting element 524, a current flows through the light emitting element 524, causing it to emit light. The forward voltage in 4 refers to the voltage required to achieve the desired brightness, and must be at least the forward threshold. greater than the minimum voltage.

[0221] The capacitance element 523 can be omitted by substituting the gate capacitance of the driving transistor 522. The gate capacitance of the driving transistor 522 can be omitted. A capacitance may be formed between the first electrode layer and the second electrode layer.

[0222] Next, a signal input to the driving transistor 522 will be described. In this case, the driving transistor 522 is either definitely on or definitely off. A video signal such as the above is input to the driving transistor 522. In order to operate the drive transistor 522 in a linear region, a voltage higher than the voltage of the power supply line 527 is applied to the drive transistor 522. A signal line 525 is connected to the gate electrode layer of the transistor 522. A voltage equal to or greater than the threshold voltage Vth of the input transistor 522 is applied.

[0223] When analog gradation driving is performed, the gate electrode layer of the driving transistor 522 is connected to the light emitting element 52 A voltage equal to or greater than the sum of the forward voltage of the transistor 4 and the threshold voltage Vth of the driving transistor 522 is applied. In addition, a video signal is input so that the driving transistor 522 operates in the saturation region. A current flows through the light emitting element 524. In addition, the driving transistor 522 is operated in a saturation region. In order to achieve this, the potential of the power supply line 527 is set higher than the gate potential of the driving transistor 522. By converting the video signal into an analog signal, a current corresponding to the video signal is passed through the light emitting element 524. , analog gray scale driving can be performed.

[0224] The configuration of the pixel circuit is not limited to the pixel configuration shown in FIG. (C) A switch, a resistive element, a capacitive element, a sensor, a transistor or a logic Circuits etc. may be added.

[0225] (Embodiment 4) In this embodiment, a semiconductor device and an electronic device using a metal oxide film according to one embodiment of the present invention will be described. The configuration will be described with reference to FIG. 13 and FIG.

[0226] FIG. 13 is a block diagram of an electronic device including a semiconductor device to which a metal oxide film of one embodiment of the present invention is applied. This is a diagram.

[0227] FIG. 14 is an external view of an electronic device including a semiconductor device to which a metal oxide film of one embodiment of the present invention is applied. It is.

[0228] The electronic device shown in FIG. 13 includes an RF circuit 901, an analog baseband circuit 902, a digital A baseband circuit 903, a battery 904, a power supply circuit 905, an application processor 906, flash memory 910, display controller 911, memory circuit 91 2. Display 913, touch sensor 919, audio circuit 917, keyboard 918, etc. It is composed of:

[0229] The application processor 906 includes a CPU 907, a DSP 908, and an interface ( The memory circuit 912 is composed of an SRAM or a DRAM. It is possible.

[0230] By applying the transistor described in Embodiment 2 to the memory circuit 912, It is possible to provide a highly reliable electronic device capable of writing and reading information.

[0231] In addition, the transistor described in the second embodiment may be included in the CPU 907 or the DSP 908. By applying this to registers, etc., it is possible to write and read information with high reliability. It is possible to provide high-quality electronic equipment.

[0232] In addition, when the off-leak current of the transistor described in the second embodiment is extremely small, It is possible to provide a memory circuit 912 capable of storing data for a long period of time and having sufficiently reduced power consumption. During the power gating period, the state before the power gating is registered. A CPU 907 or DSP 908 may be provided, which may store the data in a memory or the like.

[0233] The display 913 includes a display unit 914, a source driver 915, and a gate driver 91 It is composed of 6.

[0234] The display unit 914 has a plurality of pixels arranged in a matrix. Each pixel includes a pixel circuit. The pixel circuit is electrically connected to a gate driver 916 .

[0235] The transistor described in Embodiment 2 is used as appropriate for the pixel circuit or the gate driver 916. This makes it possible to provide a highly reliable display.

[0236] Examples of electronic devices include television sets (also known as televisions or television receivers). (hereinafter referred to as "computer monitors"), digital cameras, digital video cameras, and other cameras digital photo frames; mobile phones (also called mobile phones or mobile phone devices); Examples include game machines, mobile information terminals, audio playback devices, and large game machines such as pachinko machines. do.

[0237] FIG. 14A shows a portable information terminal, which includes a main body 1001, a housing 1002, a display unit 100 The display unit 1003b is a touch panel. The screen can be operated by touching keyboard buttons 1004 displayed on the display unit 1003b. Of course, the display unit 1003a can be configured as a touch panel. The transistor described in Embodiment 2 may be used as a switching element in a liquid crystal panel or By fabricating an organic light-emitting panel and applying it to the display units 1003a and 1003b, reliability is improved. It can be a highly portable information terminal.

[0238] The portable information terminal shown in FIG. 14(A) displays various information (still images, videos, text images, etc.). ), calendar, date or time display function, The ability to manipulate or edit the information displayed, and to process it using various software (programs) In addition, the rear and side of the housing can have external connection terminals ( It may also be configured to include an earphone jack, a USB terminal, a recording medium insertion portion, etc.

[0239] The portable information terminal shown in FIG. 14(A) can also be configured to transmit and receive information wirelessly. You can wirelessly purchase and download the desired book data from the electronic book server. It is also possible to configure it in this way.

[0240] FIG. 14B shows a portable music player. The main body 1021 has a display unit 1023 and an earphone. A fixing part 1022 for mounting, a speaker, an operation button 1024, and an external memory slot The transistor shown in the second embodiment is used as a switching element. By manufacturing a liquid crystal panel or an organic light-emitting panel as the display unit 1023, This makes it possible to provide a more reliable portable music player.

[0241] Furthermore, the portable music player shown in FIG. 14(B) has an antenna, a microphone function, and a wireless function. In addition, by linking it with a mobile phone, you can enjoy wireless hands-free driving while driving a passenger car. Conversation by telephone is also possible.

[0242] FIG. 14C shows a mobile phone, which is composed of two housings, a housing 1030 and a housing 1031. The housing 1031 includes a display panel 1032, a speaker 1033, a microphone, and a 1034, pointing device 1036, camera lens 1037, external connection terminal The housing 1030 also includes a solar cell for charging the mobile phone. The housing 10 is also provided with an antenna. The transistor described in the second embodiment is built in the display panel 1032. By applying this to the above, a highly reliable mobile phone can be achieved.

[0243] The display panel 1032 is equipped with a touch panel, and the image displayed on the display panel 1032 is shown in FIG. The operation keys 1035 are indicated by dotted lines. It also implements a boost circuit to boost the input voltage to the voltage required for each circuit.

[0244] For example, the power transistor used in a power supply circuit such as a boost circuit is also described in the second embodiment. The thickness of the metal oxide film of the transistor is set to 2 μm or more and 50 μm or less. It is possible.

[0245] The display direction of the display panel 1032 changes appropriately depending on the usage mode. Since it has a camera lens 1037 on the same surface as 1032, video telephony is possible. The speaker 1033 and the microphone 1034 are not limited to voice calls, but can also be used for video calls, Recording and playback are possible. Furthermore, the housing 1030 and the housing 1031 can be slid to each other. As shown in 14(C), the device can be folded from the unfolded state to the overlapped state, making it suitable for carrying. This makes it possible to miniaturize the device.

[0246] The external connection terminal 1038 can be connected to various cables such as AC adapters and USB cables. It is possible to charge the battery and to communicate data with a personal computer, etc. A recording medium can be inserted into the memory slot 1041 to accommodate the storage and transfer of larger amounts of data. do.

[0247] In addition to the above functions, even if the device has infrared communication function, TV reception function, etc. good.

[0248] FIG. 14D shows an example of a television device. The television device 1050 includes: A display unit 1053 is built into the housing 1051. The display unit 1053 displays images. In addition, the CPU is built into the stand 1055 that supports the housing 1051. The transistor described in the second embodiment is applied to the display unit 1053 and the CPU. This makes it possible to provide a highly reliable television device 1050.

[0249] The television device 1050 can be operated using an operation switch provided on the housing 1051 or a separate remote control. The remote control can also be operated by the remote control. A display unit for displaying the output information may be provided.

[0250] The television device 1050 is configured to include a receiver, a modem, and the like. It can receive more general television broadcasts, and can also be connected to a modem via wired or wireless connection. By connecting to a network, communication can be one-way (sender to receiver) or two-way. It is also possible to communicate information (between a sender and a receiver, or between receivers).

[0251] The television device 1050 also includes an external connection terminal 1054 and a storage medium playback / recording unit 10 52, an external memory slot. An external connection terminal 1054 is provided for connecting a USB cable, etc. It can be connected to various cables, enabling data communication with a personal computer, etc. In the storage medium playback / recording unit 1052, a disk-shaped recording medium is inserted and recorded on the recording medium. It is possible to read data stored in the external memory and write data to the recording medium. Displays images and videos stored in the external memory 1056 inserted in the slot. It is also possible to display it on the display unit 1053.

[0252] In addition, when the off-leak current of the transistor described in the second embodiment is extremely small, By applying this transistor to the external memory 1056 and the CPU, power consumption is sufficiently reduced. This can result in a television apparatus 1050 with reduced noise and reliability. [Explanation of symbols]

[0253] 100 transistors 101 Substrate 102 Gate electrode 103 Insulating layer 104 Oxide semiconductor layer 105a electrode 105b electrode 106 Insulating Layer 107 Insulating layer 110 Transistor 114 Oxide semiconductor layer 114a Oxide semiconductor layer 114b Oxide semiconductor layer 120 Transistor 124 Oxide semiconductor layer 124a Oxide semiconductor layer 124b Oxide semiconductor layer 124c Oxide semiconductor layer 150 Transistors 151 Insulating layer 152 Insulating layer 160 Transistors 161 Transistor 164 Oxide semiconductor layer 164a Oxide semiconductor layer 164b Oxide semiconductor layer 164c Oxide semiconductor layer 164d sidewall protection layer 200 Quartz glass substrate 202 Dummy board 204 Metal oxide film 210a area 210b area 500 boards 501 Pixel section 502 Scanning line driver circuit 503 Scanning line driver circuit 504 Signal line driver circuit 510 Capacitance wiring 512 Gate wiring 513 Gate wiring 514 Drain electrode layer 516 Transistor 517 Transistor 518 Liquid crystal element 519 Liquid crystal element 520 pixels 521 Switching Transistors 522 Driving Transistor 523 Capacitive element 524 Light emitting element 525 Signal Line 526 scan lines 527 Power line 528 Common electrode 901 RF circuit 902 Analog Baseband Circuit 903 Digital Baseband Circuit 904 Battery 905 Power supply circuit 906 Application Processor 907 CPU 908 DSP 910 Flash Memory 911 Display Controller 912 Memory Circuit 913 Display 914 Display section 915 Source Driver 916 Gate Driver 917 Voice Circuit 918 Keyboard 919 Touch Sensor 1001 Main unit 1002 Case 1003a Display section 1003b Display section 1004 Keyboard Buttons 1021 Main unit 1022 Fixed part 1023 Display section 1024 operation buttons 1025 external memory slot 1030 Case 1031 Case 1032 Display Panel 1033 Speaker 1034 Microphone 1035 Operation Key 1036 Pointing Device 1037 Camera Lenses 1038 External connection terminal 1040 Solar Cell 1041 External memory slot 1050 Television Equipment 1051 Case 1052 Storage media playback and recording unit 1053 Display section 1054 External connection terminal 1055 Stand 1056 External Memory

Claims

1. a first transistor, a second transistor, a light-emitting element, and a capacitor; one of a source electrode and a drain electrode of the first transistor is electrically connected to a gate electrode of the second transistor and one electrode of the capacitance element; The other electrode of the capacitance element is electrically connected to a power supply line, A display device in which a potential of the power supply line is supplied to the light emitting element through at least a channel of the second transistor, At least one of the first transistor and the second transistor includes a gate electrode, an oxide semiconductor layer, and a gate insulating film having a region located between the gate electrode and the oxide semiconductor layer; In the oxide semiconductor layer, a plurality of circumferentially arranged spots are observed in a nanobeam electron diffraction pattern, which are different from a plurality of circumferentially arranged spots having regularity indicating crystals oriented in a specific plane, the oxide semiconductor layer has a region in contact with an upper surface of the insulating film, the insulating film includes silicon oxide; The display device, wherein the gate insulating film comprises silicon oxide.

2. a first transistor, a second transistor, a light-emitting element, and a capacitor; one of a source electrode and a drain electrode of the first transistor is electrically connected to a gate electrode of the second transistor and one electrode of the capacitance element; The other electrode of the capacitance element is electrically connected to a power supply line, A display device in which a potential of the power supply line is supplied to the light emitting element through at least a channel of the second transistor, At least one of the first transistor and the second transistor includes a first conductive layer having a function as a gate electrode, a first insulating film located above the first conductive layer, and an oxide semiconductor layer having a region in contact with an upper surface of the first insulating film; In the oxide semiconductor layer, a plurality of circumferentially arranged spots are observed in a nanobeam electron diffraction pattern, which are different from a plurality of circumferentially arranged spots having regularity indicating crystals oriented in a specific plane, a second insulating film having a region in contact with an upper surface of the oxide semiconductor layer; the first insulating film includes silicon oxide; The display device, wherein the second insulating film comprises silicon oxide.

3. In claim 1 or 2, A display device in which a nanobeam electron diffraction pattern before irradiating the oxide semiconductor layer with an electron beam focused to 1 nmφ is similar to a nanobeam electron diffraction pattern after irradiating the oxide semiconductor layer with the electron beam for one minute.

4. In any one of claims 1 to 3, The carbon concentration of the oxide semiconductor layer is 4×10 ２１ atoms / cm ３ A display device that is less than

5. In any one of claims 1 to 4, The hydrogen concentration of the oxide semiconductor layer is 1×10 ２２ atoms / cm ３ A display device that is less than

6. In any one of claims 1 to 5, The nanobeam electron diffraction pattern is observed by irradiating an electron beam having a beam diameter of 1 nmφ.

7. In any one of claims 1 to 6, the oxide semiconductor layer has a plurality of crystals, The crystal plane orientations of the plurality of crystals are irregular, A display device having an area in which no peaks resulting from the plurality of crystals are observed in XRD measurement.

8. In claim 7, A display device, wherein the size of each of the plurality of crystals is not less than 1 nm and not more than 10 nm.

Images