Vertical Memory Device

Abstract

To provide a vertical memory device with improved electrical characteristics.SOLUTION: A vertical memory device includes: a lower circuit pattern formed on a first substrate including a first region, a second region, and a third region; a second substrate formed on the lower circuit pattern in the first and second regions of the first substrate; a first conductor formed on the lower circuit pattern in the third region of the first substrate, formed at the same height as that of the second substrate, and separated from the second substrate; a dielectric film structure formed on the first conductor; a capacitor formed on the dielectric film structure and including a second conductor; gate electrodes separated from each other on the second substrate along the vertical direction perpendicular to the upper surface of the first substrate in the first and second regions of the first substrate; and a channel extending vertically through the gate electrode in the first region of the first substrate, and a memory cell is formed in the first region above the lower circuit pattern, a contact plug that transmits an electrical signal to the memory cell is formed in the second region, and a through-via through which an electrical signal is transmitted to the lower circuit pattern is formed in the third region.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a vertical memory device, and more particularly to a vertical memory device having improved electrical characteristics. [Background technology]

[0002] The capacitor required in a VNAND flash memory device can be mainly secured through contact plugs formed in the peripheral circuit region, but in a COP structure in which these are not formed, the capacitor can only be secured through a through via (THV).

[0003] However, as the number of stacked levels in a VNAND flash memory device increases, the height of the mold including the gate electrode increases, and if more THVs are formed to ensure sufficient capacitor capacity, there is a problem that the possibility of cracks occurring in the mold increases. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Korean Patent Publication No. 2008-12667 Summary of the Invention [Problem to be solved by the invention]

[0005] SUMMARY OF THE PRESENT DISCLOSURE The present invention has been made in consideration of the above-mentioned problems in the conventional vertical memory devices, and an object of the present invention is to provide a vertical memory device having improved electrical characteristics. [Means for solving the problem]

[0006] In order to achieve the above object, a vertical memory device according to the present invention includes a lower circuit pattern formed on a first substrate including a first region, a second region at least partially surrounding the first region, and a third region at least partially surrounding the second region; a second substrate formed on the lower circuit pattern in the first and second regions of the first substrate; a first conductor formed on the lower circuit pattern in the third region of the first substrate, the first conductor being formed at substantially the same height as the second substrate and spaced apart from the second substrate; a capacitor including a dielectric layer structure formed on the first conductor; and a second conductor formed on the dielectric layer structure. a first region and a second region of the substrate, the first region and the second region of the substrate having gate electrodes spaced apart from each other on the second substrate along a vertical direction substantially perpendicular to an upper surface of the first substrate, and a channel extending in the vertical direction through the gate electrodes in the first region of the first substrate, a memory cell is formed in the first region above the lower circuit pattern, a contact plug is formed in the second region for transmitting an electrical signal to the memory cell, and a through via is formed in the third region for transmitting an electrical signal to the lower circuit pattern, and the first conductor has a maximum area in the third region of the first substrate without contacting the contact plug, the contact plug contacts an upper surface of the lower circuit pattern through the through via in the third region of the first substrate; In the second region of the first substrate, a sacrificial layer structure is provided at substantially the same height as the dielectric layer structure on the second substrate, the sacrificial layer structure being spaced apart from the dielectric layer structure and including substantially the same material as the dielectric layer structure.

[0008] a first contact plug electrically connected to the first conductor and a second contact plug electrically connected to the second conductor; and a through via electrically connected to the lower circuit pattern and spaced apart from the capacitor in a horizontal direction substantially parallel to an upper surface of the first substrate, the first contact plug electrically connected to the first conductor and a second contact plug electrically connected to the second conductor and a through via electrically connected to the lower circuit pattern and spaced apart from the capacitor in a horizontal direction substantially parallel to an upper surface of the first substrate, the first contact plug electrically connected to the first conductor and a second contact plug electrically connected to the second conductor and a through via electrically connected to the lower circuit pattern and spaced apart from the capacitor in a horizontal direction substantially parallel to an upper surface of the first substrate, A memory cell is formed on the lower circuit pattern, and a contact plug is formed to transmit an electrical signal to the memory cell. The first conductor is on the first substrate, The contact plug and a sacrificial layer structure on the first substrate at substantially the same height as the dielectric layer structure on the second substrate, the sacrificial layer structure being spaced apart from the dielectric layer structure and including substantially the same material as the dielectric layer structure. Effect of the Invention

[0009] According to the vertical memory device of the present invention, a capacitor including a first conductor, a dielectric film structure, and a second conductor sequentially stacked in a peripheral region surrounding a cell region is provided, so that the capacitor can have the largest possible area without contacting a through via. As a result, the vertical memory device can have a capacitor with a large electrical capacitance. [Brief description of the drawings]

[0010] [Figure 1] 1 is a cross-sectional view illustrating a schematic configuration of a vertical memory device according to an embodiment of the inventive concept; [Diagram 2] 1 is a cross-sectional view illustrating a schematic configuration of a vertical memory device according to an embodiment of the inventive concept; [Figure 3A] 1 is a plan view illustrating a schematic configuration of a vertical memory device according to an embodiment of the inventive concept; [Figure 3B] 1 is a plan view illustrating a schematic configuration of a vertical memory device according to an embodiment of the inventive concept; [Figure 4] 1A to 1C are cross-sectional views illustrating a method of manufacturing a vertical memory device according to an embodiment of the inventive concept; [Diagram 5] 1A to 1C are cross-sectional views illustrating a method of manufacturing a vertical memory device according to an embodiment of the inventive concept; [Figure 6] 1A to 1C are cross-sectional views illustrating a method of manufacturing a vertical memory device according to an embodiment of the inventive concept; [Figure 7] 1A to 1C are cross-sectional views illustrating a method of manufacturing a vertical memory device according to an embodiment of the inventive concept; [Figure 8] 1A to 1C are cross-sectional views illustrating a method of manufacturing a vertical memory device according to an embodiment of the inventive concept; [Figure 9] 1A to 1C are cross-sectional views illustrating a method of manufacturing a vertical memory device according to an embodiment of the inventive concept; [Figure 10] 1A to 1C are cross-sectional views illustrating a method of manufacturing a vertical memory device according to an embodiment of the inventive concept; [Figure 11] 1A to 1C are cross-sectional views illustrating a method of manufacturing a vertical memory device according to an embodiment of the inventive concept; [Figure 12] 1A to 1C are cross-sectional views illustrating a method of manufacturing a vertical memory device according to an embodiment of the inventive concept; [Figure 13] 1A to 1C are cross-sectional views illustrating a method of manufacturing a vertical memory device according to an embodiment of the inventive concept; [Figure 14] 1A to 1C are cross-sectional views illustrating a method of manufacturing a vertical memory device according to an embodiment of the inventive concept; [Figure 15] 1A to 1C are cross-sectional views illustrating a method of manufacturing a vertical memory device according to an embodiment of the inventive concept; [Figure 16] 1A to 1C are cross-sectional views illustrating a method of manufacturing a vertical memory device according to an embodiment of the inventive concept; [Figure 17] 1 is a cross-sectional view illustrating a vertical memory device according to an embodiment of the inventive concept; [Figure 18] 1 is a cross-sectional view illustrating a vertical memory device according to an embodiment of the inventive concept; [Figure 19] 1 is a cross-sectional view illustrating a vertical memory device according to an embodiment of the inventive concept; [Figure 20] 1A to 1C are cross-sectional views illustrating a method of manufacturing a vertical memory device according to an embodiment of the inventive concept; [Figure 21] 1 is a cross-sectional view illustrating a vertical memory device according to an embodiment of the inventive concept; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Next, a specific example of an embodiment of a vertical memory device according to the present invention will be described with reference to the drawings.

[0012] In the detailed description of the invention below, a direction substantially perpendicular to the top surface of the first substrate is defined as a first direction, and two horizontal directions substantially parallel to the top surface of the first substrate that intersect with each other are defined as a second and a third direction, respectively. In an embodiment of the present invention, the second and third directions are perpendicular to each other.

[0013] 1, 2, 3A, and 3B are cross-sectional and plan views illustrating a schematic configuration of a vertical memory device according to an embodiment of the present invention. Specifically, FIG. 1 is a cross-sectional view of a vertical memory device cut in a second direction, FIG. 2 is a cross-sectional view of the vertical memory device cut in a third direction, and FIGS. 3A and 3B are plan views showing the layout of a first conductor and a through via.

[0014] 1, 2, 3A, and 3B, the vertical memory device includes a lower circuit pattern formed on a first substrate 100, a second substrate 250 and a capacitor formed on the lower circuit pattern, a channel connection pattern 480 formed on the second substrate 250, a support film 320, a support pattern 322, a sacrificial film structure 300 and a memory cell, contact plugs (542, 543, 544, 545, 546) formed on the second substrate 250, the capacitor, and the lower circuit pattern, and an upper wiring structure. The vertical memory device further includes an isolation structure, first to third interlayer insulating films (160, 230, 240), a fourth interlayer insulating pattern 260, and fifth to thirteenth interlayer insulating films (350, 360, 440, 560, 580, 600, 620, 640, 660).

[0015] The first and second substrates (100, 250) may each comprise a semiconductor material such as silicon, germanium, silicon-germanium, or a III-V compound such as GaP, GaAs, GaSb, etc. According to some embodiments, the first and second substrates (100, 250) may each be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate. In an exemplary embodiment, the second substrate 250 may include, for example, polysilicon doped with n-type impurities.

[0016] The first substrate 100 can be divided into a field region having an isolation pattern 110 formed thereon and an active region 105 having no isolation pattern. The isolation pattern 110 includes an oxide, such as silicon oxide. In the exemplary embodiment, the first substrate 100 includes first to third regions (I, II, III). In the following detailed description of the invention, each of the first to third regions (I, II, III) includes not only the first substrate 100 itself but also the space formed above the first substrate 100 in the first direction.

[0017] In this case, the first region (I) may be a cell array region in which memory cells are formed, the second region (II) may be an extension region or pad region at least partially surrounding the first region (I) in which contact plugs and upper wiring structures for transmitting electrical signals to the memory cells are formed, and the third region (III) may be a peripheral region at least partially surrounding the second region (II) in which through vias (THVs) for transmitting electrical signals to a lower circuit pattern, contact plugs for transmitting electrical signals to a capacitor, and upper wiring structures connected to them are formed. The first and second regions (I, II) together form a cell region, whereby a third region (III), a peripheral region, at least partially surrounds the cell region. 1, 2, 3A, and 3B show a part of each of the first to third regions (I, II, III).

[0018] In an exemplary embodiment, the vertical memory device has a cell over peri (COP) structure. That is, a lower circuit pattern is formed on the first substrate 100 including the first to third regions (I, II, III), and memory cells, contact plugs, through vias, and upper wiring structures are formed on the lower circuit pattern. In this case, the memory cell is formed on the second substrate 250 in a first region (I) of the first substrate 100, the contact plug and a portion of the upper wiring structure are formed on the second substrate 250 in a second region (II) of the first substrate 100, and the contact plug and a portion of the upper wiring structure, and the through via are formed on the capacitor and the lower circuit pattern in a third region (III) of the first substrate 100.

[0019] The lower circuit pattern may include, for example, a transistor, a lower contact plug, a lower wiring, a lower via, and the like. In one embodiment, a first transistor includes a first lower gate structure 152 formed on a first substrate 100 and a first impurity region 102 formed on an active region 105 adjacent to the first lower gate structure 152; a second transistor including a second lower gate structure 154 formed on the first substrate 100 and a second impurity region 104 formed on an active region 105 adjacent to the second lower gate structure 154; a third transistor including a third lower gate structure 156 formed on the first substrate 100 and a third impurity region 106 formed on an active region 105 adjacent to the third lower gate structure 156; A fourth transistor is formed, the fourth transistor including a fourth lower gate structure 158 formed on the first substrate 100 and a fourth impurity region 108 formed on the active region 105 adjacent to the fourth lower gate structure 158.

[0020] The first lower gate structure 152 includes a first lower gate insulation pattern 122, a first lower gate electrode 132, and a first lower gate mask 142, which are sequentially stacked on the first substrate 100; the second lower gate structure 154 includes a second lower gate insulation pattern 124, a second lower gate electrode 134, and a second lower gate mask 144, which are sequentially stacked on the first substrate 100; the third lower gate structure 156 includes a third lower gate insulation pattern 126, a third lower gate electrode 136, and a third lower gate mask 146, which are sequentially stacked on the first substrate 100; and the fourth lower gate structure 158 includes a fourth lower gate insulation pattern 128, a fourth lower gate electrode 138, and a fourth lower gate mask 148, which are sequentially stacked on the first substrate 100.

[0021] The first interlayer insulating film 160 is formed on the first substrate 100 to cover the first to fourth transistors, and first to fourth lower contact plugs (172, 174, 176, 178) are formed through the first interlayer insulating film 160 to contact the first to fourth impurity regions (102, 104, 106, 108), respectively.

[0022] The first to fourth lower interconnections (182, 184, 186, 188) are formed on the first interlayer insulating film 160 and are in contact with upper surfaces of the first to fourth lower contact plugs (172, 174, 176, 178), respectively. The first lower via 192, the fifth lower wiring 202, the fifth lower via 212, and the ninth lower wiring 222 are stacked in sequence on the first lower wiring 182; the second lower via 194, the sixth lower wiring 204, the sixth lower via 214, and the ninth lower wiring 224 are stacked in sequence on the second lower wiring 184; the third lower via 196, the seventh lower wiring 206, the seventh lower via 216, and the tenth lower wiring 226 are stacked in sequence on the third lower wiring 186; and the fourth lower via 198, the eighth lower wiring 208, the eighth lower via 218, and the eleventh lower wiring 228 are stacked in sequence on the fourth lower wiring 188.

[0023] The first to fourth lower contact plugs (172, 174, 176, 178), the first to eighth lower vias (192, 194, 196, 198, 212, 214, 216, 218), and the first to eleventh lower interconnections (182, 184, 186, 188, 202, 204, 206, 208, 222, 226, 228) may include a conductive material such as a metal, a metal nitride, a metal silicide, or polysilicon doped with impurities.

[0024] The second interlayer insulating film 230 is formed on the first interlayer insulating film 160 and covers the first to eighth lower vias (192, 194, 196, 198, 212, 214, 216, 218) and the first to eighth lower interconnects (182, 184, 186, 188, 202, 204, 206, 208), while surrounding the sidewalls of the ninth to eleventh lower interconnects (222, 226, 228). The third interlayer insulating film 240 is formed on the second interlayer insulating film 230 and the ninth to eleventh lower interconnects (222, 226, 228). The first to third interlayer insulating layers 160, 230, and 240 together form a lower interlayer insulating layer structure, and may be combined to form a single layer by containing the same material, such as silicon oxide.

[0025] The second substrate 250 is formed on the third interlayer insulating film 240 in the first and second regions (I, II) of the first substrate 100, and its sidewalls are covered by a fourth interlayer insulating pattern 260 formed on the third interlayer insulating film 240. The fourth interlayer insulating pattern 260 may include an oxide, such as silicon oxide, and may thereby merge with the third interlayer insulating layer 240 .

[0026] The memory cells are formed on the second substrate 250 in the first and second regions (I, II) of the first substrate 100 . The memory cells are arranged in a second and third direction to form a memory cell array. The memory cell array includes a plurality of memory cell blocks spaced apart from one another and arranged in a third direction and separated from one another by isolation structures extending in the second direction.

[0027] The isolation structure includes a common source pattern (hereinafter, referred to as CSP) 530 formed on the second substrate 250 and extending in the second direction, and second spacers 520 formed on both side walls of the CSP in the third direction. The CSP 530 may include a metal, a metal nitride, a metal silicide, etc., and the second spacer 520 may include an oxide, such as, for example, a silicon oxide.

[0028] Each memory cell block includes a channel block therein. Each channel block includes a number of channel columns each including a number of channels 410 arranged in the second direction. Each memory cell block includes a plurality of gate electrodes (512, 514, 516) formed on the second substrate 250 and spaced apart from each other along a first direction, an insulating pattern 335 formed between adjacent gate electrodes (512, 514, 516) in the first direction, a pillar structure penetrating the gate electrodes (512, 514, 516) and the insulating pattern 335, and a capping pattern 430.

[0029] The gate electrodes (512, 514, 516) are formed on the second substrate 250 in the first and second regions (I, II) of the first substrate 100 and are stacked in a plurality of locations spaced apart from one another along the first direction, and each gate electrode (512, 514, 516) extends in the second direction on the second substrate 250 in the first and second regions (I, II). The length of the gate electrodes 512, 514, and 516 in the second direction gradually decreases from the lower layer to the upper layer, so that they have an overall stepped shape.

[0030] The gate electrodes (512, 514, 516) include first to third gate electrodes (512, 514, 516) stacked in sequence along the first direction. At this time, the first gate electrode 512 serves as a ground selection line (GSL), the second gate electrode 514 serves as a word line, and the third gate electrode 516 serves as a string selection line (SSL). Each of the first to third gate electrodes (512, 514, 516) may be formed of one or more layers. In an exemplary embodiment, the first gate electrode 512 is formed in the bottom layer, the third gate electrode 516 is formed in the top layer and one layer below it, and the second gate electrode 514 is formed in multiple layers between the first gate electrode 512 and the third gate electrode 516.

[0031] Meanwhile, each of the gate electrodes 512, 514, and 516 may include a barrier pattern covering a conductive pattern and a portion of the upper and lower surfaces and side walls thereof. The conductive pattern may include a metal having low electrical resistance, such as tungsten, titanium, tantalum, or platinum, and the barrier pattern may include a metal nitride, such as titanium nitride or tantalum nitride.

[0032] The sidewalls of the gate electrodes (512, 514, 516) stacked in a stepped shape are covered with a fifth interlayer insulating film 350, and sixth to thirteenth interlayer insulating films (360, 440, 560, 580, 600, 620, 640, 660) are stacked in sequence on the uppermost insulating pattern 335 and the fifth interlayer insulating film 350. In this case, the fifth to thirteenth interlayer insulating layers (350, 360, 440, 560, 580, 600, 620, 640, 660) may include an oxide such as silicon oxide, and may be merged with each other or even with the fourth interlayer insulating pattern 260 below.

[0033] Meanwhile, the top and bottom surfaces and side walls of each of the gate electrodes 512 , 514 , and 516 facing the channel 410 are covered with a second blocking film 500 . The second blocking film 500 may include a metal oxide, such as aluminum oxide, hafnium oxide, etc., and also covers the sidewalls of each insulating pattern 335 .

[0034] The insulating pattern 335 may, for example, comprise an oxide such as silicon oxide. Each pillar structure includes a charge storage structure 400, a channel 410, and a filling pattern 420 formed on the second substrate 250, and a capping pattern 430 is formed on each pillar structure.

[0035] The channel 410 extends in a first direction from a first region (I) of the first substrate 100 onto the second substrate 250 and has a cup shape. The charge storage structure 400 includes an upper portion extending in a first direction to cover most of the outer wall of the channel 410 , and a lower portion formed on the second substrate 250 to cover the bottom surface and lower sidewall of the channel 410 . The filling pattern 420 has a pillar shape to fill the interior space formed by the cup-shaped channel 410 . The charge storage structure 400 includes a tunnel insulating pattern 390 , a charge storage pattern 380 , and a first blocking pattern 370 , which are sequentially stacked in a horizontal direction parallel to the top surface of the first substrate 100 from an outer wall of the channel 410 .

[0036] The channel 410 may comprise single crystal silicon, which may be doped or undoped. The first blocking pattern 370 may include an oxide such as, for example, silicon oxide, the charge storage pattern 380 may include a nitride such as, for example, silicon nitride, and the tunnel insulating pattern 390 may include an oxide such as, for example, silicon oxide. The fill pattern 420 may include an oxide, such as, for example, silicon oxide.

[0037] The capping pattern 430 may include, for example, single crystal silicon doped with impurities. The capping pattern 430 penetrates the uppermost insulating pattern 335 and the sixth interlayer insulating film 360 .

[0038] The channel connection pattern 480 is formed on the second substrate 250 in the first region (I) of the first substrate 100 and contacts the lower outer wall of each channel 410, i.e., between the upper and lower parts of the charge storage structure 400, and contacts the outer wall of each channel 410 that is not covered thereby, thereby connecting the channels 410 included in each channel block to each other. The channel connection pattern 480 includes, for example, polysilicon doped with n-type impurities, and has an air gap 490 formed therein.

[0039] Meanwhile, the sacrificial layer structure 300 is formed on the second substrate 250, the fourth interlayer insulating pattern 260, and the first conductor 255 in the second and third regions (II, III) of the first substrate 100, and includes first to third sacrificial layers (270, 280, 290) sequentially stacked along a first direction. The first to third sacrificial films (270, 280, 290) may each include an oxide such as, for example, silicon oxide, a nitride such as, for example, silicon nitride, and an oxide such as, for example, silicon oxide.

[0040] In an exemplary embodiment, the channel connection pattern 480 may fill a first gap 470 (see Figures 10 and 11) formed by removing a portion of the sacrificial layer structure 300 formed on the second substrate 250 in the first region (I) of the first substrate 100, and thus be formed to substantially the same height as the sacrificial layer structure 300.

[0041] The support film 320 is formed between the bottom one of the gate electrodes 512 , 514 , 516 and the channel connection pattern 480 in the first region (I) of the first substrate 100 . However, a portion of the support film 320 penetrates the channel connection pattern 480 or the sacrificial film structure 300 and contacts the upper surface of the second substrate 250 , and this portion is referred to as a support pattern 322 . A plurality of supporting patterns 322 are formed in the first and second regions I and II of the first substrate 100 and are formed in various layouts. That is, the support patterns 322 may be formed in a plurality of pieces spaced apart from each other in the second and third directions, or some of them may extend along the second or third direction.

[0042] The capacitor includes a first conductor 255, a dielectric film structure, and a second conductor 325, which are stacked in sequence along a first direction. A first conductor 255 is formed on the third interlayer insulating layer 240 in the third region (III) of the first substrate 100 , and its sidewall is covered by a fourth interlayer insulating pattern 260 . In an exemplary embodiment, the first conductor 255 is formed to substantially the same height as the second substrate 250 and comprises substantially the same material, for example polysilicon doped with n-type impurities.

[0043] Referring to FIG. 3A, in an exemplary embodiment, a plurality of first conductors 255 are formed so as to extend in the second direction and be spaced apart from each other along the third direction. However, embodiments of the present invention are not limited to this, and the first conductor 255 may be arranged in one or more various shapes depending on the layout of the through via (THV), i.e., third contact plug 544, which is formed adjacent to the first conductor 255 and electrically connected to the lower circuit pattern. That is, the first conductors 255 may be formed in various layouts in the third region (III) of the first substrate 100 in spaces where the third contact plugs 544 are not formed.

[0044] However, referring to FIG. 3B, the first conductor 255 is formed to be spaced a certain distance (d) from each of the third contact plugs 544, so that even if misalignment occurs, each of the third contact plugs 544 does not come into contact with the first conductor 255. In an exemplary embodiment, the first conductor 255 is formed in the third region (III) of the first substrate 100 to cover the remaining area except for the adjacent area within a distance (d) from each third contact plug 544. As the first conductor 255 is formed with a larger area, the capacitance of the capacitor including the first conductor 255 can be increased.

[0045] The dielectric film structure refers to the portion of the sacrificial film structure 300 formed in the second and third regions (II, III) of the first substrate 100 that is formed between the first conductor 255 and the second conductor 325. Thus, the dielectric layer structure is formed to the same height as the sacrificial layer structure 300 and has the same structure, ie, the first to third sacrificial layers 270, 280, and 290, which are stacked in sequence. The second conductor 325 is formed in the third region (III) of the first substrate 100 and is horizontally spaced apart from the supporting film 320 portions formed in the first and second regions (I and II) of the first substrate 100 . In an exemplary embodiment, the second conductor 325 may be formed to substantially the same height as the support film 320 and may include substantially the same material, for example polysilicon doped with n-type impurities.

[0046] In an exemplary embodiment, the second conductor 325 is at least partially overlapped with the underlying first conductor 255 along the first direction, such that the first and second conductors (255, 325) and the portion of the sacrificial film structure 300 formed therebetween, i.e., the dielectric film structure, form a capacitor. In order to increase the capacitance of the capacitor, the second conductor 325 overlaps the first conductor 255 as much as possible, except for a region where a fourth contact plug 545 contacting the first conductor 255 is formed. In addition, the region in which the fifth contact plug 546 that contacts the second conductor 325 is formed does not overlap with the first conductor 255, so that even if the fifth contact plug 546 penetrates the second conductor 325 and the sacrificial film structure 300, it does not come into contact with the first conductor 255.

[0047] The first contact plug 542 penetrates the fifth to seventh interlayer insulating films (350, 360, 440), the insulating pattern 335, and the second blocking film 500 in the second region (II) of the first substrate 100 to contact the first to third gate electrodes (512, 514, 516). The second contact plug 543 penetrates the fifth to seventh interlayer insulating films (350, 360, 440), the support film 320, and the sacrificial film structure 300 in the second region (II) of the first substrate 100 to contact the upper surface of the second substrate 250. The third contact plug 544 penetrates the fifth to seventh interlayer insulating films (350, 360, 440), the support film 320, and the sacrificial film structure 300 in the third region (III) of the first substrate 100 to contact the upper surface of the second substrate 250. The fourth contact plug 545 penetrates the fifth to seventh interlayer insulating films (350, 360, 440) and the sacrificial film structure 300, the fourth interlayer insulating pattern 260, and the third interlayer insulating film 240 to contact an upper surface of the eleventh lower wiring 228, the fourth contact plug 545 penetrates the fifth to seventh interlayer insulating films (350, 360, 440) and the sacrificial film structure 300 in the third region (III) of the first substrate 100 to contact an upper surface of the first conductor 255, and the fifth contact plug 546 penetrates the fifth to seventh interlayer insulating films (350, 360, 440) in the third region (III) of the first substrate 100 to contact an upper surface of the second conductor 325. At this time, the third contact plug 544 extends in the first direction to electrically connect the lower circuit pattern and the upper wiring structure to each other, and is therefore called a through via (THV).

[0048] The upper wiring structure includes, for example, an upper contact plug, an upper wiring, an upper via, and the like. The first to fifth and seventh upper contact plugs (572, 573, 574, 575, 576, 579) penetrate the seventh interlayer insulating film 440, the isolation structure, and the eighth interlayer insulating film 560 formed on the first to fifth contact plugs (542, 543, 544, 545, 546), and respectively contact the upper surfaces of the first to fifth contact plugs (542, 543, 544, 545, 546) and the CSP 530, and the sixth upper contact plug 578 penetrates the seventh and eighth interlayer insulating films (440, 560) and contacts the upper surface of the capping pattern 430.

[0049] The first to seventh upper wirings (592, 593, 594, 595, 596, 598, 599) penetrate the eighth interlayer insulating film 560 and the ninth interlayer insulating film 580 formed on the first to seventh upper contact plugs (572, 573, 574, 575, 576, 578, 579), and respectively contact the upper surfaces of the first to seventh upper contact plugs (572, 573, 574, 575, 576, 578, 579).

[0050] The first to seventh upper vias (612, 613, 614, 615, 616, 618, 619) penetrate through a tenth interlayer insulating film 600 formed on the ninth interlayer insulating film 580 and the first to seventh upper interconnects (592, 593, 594, 595, 596, 598, 599), and respectively contact the upper surfaces of the first to seventh upper interconnects (592, 593, 594, 595, 596, 598, 599). The eighth to fourteenth upper wirings (632, 633, 634, 635, 636, 638, 639) penetrate through the tenth interlayer insulating film 600 and the eleventh interlayer insulating film 620 formed on the first to seventh upper vias (612, 613, 614, 615, 616, 618, 619), and contact the upper surfaces of the first to seventh upper vias (612, 613, 614, 615, 616, 618, 619), respectively.

[0051] The eighth to eleventh upper vias (654, ​​655, 656, 659) penetrate the eleventh interlayer insulating film 620 and the twelfth interlayer insulating film 640 formed on the eighth to fourteenth upper interconnects (632, 633, 634, 635, 636, 638, 639), and contact the upper surfaces of the tenth to fourteenth upper interconnects (634, 635, 636, 638, 639), respectively. The fifteenth to eighteenth upper wirings (674, 675, 676, 679) penetrate the twelfth interlayer insulating film 640 and the thirteenth interlayer insulating film 660 formed on the eighth to eleventh upper vias (654, ​​655, 656, 659), and contact the upper surfaces of the eighth to eleventh upper vias (654, ​​655, 656, 659), respectively.

[0052] In an exemplary embodiment, the thirteenth upper wiring 638 is formed in a plurality of pieces, extending in the third direction and spaced apart from each other along the second direction. In this case, the thirteenth upper interconnection 638 serves as a bit line of the vertical memory device.

[0053] The vertical memory device includes a first conductor 255 , a dielectric film structure 300 , and a second conductor 325 , which are sequentially stacked in a third region (III) of the first substrate 100 . Fourth and fifth contact plugs (575, 576) are connected to the first and second conductors (255, 325), respectively, through which a voltage is applied from the outside. Thus, the first and second conductors 255, 325 and the dielectric film structure 300 can function as a capacitor together. As described above, the first conductor 255 of the capacitor may have the largest possible area in the third region (III) of the first substrate 100 without contacting each of the third contact plugs 544, thereby ensuring a large electrical capacitance of the capacitor.

[0054] 4 to 16 are cross-sectional views illustrating a method for manufacturing a vertical memory device according to an embodiment of the present invention. Specifically, FIGS. 4 to 8, 11 to 12, 14, and 16 are cross-sectional views cut in the second direction, and FIGS. 9 to 10, 13, and 15 are cross-sectional views cut in the third direction.

[0055] Referring to FIG. 4, a lower circuit pattern is formed on a first substrate 100, and first to third interlayer insulating films 160, 230, and 240 for covering the lower circuit pattern are sequentially formed on the first substrate 100. As shown in FIG. The isolation pattern 110 formed on the first substrate 100 may be formed by, for example, an STI process, thereby defining an active region 105 on the first substrate 100 .

[0056] The first to fourth impurity regions (102, 104, 106, 108) are formed above each active region 105 by, for example, an ion implantation process. In addition, the first to fourth lower gate structures (152, 154, 156, 158), the first to fourth lower contact plugs (172, 174, 176, 178), the first to eighth lower vias (192, 194, 196, 198, 212, 214, 216, 218), and the first to eleventh lower interconnects (182, 184, 186, 188, 202, 204, 206, 208, 222, 226, 228) constituting the lower circuit pattern may each be formed by a relief patterning process or a damascene process.

[0057] The first interlayer insulating film 160 is formed on the first substrate 100 and surrounds sidewalls of the first to fourth lower contact plugs (172, 174, 176, 178) while covering the first to fourth impurity regions (102, 104, 106, 108) and the first to fourth lower gate structures (152, 154, 156, 158). The second interlayer insulating film 230 is formed on the first interlayer insulating film 160 and covers the first to eighth lower vias (192, 194, 196, 198, 212, 214, 216, 218) and the first to eighth lower interconnects (182, 184, 186, 188, 202, 204, 206, 208), while surrounding the sidewalls of the ninth to eleventh lower interconnects (222, 226, 228). The third interlayer insulating film 240 is formed on the second interlayer insulating film 230 and the ninth to eleventh lower wirings (222, 226, 228).

[0058] Thereafter, a second substrate 250 and a first conductor 255 are formed on the third interlayer insulating film 240 , and a fourth interlayer insulating pattern 260 covering sidewalls of the second substrate 250 and the first conductor 255 is formed on the third interlayer insulating film 240 .

[0059] The second substrate 250 is formed on the third interlayer insulating film 240 and then patterned by an etching process so that it remains only in the first and second regions (I, II) of the first substrate 100. During the etching process, the portion of the second substrate 250 formed in the third region (III) of the first substrate 100 is also patterned and remains on the first conductor 255. The second substrate 250 and the first conductor 255 may include, for example, a semiconductor material doped with n-type impurities.

[0060] Referring also to FIG. 3A, in an exemplary embodiment, the first conductors 255 are formed in a plurality of pieces extending in the second direction and spaced apart from each other along the third direction. However, the present invention is not limited thereto, and the first conductor 255 may be arranged in one or more various shapes depending on the layout of the through via (THV), ie, the third contact plug 544. That is, the first conductors 255 may be formed in various layouts in the third region (III) of the first substrate 100 in a space where the third contact plugs 544 (to be formed later) will not be formed.

[0061] However, referring to FIG. 3B, the first conductor 255 is formed to be spaced a certain distance (d) from each third contact plug 544, so that even if misalignment occurs, each third contact plug 544 does not come into contact with the first conductor 255. In an exemplary embodiment, the first conductor 255 is formed to cover the remaining area in the third region (III) of the first substrate 100, excluding the adjacent areas within a distance (d) from each third contact plug 544. The larger the area of ​​the first conductor 255, the greater the amount of capacitance that can be obtained through it.

[0062] The fourth interlayer insulating pattern 260 is formed by forming a fourth interlayer insulating film covering the second substrate 250 and the first conductor 255 on the third interlayer insulating film 240, and then planarizing the fourth interlayer insulating film until the upper surfaces of the second substrate 250 and the first conductor 255 are exposed. During the planarization process, the first conductor 255 is formed in the third region (III) of the first substrate 100 where the second substrate 250 is not formed, thereby preventing dishing, and therefore the top surface of the fourth interlayer insulating pattern 260 has a constant height.

[0063] Referring to FIG. 5, a sacrificial film structure 300 is formed on the second substrate 250, the first conductor 255, and the fourth interlayer insulating pattern 260, and then partially removed to form a first opening 310 that exposes the top surface of the second substrate 250. Then, a support film 320 that at least partially fills the first opening 310 is formed on the second substrate 250, the first conductor 255, and the fourth interlayer insulating pattern 260.

[0064] The sacrificial film structure 300 includes first to third sacrificial films (270, 280, 290) that are stacked in sequence. In this case, the first and third sacrificial layers 270 and 290 may each include an oxide, such as silicon oxide, and the second sacrificial layer 280 may include a nitride, such as silicon nitride.

[0065] The support film 320 may include a material having an etching selectivity with respect to the first to third sacrificial films (270, 280, 290), for example, polysilicon doped with n-type impurities. However, the support film 320 may be formed to include polysilicon doped with n-type impurities by performing a separate heat treatment process after depositing amorphous silicon doped with n-type impurities, or by being crystallized by heat generated during a subsequent deposition process of another film.

[0066] In an exemplary embodiment, a plurality of first openings 310 may be formed in the first and second regions (I, II) of the first substrate 100, and may be formed in various layouts. That is, a plurality of first openings 310 are formed so as to be spaced apart from each other along the second and third directions, or some of them extend along the second or third direction. The support film 320 is formed to a uniform thickness, so that a first recess is formed on the portion of the support film 320 formed in the first opening 310 . Hereinafter, the portion of the support film 320 formed in the first opening 310 will be referred to as a support pattern 322 .

[0067] Thereafter, the support film 320 portion formed in the third region (III) of the first substrate 100 is patterned to form a second conductor 325 in the third region (III) of the first substrate 100, the second conductor 325 being separated from the support film 320 portions formed in the first and second regions (I, II) of the first substrate 100. In an exemplary embodiment, the second conductor 325 at least partially overlaps the underlying first conductor 255 along the first direction, such that the first and second conductors (255, 325) and the portion of the sacrificial film structure 300 formed therebetween form a capacitor.

[0068] In order to increase the capacitance of the capacitor, the second conductor 325 is formed to overlap the first conductor 255 as much as possible, except for the region where the fourth contact plug 545 that will contact the first conductor 255 to be formed later will be formed. In addition, the region in which the fifth contact plug 546 that will contact the second conductor 325 to be formed later is formed does not overlap with the first conductor 255, so that the fifth contact plug 546 does not come into contact with the first conductor 255 even if it penetrates the second conductor 325 and the sacrificial film structure 300.

[0069] Referring to FIG. 6, an insulating layer 330 filling the first recess is formed on the supporting layer 320, the supporting pattern 322, the second conductor 325, and the sacrificial layer structure 300, and then the upper surface thereof is planarized. The insulating film 330 may include an oxide, such as silicon oxide, and the planarization process may be performed by a chemical mechanical polishing (CMP) process and / or an etch-back process. Thereafter, the fourth sacrificial film 340 and the insulating film 330 are alternately stacked on the insulating film 330 along the first direction, thereby forming a mold film including the insulating film 330 and the fourth sacrificial film 340 on the supporting film 320, the supporting pattern 322, the second conductor 325, and the sacrificial film structure 300. The fourth sacrificial layer 340 may include a material having a high etch selectivity with respect to the insulating layer 330, for example, a nitride such as silicon nitride.

[0070] Referring to FIG. 7, a photoresist pattern (not shown) that partially covers the insulating film 330 formed on the top layer is formed on the top insulating film 330, and then the top insulating film 330 and the underlying fourth sacrificial film 340 are etched using the photoresist pattern (not shown) as an etching mask. As a result, a portion of the insulating film 330 formed below the uppermost fourth sacrificial film 340 is exposed. After performing a trimming process to reduce the area of ​​the photoresist pattern at a certain rate, the top insulating film 330, the top fourth sacrificial film 340, the exposed insulating film 330, and the underlying fourth sacrificial film 340 are again etched using this as an etching mask.

[0071] By repeatedly performing the trimming process and the etching process, a mold having a staircase structure shape including a plurality of staircase layers, each of which is composed of one fourth sacrificial film 340 and one insulating film 330 stacked in sequence, is formed in the first and second regions (I, II) of the first substrate 100. In this case, the end portion of each step layer in the second direction may be exposed to the outside since it is not overlapped in the first direction by the upper step layer, and this may be called a "step." In an exemplary embodiment, the mold steps are formed in the second region (II) of the first substrate 100 . Meanwhile, as the mold is formed, the second conductor 325 and the sacrificial film structure 300 formed in the third region (III) of the first substrate 100 are exposed.

[0072] Referring to FIG. 8, after forming a fifth interlayer insulating film 350 on the mold, the second conductor 325, and the sacrificial film structure 300, the upper portion of the fifth interlayer insulating film 350 is planarized until the upper surface of the top insulating film 330 is exposed. Thereafter, a sixth interlayer insulating film 360 is formed on the fifth interlayer insulating film 350 and the top insulating film 330, and a channel hole is formed by, for example, a dry etching process, penetrating the sixth interlayer insulating film 360, the mold, the supporting film 320, and the sacrificial film structure 300 to expose the top surface of the second substrate 250 in the first region (I) of the first substrate 100.

[0073] In an exemplary embodiment, the dry etching process is performed until the channel hole exposes the top surface of the second substrate 250 , and thus the channel hole is formed to penetrate to a portion of the top of the second substrate 250 . A plurality of channel holes are formed along the second and third directions, respectively, thereby defining a channel hole array. Then, a charge storage structure 400, a channel 410, a filling pattern 420, and a capping pattern 430 are formed in the channel hole.

[0074] Specifically, a charge storage structure film and a channel film are sequentially formed on the sidewalls of the channel hole, the top surface of the second substrate 250 exposed by the channel hole, and the top surface of the sixth interlayer insulating film 360, a filling film is formed on the channel film to fill the remaining portion of the channel hole, and then the filling film, the channel film, and the charge storage structure film are planarized until the top surface of the sixth interlayer insulating film 360 is exposed. A planarization process is performed to form the charge storage structure 400 and the channel 410, each of which has a cup shape, which are sequentially stacked on the sidewall of the channel hole and the upper surface of the second substrate 250, and the inner space formed by the channel 410 is filled with the filling pattern 420.

[0075] Meanwhile, the channel holes in which the channels 410 are formed define a channel hole array, so that the channels 410 formed in the channel holes also define a channel array accordingly. In the exemplary embodiment, the charge storage structure 400 includes a first blocking pattern 370, a charge storage pattern 380, and a tunnel insulating pattern 390, which are sequentially stacked.

[0076] Then, the filling pattern 420, the channel 410, and the upper portion of the charge storage structure 400 are removed to form a second recess, and a pad film filling the second recess is formed on the sixth interlayer insulating film 360. The pad film is then planarized until the top surface of the sixth interlayer insulating film 360 is exposed, thereby forming a capping pattern 430.

[0077] Referring to FIG. 9, after forming a seventh interlayer insulating film 440 on the sixth interlayer insulating film 360 and the pad 430, a second opening 450 penetrating the sixth and seventh interlayer insulating films (360, 440) and the mold is formed in the first and second regions (I, II) of the first substrate 100, for example, by a dry etching process. The dry etching process is performed until the second opening 450 exposes the upper surface of the support film 320 or the support pattern 322, and thus is formed to penetrate to a part of the upper portion thereof. As the second opening 450 is formed, the insulating layer 330 and the fourth sacrificial layer 340 included in the mold are exposed through the sidewalls thereof.

[0078] In an exemplary embodiment, the second openings 450 extend in the second direction from the first and second regions (I, II) of the first substrate 100 and are formed in a plurality along the third direction. As the second opening 450 is formed, the insulating layer 330 is transformed into an insulating pattern 335 extending in the second direction, and the fourth sacrificial layer 340 is transformed into a fourth sacrificial pattern 345 extending in the second direction.

[0079] Thereafter, a first spacer film is formed on the sidewalls of the second opening 450 and the seventh interlayer insulating film 440, and then the portion formed on the bottom surface of the second opening 450 is removed by an anisotropic etching process to form a first spacer 460, thereby partially exposing the upper surfaces of the support film 320 and the support pattern 322. Thereafter, the exposed support film 320 and support pattern 322 and the underlying sacrificial film structure 300 are removed to expand the second opening 450 downward. As a result, the second opening 450 exposes the upper surface of the second substrate 250, and further penetrates even a portion of the upper portion of the second substrate 250.

[0080] In an exemplary embodiment, the first spacer 460 may include, for example, undoped amorphous silicon or undoped polysilicon. However, if the first spacer 460 includes amorphous silicon that is not doped with impurities, it may be crystallized by heat generated during a subsequent deposition process of other layers to be formed to include polysilicon. When the sacrificial film structure 300 is partially removed, the sidewall of the second opening 450 is covered by the first spacer 460, so the insulating pattern 335 and the fourth sacrificial pattern 345 included in the mold may not be removed.

[0081] 10 and 11, a portion of the sacrificial layer structure 300 formed in the first region (I) of the first substrate 100 is removed through the second opening 450, for example, by a wet etching process, thereby forming a first gap 470. In an exemplary embodiment, during the wet etching process, the sacrificial layer structure 300 portion formed in the third region (III) of the first substrate 100 is not removed but remains, and will hereinafter be referred to as a dielectric layer structure. Meanwhile, the sacrificial film structure 300 formed in the second region (II) of the first substrate 100 remains in whole or in part. The wet etching process may be carried out using, for example, hydrofluoric acid (HF) and / or phosphoric acid (H 3 PO 4 )

[0082] As the first gap 470 is formed in the first region (I) of the first substrate 100, the lower portion of the support film 320 adjacent to the second opening 450 and the upper portion of the second substrate 250 are exposed. In addition, a portion of the sidewall of the charge storage structure 400 is exposed by the first gap 470, and the exposed sidewall of the charge storage structure 400 is also removed during the wet etching process, thereby exposing the outer wall of the channel 410. As a result, the charge storage structure 400 is separated into an upper portion that penetrates the mold and covers most of the outer walls of the channels 410 , and a lower portion that covers the bottom surface of the channels 410 and is formed on the upper portion of the second substrate 250 . Meanwhile, when the first gap 470 is formed by the wet etching process, the support film 320 and the support pattern 322 may not be removed so that the mold remains intact and does not collapse.

[0083] 12 and 13, the first spacer 460 is removed, and a channel connection layer is formed on the sidewall of the second opening 450 and in the first gap 470, and then, for example, an etch-back process is performed to remove the portion of the channel connection layer formed in the second opening 450, thereby forming a channel connection pattern 480 in the first gap 470. As the channel connection pattern 480 is formed, the channels 410 forming the channel array connect with each other.

[0084] The channel connection pattern 480 may include, for example, amorphous silicon doped with n-type impurities, and may subsequently include polysilicon doped with n-type impurities by being crystallized by heat generated during the deposition process of other layers. Meanwhile, an air gap 490 is formed within the channel connection pattern 480 .

[0085] 14 and 15, the fourth sacrificial pattern 345 exposed by the second opening 450 is removed to form a second gap between the insulating patterns 335 formed in each layer, and a portion of the outer wall of the first blocking pattern 370 is exposed by the second gap. According to an exemplary embodiment, phosphoric acid (H 3 PO 4 ) or sulfuric acid (H 2 SO 4) may be used to remove the fourth sacrificial pattern 345.

[0086] Then, a second blocking film 500 is formed on the exposed outer walls of the first blocking pattern 370, the inner walls of the second gap, the surface of the insulating pattern 335, the sidewalls and a portion of the bottom surface of the support film 320, the sidewalls of the support pattern 322, the sidewalls of the channel connection pattern 480, the top surface of the second substrate 250, and the top surface of the seventh interlayer insulating film 440, and a gate electrode film is formed on the second blocking film 500. The gate electrode layer may include a gate barrier layer and a gate conductive layer, which are stacked in sequence.

[0087] Thereafter, the gate electrode film is partially removed to form a gate electrode inside each of the second gaps. According to an exemplary embodiment, the gate electrode film may be partially removed by a wet etching process. In an exemplary embodiment, the gate electrode is stacked in a plurality of layers that extend in the second direction and are spaced apart from one another along the first direction. Moreover, a plurality of gate electrodes are formed along the third direction. That is, the gate electrodes formed in the same layer are spaced apart from one another in the third direction by the second openings 450 . The gate electrodes include first to third gate electrodes (512, 514, 516) formed in sequence along a first direction.

[0088] Thereafter, a second spacer 520 is formed on the sidewall of the second opening 450, and a common source pattern (CSP) 530 filling the remaining portion of the second opening 450 is formed. The second spacer 520 is formed on the side wall of the second opening 450 by forming a second spacer film on the upper surface of the second substrate 250 exposed by the second opening 450, the side wall of the second opening 450, and the seventh interlayer insulating film 440, and anisotropically etching the second spacer film. The CSP 530 is formed by forming a CSP film on the upper surface of the second substrate 250 exposed by the second opening 450, the second spacer 520, and the seventh interlayer insulating film 440, and planarizing the CSP film until the upper surface of the seventh interlayer insulating film 440 is exposed. In the exemplary embodiment, the CSP 530 extends in the second direction and separates the first to third gate electrodes (512, 514, 516) in the third direction together with the second spacers 520 formed on the sidewalls thereof.

[0089] 16, a first contact plug 542 penetrates the fifth to seventh interlayer insulating films (350, 360, 440), the insulating pattern 335, and the second blocking film 500 in the second region (II) of the first substrate 100 and contacts the first to third gate electrodes (512, 514, 516); a second contact plug 543 penetrates the fifth to seventh interlayer insulating films (350, 360, 440), the support film 320, and the sacrificial film structure 300 in the second region (II) of the first substrate 100 and contacts the upper surface of the second substrate 250; 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 40, 37, 41, 42, 43, 44, 45, 46, 47, 48, 50, 51, 52, 60, 63, 64, 70, 75, 80, 81, 82, 83, 84, 85, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 110, 120, 130, 140, 150, 160, 41, 42, 43, 44, 45, 47, 48, 50, 51, 64, 75,

[0090] 1 and 2, eighth to thirteenth interlayer insulating films (560, 580, 600, 620, 640, 660) are formed on the seventh interlayer insulating film 440, the CSP 530, and the first to fifth contact plugs (542, 543, 544, 545, 546), and then first to seventh upper contacts (560, 580, 600, 620, 640, 660) are formed through the seventh interlayer insulating film 440, the CSP 530, and the first to fifth contact plugs (542, 543, 544, 545, 546), the capping pattern 430, and the CSP 530. The fabrication of the vertical memory device is completed by forming tact plugs (572, 573, 574, 575, 576, 578, 579), first through eighteenth upper interconnections (592, 593, 594, 595, 596, 598, 599, 632, 633, 634, 635, 636, 638, 639, 674, 675, 676, 679), and first through eleventh upper vias (612, 613, 614, 615, 616, 618, 619, 654, 655, 656, 659).

[0091] As described above, the portion of the second substrate 250 formed in the third region (III) of the first substrate 100 is patterned to form the first conductor 255, the sacrificial layer structure 300 for forming the channel connection pattern 480 is left in the third region (III) of the first substrate 100 to form the dielectric layer structure 300, and a portion of the support layer 320 is patterned in the third region (III) of the first substrate 100 to form the second conductor 325. Fourth and fifth contact plugs 545 and 546 are in contact with the first and second conductors 255 and 325, respectively, through which a voltage can be applied from the outside. Thus, a capacitor including the first and second conductors (255, 325) and the dielectric film structure 300 is easily formed in the third region (III) of the first substrate 100.

[0092] 17 and 18 are cross-sectional views illustrating a vertical memory device according to an embodiment of the present invention. The vertical memory device is substantially the same as or similar to the vertical memory device shown in FIGS. 1 to 3 except for some components, so a duplicated description thereof will be omitted.

[0093] Referring to FIG. 17, the fifth contact plug 546 penetrates the second conductor 325 to contact the dielectric layer structure 300 formed thereunder. Although not shown in the drawing, the fifth contact plug 546 also penetrates the dielectric layer structure 300 to contact the underlying fourth interlayer insulating pattern 260 or a lower interlayer insulating layer structure. Referring to FIG. 18, the sacrificial layer structure 300 does not extend across the second and third regions (II, III) of the first substrate 100, but is formed in each of the regions and is separated from each other. At this time, the dielectric film structure 300 remains only under the second conductor 325 in the third region (III) of the first substrate 100 .

[0094] FIG. 19 is a cross-sectional view illustrating a vertical memory device according to an embodiment of the inventive concept. The vertical memory device is substantially the same as or similar to the vertical memory device shown in FIGS. 1 to 3 except for some components, so a duplicated description thereof will be omitted.

[0095] Referring to FIG. 19, the sacrificial layer structure 300 does not extend across the second and third regions (II, III) of the first substrate 100, but is formed in each of the regions and separated from each other, and a dielectric pattern structure 305 is formed under the second conductor 325 in the third region (III) of the first substrate 100. The dielectric pattern structure 305 includes first, second and third patterns (275, 285, 295) stacked in sequence. Meanwhile, the fifth contact plug 546 contacts a portion of the second conductor 325 formed on the upper surface of the fourth interlayer insulating pattern 260 .

[0096] FIG. 20 is a cross-sectional view illustrating a method for manufacturing a vertical memory device according to an embodiment of the present invention. The method of manufacturing a vertical memory device includes steps that are substantially the same as or similar to those described with reference to FIGS. 4 to 16 and 1 and 2, and therefore a duplicated description thereof will be omitted.

[0097] Referring to FIG. 20, steps substantially the same as or similar to those described with reference to FIGS. 4-5 are carried out. However, the sacrificial film structure 300 formed in the third region (III) of the first substrate 100 is patterned to form a dielectric pattern structure 305 that at least partially overlaps the first conductor 255 in the first direction and is separated from the sacrificial film structure 300 formed in the second region (II) of the first substrate 100.

[0098] Then, after forming the support film 320, the support film 320 formed in the third region (III) of the first substrate 100 is patterned to form a second conductor 325 on the upper surface, one sidewall, and the upper surface of the adjacent fourth interlayer insulating pattern 260 of the dielectric pattern structure 305. Referring again to FIG. 19, the fabrication of the vertical memory device is completed by performing processes that are substantially the same as or similar to those described with reference to FIGS. 6-16 and 1 and 2.

[0099] FIG. 21 is a cross-sectional view illustrating a vertical memory device according to an embodiment of the inventive concept. The vertical memory device is substantially the same as or similar to the vertical memory device shown in FIG. 19 except for some components, so a duplicated description thereof will be omitted.

[0100] Referring to FIG. 21, the fourth and fifth contact plugs 545 and 546 in contact with the upper surfaces of the first and second conductors 255 and 325 and the upper wiring structure connected thereto may not be formed. However, a third conductor 259 contacting the bottom surface of the second conductor 325 is formed within the fourth interlayer insulating pattern 260, ninth and tenth lower vias (247, 249) are additionally formed within the third interlayer insulating film 240, contacting the bottom surfaces of the first and third conductors (255, 259), respectively, and twelfth and thirteenth lower wirings (227, 229) are formed on the top of the second interlayer insulating film 230, contacting the bottom surfaces of the ninth and tenth lower vias (247, 249), respectively. As a result, in a capacitor including a first conductor 255, a dielectric pattern structure 305, and a second conductor 325 stacked in sequence, the first conductor 255 is electrically connected to the ninth lower via 247 and the twelfth lower wiring 227 formed thereunder, and the second conductor 325 is electrically connected to the tenth lower via 249 and the thirteenth lower wiring 229 formed thereunder.

[0101] The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the technical scope of the present invention. [Explanation of symbols]

[0102] 100 First substrate 102, 104, 106, 108 1st to 4th impurity regions 110 Element isolation pattern 122, 124, 126, 128 1st to 4th lower gate insulation patterns 132, 134, 136, 138 First to fourth lower gate electrodes 142, 144, 146, 148 1st to 4th lower gate masks 152, 154, 156, 158 1st to 4th Lower Gate Structures 160, 230, 240 1st to 3rd interlayer insulating films 172, 174, 176, 178 First to fourth lower contact plugs 182, 184, 186, 188, 202, 204, 206, 208, 222, 226, 228 1st to 11th lower wiring 192, 194, 196, 198, 212, 214, 216, 218 1st to 8th lower vias 250 Second board 255, 325 First and second conductors 260 4th layer insulation pattern 270, 280, 290 1st to 3rd sacrificial films 300 Sacrificial Membrane Structure 320 Support membrane 322 Support Pattern 335 Insulation Pattern 350, 360, 440, 560, 580, 600, 620, 640, 660 5th to 13th interlayer insulating films 370 First Blocking Pattern 380 Charge Storage Pattern 390 Tunnel Insulation Pattern 400 Charge storage structure 410 Channels 420 Filling Pattern 430 Capping Pattern 480 channel connection pattern 490 Air Gap 460, 520 1st and 2nd spacers 500 Second Blocking Film 512, 514, 516 (first to third) gate electrodes 530 Common Source Pattern (CSP) 542, 543, 544, 545, 546, 578, 579 (1st to 7th) Contact plugs 592, 593, 594, 595, 596, 598, 599 1st to 7th upper wiring 612, 613, 614, 615, 616, 618, 619 1st to 7th upper vias 632, 633, 634, 635, 636, 638, 639 8th to 14th upper wiring 654, 655, 656, 659 8th to 11th upper vias 674, 675, 676, 679 15th to 18th upper wiring

Claims

1. a lower circuit pattern formed on a first substrate, the lower circuit pattern including a first region, a second region at least partially surrounding the first region, and a third region at least partially surrounding the second region; a second substrate formed on the lower circuit pattern in a first region and a second region of the first substrate; a first conductor formed on the lower circuit pattern in a third region of the first substrate, the first conductor being formed at substantially the same height as the second substrate and spaced apart from the second substrate; a dielectric film structure formed on the first conductor; a capacitor including a second conductor formed on the dielectric film structure; gate electrodes spaced apart from one another on the second substrate along a vertical direction substantially perpendicular to an upper surface of the first substrate in the first and second regions of the first substrate; a channel extending in the vertical direction through the gate electrode in the first region of the first substrate, a memory cell is formed in the first region above the lower circuit pattern, a contact plug is formed in the second region to transmit an electrical signal to the memory cell, and a through via is formed in the third region to transmit an electrical signal to the lower circuit pattern; the first conductor has a maximum area in the third region of the first substrate without contacting the contact plug; the contact plug contacts an upper surface of the lower circuit pattern through the through via in the third region of the first substrate; a sacrificial film structure at a second region of the first substrate and at substantially the same height as the dielectric film structure on the second substrate; The vertical memory device, wherein the sacrificial layer structure is spaced apart from the dielectric layer structure and comprises substantially the same material as the dielectric layer structure.

2. 2. The vertical memory device of claim 1, wherein the first conductor comprises substantially the same material as the second substrate.

3. 3. The vertical memory device of claim 2, wherein the second substrate and the first conductor comprise polysilicon doped with impurities.

4. 2. The vertical memory device of claim 1, wherein the dielectric layer structure includes a first layer, a second layer, and a third layer sequentially stacked along the vertical direction, each of which includes an oxide, a nitride, and an oxide, respectively.

5. 2. The vertical memory device of claim 1, wherein the dielectric layer structure extends in a horizontal direction substantially parallel to an upper surface of the first substrate.

6. The channel includes a plurality of channels spaced apart from one another in a first region of the first substrate, 2. The vertical memory device of claim 1, further comprising a channel connection pattern formed on the second substrate under the gate electrode for connecting the channels to each other.

7. 7. The vertical memory device of claim 6, wherein the channel connection pattern is formed to have substantially the same height as the dielectric film structure.

8. 7. The vertical memory device of claim 6, further comprising a support layer formed between the channel connection pattern and the gate electrode, the support layer including impurity-doped polysilicon.

9. 9. The vertical memory device of claim 8, wherein the second conductor is spaced apart from the support film, has substantially the same height as the support film, and includes substantially the same material as the support film.

10. 2. The vertical memory device of claim 1, wherein a portion of the first conductor does not overlap the second conductor in the vertical direction.

11. a first contact plug contacting an upper portion of the first conductor and extending in the vertical direction; 11. The vertical memory device of claim 10, further comprising: a second contact plug contacting an upper portion of the second conductor and extending in the vertical direction.

12. 12. The vertical memory device of claim 11, wherein the first contact plug does not overlap the second conductor in the vertical direction and contacts the portion of the first conductor.

13. 12. The vertical memory device of claim 11, wherein the first contact plug penetrates the sacrificial layer structure.

14. 12. The vertical memory device of claim 11, wherein the first contact plug does not contact the dielectric layer structure.

15. 12. The vertical memory device of claim 11, wherein the second contact plug contacts the second conductor.

16. an interlayer insulating pattern formed in a third region of the first substrate and covering sidewalls of the second substrate and the first conductor; 2. The vertical memory device of claim 1, wherein the second conductor is formed on an upper surface and one sidewall of the dielectric layer structure and on an upper surface of the interlayer insulating pattern.

17. 17. The vertical memory device of claim 16, further comprising a contact plug extending vertically and contacting an upper portion of the second conductor formed on the upper surface of the interlayer insulating pattern.

18. a third conductor formed in the interlayer insulating pattern and in contact with a bottom surface of the second conductor; a first lower contact plug contacting a bottom surface of the first conductor and electrically connected to the lower circuit pattern; 17. The vertical memory device of claim 16, further comprising: a second lower contact plug contacting a bottom surface of the third conductor and electrically connected to the lower circuit pattern.

19. an interlayer insulating pattern formed in a third region of the first substrate and covering sidewalls of the second substrate and the first conductor; a through via disposed apart from the capacitor in a horizontal direction substantially parallel to an upper surface of the first substrate; 2. The vertical memory device of claim 1, wherein the through via penetrates the interlayer insulating pattern and is electrically connected to the lower circuit pattern.

20. A transistor formed on a first substrate; a lower circuit pattern formed on the first substrate and electrically connected to the transistor; an interlayer insulating film formed on the first substrate to cover the transistor and the lower circuit pattern; a second substrate formed on the interlayer insulating film; a first conductor spaced apart from the second substrate at substantially the same height as the second substrate; a dielectric film structure formed on the first conductor; a capacitor including a second conductor formed on the dielectric film structure; gate electrodes spaced apart from one another along a vertical direction substantially perpendicular to an upper surface of the first substrate on the second substrate; a plurality of channels extending in the vertical direction on the second substrate and penetrating the gate electrode; a charge storage structure formed on an outer wall of each of the channels; an upper wiring formed on the gate electrodes and electrically connected to each of the gate electrodes; a first contact plug electrically connected to the first conductor; a second contact plug electrically connected to the second conductor; a through via spaced apart from the capacitor in a horizontal direction substantially parallel to an upper surface of the first substrate and electrically connected to the lower circuit pattern; A memory cell is formed on the lower circuit pattern, and a contact plug is formed to transmit an electrical signal to the memory cell. the first conductor has a maximum area on the first substrate without contacting the contact plug; the first substrate has a sacrificial film structure at substantially the same height as the dielectric film structure on the second substrate; The vertical memory device, wherein the sacrificial layer structure is spaced apart from the dielectric layer structure and comprises substantially the same material as the dielectric layer structure.

21. a channel connection pattern formed on the second substrate and in contact with a lower portion of the channel; 21. The vertical memory device of claim 20, further comprising a support layer formed between the channel connection pattern and the gate electrode.

Images