3D semiconductor memory device

Abstract

To provide a three-dimensional semiconductor memory device with higher reliability and higher integration.SOLUTION: A three-dimensional semiconductor memory device includes a first peripheral circuit part including a plurality of different decoder circuit parts as a logic chip, a first memory part disposed thereon, and a second memory part disposed thereon. The first memory part includes a first stack structure including a plurality of first electrode layers that are stacked, and a plurality of first electrode interlayer insulating films existing between the layers, and a first flat insulating film covering an end of the first stack structure. The second memory part includes a second stack structure including a plurality of second electrode layers that are stacked, and a plurality of second electrode interlayer insulating films existing between the layers, and a second flat insulating film covering an end of the second stack structure. The first memory part includes a first penetration veer penetrating the end of the first stack structure and the first flat insulating film, insulated from the first electrode layer, and connected to one of the decoder circuit parts. The second memory part includes a second cell contact plug penetrating the second flat insulating film and connecting one of the second electrode layers to the first penetration veer.SELECTED DRAWING: Figure 3A

Description

[Technical field]

[0001] The present invention relates to a three-dimensional semiconductor memory device, and more particularly to a three-dimensional semiconductor memory device having improved reliability. [Background technology]

[0002] To meet consumer demands for superior performance and lower prices, there is a demand for increased integration density of semiconductor devices. In the case of semiconductor devices, since the integration density is an important factor determining the price of the product, there is a particular demand for increased integration density. In the case of two-dimensional or planar semiconductor devices, the degree of integration is determined mainly by the area occupied by a unit memory cell, and is therefore greatly influenced by the level of fine pattern formation technology.

[0003] However, the need for extremely expensive equipment to miniaturize patterns continues to limit the integration density of two-dimensional semiconductor devices, even as it increases. Therefore, a three-dimensional semiconductor memory device having memory cells arranged three-dimensionally has been proposed.

[0004] However, for a three-dimensional semiconductor memory device having memory cells arranged three-dimensionally, further improvement in reliability is an issue to be addressed. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] U.S. Pat. No. 10,074,667 [Patent Document 2] U.S. Patent No. 10,283,493 Summary of the Invention [Problem to be solved by the invention]

[0006] The present invention has been made in consideration of the problems associated with the above-mentioned conventional three-dimensional semiconductor memory devices, and an object of the present invention is to provide a highly integrated three-dimensional semiconductor memory device with improved reliability. [Means for solving the problem]

[0007] In order to achieve the above object, a three-dimensional semiconductor memory device according to the present invention includes a first peripheral circuit section which is a logic chip and includes a plurality of mutually different decoder circuit sections, a first memory section which is stacked and disposed on the first peripheral circuit section, and a second memory section which is stacked and disposed on the first memory section, the first memory section includes a first stack structure including a plurality of first electrode layers stacked on each other and a plurality of first electrode interlayer insulating films interposed therebetween, and a first planar insulating film covering an end portion of the first stack structure, and the second memory section includes a plurality of first electrode layers stacked on each other and a first planar insulating film covering an end portion of the first stack structure. a second stack structure including a plurality of second electrode layers and a plurality of second electrode interlayer insulating films interposed therebetween; and a second planar insulating film covering an end portion of the second stack structure, the first memory unit further including a first through via penetrating the end portion of the first stack structure and the first planar insulating film, being insulated from the first electrode layers and electrically connected to any one of the decoder circuit units, and the second memory unit further including a second cell contact plug penetrating the second planar insulating film and electrically connecting any one of the second electrode layers to the first through via. the first memory unit further includes a plurality of first vertical patterns penetrating the first electrode layer and a plurality of first bit lines parallel to each other, each connected to an end of the first vertical patterns; the second memory unit further includes a plurality of second vertical patterns penetrating the second electrode layer and a plurality of second bit lines parallel to each other, each connected to an end of the second vertical patterns; the first peripheral circuit unit further includes a page buffer circuit unit, the first bit lines being connected to one of the page buffer circuit units and the second bit lines not being connected to the one of the page buffer circuit units. It is characterized by:

[0008] In order to achieve the above object, a three-dimensional semiconductor memory device according to the present invention includes a peripheral circuit section including first to fourth decoder circuit sections that are different from each other, a first memory section disposed on the peripheral circuit section, and a second memory section disposed on the first memory section, the first memory section including a first stack structure and a second stack structure spaced apart from each other in a first direction parallel to an upper surface of the peripheral circuit section, the first stack structure including a plurality of first electrode layers stacked on each other, the second stack structure including a plurality of second electrode layers stacked on each other, the second memory section including a third stack structure and a fourth stack structure spaced apart from each other in the first direction, the third stack structure including a plurality of third electrode layers stacked on each other, the fourth stack structure including a plurality of fourth electrode layers stacked on each other, the first electrode layer being electrically connected to the first decoder circuit section, and the third electrode layer being electrically connected to the third decoder circuit section. the second electrode layer is electrically connected to the second decoder circuit unit, the fourth electrode layer is electrically connected to the fourth decoder circuit unit and in contact with the first electrode layer, and further includes a plurality of first cell contact plugs each connecting the first electrode layer to the first decoder circuit unit, a plurality of second cell contact plugs each in contact with the third electrode layer, and a plurality of first through vias each connecting the second cell contact plugs to the third decoder circuit unit and insulated from the first electrode layer, the first memory unit includes a first planar insulating film covering ends of the first stack structure and the second stack structure, the third decoder circuit unit and the fourth decoder circuit unit are spaced apart from the first decoder circuit unit and the second decoder circuit unit in a second direction that is parallel to an upper surface of the peripheral circuit unit and intersects with the first direction, and any one of the second electrode layers is connected to the second decoder circuit unit through the second cell contact plug and the first through via. the first memory unit further includes a fifth decoder circuit unit and a sixth decoder circuit unit electrically connected to the third decoder circuit unit, the fifth decoder circuit unit and the sixth decoder circuit unit being parallel to an upper surface of the peripheral circuit unit and disposed in parallel to the first decoder circuit unit and the second decoder circuit unit in a second direction intersecting the first direction, the first memory unit further includes a fifth stack structure and a sixth stack structure spaced apart from the first stack structure in the second direction, the fifth stack structure including a plurality of fifth electrode layers stacked on each other and a plurality of fifth electrode interlayer insulating films interposed therebetween, the sixth stack structure including a plurality of sixth electrode layers stacked on each other and a plurality of sixth electrode interlayer insulating films interposed therebetween, the first planar insulating film extending to cover ends of the fifth stack structure and the sixth stack structure, the first memory unit further includes a third cell contact plug penetrating the first planar insulating film and electrically connecting any one of the fifth electrode layers and the sixth electrode layer to the third decoder circuit unit. It is characterized by:

[0009] In order to achieve the above object, a three-dimensional semiconductor memory device according to the present invention includes a peripheral circuit section including first and second decoder circuit sections that are different from each other and are arranged in parallel in a first direction, a first memory section that is stacked and arranged on the peripheral circuit section and includes a first stack structure, and a second memory section that is arranged on the first memory section and includes a second stack structure, wherein the first stack structure is electrically connected to the first decoder circuit section, the second stack structure is electrically connected to the second decoder circuit section, and a part of the second stack structure is electrically connected to the first stack structure. of Protruding from the side the peripheral circuit unit further includes a third decoder circuit unit spaced apart from the first decoder circuit unit in a direction opposite to the first direction, the first stack structure including a first recess region on the third decoder circuit unit, and the second stack structure including a second recess region on the third decoder circuit unit; a third memory unit stacked and disposed on the second memory unit and including a third stack structure; a cell contact plug contacting the third stack structure on the third decoder circuit unit; a first through via disposed in the first recess region and electrically connected to the cell contact plug; and a second through via disposed in the second recess region and electrically connected to the cell contact plug. It is characterized by:

[0010] A three-dimensional semiconductor memory device according to another embodiment of the present invention includes a first peripheral circuit unit including first to fourth decoder circuit units that are different from each other, a first memory unit stacked on the first peripheral circuit unit, and a second memory unit disposed on the first memory unit, wherein the first memory unit includes a first stack structure and a second stack structure spaced apart from each other, and the second memory unit includes a third stack structure and a fourth stack structure spaced apart from each other, the first stack structure and the third stack structure overlap with at least one of the first decoder circuit unit and the third decoder circuit unit, and the second stack structure and the fourth stack structure overlap with at least one of the second decoder circuit unit and the fourth decoder circuit unit.

[0011] A three-dimensional semiconductor memory device according to another embodiment of the present invention includes a peripheral circuit unit including first and second decoder circuit units different from each other, a first memory unit stacked on the peripheral circuit unit, and a second memory unit disposed on the first memory unit, wherein the first memory unit includes a first stack structure including first electrode layers stacked on each other and a first electrode interlayer insulating film interposed therebetween, a plurality of first vertical patterns penetrating the first stack structure, a first gate insulating film interposed between the first vertical patterns and the first stack structure, and a first planar insulating film covering an end of the first stack structure, and the second memory unit includes a second stack structure including second electrode layers stacked on each other and a second electrode interlayer insulating film interposed therebetween, a plurality of second vertical patterns penetrating the second stack structure, a second gate insulating film interposed between the second vertical patterns and the second stack structure, and a second planar insulating film covering an end of the second stack structure, and the first electrode layer is electrically connected to the first decoder circuit unit and the second electrode layer is electrically connected to the second decoder circuit unit. Effect of the Invention

[0012] The three-dimensional semiconductor memory device of the present invention includes multiple memory chips stacked on a logic chip, and the drive circuits (or pass transistors or bit line selection transistors) that operate the memory blocks included in each memory chip can be separated. Therefore, the reliability of the semiconductor memory device can be improved, and this is advantageous for high integration. [Brief description of the drawings]

[0013] [Figure 1A] 1 is a perspective view illustrating a schematic configuration of a three-dimensional semiconductor memory device according to an embodiment of the present invention. [Figure 1B] 1 is a schematic circuit diagram of a three-dimensional semiconductor memory device according to an embodiment of the present invention; [Figure 2A] FIG. 1B is a plan view of the logic chip of FIG. 1A according to an embodiment of the present invention. [Figure 2B] FIG. 1B is a plan view of the first memory chip of FIG. 1A according to an embodiment of the present invention. [Figure 2C] FIG. 1B is a plan view of the second memory chip of FIG. 1A according to an embodiment of the present invention. [Figure 3A] 2C is a cross-sectional view taken along the line of FIG. 2A or FIG. 2B according to an embodiment of the present invention. [Figure 3B] FIG. 2C is a cross-sectional view taken along line BB' of FIG. 2B or FIG. 2C according to an embodiment of the present invention. [Figure 3C] FIG. 3 is a cross-sectional view taken along line CC' of FIG. 2B or FIG. 2C according to an embodiment of the present invention. [Figure 4A] FIG. 3B is an enlarged cross-sectional view of portion "P1" of FIG. 3A according to an embodiment of the present invention. [Figure 4B] FIG. 3B is an enlarged cross-sectional view of portion "P2" of FIG. 3A according to an embodiment of the present invention. [Figure 4C] FIG. 3D is an enlarged cross-sectional view of portion "P3" of FIG. 3C according to an embodiment of the present invention. [Figure 4D] FIG. 3B is an enlarged cross-sectional view of portion "P10" of FIG. 3A according to an embodiment of the present invention. [Diagram 5]FIG. 1B is a perspective view showing a detailed structure of FIG. 1A according to an embodiment of the present invention. [Figure 6A] 1B is a plan view showing a schematic configuration of the logic chip of FIG. 1A according to another embodiment of the present invention. [Figure 6B] 1B is a partial plan view showing a schematic configuration of the first memory chip of FIG. 1A according to another embodiment of the present invention. [Figure 6C] 1B is a partial plan view showing a schematic configuration of the second memory chip of FIG. 1A according to another embodiment of the present invention. [Figure 7A] 6B or 6C according to another embodiment of the present invention. FIG. [Figure 7B] FIG. 7 is a cross-sectional view taken along line BB' of FIG. 6B or FIG. 6C according to another embodiment of the present invention. [Figure 8] FIG. 1B is a perspective view showing a detailed structure of FIG. 1A according to another embodiment of the present invention. [Figure 9A] 1B is a partial plan view showing a schematic configuration of the first memory chip of FIG. 1A according to still another embodiment of the present invention. [Figure 9B] 1B is a partial plan view showing a schematic configuration of a second memory chip of FIG. 1A according to still another embodiment of the present invention. [Figure 10] 9B according to still another embodiment of the present invention. FIG. [Figure 11] FIG. 1B is a perspective view showing a detailed structure of FIG. 1A according to still another embodiment of the present invention. [Figure 12] 11 is a perspective view illustrating a schematic configuration of a three-dimensional semiconductor memory device according to still another embodiment of the present invention. [Figure 13A] 13 is a cross-sectional view taken along line AA' of FIG. 12 according to still another embodiment of the present invention. [Figure 13B] 13 is a cross-sectional view taken along line BB' of FIG. 12 according to still another embodiment of the present invention. [Figure 14] 11 is a perspective view illustrating a schematic configuration of a three-dimensional semiconductor memory device according to still another embodiment of the present invention. [Figure 15]15 is a cross-sectional view taken along line BB' of FIG. 14 according to still another embodiment of the present invention. [Figure 16] 11 is a perspective view illustrating a schematic configuration of a three-dimensional semiconductor memory device according to still another embodiment of the present invention. [Figure 17] 11 is a perspective view illustrating a schematic configuration of a three-dimensional semiconductor memory device according to still another embodiment of the present invention. [Figure 18] 11 is a perspective view illustrating a schematic configuration of a three-dimensional semiconductor memory device according to still another embodiment of the present invention. [Figure 19] 11 is a perspective view illustrating a schematic configuration of a three-dimensional semiconductor memory device according to still another embodiment of the present invention. [Figure 20] 1 is a partial cross-sectional view showing a schematic configuration of a three-dimensional semiconductor memory device according to an embodiment of the present invention. [Figure 21] 11 is a perspective view illustrating a schematic configuration of a three-dimensional semiconductor memory device according to still another embodiment of the present invention. [Figure 22A] 11 is a perspective view illustrating a schematic configuration of a three-dimensional semiconductor memory device according to still another embodiment of the present invention. [Figure 22B] 22B is a plan view of a logic chip included in the three-dimensional semiconductor memory device of FIG. 22A. [Figure 22C] 22B is a plan view of first and third memory chips included in the three-dimensional semiconductor memory device of FIG. 22A. [Figure 22D] 22B is a plan view of second and fourth memory chips included in the three-dimensional semiconductor memory device of FIG. 22A. [Figure 22E] FIG. 22D is an enlarged plan view of portion “P4” in FIG. 22C. [Figure 22F] FIG. 22C is an enlarged plan view of the first decoder circuit portion of FIG. 22B. [Figure 23] 11 is a perspective view illustrating a schematic configuration of a three-dimensional semiconductor memory device according to still another embodiment of the present invention. [Figure 24] 1 is a cross-sectional view showing a schematic configuration of a three-dimensional semiconductor memory device according to an embodiment of the present invention. [Diagram 25] 1 is a cross-sectional view showing a schematic configuration of a three-dimensional semiconductor memory device according to an embodiment of the present invention. [Figure 26] 2B or 2C according to an embodiment of the present invention. [Figure 27] 11 is a perspective view illustrating a schematic configuration of a three-dimensional semiconductor memory device according to still another embodiment of the present invention. [Figure 28] 28 is a cross-sectional view taken along line AA' in FIG. 27. [Figure 29] 11 is a perspective view illustrating a schematic configuration of a three-dimensional semiconductor memory device according to still another embodiment of the present invention. [Diagram 30] 11 is a partial cross-sectional view illustrating a schematic configuration of a three-dimensional semiconductor memory device according to still another embodiment of the present invention. [Diagram 31] 11 is a partial cross-sectional view illustrating a schematic configuration of a three-dimensional semiconductor memory device according to still another embodiment of the present invention. [Diagram 32] 11 is a partial cross-sectional view illustrating a schematic configuration of a three-dimensional semiconductor memory device according to still another embodiment of the present invention. [Diagram 33] 11 is a partial cross-sectional view illustrating a schematic configuration of a three-dimensional semiconductor memory device according to still another embodiment of the present invention. [Diagram 34] 2 is a perspective view showing a schematic configuration of an end portion of a first stack structure according to an embodiment of the present invention. FIG. [Diagram 35] 11 is a partial cross-sectional view illustrating a schematic configuration of a three-dimensional semiconductor memory device according to still another embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] Next, a specific example of an embodiment of a three-dimensional semiconductor memory device according to the present invention will be described with reference to the drawings.

[0015] FIG. 1A is a perspective view illustrating a schematic configuration of a three-dimensional semiconductor memory device according to an embodiment of the present invention. 1A, in a three-dimensional semiconductor memory device according to an embodiment of the present invention, a plurality of memory chips (200, 300) are sequentially stacked on a logic chip 100. In the three-dimensional semiconductor memory device shown in FIG. The memory chips (200, 300) include, for example, a first memory chip 200 and a second memory chip 300.

[0016] The logic chip 100 may include a decoder circuit section, a page buffer circuit section, and a control circuit section. The first memory chip 200 includes a plurality of memory blocks (BLK1, BLK2). The second memory chip 300 includes a plurality of memory blocks (BLK3, BLK4). Each of the memory blocks (BLK1 to BLK4) includes a memory cell array having a three-dimensional structure (or vertical structure). For the sake of convenience, four memory blocks (BLK1 to BLK4) are shown in FIG. 1A, but the number of memory blocks is not limited to this and may be greater than this. In the present invention, the driving circuits (decoder circuit section, page buffer circuit section) that operate the memory blocks (BLK1 to BLK4) included in each memory chip (200, 300) are separated, thereby improving the performance of the semiconductor memory device and being advantageous for high integration.

[0017] FIG. 1B is a schematic circuit diagram of a three-dimensional semiconductor memory device according to an embodiment of the present invention. Referring to FIG. 1B, in each of the memory blocks BLK0 to BLKn, the cell strings CSTR are two-dimensionally arranged along first and second directions D1 and D2 and extend along a third direction D3. A plurality of cell strings CSTR are connected in parallel to each of the bit lines (BL0 to BL2). The multiple cell strings CSTR are commonly connected to a common source line CSL.

[0018] The bit lines (BL0 to BL2) are arranged two-dimensionally, and a plurality of cell strings CSTR are connected in parallel to each of the bit lines (BL0 to BL2). The multiple cell strings CSTR are commonly connected to a common source line CSL. That is, a plurality of cell strings CSTR are arranged between a plurality of bit lines (BL0 to BL2) and one common source line CSL. A plurality of common source lines CSL are arranged two-dimensionally. Here, the same voltage may be applied to the common source lines CSL, or each of the common source lines CSL may be electrically controlled.

[0019] According to the embodiment, one of the cell strings CSTR is composed of serially connected string selection transistors (SST21, SST11), serially connected memory cell transistors MCT, and a ground selection transistor GST. In addition, each of the memory cell transistors MCT includes a data storage element. One of the cell strings CSTR may further include dummy cells DMC connected between the eleventh string selection transistor SST11 and the memory cell transistor MCT, and between the ground selection transistor GST and the memory cell transistor MCT, respectively. Other cell strings CSTR may have the same / similar structure.

[0020] The twenty-first string selection transistor SST21 is connected to the first bit line BL1, and the ground selection transistor GST is connected to the common source line CSL. The memory cell transistor MCT connected to one cell string CSTR among the memory cell transistors MCT is connected in series between, for example, an eleventh string selection transistor SST11 and a ground selection transistor GST. As another example, the ground selection transistor GST in each cell string CSTR may be composed of a plurality of MOS transistors connected in series, similar to the string selection transistors SST21 and SST11. As another example, each cell string CSTR may include one string selection transistor.

[0021] According to an embodiment, the eleventh string select transistor SST11 is controlled by an eleventh string select line SSL11, and the twenty-first string select transistor SST21 is controlled by a twenty-first string select line SSL21. The memory cell transistors MCT are controlled by a plurality of word lines (WL0 to WLn), and the dummy cells DMC are controlled by a dummy word line DWL. Moreover, the ground selection transistor GST is controlled by one of the ground selection lines (GSL0 to GSL2). A common source line CSL is commonly connected to the sources of the ground selection transistors GST. The ground selection lines (GSL0 to GSL2) can be connected together and operate simultaneously, or can be separated from each other and operate independently.

[0022] One cell string CSTR is composed of a plurality of memory cell transistors MCT each having a different distance from a common source line CSL. A plurality of word lines (WL0 to WLn, DWL) are disposed between the common source line CSL and the bit lines (BL0 to BL2). The gate electrodes of the memory cell transistors MCT, which are arranged at substantially the same distance from the common source line CSL, are commonly connected to one of the word lines (WL0 to WLn, DWL) and are in an equipotential state. Alternatively, even if the gate electrodes of the memory cell transistors MCT are arranged at substantially the same distance from the common source line CSL, the gate electrodes arranged in different rows or columns may be controlled independently.

[0023] The operation of the three-dimensional semiconductor memory device of FIG. 1B is as follows. For example, during a write operation, the decoder circuitry applies a program voltage to a selected word line of a selected memory block among the memory blocks (BLK1 to BLK4) according to an address, and applies a pass voltage to unselected word lines of a selected memory block among the memory blocks (BLK1 to BLK4). The decoder circuitry applies a turn-off voltage to the ground selection lines (GSL0 to GSL2) of the selected memory block, and applies a turn-on voltage to the dummy word lines DWL and the string selection lines (SSL11 to SSL13, SSL21 to SSL23).

[0024] During a read operation, the decoder circuitry applies a selective read voltage to a selected word line of a memory block selected among the memory blocks (BLK1 to BLK4) according to an address, and applies a non-selected read voltage to non-selected word lines of the selected memory block. The decoder circuitry applies a turn-on voltage to the ground selection lines (GSL0 to GSL2), the dummy word lines DWL, and the string selection lines (SSL11 to SSL13, SSL21 to SSL23) of the selected memory block.

[0025] During an erase operation, the decoder circuitry applies an erase voltage (eg, a ground voltage or a low voltage having a similar level to the ground voltage) to a word line of a memory block selected from among the memory blocks BLK1 to BLK4 according to an address. The decoder circuit unit floats the ground selection lines (GSL0 to GSL2), the dummy word lines DWL, and the string selection lines (SSL11 to SSL13, SSL21 to SSL23) of the selected memory block.

[0026] The page buffer circuit unit is connected to the memory cell array through a plurality of bit lines (BL0 to BL2). The page buffer circuitry is connected to the data input and output circuits. The page buffer circuit section operates under the control of the control logic circuit. During a write operation, the page buffer circuitry stores the data to be written to the memory cells. Based on the stored data, the page buffer circuitry applies voltages to a number of bit lines BL0 to BL2. During a verify read of a read, write, or erase operation, the page buffer circuit senses the voltages of the bit lines BL0 to BL2 and stores the sensed results.

[0027] 2A is a plan view of the logic chip of FIG. 1A according to an embodiment of the present invention, FIG. 2B is a plan view of a first memory chip of FIG. 1A according to an embodiment of the present invention, FIG. 2C is a plan view of a second memory chip of FIG. 1A according to an embodiment of the present invention, FIG. 3A is a cross-sectional view taken along line A-A' of FIG. 2A or FIG. 2B according to an embodiment of the present invention, FIG. 3B is a cross-sectional view taken along line B-B' of FIG. 2B or FIG. 2C according to an embodiment of the present invention, and FIG. 3C is a cross-sectional view taken along line B-B' of FIG. 2B or FIG. 2C according to an embodiment of the present invention. 2B or a cross-sectional view cut along line C-C' of FIG. 2C, FIG. 4A is an enlarged cross-sectional view of the "P1" portion of FIG. 3A according to an embodiment of the present invention, FIG. 4B is an enlarged cross-sectional view of the "P2" portion of FIG. 3A according to an embodiment of the present invention, FIG. 4C is an enlarged cross-sectional view of the "P3" portion of FIG. 3C according to an embodiment of the present invention, FIG. 4D is an enlarged cross-sectional view of the "P10" portion of FIG. 3A according to an embodiment of the present invention, and FIG. 5 is a perspective view showing a detailed structure of FIG. 1A according to an embodiment of the present invention.

[0028] 2A, 3A, and 3B, logic chip 100 includes a logic substrate 103. As shown in FIG. The logic substrate 103 is, for example, a silicon single crystal substrate or an SOI (silicon on insulator) substrate. An isolation film 105 is disposed on the logic substrate 103 to define an active region. The element isolation film 105 may include at least one of a silicon oxide film, a silicon nitride film, or a silicon oxynitride film.

[0029] A plurality of logic transistors (PST1 to PST4, PTR) are arranged in the active region. Each of the logic transistors (PST1 to PST4, PTR) is at least one of a planar type MOSFET, a FinFET, an MBCFET, and a VFET. The transistors (PST1 to PST4, PTR) are covered with a logic interlayer insulating film 107. The logic interlayer insulating film 107 may include at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a porous insulating film, and a low dielectric constant insulating film. A multi-layer logic wiring 109 is disposed in the logic interlayer insulating film 107 . The logic transistors (PST1 to PST4, PTR) and the logic wiring 109 constitute first to fourth decoder circuit units (DCR1 to DCR4) and a page buffer circuit unit PB.

[0030] The logic transistors (PST1 to PST4, PTR) include first to fourth pass transistors (PST1 to PST4) and a bit line selection transistor PTR. The first to fourth pass transistors (PST1 to PST4) belong to the first to fourth decoder circuit parts (DCR1 to DCR4), respectively. The bit line selection transistor PTR belongs to the page buffer circuit section PB. A logic connection terminal 150 is disposed on the upper end of the logic interlayer insulating film 107 . The logic connection terminal 150 is electrically connected to the logic wiring 109 . The page buffer circuit unit PB is disposed in the center of the logic chip 100 . The first and fourth decoder circuit units DCR1 and DCR4 are adjacent to one side of the page buffer circuit unit PB. The second and third decoder circuit units DCR2 and DCR3 are adjacent to the other side of the page buffer circuit unit PB.

[0031] 2B, 3A, and 3B, the first memory chip 200 includes a first memory substrate 201. The first memory chip 200 includes a first connection region CNR1 and a second connection region CNR2 spaced apart from each other in a first direction D1, and a cell array region CAR located therebetween. The cell array region CAR overlaps with the page buffer circuit unit PB of the logic chip 100 . The first connection region CNR1 overlaps with the first and fourth decoder circuit units (DCR1, DCR4). The second connection region CNR2 overlaps with the second and third decoder circuit units (DCR2, DCR3).

[0032] The first memory substrate 201 is, for example, a silicon single crystal substrate or a silicon on insulator (SOI) substrate. The first memory substrate 201 is a semiconductor film or an insulating film. The first memory substrate 201 includes a first surface 201a and a second surface 201b facing each other. The first surface 201 a of the first memory substrate 201 faces the logic chip 100 . On the first surface 201a of the first memory substrate 201, the source layer SCL is disposed.

[0033] A first stack structure ST1 and a second stack structure ST2 spaced apart from each other in the second direction D2 are disposed on the source layer SCL. The first stack structure ST1 corresponds to a part of the first memory block BLK1 in FIG. 1B. The second stack structure ST2 corresponds to a part of the second memory block BLK2 in FIG. 1B. The second stack structure ST2 has a shape obtained by rotating the first stack structure ST1 by 180 degrees. The first stack structure ST1 includes a first electrode layer EL1 stacked therebetween and an inter-electrode layer insulating film 12 interposed therebetween.

[0034] The first electrode layer EL1 may, for example, contain a metal such as tungsten. The electrode interlayer insulating film 12 may include, for example, a silicon oxide film. The first electrode layer EL1 that is closest to the logic chip 100 is separated into a plurality of parts by the separating insulating pattern 9 and the groove region GR to form a plurality of conductive lines. The conductive line also corresponds to one of the string selection lines (SSL11 to SSL13, SSL21 to SSL23) in the first memory block BLK1. The first electrode layer EL1 closest to the source layer SCL may be formed into a plurality of conductive lines by other isolation insulating patterns (not shown), which correspond to one of the ground selection lines GSL in the first memory block BLK1 as well. The first electrode layers EL1 located in the middle correspond to the word lines (WL0 to WLn) in FIG. 1B.

[0035] The end of the first stack structure ST1 in the first connection region CNR1 and the second connection region CNR2 forms a staircase structure. The end portion of the first stack structure ST1 is covered with a flat insulating film 20. The first stack structure ST1 includes a groove region GR that is long in a first direction D1 in each of the cell array region CAR and the first connection region CNR1. The first electrode layer EL1 of the first stack structure ST1 includes a first recess region RC1 in each of the second connection regions CNR2. The inner walls of the first recess regions RC1 are aligned with each other.

[0036] The second stack structure ST2 includes stacked second electrode layers EL2 and an inter-electrode insulating film 12 interposed therebetween. The second electrode layer EL2 may, for example, contain a metal such as tungsten. The second electrode layer EL2 that is closest to the logic chip 100 is separated into a plurality of portions by the separating insulating pattern 9 and the groove region GR to form a plurality of conductive lines. The conductive line also corresponds to one of the string selection lines (SSL11 to SSL13, SSL21 to SSL23) in the second memory block BLK2. The first electrode layer EL1 closest to the source layer SCL may be formed into multiple conductive lines by other isolation insulating patterns (not shown), which also correspond to one of the ground selection lines GSL in the second memory block BLK2. The first electrode layers EL1 located in the middle correspond to the word lines (WL0 to WLn) in FIG. 1B.

[0037] The end of the second stack structure ST2 in the first connection region CNR1 and the second connection region CNR2 forms a staircase structure. The end portion of the second stack structure ST2 is covered with a flat insulating film 20. The second stack structure ST2 includes a groove region GR that is long in the first direction D1 in each of the cell array region CAR and the second connection region CNR2. The second electrode layer EL2 of the second stack structure ST2 includes a second recess region RC2 in each of the first connection regions CNR1. The inner walls of the second recess regions RC2 are aligned with each other. The first recessed area RC1 and the second recessed area RC2 are each filled with a remaining sacrificial pattern 18. The remaining sacrificial pattern 18 may be formed of a material having an etching selectivity with respect to the electrode interlayer insulating film 12, for example, a silicon nitride film.

[0038] In the cell array region CAR, a plurality of cell vertical patterns VS penetrate the first stack structure ST1 and the second stack structure ST2, respectively. One end of the cell vertical pattern VS is connected by a first layer bit line L1BL. The first layer bit lines L1BL extend in a second direction D2 and are parallel to each other. One first layer bit line L1BL passes through the first stack structure ST1 and the second stack structure ST2, and simultaneously connects one end of the cell vertical patterns VS arranged in a row along the second direction D2. Although a part of the first layer bit lines L1BL is omitted in FIG. 2A for the sake of simplicity, the first layer bit lines L1BL are disposed throughout the entire cell array region CAR.

[0039] In the cell array region CAR, a first through-cell via CTHV1 penetrates the first stack structure ST1 and the first memory substrate 201, and a second through-cell via CTHV2 penetrates the second stack structure ST2 and the first memory substrate 201. In plan view, the first through-cell via CTHV1 and the second through-cell via CTHV2 are located between the first layer bit line L1BL. The first through-cell via CTHV1 and the second through-cell via CTHV2 are each electrically connected to one of the first-layer bit lines L1BL by a bit line connecting wiring BLCP. In the first memory chip 200, the bit line connecting wiring BLCP is a part of the first layer bit line L1BL protruding laterally, or is a conductive pattern located at a different height from the first layer bit line L1BL.

[0040] 2B, 3A, and 5, a first edge-through via ETHV1 penetrates the first stack structure ST1 and the first memory substrate 201 in the second connection region CNR2. The first edge through via ETHV1 is disposed within the first recess region RC1. The first edge through via ETHV1 penetrates the planar insulating film 20, the inter-electrode insulating film 12, and the remaining sacrificial pattern .

[0041] 2B, 3A, and 5, a second edge-through via ETHV2 penetrates the second stack structure ST2 and the first memory substrate 201 in the first connection region CNR1. The second edge through via ETHV2 is disposed within the second recess region RC2. The second edge through via ETHV2 penetrates the flat insulating film 20, the inter-electrode layer insulating film 12, and the remaining sacrificial pattern . The first and second end through-vias (ETHV1, ETHV2) do not have to be electrically connected to either the first electrode layer EL1 or the second electrode layer EL2. The first and second through-end vias (ETHV1, ETHV2) may be arranged in a zigzag shape or aligned in a line along the first direction D1 in a plan view.

[0042] 2B, 3A, and 4A, the first and second through vias (CTHV1, CTVH2) and the first and second end through vias (ETHV1, ETHV2) are surrounded by a via insulating film 16. The via insulating film 16 may include, for example, a silicon oxide film. The via insulating film 16 has a first thickness TK1 that is parallel to the first direction D1. Any one of the inter-electrode layer insulating films 12 has a second thickness TK2 that is parallel to a third direction D3 that is perpendicular to the first direction D1. When the via insulating film 16 contains the same material as the inter-electrode insulating film 12, the first thickness TK1 is equal to or greater than the second thickness TK2. Therefore, even if a voltage is applied to the first and second cell through-vias (CTHV1, CTVH2) and the first and second end through-vias (ETHV1, ETHV2), signal interference between the adjacent first electrode layer EL1 and the first and second end through-vias (ETHV1, ETHV2) can be reduced or prevented.

[0043] In the first connection region CNR1, the first cell contact plugs CC1 each penetrate the flat insulating film 20 and the inter-electrode layer insulating film 12 to contact an end of the first electrode layer EL1. In the second connection region CNR2, the second cell contact plugs CC2 each penetrate the flat insulating film 20 and the inter-electrode layer insulating film 12 to contact an end of the second electrode layer EL2. The first cell contact plug CC1 and the second cell contact plug CC2 are each surrounded by a contact insulating film 14. The contact insulating film 14 may include, for example, a silicon nitride film or a silicon oxide film. The contact insulating film 14 has a third thickness TK3 that is parallel to the first direction D1. The third thickness TK3 is smaller than the first thickness TK1.

[0044] 2B and 3C, a first source contact plug CSPLG1 is disposed in the separation region SR between the first stack structure ST1 and the second stack structure ST2. A second source contact plug CSPLG2 is disposed in the groove region GR. The first source contact plug CSPLG1 and the second source contact plug CSPLG2 are spaced apart from each other and adjacent to the first memory substrate 201 through the first and second stack structures ST1 and ST2.

[0045] An insulating spacer SP is interposed between the first and second source contact plugs (CSPLG1, CSPLG2) and the first and second stack structures (ST1, ST2). Between the isolation insulating patterns 9, a central dummy vertical pattern CDVS is disposed. The central dummy vertical patterns CDVS are arranged in a row along the first direction D1. The central dummy vertical pattern CDVS is not electrically connected to the first layer bit line L1BL. In the connection regions (CNR1, CNR2), the edge dummy vertical pattern EDVS penetrates the flat insulating film 20 and the ends of the first and second stack structures (ST1, ST2).

[0046] The cell vertical pattern VS, the center dummy vertical pattern CDVS, and the edge dummy vertical pattern EDVS each have a hollow cup shape, and the internal empty space is filled with a buried insulating pattern 29. The buried insulating pattern 29 may include, for example, a silicon oxide film. Bit line conductive pads 34 are formed on the cell vertical patterns VS, the center dummy vertical patterns CDVS, and the edge dummy vertical patterns EDVS, respectively. The bit line conductive pad 34 may be an impurity region doped with impurities or may be made of a conductive material.

[0047] As shown in FIG. 4A or 4C, a gate insulating film GO is interposed between the vertical patterns (VS, CDVS, EDVS) and the first and second stack structures (ST1, ST2). The gate insulating film GO includes a tunnel insulating film TL, a charge storage film SN, and a blocking insulating film BCL. The charge storage film SN is a trap insulating film, a floating gate electrode, or an insulating film including conductive nano dots.

[0048] More specifically, the charge storage film SN may include at least one of a silicon nitride film, a silicon oxynitride film, a silicon-rich nitride film, a nanocrystalline silicon, and a laminated trap layer. The tunnel insulating film TL is one of materials having a larger band gap than the charge storage film SN, and the blocking insulating film BCL is a high dielectric film such as an aluminum oxide film or a hafnium oxide film. The gate insulating film GO may further include a high dielectric film HL. The high dielectric film HL is interposed between the blocking insulating film BCL and the electrode layers (EL1 to EL4). The high dielectric film HL is interposed between the electrode layers (EL1 to EL4) and the inter-electrode insulating film 12. The high dielectric film HL may include a metal oxide film, such as a hafnium oxide film or an aluminum oxide film, as a film having a higher dielectric constant than a silicon oxide film.

[0049] 3C and 4C, the source layer SCL includes a first source pattern SC1 and a second source pattern SC2. Each of the first source pattern SC1 and the second source pattern SC2 may include, for example, a silicon single crystal pattern or a polysilicon pattern doped with impurities of a first conductivity type. The second source patterns SC2 pass through the tunnel insulating layer TL, the charge storage layer SN, and the blocking insulating layer BCL to contact the sidewalls of the vertical patterns VS, CDVS, and EDVS.

[0050] 3A and 4B, the second surface 201b of the first memory substrate 201 is covered with a first interlayer insulating film 3. As shown in FIG. A second interlayer insulating film 30 and a third interlayer insulating film 40 are sequentially stacked on the lower surface of the flat insulating film 20 . In the cell array region CAR, the first layer bit line L1BL is disposed between the second interlayer insulating film 30 and the third interlayer insulating film 40. In the connection regions (CNR1, CNR2), the first and second edge through-vias (ETHV1, ETHV2) and the first and second cell contact plugs (CC1, CC2) are electrically connected to the first conductive pattern VPa, respectively. The first conductive pattern VPa is disposed between the second interlayer insulating film 30 and the third interlayer insulating film 40.

[0051] The first and second through-cell vias (CTHV1, CTHV2) and the first and second through-edge vias (ETHV1, ETHV2) are electrically connected to a second conductive pattern VPb arranged on the second surface 201b of the first memory substrate 201, respectively. The first interlayer insulating film 3 of the first memory chip 200 and the third interlayer insulating film 40 of the second memory chip 300 are in contact with each other. Alternatively, as shown in FIG. 4B, a first passivation film 242 may be formed on the first interlayer insulating film 3, and a second passivation film 342 may be formed on the lower surface of the third interlayer insulating film 40. The first and second passivation films (242, 342) may be formed of, for example, a silicon oxide film. Then, the first and second passivation films (242, 342) contact each other.

[0052] The first memory chip further includes a first connection terminal 50 a arranged at the lower end of the third interlayer insulating film 40 and a second connection terminal 50 b arranged at the upper end of the first interlayer insulating film 3 . The connection terminals (50a, 50b) may include a metal such as copper, aluminum, tungsten, nickel, or tin. Preferably, the connection terminals (50a, 50b) are made of copper. As shown in FIG. 4B, the connection terminals (50a, 50b) contact each other. Or, the connection terminals (50a, 50b) can be fused together to form a one-piece shape with no interface therebetween. The conductive patterns (VPa, VPb) are electrically connected to the connection terminals (50a, 50b) by vias CT, respectively.

[0053] Referring to FIG. 4B, each of the first to fourth stack structures (SST1 to SST4) includes a first sub-stack structure SBST1 and a second sub-stack structure SBST2. The second substack structure SBST2 is closer to the source layer SCL than the first substack structure SBST1. The first substack structure SBST1 is closer to the logic chip 100 than the second substack structure SBST2. Adjacent to the boundary between the first substack structure SBST1 and the second substack structure SBST2, the sidewall of the vertical pattern (VS, CDVS, EDVS) has an inflection point SIP. In addition, the sidewall of the gate insulating film GO also has an inflection point adjacent to the boundary between the first substack structure SBST1 and the second substack structure SBST2.

[0054] 3A and 3B, the source layer SCL does not have to be penetrated by the through vias (CTHV1, CTHV2, ETHV1, ETHV2). A first insulating pattern IP1 is interposed between a via insulating film 16 covering the side walls of the first and second through-cell vias (CTHV1, CTHV2) and the source layer SCL. A second insulating pattern IP2 is interposed between the source layer SCL and the via insulating film 16 covering the sidewalls of the first and second edge through-vias ETHV1 and ETHV2 adjacent to the cell array region CAR. The first and second insulating patterns IP1 and IP2 may be formed of, for example, a silicon oxide film.

[0055] 2C, 3A, and 3B, the second memory chip 300 includes a second memory substrate 301. The structure of the second memory chip 300 is similar to that of the first memory chip 200 . The first surface 301 a of the second memory substrate 301 faces the logic chip 100 . On the first surface 301a of the second memory substrate 301, the source layer SCL is disposed.

[0056] A third stack structure ST3 and a fourth stack structure ST3 are disposed on the source layer SCL and spaced apart from each other in the second direction D2. The third stack structure ST3 corresponds to a part of the third memory block BLK3 in FIG. 1B. The fourth stack structure ST4 corresponds to a part of the fourth memory block BLK4 in FIG. 1B. The fourth stack structure ST4 has a shape obtained by rotating the third stack structure ST3 by 180 degrees. The third stack structure ST3 includes a third electrode layer EL3 stacked therebetween and an inter-electrode layer insulating film 12 interposed therebetween. The fourth stack structure ST4 includes a fourth electrode layer EL4 stacked therebetween and an inter-electrode layer insulating film 12 interposed therebetween.

[0057] In the first connection region CNR1 and the second connection region CNR2, the ends of the fourth stack structure ST4 and the third stack structure ST3 form a staircase structure. The total number of the third electrode layers EL3 may be the same as or different from the total number of the fourth electrode layers EL4. The total number of the third electrode layers EL3 may be the same as or different from the total number of the first electrode layers EL1. Unlike the first electrode layer EL1, the third electrode layer EL3 does not have to have the first recess region RC1. Unlike the second electrode layer EL2, the fourth electrode layer EL4 does not have to have the second recess region RC2.

[0058] In the cell array region CAR, a plurality of cell vertical patterns VS penetrate the third stack structure ST3 and the fourth stack structure ST4, respectively. One end of the cell vertical pattern VS is connected by a second layer bit line L2BL. The second layer bit lines L2BL extend in a second direction D2 and are parallel to each other. In the second memory chip 300, the bit line connecting wiring BLCP is a part of the second layer bit line L2BL that protrudes laterally, or is a conductive pattern located at a different height from the second layer bit line L2BL.

[0059] In the cell array region CAR, a third through-cell via CTHV3 penetrates the first stack structure ST3 and the second memory substrate 301, and a fourth through-cell via CTHV4 penetrates the fourth stack structure ST4 and the second memory substrate 301. The third through-cell via CTHV3 and the fourth through-cell via CTHV4 are each electrically connected to one of the second layer bit lines L2BL by a bit line connecting wiring BLCP. The second memory chip 300 does not need to include the edge through vias E (THV1, ETHV2) of the first memory chip 200.

[0060] In the second connection region CNR2, the third cell contact plugs CC3 each penetrate the flat insulating film 20 and the inter-electrode layer insulating film 12 to contact an end of the third electrode layer EL3. In the first connection region CNR1, the fourth cell contact plug CC4 penetrates the planar insulating film 20 and the inter-electrode layer insulating film 12 and contacts an end of the fourth electrode layer EL4. The third cell contact plug CC3 and the fourth cell contact plug CC4 are each surrounded by a contact insulating film 14. The rest of the configuration is the same as or similar to the first memory chip 200 .

[0061] 3A and 5, the ends of the first to fourth stack structures (ST1 to ST4) have a staircase shape with a distance that increases from the logic chip 100 in the first direction D1. The first electrode layer EL1 of the first stack structure ST1 of the first memory chip 200 is electrically connected to the first pass transistor PST1 of the first decoder circuit unit DCR1 by the first cell contact plug CC1, the first conductive pattern VPa, the first connection terminal 50a, and the logic connection terminal 150, respectively. That is, the ground selection lines (GSL0 to GSL2 in FIG. 1B), word lines (WL0 to WLn in FIG. 1B), dummy word lines (DWL in FIG. 1B), and string selection lines (SSL11 to SSL13, SSL21 to SSL23 in FIG. 1B) belonging to the first memory block BLK1 in FIG. 1A are each electrically connected to the first pass transistor PST1 of the first decoder circuit unit DCR1.

[0062] Referring to Figures 3B and 5, the second electrode layer EL2 of the second stack structure ST2 of the first memory chip 200 is electrically connected to the second pass transistor PST2 of the second decoder circuit unit DCR2 by the second cell contact plug CC2, the first conductive pattern VPa, the first connection terminal 50a, and the logic connection terminal 150, respectively. That is, the ground selection lines (GSL0 to GSL2 in FIG. 1B), word lines (WL0 to WLn in FIG. 1B), dummy word lines (DWL in FIG. 1B), and string selection lines (SSL11 to SSL13, SSL21 to SSL23 in FIG. 1B) belonging to the second memory block BLK2 in FIG. 1A are each electrically connected to the second pass transistor PST2 of the second decoder circuit unit DCR2.

[0063] 3A and 5, the third electrode layer EL3 of the third stack structure ST3 of the second memory chip 300 is electrically connected to the third pass transistor PST3 of the third decoder circuit unit DCR3 by the third cell contact plug CC3, the first conductive pattern VPa, the first connection terminal 50a, the second conductive pattern VPb, the second connection terminal 50b, the first edge through via ETHV1, and the logic connection terminal 150, respectively. That is, the ground selection lines (GSL0 to GSL2 in FIG. 1B), word lines (WL0 to WLn in FIG. 1B), dummy word lines (DWL in FIG. 1B), and string selection lines (SSL11 to SSL13, SSL21 to SSL23 in FIG. 1B) belonging to the third memory block BLK3 in FIG. 1A are each electrically connected to the third pass transistor PST3 of the third decoder circuit unit DCR1.

[0064] 3B and 5, the fourth electrode layer EL4 of the fourth stack structure ST4 of the second memory chip 300 is electrically connected to the fourth pass transistor PST4 of the fourth decoder circuit unit DCR4 by the fourth cell contact plug CC4, the first conductive pattern VPa, the first connection terminal 50a, the second conductive pattern VPb, the second connection terminal 50b, the second edge through via ETHV2, and the logic connection terminal 150, respectively. That is, the ground selection lines (GSL0 to GSL2 in FIG. 1B), word lines (WL0 to WLn in FIG. 1B), dummy word lines (DWL in FIG. 1B), and string selection lines (SSL11 to SSL13, SSL21 to SSL23 in FIG. 1B) belonging to the fourth memory block BLK4 in FIG. 1A are each electrically connected to the fourth pass transistor PST4 of the fourth decoder circuit unit DCR4.

[0065] In the three-dimensional semiconductor memory device according to an embodiment of the present invention, the regions in which the decoder circuit units (DCR1 to DCR4) or the pass transistors are arranged are separated from each other, and electrical signals can be applied independently to the first to fourth electrode layers (EL1 to EL4). This can have the effect of increasing the actual storage space compared to when all the memory blocks of a memory chip are commonly connected to one decoder circuit unit and operate simultaneously. Therefore, an increase in memory blocks and repair blocks can be prevented, and the size of the entire memory block and the semiconductor memory device can be reduced. In addition, if all memory blocks are commonly connected, the signal transmission length becomes longer, which may increase noise or degrade the performance of the semiconductor device. However, the present invention solves these problems and improves the reliability of the semiconductor device.

[0066] The method for manufacturing the three-dimensional semiconductor memory device described with reference to FIGS. 2A to 5 is as follows. A logic chip 100, a first memory chip 200, and a second memory chip 300 are each manufactured. Then, logic chip 100, first memory chip 200, and second memory chip 300 are positioned so that connection terminals 150, 50a, and 50b correspond to each other, and a thermocompression process is performed to bond them together. Although not shown in the figure, bumps or solder balls may be interposed between the connection terminals (150, 50a, 50b), and in this case, the passivation films (242, 342) may be spaced apart from each other. Although not shown, additional first and second memory chips (200, 300) may be repeatedly and alternately stacked on the second memory chip 300 in FIG.

[0067] FIG. 6A is a plan view showing a schematic configuration of the logic chip of FIG. 1A according to another embodiment of the present invention, FIG. 6B is a partial plan view showing a schematic configuration of the first memory chip of FIG. 1A according to another embodiment of the present invention, FIG. 6C is a partial plan view showing a schematic configuration of the second memory chip of FIG. 1A according to another embodiment of the present invention, FIG. 7A is a cross-sectional view taken along line A-A' of FIG. 6B or FIG. 6C according to another embodiment of the present invention, FIG. 7B is a cross-sectional view taken along line B-B' of FIG. 6B or FIG. 6C according to another embodiment of the present invention, and FIG. 8 is a perspective view showing a detailed structure of FIG. 1A according to another embodiment of the present invention.

[0068] Referring to FIG. 6A, logic chip 100 includes a logic substrate 103 . On the logic board 103, first to fourth decoder circuit units (DCR1 to DCR4) and a page buffer circuit unit PB are arranged. In this specification, the decoder circuitry may also be referred to as a decoder area. Alternatively, in this specification, the decoder circuit portion may refer to a region in which a pass transistor connected to an electrode layer is disposed. The first to fourth decoder circuit units DCR1 to DCR4 and the page buffer circuit unit PB are spaced apart from each other in a first direction D1. The page buffer circuit unit PB is disposed in the center of the logic chip 100.

[0069] The third decoder circuit unit DCR3 and the fourth decoder circuit unit DCR4 are separated from each other via the logic chip 100. The first decoder circuit unit DCR1 is disposed between the third decoder circuit unit DCR3 and the page buffer circuit unit PB. The second decoder circuit unit DCR2 is disposed between the fourth decoder circuit unit DCR4 and the page buffer circuit unit PB. The rest of the configuration is the same or similar to that described above.

[0070] 6B, 7A, 7B, and 8, the first memory chip 200 includes a first stack structure ST1 and a second stack structure ST2 spaced apart from each other in a second direction D2. The second stack structure ST2 has a shape obtained by rotating the first stack structure ST1 by 180 degrees. The first memory chip 200 includes a first connection region CNR1 and a second connection region CNR2 spaced apart from each other in a first direction D1, and a cell array region CAR located therebetween. In this embodiment, the cell array region CAR overlaps with the page buffer circuit unit PB of the logic chip 100 . The first connection region CNR1 overlaps with the second and fourth decoder circuit units (DCR2, DCR4). The second connection region CNR2 overlaps with the first and third decoder circuit units (DCR1, DCR3).

[0071] In FIG. 6B, a plan view of the first stack structure ST1 in the first connection region CNR1 is omitted, but in the first connection region CNR1, the first stack structure ST1 has the shape of the second stack structure ST2 in the second connection region CNR2. Similarly, in FIG. 6B, a plan view of the second stack structure ST2 in the first connection region CNR1 is omitted, but in the first connection region CNR1, the second stack structure ST2 has the shape of the first stack structure ST1 in the second connection region CNR2. The first electrode layer EL1 included in the first stack structure ST1 has a first recess region RC1 in the first connection region CNR1. The second electrode layer EL2 included in the second stack structure ST2 has a second recess region RC2 in the second connection region CNR2.

[0072] In the second connection region CNR2, the first electrode layers EL1 are connected to the first cell contact plugs CC1, respectively. The first cell contact plugs CC1 are each connected to a first electrode connecting line (VPa_E1). In the first connection region CNR1, the second electrode layers EL2 are respectively connected to second cell contact plugs CC2. The second cell contact plugs CC2 are each connected to a second electrode connecting line (VPa_E2). The first and second electrode connecting wires (VPa_E1, VPa_E2) extend in the second direction D2. In the first memory chip 200, the first and second electrode connecting wires (VPa_E1, VPa_E2) are located at the same height as the first conductive pattern VPa.

[0073] The second edge through-via ETHV2 is adjacent to the second stack structure ST2 more than the first stack structure ST1 in the second connection region CNR2, and is disposed outside the second stack structure ST2. The first edge through-via ETHV1 is adjacent to the first stack structure ST1 more than the second stack structure ST2 in the first connection region CNR1, and is disposed outside the first stack structure ST1. The first and second edge through vias (ETHV1, ETHV2) may not pass through the first and second stack structures (ST1, ST2), respectively. The first and second edge through vias (ETHV1, ETHV2) penetrate the planar insulating film 20 and the first memory substrate 201, respectively. The rest of the configuration is the same or similar to that described above.

[0074] 6C, 7A, 7B, and 8, the second memory chip 300 includes a third stack structure ST3 and a fourth stack structure ST3 spaced apart from each other in the second direction D2. The third stack structure ST3 has a shape obtained by rotating the fourth stack structure ST3 by 180 degrees.

[0075] Although a plan view of the third stack structure ST3 in the first connection region CNR1 is omitted in FIG. 6C, the third stack structure ST3 in the first connection region CNR1 has the shape of the fourth stack structure ST4 in the second connection region CNR2. Similarly, although a plan view of the fourth stack structure ST4 in the first connection region CNR1 is omitted in FIG. 6C, the fourth stack structure ST4 in the first connection region CNR1 has the shape of the third stack structure ST3 in the second connection region CNR2. The first electrode layer EL3 included in the third stack structure ST3 has a third recess region RC3 in the second connection region CNR2. The fourth electrode layer EL4 included in the fourth stack structure ST4 has a fourth recess region RC4 in the first connection region CNR1.

[0076] In the second connection region CNR2, the third electrode layers EL3 are respectively connected to the third cell contact plugs CC3. The third cell contact plugs CC3 are each connected to a third electrode connecting line (VPa_E3). In the first connection region CNR1, the second electrode layers EL2 are respectively connected to second cell contact plugs CC2. The fourth cell contact plugs CC4 are each connected to a fourth electrode connecting line (VPa_E4). The third and fourth electrode connecting wires (VPa_E3, VPa_E4) extend in the second direction D2. In the second memory chip 300, the third and fourth electrode connecting wires (VPa_E3, VPa_E4) are located at the same height as the first conductive pattern VPa. The second edge through-vias ETHV2 are each electrically connected to the third electrode connection wiring (VPa_E3).

[0077] Referring to FIG. 8, in the first and second connection regions CNR1 and CNR2, ends of the third stack structure ST3 protrude from the sides of the first stack structure ST1. In the first and second connection regions (CNR1, CNR2), the ends of the fourth stack structure ST4 protrude from the sides of the second stack structure ST2. The third and fourth electrode layers (EL3, EL4) are longer in the first direction D1 than the first and second electrode layers (EL1, EL2). The first and second stack structures (ST1, ST2) each have a first maximum width MAXW1 parallel to the first direction. The third and fourth stack structures (ST3, ST4) each have a second maximum width MAXW2 parallel to the first direction. The second maximum width MAXW2 is greater than the first maximum width MAXW1. The minimum widths parallel to the first direction of the third and fourth stack structures (ST3, ST4) are also greater than the first maximum width MAXW1. The rest of the configuration is the same or similar to that described above.

[0078] Referring to Figures 7A, 7B, and 8, the first electrode layer EL1 of the first stack structure ST1 of the first memory chip 200 is electrically connected to the first pass transistor PST1 of the first decoder circuit unit DCR1 by the first cell contact plug CC1, the first electrode connection wiring (VPa_E1), the first connection terminal 50a, and the logic connection terminal 150, respectively.

[0079] Referring to FIG. 8, the second electrode layer EL2 of the second stack structure ST2 of the first memory chip 200 is electrically connected to the second pass transistor PST2 of the second decoder circuit unit DCR2 by the second cell contact plug CC2, the second electrode connection wiring (VPa_E2), the first connection terminal 50a, and the logic connection terminal 150, respectively.

[0080] 7A, 7B, and 8, the third electrode layer EL3 of the third stack structure ST3 of the second memory chip 300 is electrically connected to the third pass transistor PST3 of the third decoder circuit unit DCR3 by the third cell contact plug CC3, the third electrode connection wiring (VPa_E3), the first connection terminal 50a, the second conductive pattern VPb, the second connection terminal 50b, the second edge through via ETHV2, and the logic connection terminal 150, respectively.

[0081] Referring to FIG. 8, the fourth electrode layer EL4 of the fourth stack structure ST4 of the second memory chip 300 is electrically connected to the fourth pass transistor PST4 of the fourth decoder circuit unit DCR4 by the fourth cell contact plug CC4, the fourth electrode connection wiring (VPa_E4), the first connection terminal 50a, the second conductive pattern VPb, the second connection terminal 50b, the first edge through via ETHV1, and the logic connection terminal 150, respectively.

[0082] FIG. 9A is a partial plan view showing a schematic configuration of the first memory chip of FIG. 1A according to another embodiment of the present invention, FIG. 9B is a partial plan view showing a schematic configuration of the second memory chip of FIG. 1A according to another embodiment of the present invention, FIG. 10 is a cross-sectional view cut along line B-B' of FIG. 9A or FIG. 9B according to another embodiment of the present invention, and FIG. 11 is a perspective view showing a detailed structure of FIG. 1A according to another embodiment of the present invention. In FIG. 11, the shape of the stack structure is simplified. Also, for clarity of the drawing, only one each of the plurality of contact plugs and through vias are shown in FIG. 11 as an example. A cross section taken along line AA' in FIG. 9A or FIG. 9B is the same as FIG. 7A.

[0083] 9A to 11, the first memory chip 200 further includes a first layer edge through via L1ETHV. In the second connection region CNR2 of the first memory chip 200, one end of the first electrode connection wiring (VPa_E1) contacts one of the first layer edge through-vias L1ETHV. The first layer edge through via L1ETHV is disposed within the second recess region RC2. The first layer edge through via L1ETHV is separated from the second edge through via ETHV2.

[0084] In the first connection region CNR1 of the first memory chip 200, one end of the second electrode connection wiring (VPa_E1) contacts another one of the first layer edge through-vias L1ETHV. The first layer edge through via L1ETHV is disposed in the first recess region RC1. The first layer edge through via L1ETHV is separated from the first edge through via ETHV1. The third electrode layer EL3 of the third stack structure ST3 in the second memory chip 300 has a third recess region RC3 in the first connection region CNR1. The width of the third recess region RC3 parallel to the first direction D1 is greater than the width of the first recess region RC1 parallel to the first direction D1 of the first electrode layer EL1 of the first stack structure ST1. The fourth electrode layer EL4 of the fourth stack structure ST4 has a fourth recess region RC4 in the second connection region CNR2. The width of the fourth recess region RC4 parallel to the first direction D1 is greater than the width of the second recess region RC2 of the second electrode layer EL2 of the second stack structure ST2 parallel to the first direction D1.

[0085] The second memory chip 300 further includes a second layer edge through via L2ETHV. In the second connection region CNR2 of the second memory chip 300, one end of the third electrode connection wiring (VPa_E3) contacts one of the second layer edge through-vias L2ETHV. The second layer edge through via L2ETHV is disposed in the fourth recess region RC4. The second-layer edge through-via L2ETHV is spaced apart from the third cell contact plug CC3. In the first connection region CNR1 of the second memory chip 300, one end of the fourth electrode connection wiring (VPa_E4) contacts another one of the second layer edge through-vias L2ETHV. The second-layer edge through via L2ETHV is disposed in the third recess region RC3. The rest of the configuration is the same or similar to that described above.

[0086] The first layer edge through via L1ETHV and the second layer edge through via L2ETHV exist to connect the electrode layers (EL1 to EL4) of the first to fourth stack structures (ST1 to ST4) to memory chips or wiring that are additionally arranged on the second memory chip 300. The first layer edge through vias L1ETHV and the second layer edge through vias L2ETHV can be used to modify the wiring connection relationship of a three-dimensional semiconductor memory device in various ways.

[0087] FIG. 12 is an oblique view showing a schematic configuration of a three-dimensional semiconductor memory device according to another embodiment of the present invention, FIG. 13A is a cross-sectional view taken along line A-A' of FIG. 12 according to another embodiment of the present invention, and FIG. 13B is a cross-sectional view taken along line B-B' of FIG. 12 according to another embodiment of the present invention.

[0088] 12, 13A, and 13B, the logic chip 100 includes first to sixth decoder circuit units (DCR1 to DCR6) and a page buffer circuit unit PB. The first to sixth decoder circuit units DCR1 to DCR6 and the page buffer circuit unit PB are spaced apart from each other in a first direction D1. The page buffer circuit unit PB is disposed in the center of the logic chip 100. The sixth decoder circuit unit DCR6 and the sixth decoder circuit unit DCR6 are separated from each other via the logic chip 100.

[0089] The fourth decoder circuit unit DCR4 is disposed between the sixth decoder circuit unit DCR6 and the page buffer circuit unit PB. The second decoder circuit unit DCR2 is disposed between the fourth decoder circuit unit DCR4 and the page buffer circuit unit PB. The third decoder circuit unit DCR3 is disposed between the fifth decoder circuit unit DCR5 and the page buffer circuit unit PB. The first decoder circuit unit DCR1 is disposed between the third decoder circuit unit DCR3 and the page buffer circuit unit PB.

[0090] As shown in FIG. 2B, the first to third memory chips 200, 300, and 400 include a first connection region CNR1 and a second connection region CNR2 spaced apart from each other in a first direction D1, and a cell array region CAR located therebetween. In this embodiment, the cell array region CAR overlaps with the page buffer circuit unit PB of the logic chip 100 . The first connection region CNR1 overlaps with the second, fourth, and sixth decoder circuit units (DCR2, DCR4, and DCR6). The second connection region CNR2 overlaps with the first, third, and fifth decoder circuit parts (DCR1, DCR3, and DCR5).

[0091] In the state of FIG. 8, third memory chip 400 is disposed on second memory chip 300 . The third memory chip 400 includes a fifth stack structure ST5 and a sixth stack structure ST6 spaced apart from each other in the second direction D2. The sixth stack structure ST6 has a shape obtained by rotating the fifth stack structure ST5 by 180 degrees. The fifth stack structure ST5 includes a fifth electrode layer EL5 and an inter-electrode layer insulating film 12 interposed therebetween. The sixth stack structure ST6 includes a sixth electrode layer EL6 and an inter-electrode layer insulating film 12 interposed therebetween.

[0092] The maximum width parallel to the first direction D1 of each of the fifth and sixth stack structures (ST5, ST6) is greater than the maximum width parallel to the first direction D1 of each of the third and fourth stack structures (ST3, ST4). The minimum width parallel to the first direction D1 of each of the fifth and sixth stack structures (ST5, ST6) is greater than the maximum width parallel to the first direction D1 of each of the third and fourth stack structures (ST3, ST4). In the first connection region CNR1, the fifth electrode layer EL5 of the fifth stack structure ST5 has a fifth recess region R5. In the second connection region CNR2, the sixth electrode layer EL6 of the sixth stack structure ST6 has a sixth recess region R6.

[0093] In the cell array region CAR, the fifth and sixth stack structures ST5 and ST6 are each penetrated by a plurality of cell vertical patterns VS. One end of the cell vertical pattern VS is connected by a third layer bit line L3BL. A fifth through-cell via CTHV5 penetrating the fifth stack structure ST5 is disposed between the cell vertical patterns VS. The fifth through-cell via CTHV5 is electrically connected to one of the third layer bit lines L3BL. A sixth through-cell via CTHV6 penetrating the sixth stack structure ST6 is disposed between the cell vertical patterns VS. The sixth through-cell via CTHV6 is electrically connected to one of the third layer bit lines L3BL.

[0094] In the second connection region CNR2, the fifth electrode layers EL5 are respectively connected to the fifth cell contact plugs CC5. The fifth cell contact plugs CC5 are each connected to a fifth electrode connecting line (VPa_E5). In the second connection region CNR2, the sixth electrode layers EL6 are respectively connected to the sixth cell contact plugs. The sixth cell contact plugs are each connected to a sixth electrode connecting wire (VPa_E6 in FIG. 15). The first memory chip 200 includes a first layer edge through via L1ETHV. A part of the first layer edge through via L1ETHV corresponds to the first and second edge through vias (ETHV1, ETHV2) described with reference to FIGS. 2A to 11. The second memory chip 300 includes second-level edge-through vias L2ETHV.

[0095] The first electrode layer EL1 of the first stack structure ST1 of the first memory chip 200 is electrically connected to the first pass transistor of the first decoder circuit unit DCR1 by a first cell contact plug CC1 and a first electrode connection wiring (VPa_E1). The first electrode layer EL2 of the second stack structure ST2 of the first memory chip 200 is electrically connected to the second pass transistor of the second decoder circuit unit DCR2 by a second cell contact plug and a second electrode connection wiring. The third electrode layer EL3 of the third stack structure ST3 of the second memory chip 300 is electrically connected to the third pass transistor of the third decoder circuit unit DCR3 by the third cell contact plug CC3, the third electrode connection wiring (VPa_E3), and a portion of the first layer edge through via L1ETHV.

[0096] The fourth electrode layer EL4 of the fourth stack structure ST4 of the second memory chip 300 is electrically connected to the fourth pass transistor of the fourth decoder circuit unit DCR4 by a fourth cell contact plug, a fourth electrode connection wiring, and a portion of the first layer edge through via L1ETHV, respectively. The fifth electrode layer EL5 of the fifth stack structure ST5 of the third memory chip 400 is electrically connected to the fifth pass transistor of the fifth decoder circuit unit DCR5 by a fifth cell contact plug CC5, a fifth electrode connection wiring (VPa_E5), a portion of the second layer edge through via L2ETHV, and a portion of the first layer edge through via L1ETHV. The sixth electrode layer EL6 of the sixth stack structure ST6 of the third memory chip 400 is electrically connected to the sixth pass transistor of the sixth decoder circuit unit DCR6 by a sixth cell contact plug, a sixth electrode connection wiring (VPa_E6), a portion of the second layer edge through via L2ETHV, and a portion of the first layer edge through via L1ETHV.

[0097] FIG. 14 is a perspective view of a three-dimensional semiconductor memory device according to still another embodiment of the present invention, and FIG. 15 is a cross-sectional view taken along line BB' of FIG. 14 according to still another embodiment of the present invention. The cross-sectional view taken along line AA' in FIG. 14 is the same as FIG. 13B.

[0098] 13B, 14, and 15, the first memory chip 200 includes a plurality of first layer edge through vias L1ETHV that penetrate the first and second stack structures (ST1, ST2), respectively. The second memory chip 300 includes a plurality of second layer edge through vias L2ETHV that penetrate the third and fourth stack structures (ST3, ST4), respectively. The third memory chip 400 includes a plurality of third layer edge through vias L3ETHV that penetrate the fifth and sixth stack structures (ST5, ST6), respectively. The first to third layer edge through vias (L1ETHV, L2ETHV, L3ETHV) exist to connect the first to sixth stack structures (ST1 to ST6) to memory chips or wiring additionally arranged on the third memory chip 400. The rest of the structure is the same or similar to that described with reference to FIGS.

[0099] FIG. 16 is a perspective view illustrating a schematic configuration of a three-dimensional semiconductor memory device according to still another embodiment of the present invention. With reference to FIG. 16, first to fourth memory chips (200, 300, 400, 500) are stacked in sequence on a logic chip 100. The logic chip 100 includes first to eighth decoder circuit units (DCR1 to DCR8) and a page buffer circuit unit PB.

[0100] The first to eighth decoder circuit units DCR1 to DCR8 and the page buffer circuit unit PB are spaced apart from each other in a first direction D1. The page buffer circuit unit PB is disposed in the center of the logic chip 100. The second, fourth, sixth and eighth decoder circuit units DCR2, DCR4, DCR6 and DCR8 are arranged in sequence farther from one side of the page buffer circuit unit PB. The first, third, fifth and seventh decoder circuit units DCR1, DCR3, DCR5 and DCR7 are arranged in sequence farther from the other side of the page buffer circuit unit PB.

[0101] As shown in FIG. 2B, each of the first to fourth memory chips 200, 300, 400, and 500 includes a first connection region CNR1 and a second connection region CNR2 spaced apart from each other in a first direction D1, and a cell array region CAR located therebetween. In this embodiment, the cell array region CAR overlaps with the page buffer circuit unit PB of the logic chip 100 . The first connection region CNR1 overlaps with the second, fourth, sixth, and eighth decoder circuit units (DCR2, DCR4, DCR6, and DCR8). The second connection region CNR2 overlaps with the first, third, fifth, and seventh decoder circuit units (DCR1, DCR3, DCR5, and DCR7).

[0102] The fourth memory chip 500 includes a seventh stack structure ST7 and an eighth stack structure ST8 spaced apart in the second direction D2. The minimum widths of the seventh and eighth stack structures (ST7, ST8) parallel to the first direction D1 are greater than the maximum widths of the fifth and sixth stack structures (ST5, ST6) parallel to the first direction D1. The first, third, fifth, seventh stack structures (ST1, ST3, ST5, ST7) include a recess region RC in the first connection region CNR1. The second, fourth, sixth, eighth stack structures (ST2, ST4, ST6, ST8) include a recess region RC in the second connection region CNR2. A part of the recess region RC corresponds to the first to sixth recess regions (RC1 to RC6) described with reference to FIGS. 2A to 15.

[0103] The fourth memory chip 500 further includes a fourth-layer edge through-via L4ETHV. The electrode layers of the first to eighth stack structures (ST1 to ST8) are electrically connected to the first to eighth decoder circuit units (DCR1 to DCR8), respectively, using cell contact plugs CC, first to fourth layer electrode connection wirings (VPa_L1 to VPa_L4), and edge through vias (L1ETHV to L4ETHV). The detailed shape of the cell contact plug CC is the same as or similar to the cell contact plugs (CC1 to CC6) described with reference to FIGS. 3A, 3B, 7A, and 13A. The detailed configurations of the edge through vias (L1ETHV to L4ETHV) are the same as or similar to the edge through vias ETHV1 and ETHV2 described with reference to FIGS. 3A, 7A, and 10.

[0104] FIG. 17 is a perspective view illustrating a schematic configuration of a three-dimensional semiconductor memory device according to still another embodiment of the present invention. With reference to FIG. 17, first to third memory chips (200, 300, 400) are stacked in sequence on a logic chip 100. The logic chip 100 includes first to sixth decoder circuit units (DCR1 to DCR6) and a page buffer circuit unit PB.

[0105] The page buffer circuit unit PB is disposed adjacent to the center of the logic chip 100. The fifth and sixth decoder circuit units DCR5 and DCR6 are adjacent to one side of the page buffer circuit unit PB. The fifth and sixth decoder circuit units (DCR5, DCR6) are arranged in parallel along the second direction D2. The third and fourth decoder circuit units DCR3 and DCR4 are spaced apart from the page buffer circuit unit PB. The third and fourth decoder circuit units DCR3 and DCR4 are arranged in parallel along the second direction D2. The first decoder circuit section DCR1 is disposed between the third decoder circuit section DCR3 and the page buffer circuit section PB. The second decoder circuit unit DCR2 is disposed between the fourth decoder circuit unit DCR4 and the page buffer circuit unit PB.

[0106] As shown in FIG. 2B, each of the first to third memory chips 200, 300, and 400 includes a first connection region CNR1 and a second connection region CNR2 spaced apart from each other in a first direction D1, and a cell array region CAR located therebetween. In this embodiment, the cell array region CAR overlaps with the page buffer circuit unit PB of the logic chip 100 . The first connection region CNR1 overlaps with the fifth and sixth decoder circuit units (DCR5, DCR6). The second connection region CNR2 overlaps with the first to fourth decoder circuit units (DCR1 to DCR4).

[0107] The width of the first and second stack structures (ST1, ST2) of the first memory chip 200 is the same as the width of the fifth and sixth stack structures (ST5, ST6) of the third memory chip 400. The maximum width of the third and fourth stack structures (ST3, ST4) of the second memory chip 300 is greater than the maximum width of the first and second stack structures (ST1, ST2) of the first memory chip 200. The third and fourth stack structures ST3 and ST4 of the second memory chip 300 protrude laterally from the first and second stack structures ST1 and ST2 of the first memory chip 200. In the first connection region CNR1, the ends of the first, third, and fifth stack structures (ST1, ST3, ST5) are aligned with each other.

[0108] The first to fourth stack structures (ST1 to ST4) all include a recess region RC in the first connection region CNR1. The fifth and sixth stack structures (ST5, ST6) do not have to have the recess region RC. The electrode layers of the first to sixth stack structures (ST1 to ST6) are electrically connected to the first to sixth decoder circuit units (DCR1 to DCR6), respectively, by using cell contact plugs CC and edge through vias (L1ETHV to L2ETHV).

[0109] FIG. 18 is a perspective view illustrating a schematic configuration of a three-dimensional semiconductor memory device according to still another embodiment of the present invention. With reference to FIG. 18, first to fourth memory chips (200, 300, 400, 500) are stacked in sequence on a logic chip 100. The logic chip 100 includes first to fourth decoder circuit units (DCR1 to DCR4) and a page buffer circuit unit PB. The page buffer circuit unit PB is disposed adjacent to the center of the logic chip 100. The second and fourth decoder circuit units DCR2 and DCR4 are arranged successively farther from one side of the page buffer circuit unit PB. The first and third decoder circuit units DCR1 and DCR3 are arranged successively farther from the other side of the page buffer circuit unit PB.

[0110] As shown in FIG. 2B, each of the first to fourth memory chips 200, 300, 400, and 500 includes a first connection region CNR1 and a second connection region CNR2 spaced apart from each other in a first direction D1, and a cell array region CAR located therebetween. The first connection region CNR1 overlaps with the second and fourth decoder circuit units (DCR2, DCR4). The second connection region CNR2 overlaps with the first and third decoder circuit units (DCR1, DCR3). The first and second stack structures (ST1, ST2) of the first memory chip 200 have the same structures as the fifth and sixth stack structures (ST5, ST6) of the third memory chip 400, respectively. The third and fourth stack structures (ST3, ST4) of the second memory chip 300 have the same structures as the seventh and eighth stack structures (ST7, ST8) of the fourth memory chip 500, respectively.

[0111] Using cell contact plugs CC, first and third layer electrode connection wiring (VPa_L1, VPa_L3), and first and second layer edge through vias (L1ETHV, L2ETHV), the first and fifth electrode layers (EL1, EL5) of the first and fifth stack structures (ST1, ST5) are commonly connected to the first decoder circuit unit DCR1. That is, the first and fifth stack structures (ST1, ST5) operate simultaneously as if they were one memory block. Using cell contact plugs CC, second and fourth layer electrode connection wiring (VPa_L2, VPa_L4), and first to third layer edge through vias (L1ETHV, L2ETHV, L3ETHV), the third and seventh electrode layers (EL3, EL7) of the third and seventh stack structures (ST3, ST7) are commonly connected to the third decoder circuit unit DCR3. That is, the third and seventh stack structures (ST3, ST7) operate simultaneously as if they were one memory block.

[0112] Similarly, the second and sixth electrode layers (EL2, EL6) of the second and sixth stack structures (ST2, ST6) are commonly connected to the second decoder circuit unit DCR2 using the cell contact plugs CC and the first and second layer edge through vias (L1ETHV, L2ETHV). That is, the second and sixth stack structures (ST2, ST6) operate simultaneously as if they were one memory block. Using cell contact plugs CC and the first to third layer edge through vias (L1ETHV, L2ETHV, L3ETHV), the fourth and eighth electrode layers (EL4, EL8) of the fourth and eighth stack structures (ST4, ST8) are commonly connected to the fourth decoder circuit unit DCR4. That is, the fourth and eighth stack structures (ST4, ST8) operate simultaneously as if they were one memory block.

[0113] In the semiconductor memory device of the present invention, one decoder circuit unit is connected to two stack structures at the same time, so that the number of decoder circuit units can be reduced, and the size of the logic chip 100 can be reduced. Furthermore, when additional memory chips are stacked on fourth memory chip 500 in FIG. 18, the stack structures of odd-numbered memory chips are connected to each other, and the stack structures of even-numbered memory chips are connected to each other.

[0114] FIG. 19 is a perspective view illustrating a schematic configuration of a three-dimensional semiconductor memory device according to still another embodiment of the present invention. With reference to FIG. 19, first to fourth memory chips (200, 300, 400, 500) are stacked in sequence on a logic chip 100. The logic chip 100 includes first to eighth decoder circuit units (DCR1 to DCR8) and a page buffer circuit unit PB. The page buffer circuit unit PB is disposed adjacent to the center of the logic chip 100.

[0115] The fourth and eighth decoder circuit units DCR4 and DCR8 are spaced apart from one side of the page buffer circuit unit PB and are arranged in parallel in the second direction D2. The second decoder circuit part DCR2 is disposed between the fourth decoder circuit part DCR4 and one side of the page buffer circuit part PB. A sixth decoder circuit unit DCR6 is disposed between the eighth decoder circuit unit DCR8 and one side of the page buffer circuit unit PB. The third and seventh decoder circuit units DCR3 and DCR7 are spaced apart from the other side of the page buffer circuit unit PB and are arranged in parallel in the second direction D2. The first decoder circuit unit DCR1 is disposed between the third decoder circuit unit DCR3 and the other side of the page buffer circuit unit PB. A fifth decoder circuit unit DCR5 is disposed between the seventh decoder circuit unit DCR7 and the other side of the page buffer circuit unit PB.

[0116] As shown in FIG. 2B, each of the first to fourth memory chips 200, 300, 400, and 500 includes a first connection region CNR1 and a second connection region CNR2 spaced apart from each other in a first direction D1, and a cell array region CAR located therebetween. The first connection region CNR1 overlaps with the second, fourth, sixth, and eighth decoder circuit units (DCR2, DCR4, DCR6, and DCR8). The second connection region CNR2 overlaps with the first, third, fifth, and seventh decoder circuit units (DCR1, DCR3, DCR5, and DCR7). The first, third, fifth, seventh stack structures (ST1, ST3, ST5, ST7) have a recess region RC in the first connection region CNR1. The second, fourth, sixth, eighth stack structures (ST2, ST4, ST6, ST8) have a recess region RC in the second connection region CNR2. The first to eighth stack structures (ST1 to ST8) are connected to the first to eighth decoder circuit units (DCR1 to DCR8), respectively, by using cell contact plugs CC and edge through vias (L1ETHV to L3ETHV).

[0117] FIG. 20 is a partial cross-sectional view illustrating a schematic configuration of a three-dimensional semiconductor memory device according to an embodiment of the present invention. With reference to FIG. 20, first to fourth memory chips (200, 300, 400, 500) are stacked in sequence on a logic chip 100. The first memory chip 200 includes a first cell through-via CTHV1 and a first layer edge through-via L1ETHV. The second memory chip 300 includes a second cell through-via CTHV2 and a second layer edge through-via L2ETHV. The third memory chip 400 includes a third cell through-via CTHV3 and a third layer edge through-via L3ETHV.

[0118] As shown in FIG. 20, if no additional memory chips are disposed on the fourth memory chip 500 or no additional electrical connections are required on the top surface of the fourth memory chip 500, the fourth memory chip 500 located on the top layer may not include through-cell vias and through-edge vias. The rest of the configuration is the same or similar to that described above.

[0119] FIG. 21 is a perspective view illustrating a schematic configuration of a three-dimensional semiconductor memory device according to still another embodiment of the present invention. With reference to FIG. 21, first to third memory chips (200, 300, 400) are stacked in sequence on a logic chip 100. The logic chip 100 includes first to sixth decoder circuit units (DCR1 to DCR6) and a page buffer circuit unit PB. The page buffer circuit unit PB is disposed adjacent to the center of the logic chip 100.

[0120] The second, fourth and sixth decoder circuit units DCR2, DCR4 and DCR6 are adjacent to one side of the page buffer circuit unit PB. The second decoder circuit unit DCR2 is located under one end of the second stack structure ST2. The second, fourth, and sixth decoder circuit units DCR2, DCR4, and DCR6 are sequentially arranged in parallel along a direction opposite to the second direction D2. The first, third and fifth decoder circuit units DCR1, DCR3 and DCR5 are adjacent to the other side of the page buffer circuit unit PB. The first, third, and fifth decoder circuit units DCR1, DCR3, and DCR5 are sequentially arranged in parallel along the second direction D2.

[0121] As shown in FIG. 2B, each of the first to third memory chips 200, 300, and 400 includes a first connection region CNR1 and a second connection region CNR2 spaced apart from each other in a first direction D1, and a cell array region CAR located therebetween. The first connection region CNR1 overlaps with the second, fourth, and sixth decoder circuit units (DCR2, DCR4, and DCR6). The second connection region CNR2 overlaps with the first, third, and fifth decoder circuit parts (DCR1, DCR3, and DCR5). The first, third, and fifth stack structures (ST1, ST3, ST5) have a recess region RC in the first connection region CNR1 and have the same shape as each other. The second, fourth, and sixth stack structures (ST2, ST4, ST6) have a recess region RC in the second connection region CNR2 and have the same shape as each other.

[0122] The second, fourth and sixth stack structures (ST2, ST4 and ST6) have structures in which the first, third and fifth stack structures (ST1, ST3 and ST5) are rotated 180°, respectively. The first to sixth stack structures (ST1 to ST6) are connected to the first to sixth decoder circuit units (DCR1 to DCR6), respectively, by using cell contact plugs CC and edge through vias (L1ETHV to L2ETHV). At this time, first layer edge through vias L1ETHV for connecting different stack structures (eg, ST1, ST3) to each other are simultaneously disposed inside one recess region RC.

[0123] FIG. 22A is an oblique view showing a schematic configuration of a three-dimensional semiconductor memory device according to another embodiment of the present invention, FIG. 22B is a plan view of a logic chip included in the three-dimensional semiconductor memory device of FIG. 22A, FIG. 22C is a plan view of first and third memory chips included in the three-dimensional semiconductor memory device of FIG. 22A, FIG. 22D is a plan view of second and fourth memory chips included in the three-dimensional semiconductor memory device of FIG. 22A, FIG. 22E is an enlarged plan view of the "P4" portion of FIG. 22C, and FIG. 22F is an enlarged plan view of the first decoder circuit portion of FIG. 22B.

[0124] 22A to 22F, first to fourth memory chips (200, 300, 400, 500) are stacked in sequence on logic chip 100. The logic chip 100 includes first to fourth decoder circuit units (DCR1 to DCR4) and a page buffer circuit unit PB. The page buffer circuit unit PB is disposed adjacent to the center of the logic chip 100. The first and fourth decoder circuit units DCR1 and DCR4 are adjacent to one side of the page buffer circuit unit PB. The first and fourth decoder circuit units DCR1 and DCR4 are arranged in parallel in the second direction D2. The second and third decoder circuit units DCR2 and DCR3 are adjacent to the other side of the page buffer circuit unit PB. The second and third decoder circuit units DCR2 and DCR3 are arranged in parallel in a direction opposite to the second direction D2.

[0125] As shown in FIG. 2B, each of the first to fourth memory chips 200, 300, 400, and 500 includes a first connection region CNR1 and a second connection region CNR2 spaced apart from each other in a first direction D1, and a cell array region CAR located therebetween. The first connection region CNR1 overlaps with the first and fourth decoder circuit units (DCR1, DCR4). The second connection region CNR2 overlaps with the second and third decoder circuit units (DCR2, DCR3).

[0126] The first electrode layer EL1 of the first stack structure ST1 of the first memory chip 200 is electrically connected to the first decoder circuit unit DCR1 by the first cell contact plug CC1 and the first layer (VPa_L1). The fifth electrode layer EL5 of the fifth stack structure ST5 of the third memory chip 400 is electrically connected to the first decoder circuit unit DCR1 by the fifth cell contact plug CC5, the third layer (VPa_L3), the second layer edge through via L2ETHV and the first layer edge through via L1ETHV. Similarly, the second electrode layer EL2 of the second stack structure ST2 of the first memory chip 200 and the sixth electrode layer EL6 of the sixth stack structure ST6 of the third memory chip 400 are electrically connected to the second decoder circuit unit DCR2.

[0127] The fourth electrode layer EL4 of the fourth stack structure ST4 of the second memory chip 300 is electrically connected to the fourth decoder circuit unit DCR4 by the fourth cell contact plug CC4, the second layer (VPa_L2) and the first layer edge through-via L1ETHV. The eighth electrode layer EL8 of the eighth stack structure ST8 of the fourth memory chip 500 is electrically connected to the fourth decoder circuit unit DCR4 by the eighth cell contact plug CC8, the fourth layer (VPa_L4), the third layer edge through via L3ETHV, the second layer edge through via L2ETHV, and the first layer edge through via L1ETHV. Similarly, the third electrode layer EL3 of the third stack structure ST3 of the second memory chip 300 and the seventh electrode layer EL7 of the seventh stack structure ST7 of the fourth memory chip 500 are electrically connected to the third decoder circuit unit DCR3.

[0128] 22C, 22D, and 22E, the electrode connection wirings (VPa_L1 to VPa_L4) connect the electrode layers (EL1 to EL8) belonging to each stack structure (ST1 to ST8) to the edge through vias (L1ETHV to L4ETHV), respectively. The planar shapes of the electrode connection wirings (VPa_L1 to VPa_L4) can be various, such as "I" shape, "L" shape, "C" shape, "N" shape, "W" shape, etc., as required. For example, referring to FIG. 22E and FIG. 22A, the first electrode layer EL1 includes the first to fourth string selection lines (SSL1 to SSL4) closest to the logic chip 100. In FIG. The first to fourth string selection lines SSL1 to SSL4 are spaced apart from each other in the second direction D2.

[0129] The first electrode layer EL1 includes the ground selection line GSL that is farthest from the logic chip 100. The first electrode layer EL1 includes word lines (WL0 to WLn) located between the ground selection line GSL and the string selection lines (SSL1 to SSL4). The string selection lines (SSL1 to SSL4), the word lines (WL0 to WLn), and the ground selection line GSL are each connected in a 1:1 relationship to the first layer edge through-vias L1ETHV by the first layer electrode connection wiring (VPa_L1).

[0130] Referring to FIG. 22F, the first decoder circuit section DCR1 includes, for example, eleventh to nineteenth pass transistors (PST11 to PST19). An active area AR is defined by an isolation film 105 disposed on a logic substrate (103 in FIG. 3A). Eleventh to nineteenth pass selection transistors (PST11 to PST19) are arranged in the active region AR, respectively. In the first decoder circuit portion DCR1, source / drain regions are arranged in active regions AR on one side of the eleventh to nineteenth pass transistors PST11 to PST19, respectively. Then, first to ninth peripheral contact plugs (PCT1 to PCT9) are disposed on the source / drain regions, respectively.

[0131] Referring to Figures 22E and 22F, the first string selection line SSL1 is electrically connected to the source / drain region of the 11th pass transistor PST11 by one of the first cell contact plugs CC1, one of the first layer electrode connecting wirings (VPa_L1), and the first peripheral contact plug PCT1. Similarly, the second to fourth string selection lines (SSL2 to SSL4) are electrically connected to the source / drain regions of the twelfth to fourteenth pass transistors (PST12 to PST14) by the second to fourth peripheral contact plugs (PCT2 to PCT4) in a 1:1 correspondence, respectively. Similarly, the 0th to nth word lines (WL0 to WLn) are electrically connected to the source / drain regions of the 15th to 18th pass transistors (PST15 to PST18) by the 5th to 8th peripheral contact plugs (PCT5 to PCT8) in a 1:1 correspondence, respectively. Similarly, the ground select line GSL is electrically connected to the source / drain region of the nineteenth pass transistor PST19 by a ninth peripheral contact plug PCT9.

[0132] 22C, 22D, and 22E, the fifth electrode layer EL5 also includes string selection lines (SSL1 to SSL4), word lines (WL0 to WLn), and a ground selection line GSL. The fifth electrode layer EL5 (or the string selection lines (SSL1 to SSL4), word lines (WL0 to WLn), and ground selection line GSL included in the fifth stack structure ST5) are respectively connected 1:1 to the first to ninth peripheral contact plugs (PCT1 to PCT9) of the first decoder circuit unit DCR1 by the fifth cell contact plug CC5, the third layer electrode connection wiring (VPa_L3), and the third edge through via L3ETHV. Similarly, the second to eighth electrode layers EL2 to EL8 each include string selection lines SSL1 to SSL4, word lines WL0 to WLn, and a ground selection line GSL.

[0133] The string selection lines (SSL1 to SSL4), word lines (WL0 to WLn), and ground selection line GSL belonging to the second and sixth electrode layers (EL2, EL6) are electrically connected in a 1:1 manner to the source / drain regions of the pass transistors arranged in the second decoder circuit unit DCR2. The string selection lines (SSL1 to SSL4), word lines (WL0 to WLn), and ground selection line GSL belonging to the third and seventh electrode layers (EL3, EL7) are electrically connected in a 1:1 manner to the source / drain regions of the pass transistors arranged in the third decoder circuit unit DCR3. The string selection lines (SSL1 to SSL4), word lines (WL0 to WLn), and ground selection line GSL belonging to the fourth and eighth electrode layers (EL4, EL8) are electrically connected in a 1:1 manner to the source / drain regions of the pass transistors arranged in the fourth decoder circuit unit DCR4.

[0134] FIG. 23 is a perspective view illustrating a schematic configuration of a three-dimensional semiconductor memory device according to still another embodiment of the present invention. 23, first to fourth memory chips (200, 300, 400, 500) are stacked in sequence on a logic chip 100. The logic chip 100 includes first to eighth decoder circuit units (DCR1 to DCR8) and a page buffer circuit unit PB. The page buffer circuit unit PB is disposed adjacent to the center of the logic chip 100.

[0135] The second, fourth, sixth and eighth decoder circuit units DCR2, DCR4, DCR6 and DCR8 are adjacent to one side of the page buffer circuit unit PB. The second, fourth, sixth, and eighth decoder circuit units (DCR2, DCR4, DCR6, and DCR8) are sequentially arranged in parallel in a direction opposite to the second direction D2. The first, third, fifth and seventh decoder circuit units (DCR1, DCR3, DCR5 and DCR7) are adjacent to the other side of the page buffer circuit unit PB. The first, third, fifth and seventh decoder circuit units (DCR1, DCR3, DCR5 and DCR7) are sequentially arranged in parallel in the second direction D2.

[0136] As shown in FIG. 2B, each of the first to fourth memory chips 200, 300, 400, and 500 includes a first connection region CNR1 and a second connection region CNR2 spaced apart from each other in a first direction D1, and a cell array region CAR located therebetween. The first connection region CNR1 overlaps with the second, fourth, sixth, and eighth decoder circuit units (DCR2, DCR4, DCR6, and DCR8). The second connection region CNR2 overlaps with the first, third, fifth, and seventh decoder circuit units (DCR1, DCR3, DCR5, and DCR7). The first to eighth stack structures (ST1 to ST8) are electrically connected to the first to eighth decoder circuit units (DCR1 to DCR8), respectively, by utilizing cell contact plugs CC and edge through vias (L1ETHV to L3ETHV).

[0137] 24 and 25 are cross-sectional views illustrating a schematic configuration of a three-dimensional semiconductor memory device according to an embodiment of the present invention. 24, first to fourth memory chips (200, 300, 400, 500) are stacked in sequence on a logic chip 100. The logic chip 100 includes a plurality of page buffer circuit units that are different from one another. One of the page buffer circuit units is a first page buffer circuit unit PB1. The first page buffer circuit section PB1 is different from the other page buffer circuit sections. The first memory chip 200 includes a first through-cell via CTHV1 that penetrates the first stack structure ST1. The second memory chip 300 includes a third through-cell via CTHV3 that penetrates the third stack structure ST3. The third memory chip 400 includes a fifth through-cell via CTHV5 that penetrates the fifth stack structure ST5. The fourth memory chip 500 includes a seventh through-cell via CTHV7 that penetrates the seventh stack structure ST7.

[0138] The first, third, fifth, and seventh through-cell vias (CTHV1, CTHV3, CTHV5, and CTHV7) vertically overlap one another and are electrically connected to one another. The first, third, fifth, and seventh through-cell vias (CTHV1, CTHV3, CTHV5, and CTHV7) are electrically connected to the bit line selection transistors PTR of the first page buffer circuit unit of the logic chip 100. The seventh through-cell via CTHV7 is connected to a fourth bit line connecting wiring BLCP4 that is electrically connected to one of the fourth layer bit lines L4BL. The third through-cell via CTHV3 is connected to a second bit line connecting wiring BLCP2 that is electrically connected to one of the second layer bit lines L2BL. However, the first through-cell via CTHV1 connected to the third through-cell via CTHV3 does not have to be electrically connected to the first layer bit line L1BL. Furthermore, the fifth through cell via CTHV5 connected to the seventh through cell via CTHV7 does not have to be electrically connected to the third layer bit line L3BL.

[0139] In the semiconductor memory device according to this embodiment, bit lines of the second memory chip 300 and the fourth memory chip 500 are connected to a first page buffer circuit unit PB1. The bit lines of the first and third memory chips 200 and 400 are not connected to the first page buffer circuit unit PB1, but are connected to a page buffer circuit unit different from the first page buffer circuit unit PB1.

[0140] Also, referring to FIG. 25, only the seventh through-cell via CTHV7 of the fourth memory chip 500 is electrically connected to any one of the fourth layer bit lines L4BL. The first, third, fifth and fourth through-cell vias (CTHV1, CTHV3, CTHV5) connected to the seventh through-cell via CTHV7 are not connected to the first to third layer bit lines (L1BL, L2BL, L3BL). That is, only the fourth layer bit line L4BL of the fourth memory chip 500 is electrically connected to the first page buffer circuit unit PB1. The bit lines of the first to third memory chips (200, 300, 400) are not connected to the first page buffer circuit unit PB1, but are each connected to a page buffer circuit unit different from the first page buffer circuit unit PB1. As shown in Figures 24 and 25, when multiple memory chips are stacked, the connections between the bit lines can be separated to reduce the total resistance of each bit line and reduce the parasitic capacitance between the bit lines, thereby improving the performance of the semiconductor memory device.

[0141] FIG. 26 is a cross-sectional view taken along line CC' of FIG. 2B or FIG. 2C according to another embodiment of the present invention. Referring to FIG. 26, each of the first to fourth stack structures (SST1 to SST4) includes a first sub-stack structure SBST1 and a second sub-stack structure SBST2. The second substack structure SBST2 is closer to the source layer SCL than the first substack structure SBST1. The first substack structure SBST1 is closer to the logic chip 100 than the second substack structure SBST2. Adjacent to the boundary between the first substack structure SBST1 and the second substack structure SBST2, the sidewall of the vertical pattern (VS, CDVS, EDVS) has an inflection point SIP. In addition, the sidewall of the gate insulating film GO also has an inflection point adjacent to the boundary between the first substack structure SBST1 and the second substack structure SBST2. The rest of the structure is the same or similar to that described with reference to FIG. 3C.

[0142] FIG. 27 is a perspective view showing a schematic configuration of a three-dimensional semiconductor memory device according to still another embodiment of the present invention, and FIG. 28 is a cross-sectional view taken along line AA' of FIG. 27 and 28, a first semiconductor chip 100a, a second semiconductor chip 200a, and a third semiconductor chip 300a are stacked in sequence. The first semiconductor chip 100a, the second semiconductor chip 200a, and the third semiconductor chip 300a are bonded to one another. The first semiconductor chip 100a is electrically connected to the second semiconductor chip 200a. However, in this embodiment, the second semiconductor chip 200a is not electrically connected to the third semiconductor chip 300a.

[0143] The first semiconductor chip 100a corresponds to the logic chip 100 described above. The first semiconductor chip 100a includes a first decoder circuit unit DCR1, a first page buffer circuit unit PB1, and a second decoder circuit unit DCR2 arranged in parallel in a first direction D1. The first decoder circuit section DCR1 includes a plurality of first pass transistors PST1. The second decoder circuit section DCR2 includes a plurality of second pass transistors PST2. The first page buffer circuit unit PB1 includes a plurality of first bit line selection transistors PTR1.

[0144] The second semiconductor chip 200a corresponds to the first memory chip 200 described above. The second semiconductor chip 200a includes a first stack structure ST1 and a second stack structure ST2 that are spaced apart from each other in the second direction and arranged in parallel. The first stack structure ST1 includes a first electrode layer EL1 that is stacked. The second stack structure ST2 includes a stacked second electrode layer EL2. The ends of the first stack structure ST1 and the second stack structure ST2 have a stepped shape, and become farther away from the first semiconductor chip 100a in the first direction D1. The ends of the first electrode layer EL1 of the first stack structure ST1 are electrically connected to the first pass transistor PST1 of the first decoder circuit unit DCR1 by the first cell contact plug CC1, the first conductive pattern VPa, the logic connection terminal 150, etc. The ends of the second electrode layer EL2 of the second stack structure ST2 are electrically connected to the second pass transistor PST2 of the second decoder circuit unit DCR2 by the second cell contact plug CC2, the first conductive pattern VPa, the logic connection terminal 150, etc.

[0145] The first electrode layer EL1 is penetrated by a first through-cell via CTHV1. The second electrode layer EL2 is penetrated by a second through-cell via CTHV2. The first layer bit line L1BL is connected to the first and second through-cell vias CTHV1 and CTHV2. The first layer bit line L1BL is electrically connected to the first bit line selection transistor PTR1 of the first page buffer circuit unit PB1 by the first conductive pattern VPa and the logic connection terminal 150, etc. The third semiconductor chip 300a has a COP (Cell on Peri) structure in which a memory cell array is arranged on a peripheral circuit portion. Specifically, the third semiconductor chip 300a includes a third substrate 301, a third decoder circuit unit DCR3, a second page buffer circuit unit PB2, a fourth decoder circuit unit DCR4 arranged in parallel along the first direction D1 on the third substrate 301, and a third stack structure ST3 and a fourth stack structure ST4 arranged above them and spaced apart in the second direction D2.

[0146] The third substrate 301 is preferably a silicon single crystal substrate or a silicon on insulator (SOI) substrate. A third device isolation layer 301 is disposed on the third substrate 301 to define an active region. The third substrate 301 includes a third pass transistor PST3, a fourth pass transistor PST4, and a second bit line select transistor PTR2. The third substrate 301 is covered with a circuit insulating film 307 . The circuit insulating film 307 may have a single film or a multi-film structure of at least one selected from a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and a porous insulating film. A multi-layer third wiring 309 is disposed in the circuit insulating film 307 . The third pass transistor PST3 and a part of the third wiring 309 configure a third decoder circuit section DCR3. The fourth pass transistor PST4 and another part of the third wiring 309 constitute a fourth decoder circuit section DCR4. The second bit line selection transistor PTR2 and another part of the third wiring 309 constitute a second page buffer circuit unit PB2.

[0147] The third stack structure ST3 includes a stacked third electrode layer EL3. The fourth stack structure ST4 includes a fourth electrode layer EL4 that is stacked. The ends of the third stack structure ST3 and the fourth stack structure ST4 have a stepped shape, and become farther away from the first semiconductor chip 100a in the first direction D1. The ends of the third electrode layer EL3 of the third stack structure ST3 are each electrically connected to the third pass transistor PST3 of the third decoder circuit unit DCR3 by a third cell contact plug CC3, a second layer electrode connection wiring (VPa_L2), a second layer edge through via L2ETHV, and a third wiring 309. The ends of the fourth electrode layer EL4 of the fourth stack structure ST4 are each electrically connected to the fourth pass transistor PST4 of the fourth decoder circuit unit DCR4 by a fourth cell contact plug CC4, a second layer electrode connection wiring (VPa_L2), a second layer edge through via L2ETHV, and a third wiring 309.

[0148] The third electrode layer EL3 is penetrated by a third through-cell via CTHV3. The fourth electrode layer EL4 is penetrated by a fourth through-cell via CTHV4. The second layer bit line L2BL is connected to the third and fourth through-cell vias CTHV3 and CTHV4. The second layer bit line L2BL is electrically connected to the second bit line selection transistor PTR2 of the second page buffer circuit unit PB2 by the third and fourth through cell vias (CTHV3, CTHV4) and the third wiring 309. The rest of the configuration is the same or similar to that described above.

[0149] FIG. 29 is a perspective view illustrating a schematic configuration of a three-dimensional semiconductor memory device according to still another embodiment of the present invention. With reference to FIG. 29, first to fifth semiconductor chips (100a to 500a) are stacked in sequence. The first to fifth semiconductor chips (100a to 500a) are bonded to each other. The second and third semiconductor chips (200a, 300a) are electrically connected to the first semiconductor chip 100a. The fourth semiconductor chip 400a is electrically connected to the fifth semiconductor chip 500a. There may be no electrical connection between the third semiconductor chip 300a and the fourth semiconductor chip 400a.

[0150] The first semiconductor chip 100a corresponds to the logic chip 100 described above. The first semiconductor chip 100a includes first and fourth decoder circuit units (DCR1, DCR4) arranged on one side of the first page buffer circuit unit PB1, and second and third decoder circuit units (DCR2, DCR3) arranged on the other side of the first page buffer circuit unit PB1. The second to fourth semiconductor chips (200a, 300a, 400a) correspond to the first to third memory chips (200, 300, 400) described above. The second semiconductor chip 200a includes first and second stack structures ST1 and ST2 spaced apart from each other in the second direction D2. The third semiconductor chip 300a includes third and fourth stack structures ST3 and ST4 spaced apart from each other in the second direction D2. The fourth semiconductor chip 400a includes fifth and sixth stack structures ST5 and ST6 spaced apart from each other in the second direction D2.

[0151] The fifth semiconductor chip 500a has a cell on peri (COP) structure, similar to the third semiconductor chip 300a described with reference to FIGS. The fifth semiconductor chip 500a includes a second page buffer circuit unit PB2 arranged on a fifth substrate 501, fifth and eighth decoder circuit units (DCR5, DCR8) arranged on one side of the second page buffer circuit unit PB2, and sixth and seventh decoder circuit units (DCR6, DCR7) arranged on the other side of the second page buffer circuit unit PB2. The semiconductor chip 500a also includes seventh and eighth stack structures ST7 and ST8 disposed on the second page buffer circuit unit PB2 and spaced apart from each other in the second direction D2.

[0152] The first electrode layer EL1 included in the first stack structure ST1 is connected to the first decoder circuit unit DCR1 by a first cell contact plug CC1 and a first layer electrode connecting wiring VPa_L1. The second electrode layer EL2 included in the second stack structure ST2 is connected to the second decoder circuit unit DCR2 by a second cell contact plug CC2 and a first layer electrode connecting wiring VPa_L1. The third electrode layer EL3 included in the third stack structure ST3 is connected to the third decoder circuit unit DCR3 by a third cell contact plug CC3, a second layer electrode connection wiring (VPa_L2), and a first layer edge through-via L1ETHV. The fourth electrode layer EL4 included in the fourth stack structure ST4 is connected to the fourth decoder circuit unit DCR4 by a fourth cell contact plug CC4, a second layer electrode connection wiring (VPa_L2), and a first layer edge through-via L1ETHV.

[0153] The fifth electrode layer EL5 included in the fifth stack structure ST5 is connected to the fifth decoder circuit unit DCR5 by a fifth cell contact plug CC5, a third layer electrode connection wiring (VPa_L3), a third layer edge through via L3ETHV, and a fourth layer edge through via L4ETHV. The sixth electrode layer EL6 included in the sixth stack structure ST6 is connected to the sixth decoder circuit unit DCR6 by a sixth cell contact plug CC6, a third layer electrode connection wiring (VPa_L3), a third layer edge through via L3ETHV, and a fourth layer edge through via L4ETHV. The seventh electrode layer EL7 included in the seventh stack structure ST7 is connected to the seventh decoder circuit unit DCR7 by a seventh cell contact plug CC7, a fourth-layer electrode connection wiring (VPa_L4), and a fourth-layer edge through-via L4ETHV. The eighth electrode layer EL8 included in the eighth stack structure ST8 is connected to the eighth decoder circuit unit DCR8 by an eighth cell contact plug CC8, a fourth layer electrode connection wiring (VPa_L4), and a fourth layer edge through via L4ETHV. The rest of the structure is the same or similar to that described above.

[0154] In the three-dimensional semiconductor memory device described with reference to FIGS. 1A to 25, logic chip 100 may be referred to as a peripheral circuit portion or a peripheral circuit region. The memory chips may each be referred to as a memory portion or a memory region. In the three-dimensional semiconductor memory device described with reference to FIGS. 1A to 25, the logic chip 100 and the first memory chip 200 may belong to one semiconductor chip as a COP structure. An example of this will be described with reference to FIGS.

[0155] 30 and 31 are partial cross-sectional views illustrating a schematic configuration of a three-dimensional semiconductor memory device according to still another embodiment of the present invention. Referring to FIG. 30, a first semiconductor chip 100a, a second semiconductor chip 200a, and a third semiconductor chip 300a are stacked in sequence. The first semiconductor chip 100a, the second semiconductor chip 200a, and the third semiconductor chip 300a are bonded to one another. The first semiconductor chip 100a, the second semiconductor chip 200a, and the third semiconductor chip 300a are electrically connected to each other.

[0156] The first semiconductor chip 100a has a structure including the logic chip 100 and the first memory chip 200 described with reference to FIG. 22A. The first semiconductor chip 100a has a cell on peri (COP) structure. Specifically, the first semiconductor chip 100a includes a first substrate 103a, a first decoder circuit unit DCR1 arranged in parallel along a first direction D1 on the first substrate 103a, a page buffer circuit unit PB, a third decoder circuit unit DCR3, and a first stack structure ST1 arranged on top of them. Although not shown in the figure, the first semiconductor chip 100a also includes second and fourth decoder circuit units (DCR2, DCR4) and a second stack structure ST2. The decoder circuits (DCR1 to DCR4) are covered with a circuit insulating film 107a.

[0157] The second semiconductor chip 200a and the third semiconductor chip 300a correspond to the second memory chip 300 and the third memory chip 400, respectively, described with reference to FIG. 22A. The stack structures (ST1 to ST6) included in the first to third semiconductor chips (100a, 200a, 300a) both include recess regions RC as shown in FIG. 22A. However, the first to sixth stack structures (ST1 to ST6) in FIG. 30 have structures that are inverted from the first to sixth stack structures (ST1 to ST6) in FIG. 22A. That is, the ends of the first to sixth stack structures (ST1 to ST6) in FIG. 30 have a staircase shape, and the upper surfaces of the ends of the first to sixth stack structures (ST1 to ST6) become closer to the first substrate 103a in the first direction D1.

[0158] In the three-dimensional semiconductor memory device of FIG. 31, the second semiconductor chip 200a and the third semiconductor chip 300a in the structure of FIG. 30 are turned upside down. The rest of the structure is the same as in FIG. Looking at the "P5" portion of Figures 30 and 31, it can be seen that one of the first electrode layers EL1 and one of the fifth electrode layers EL5 are commonly electrically connected to one of the first pass transistors PST1. When looking at the "P6" portion in FIG. 30 and FIG. 31, it can be seen that one of the third electrode layers EL3 is electrically connected to one of the third transistors PST3. 30 and 31, the connection relationship of the stack structures (ST1 to ST6) is the same as that in FIG. 22, except for the seventh and eighth stack structures (ST7, ST8). In the three-dimensional semiconductor memory device of FIG. 30, the first to third semiconductor chips (100a, 200a, 300a) may belong to one semiconductor chip. An example of this will be described with reference to FIG.

[0159] FIG. 32 is a partial cross-sectional view illustrating a schematic configuration of a three-dimensional semiconductor memory device according to still another embodiment of the present invention. 32, a semiconductor chip 100b includes a first substrate 103a, a first decoder circuit unit DCR1, a page buffer circuit unit PB, and a third decoder circuit unit DCR3 arranged in parallel along a first direction D1 on the first substrate 103a. Although not shown in the figure, the semiconductor chip 100b also includes second and fourth decoder circuit units (DCR2, DCR4). The decoder circuits (DCR1 to DCR4) are covered with a circuit insulating film 107a. A first stack structure ST1, a third stack structure ST3, and a fifth stack structure ST5 are stacked in this order on the circuit insulating film 107a. Although not shown, first, third, and fifth stack structures (ST1, ST3, and ST5) and second, fourth, and sixth stack structures (ST2, ST4, and ST6) spaced apart from each other in the second direction D2 are sequentially stacked on the circuit insulating film 107a.

[0160] The ends of the first, third and fifth stack structures (ST1, ST3 and ST5) are penetrated by first layer, second layer and third layer edge through vias (L1ETHV, L2ETHV and L3ETHV), respectively. First, second and third layer electrode connection wiring (VPa_L1, VPa_L2, VPa_L3) are arranged on the first, third and fifth stack structures (ST1, ST3, ST5), respectively, to connect the first, third and fifth cell contact plugs (CC1, CC3, CC5) to portions of the first, second and third layer edge through vias (L1ETHV, L2ETHV, L3ETHV). In the cell array region CAR, the first, third and fifth stack structures (ST1, ST3 and ST5) are penetrated by the first, third and fifth cell through vias (CTHV1, CTHV3 and CTHV5), respectively. The first, third and fifth cell through-vias (CTHV1, CTHV3 and CTHV5) are respectively connected to the first, second and third layer bit lines (L1BL, L2BL and L3BL) arranged on the first, third and fifth stack structures (ST1, ST3 and ST5).

[0161] Between the first, third and fifth stack structures (ST1, ST3 and ST5) there is an inter-stack insulating film STL. The insulating film STL between the stacks may have a single-film or multi-film structure of at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. Connection via plugs CVA are disposed in the insulating film STL between the stacks to electrically connect the first layer, second layer, and third layer edge through vias (L1ETHV, L2ETHV, L3ETHV). Furthermore, a part of the connection via plug CVA electrically connects the first, third, and fifth through-cell vias (CTHV1, CTHV3, CTHV5). The rest of the structure is the same as or similar to that described with reference to FIG.

[0162] FIG. 33 is a partial cross-sectional view illustrating a schematic configuration of a three-dimensional semiconductor memory device according to still another embodiment of the present invention. Referring to FIG. 33, a first semiconductor chip 100a, a second semiconductor chip 200a, and a third semiconductor chip 300a are stacked in sequence. The first semiconductor chip 100a, the second semiconductor chip 200a, and the third semiconductor chip 300a are bonded to one another. The first semiconductor chip 100a and the second semiconductor chip 200a are electrically connected to each other but are insulated from the third semiconductor chip 300a.

[0163] The first semiconductor chip 100a and the second semiconductor chip 200a in FIG. 33, which are electrically connected to each other, correspond to the first semiconductor chip 100a and the second semiconductor chip 200a in FIG. 31, respectively, and have the same or similar structures and connection relationships. The third semiconductor chip 300a in FIG. 33 is the same as or similar to the third semiconductor chip 300a in FIG. The first semiconductor chip 100a and the third semiconductor chip 300a each have a COP structure. FIG. 33 corresponds to an example in which FIG. 31 and FIG. 28 are combined.

[0164] FIG. 34 is a perspective view showing a schematic configuration of an end portion of the first stack structure according to the embodiment of the present invention. 3A and 34, for example, the first and second electrode layers (EL1, EL2) included in the first stack structure ST1 have pad portions (ELPa, ELPb) that contact the first cell contact plug CC1 in the first connection region CNR1.

[0165] Specifically, among the first electrode layers EL1 stacked on the first memory substrate 201, the odd-numbered first electrode layers EL1 stacked on the first memory substrate 201 each have a first pad portion ELPa. Among the first electrode layers EL1, the even-numbered stacked first electrode layers EL1 each have a second pad portion ELPb. The first pad portion ELPa does not overlap the second pad portion ELPb. The first pad portion ELPa protrudes to the side of the second pad portion ELPb (in the second direction D2). The first pad portion ELPa has a step with the second pad portion ELPb in the second direction D2. The first cell contact plugs CC1 penetrate the inter-electrode layer insulating film 12 and are in contact with the first pad portion ELPa and the second pad portion ELPb, respectively.

[0166] The first electrode layer EL1 has the same or a similar structure in the second connection region CNR2. In the three-dimensional semiconductor memory device described with reference to FIGS. 1A to 33, the ends of the second to eighth electrode layers (EL2 to EL8) also have such a structure. In this way, the positions of the pads are secured, bridging between the cell contact plugs is prevented, and the degree of freedom in wiring can be increased. Therefore, the reliability of the three-dimensional semiconductor memory device can be improved. In the example of Figure 34, the positions of the pad portions of the odd-numbered and even-numbered electrode layers are different, but three or more electrode layers may be formed as a set and protrude in the second direction D2, having pad portions that form a staircase shape.

[0167] FIG. 35 is a partial cross-sectional view illustrating a schematic configuration of a three-dimensional semiconductor memory device according to still another embodiment of the present invention. 35, the total number of electrode layers (EL1, EL3, EL5) belonging to each stack structure (ST1, ST3, ST5) in FIG. 30 is different. For example, the total number of the third electrode layers EL3 is smaller than the total number of the first electrode layers EL1 and is greater than the total number of the fifth electrode layers EL5. Therefore, the vertical lengths (thicknesses) of the stack structures (ST1, ST3, ST5) also differ. For example, the third stack structure ST3 is thinner than the first stack structure ST1 and thicker than the fifth stack structure ST5. Similarly, the vertical lengths of the through-edge vias (L1ETHV, L2ETHV, L3ETHV) and the vertical patterns VS are also different. The rest of the configuration and connections are the same as or similar to those in FIG.

[0168] The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the technical scope of the present invention. For example, the embodiments described with reference to FIGS. 1A to 35 can be combined with each other. [Explanation of symbols]

[0169] 3, 30, 40 (1st to 3rd) interlayer insulating film 9 Separation insulation pattern 12 Electrode interlayer insulating film 14 Contact insulating film 16 Via insulating film 18 Residual Sacrifice Pattern 20 Flat insulating film 29 Buried insulation pattern 34 Bitline conductive pad 50a, 50b Connection terminals 100 Logic Chips 103 Logic Board 105 Element isolation film 107 Logic interlayer insulating film 109 Logic Wiring 150 Logic connection terminal 200, 300, 300, 400, 500 (1st to 4th) memory chips 201, 301 (1st, 2nd) memory board BLCP Bit line connection wiring CAR cell array area CC1~CC4 (1st~4th) cell contact plugs CNR1, CNR2 (first, second) connection area CDVS Center Dummy Vertical Pattern CSPLG1, CSPLG2 (first, second) source contact plugs ( CTHV1~CTHV4 (1st~4th) Cell Through Vias DCR1~DCR4 (1st~4th) Decoder Circuit Section EDVS Edge dummy vertical pattern EL1 to EL4 (1st to 4th) electrode layers ETHV1, ETHV2 (1st, 2nd) Through Edge Vias GO gate insulating film GR Groove Area IP1, IP2 (1st, 2nd) insulation patterns L1BL, L2BL (1st, 2nd) layer bit lines PB Page buffer circuit section PST1 to PST4 (1st to 4th) pass transistors PTR Bit Line Select Transistor RC1, RC2 (1st, 2nd) recess area VPa, VPb Conductive pattern VS Cell Vertical Pattern SC1, SC2 (1st, 2nd) source patterns SCL Source Layer ST1 to ST4 (1st to 4th) stack structures

Claims

1. a first peripheral circuit unit including a plurality of mutually different decoder circuit units, the first peripheral circuit unit being a logic chip; a first memory unit that is stacked and disposed on the first peripheral circuit unit; A second memory unit is stacked and disposed on the first memory unit, the first memory unit includes a first stack structure including a plurality of first electrode layers stacked on each other and a plurality of first inter-electrode insulating films interposed therebetween, and a first planar insulating film covering an end portion of the first stack structure; the second memory unit includes a second stack structure including a plurality of second electrode layers stacked on each other and a plurality of second inter-electrode insulating films interposed therebetween, and a second planar insulating film covering an end portion of the second stack structure; the first memory unit further includes a first through via that penetrates an end of the first stack structure and the first planar insulating film, is insulated from the first electrode layer, and is electrically connected to any one of the decoder circuit units; the second memory unit further includes a second cell contact plug penetrating the second planar insulating film and electrically connecting one of the second electrode layers to the first through via; the first memory unit further includes a plurality of first vertical patterns penetrating the first electrode layer; and a plurality of first bit lines each connected to an end of the first vertical patterns and parallel to each other, the second memory unit further includes a plurality of second vertical patterns penetrating the second electrode layer, and a plurality of second bit lines each connected to an end of the second vertical patterns and parallel to each other, the first peripheral circuit further includes a page buffer circuit, the first bit line is connected to one of the page buffer circuit units, and the second bit line is not connected to the one of the page buffer circuit units.

2. The first memory unit further includes a first through insulating film surrounding the first through via, the second memory portion further includes a second contact insulating film surrounding the second cell contact plug; 2. The three-dimensional semiconductor memory device of claim 1, wherein the first through insulating film is thicker than the second contact insulating film.

3. The first memory unit further includes a first through insulating film surrounding the first through via, the first through insulating film has a first thickness parallel to a first direction parallel to an upper surface of the first peripheral circuit unit of the logic chip; any one of the first inter-electrode insulating films has a second thickness parallel to a second direction perpendicular to a top surface of the first peripheral circuit portion of the logic chip; 2. The three-dimensional semiconductor memory device of claim 1, wherein the first thickness is equal to or greater than the second thickness.

4. the first electrode layers each include a first recessed region at an end of the first stack structure, inner walls of the first recessed regions being vertically aligned with each other; the first stack structure further includes first remaining sacrificial patterns each filling the first recessed regions; 2. The three-dimensional semiconductor memory device of claim 1, wherein the first through via penetrates the first remaining sacrificial pattern of the first stack structure.

5. the decoder circuitry includes a first decoder circuitry and a second decoder circuitry spaced apart from each other in a first direction parallel to an upper surface of the first peripheral circuitry; 2. The three-dimensional semiconductor memory device of claim 1, wherein one of the second electrode layers is electrically connected to the second decoder circuit unit through the second cell contact plug and the first through via.

6. 6. The three-dimensional semiconductor memory device of claim 5, wherein the first memory unit further includes a first cell contact plug penetrating the first planar insulating film and electrically connecting any one of the first electrode layers to the first decoder circuit unit.

7. the decoder circuitry further includes a third decoder circuitry that is parallel to an upper surface of the first peripheral circuitry and is disposed in parallel with the second decoder circuitry in a second direction that intersects with the first direction; the first memory unit further includes a third stack structure spaced apart from the first stack structure in the second direction, the third stack structure includes a plurality of third electrode layers stacked on one another and a plurality of third electrode interlayer insulating films interposed therebetween; the first planar insulating film is extended to cover an end portion of the third stack structure; 6. The three-dimensional semiconductor memory device of claim 5, wherein the first memory unit further includes a third cell contact plug penetrating the first planar insulating film and electrically connecting any one of the third electrode layers to the third decoder circuit unit.

8. 8. The three-dimensional semiconductor memory device of claim 7, wherein the third stack structure is positioned at the same height as the first stack structure.

9. 9. The three-dimensional semiconductor memory device of claim 8, wherein the third stack structure has a shape obtained by rotating the first stack structure by 180 degrees.

10. the first stack structure has a first maximum width parallel to a first direction parallel to a top surface of the first peripheral circuit portion of the logic chip; the second stack structure has a second maximum width parallel to the first direction; 2. The three-dimensional semiconductor memory device of claim 1, wherein the second maximum width is greater than the first maximum width.

11. 2. The three-dimensional semiconductor memory device of claim 1, wherein an end of the second stack structure protrudes laterally from an end of the first stack structure.

12. the decoder circuit unit includes a first decoder circuit unit and a second decoder circuit unit; The memory device further includes a third memory unit stacked and disposed on the second memory unit, the third memory unit includes a third stack structure including a plurality of third electrode layers stacked on each other and a plurality of third electrode interlayer insulating films interposed therebetween, and a third planar insulating film covering an end portion of the third stack structure, the third electrode layer and the first electrode layer are electrically connected to the first decoder circuit unit; 2. The three-dimensional semiconductor memory device of claim 1, wherein the second electrode layer is electrically connected to the second decoder circuit unit.

13. A third memory unit is stacked and disposed on the second memory unit, the third memory unit includes a third stack structure including a plurality of third electrode layers stacked on each other and a plurality of third electrode interlayer insulating films interposed therebetween, and a third planar insulating film covering an end portion of the third stack structure, the third memory unit further includes a plurality of third vertical patterns penetrating the third electrode layer, and a plurality of third bit lines each connected to an end of the third vertical patterns and parallel to each other, 2. The three-dimensional semiconductor memory device of claim 1, wherein the third bit line is connected to the one of the page buffer circuit units.

14. a third memory unit stacked and disposed on the second memory unit; A second peripheral circuit unit is stacked and arranged on the third memory unit, 2. The three-dimensional semiconductor memory device of claim 1, wherein the third memory unit is insulated from the first peripheral circuit unit, the first memory unit, and the second memory unit, and is electrically connected to the second peripheral circuit unit.

15. a peripheral circuit unit including first to fourth decoder circuit units different from each other; a first memory unit disposed on the peripheral circuit unit; a second memory portion disposed on the first memory portion, the first memory unit includes a first stack structure and a second stack structure spaced apart from each other in a first direction parallel to an upper surface of the peripheral circuit unit, the first stack structure includes a plurality of first electrode layers stacked on each other, and the second stack structure includes a plurality of second electrode layers stacked on each other; the second memory unit includes a third stack structure and a fourth stack structure spaced apart from each other in the first direction, the third stack structure includes a plurality of third electrode layers stacked on each other, and the fourth stack structure includes a plurality of fourth electrode layers stacked on each other; the first electrode layer is electrically connected to the first decoder circuit unit; the third electrode layer is electrically connected to the third decoder circuit unit; the second electrode layer is electrically connected to the second decoder circuit unit; The fourth electrode layer is electrically connected to the fourth decoder circuit unit. a plurality of first cell contact plugs in contact with the first electrode layer and connecting the first electrode layer to the first decoder circuit unit, respectively; a plurality of second cell contact plugs each in contact with the third electrode layer; a plurality of first through vias that connect the second cell contact plugs and the third decoder circuit unit, respectively, and are insulated from the first electrode layer; the first memory unit includes a first planar insulating film covering ends of the first stack structure and the second stack structure, the third decoder circuit unit and the fourth decoder circuit unit are spaced apart from the first decoder circuit unit and the second decoder circuit unit in a second direction parallel to an upper surface of the peripheral circuit unit and intersecting the first direction; any one of the second electrode layers is electrically connected to the second decoder circuit unit through the second cell contact plug and the first through via; a fifth decoder circuit unit and a sixth decoder circuit unit that are parallel to an upper surface of the peripheral circuit unit and are arranged in parallel to the first decoder circuit unit and the second decoder circuit unit in a second direction that intersects with the first direction; the first memory unit further includes a fifth stack structure and a sixth stack structure spaced apart from the first stack structure in the second direction, the fifth stack structure includes a plurality of fifth electrode layers stacked on one another and a plurality of fifth electrode interlayer insulating films interposed therebetween, the sixth stack structure includes a plurality of sixth electrode layers stacked on one another and a plurality of sixth inter-electrode insulating films interposed therebetween; the first planar insulating layer is extended to cover ends of the fifth stack structure and the sixth stack structure; the first memory unit further includes a third cell contact plug penetrating the first planar insulating film and electrically connecting one of the fifth electrode layer and the sixth electrode layer to the third decoder circuit unit.

16. a peripheral circuit unit including first and second decoder circuit units that are different from each other and are arranged in parallel in a first direction; a first memory unit that is stacked and disposed on the peripheral circuit unit and includes a first stack structure; a second memory portion disposed on the first memory portion and including a second stack structure; the first stack structure is electrically connected to the first decoder circuit unit; the second stack structure is electrically connected to the second decoder circuit unit; A portion of the second stack structure protrudes from a side of the first stack structure, the peripheral circuitry further includes a third decoder circuitry spaced apart from the first decoder circuitry in a direction opposite to the first direction, the first stack structure includes a first recessed area above the third decoder circuit portion; the second stack structure includes a second recessed area above the third decoder circuit portion; a third memory section including a third stack structure, the third memory section being stacked and disposed on the second memory section; a cell contact plug in contact with the third stack structure on the third decoder circuit portion; a first through via disposed in the first recess region and electrically connected to the cell contact plug; a second through via disposed in the second recess region and electrically connected to the cell contact plug.

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