Semiconductor device and method for testing SRAM circuit

Abstract

To provide a method of testing a semiconductor device and an SRAM circuit for testing a degree of deterioration of the SRAM circuit mounted on the semiconductor device in use by a user.SOLUTION: In an SRAM circuit 100 mounted on a semiconductor device, power supply voltage reduction circuits 30 to 32 generate a reduced voltage obtained by reducing an external power supply voltage VDD. A first power supply voltage selection circuit 35 selects one of the external power supply voltage and the reduced voltage as a driving voltage to be supplied to a word line driver WD. A second power supply voltage selection circuit 34 selects one of the external power supply voltage and the reduced voltage as a voltage of a power supply line PL for supplying an operation voltage to memory cells MC.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device and a method for testing an SRAM circuit, and for example, to a technique for predicting the life of an SRAM (Static Random Access Memory). [Background technology]

[0002] Regarding a technique for notifying a user of the possibility that a semiconductor device will fail before the semiconductor device actually fails, for example, Japanese Patent Application Laid-Open No. 2017-173242 (Patent Document 1) is known.

[0003] Specifically, the semiconductor device disclosed in this document includes functional units and a life prediction circuit. One of the functional units is a central processing circuit. The life prediction circuit acquires the degree of deterioration of the functional units by lowering the power supply voltage of the semiconductor device and executing a test on the functional units. When the degree of deterioration exceeds a predetermined threshold, the life prediction circuit notifies a user that the semiconductor device is nearing the end of its life. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2017-173242 A Summary of the Invention [Problem to be solved by the invention]

[0005] In the case of the technology disclosed in the above-mentioned JP 2017-173242 A (Patent Document 1), when a degradation prediction test is performed, it is necessary to lower the power supply voltage of the entire semiconductor device. Therefore, the degradation prediction test can be performed only when the semiconductor device is powered on, and the degradation degree of the semiconductor device cannot be tested while the user is using it.

[0006] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0007] An SRAM circuit mounted on a semiconductor device of one embodiment includes a power supply voltage reduction circuit, a first power supply voltage selection circuit, and a second power supply voltage selection circuit. The power supply voltage reduction circuit generates a reduced voltage by reducing an external power supply voltage. The first power supply voltage selection circuit selects one of the external power supply voltage and the reduced voltage as a drive voltage to be supplied to a word line driver. The second power supply voltage selection circuit selects one of the external power supply voltage and the reduced voltage as a voltage of a power supply line that supplies an operating voltage to a memory cell. Effect of the Invention

[0008] According to the above embodiment, the degree of degradation of the SRAM circuit mounted on the semiconductor device can be tested while the user is using the device. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a diagram illustrating an overall configuration of an SRAM circuit. [Diagram 2] 11 is a diagram showing, in table form, the potentials of the word lines WL and the power supply lines PL according to the operation modes. [Diagram 3] 11A and 11B are diagrams for explaining the effect of applying a reduced voltage to a power supply line when reading data. [Figure 4] 11A and 11B are diagrams for explaining the effect of applying a reduced voltage to a word line when writing data. [Diagram 5] 2 is a circuit diagram showing an example of a circuit configuration of a power supply voltage reducing circuit and a power supply voltage selecting circuit in FIG. 1; [Figure 6] 1 is a block diagram showing an overall configuration of a semiconductor device according to a first embodiment; [Figure 7] 10 is a flowchart showing a procedure of a power-on diagnosis. [Figure 8] 13 is a flowchart showing a procedure for runtime diagnosis. [Figure 9A] 9 is a diagram for explaining an example of a procedure for carrying out the deterioration prediction test of FIG. 8.

[0023] FIG. [Figure 9B] 9 is a diagram for explaining an example of a procedure for carrying out the deterioration prediction test of FIG. 8.

[0023] FIG. [Figure 9C] 9 is a diagram for explaining an example of a procedure for carrying out the deterioration prediction test of FIG. 8.

[0023] FIG. [Figure 9D] 9 is a diagram for explaining an example of a procedure for carrying out the deterioration prediction test of FIG. 8.

[0023] FIG. [Figure 10] FIG. 2 is a diagram for explaining the effect of the first embodiment. [Figure 11] FIG. 11 is a diagram illustrating an example of the configuration of a power supply voltage reducing circuit in an SRAM circuit 100A according to a second embodiment. [Figure 12] FIG. 2 is a diagram for explaining the magnitude of a reduced voltage according to test mode signals TM1 and TM2. [Figure 13] FIG. 11 is a block diagram showing an overall configuration of a semiconductor device according to a second embodiment. [Figure 14] 10 is a flowchart showing a procedure of a runtime diagnosis in the second embodiment. [Figure 15] 1 is a diagram for explaining a method for predicting the time of failure of an SRAM circuit. [Figure 16] 14 is a flowchart showing a procedure for a main controller to predict a failure time in the semiconductor device of FIG. 13. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, each embodiment relating to degradation prediction of an SRAM will be described in detail with reference to the drawings. Note that the same or corresponding parts are designated by the same reference characters and their description may not be repeated.

[0011] <First embodiment> [Outline of SRAM configuration] 1 is a diagram showing a schematic overall configuration of an SRAM circuit, which is also referred to as an SRAM macro (MACRO) in this specification.

[0012] As shown in Fig. 1, the SRAM circuit 100 includes a memory cell array 10 in which memory cells MC are arranged in a matrix. In the example of Fig. 1, memory cells MC are provided in (n+1) rows and (m+1) columns. Hereinafter, the row direction of the memory cell array 10 is also referred to as the X direction, and the column direction of the memory cell array 10 is also referred to as the Y direction. A detailed configuration of each memory cell MC will be described later with reference to Fig. 3.

[0013] Word lines WL0 to WLn are provided corresponding to the rows of the memory cell array 10. The word lines WL0 to WLn are electrically connected to each memory cell MC in the corresponding row. Bit line pairs BL0, / BL0 to BLm, / BLm are provided corresponding to the columns of the memory cell array 10. Each of the bit line pairs BL0, / BL0 to BLm, / BLm is electrically connected to each memory cell MC in the corresponding column. Furthermore, power supply lines PL0 to PLm are provided corresponding to the columns of the memory cell array 10. Each of the power supply lines PL0 to PLm supplies an operating voltage to each memory cell MC in the corresponding column. Note that, as described later, an external power supply voltage VDD and a reduced voltage VDD-α obtained by reducing the external power supply voltage VDD can be selectively supplied as the operating voltage.

[0014] In the following description, word lines WL0 to WLn are collectively referred to as word line WL when referring to them or any one of them. Bit line pairs BL0, / BL0 to BLm, / BLm are collectively referred to as bit line pair BL, / BL when referring to them or any one of them. Power lines PL0 to PLm are collectively referred to as power line PL when referring to them or any one of them.

[0015] The SRAM circuit 100 includes a row decoder 21 and word line drivers WD0 to WDn to control the word lines WL. The row decoder 21 generates a row selection signal in accordance with a row address signal RA. Each of the word line drivers WD0 to WDn drives a corresponding one of the word lines WL0 to WLn to a power supply voltage in accordance with the row selection signal. The word line drivers WD0 to WDn are connected to a power supply line 25 to receive the power supply voltage. As will be described later, the power supply voltage supplied to the word line drivers WD0 to WDn can be selected from an external power supply voltage VDD and a reduced voltage VDD-α obtained by lowering the external power supply voltage VDD. In the following description, the word line drivers WD0 to WDn are collectively referred to as a word line driver WD when referring to any one of them.

[0016] Furthermore, the SRAM circuit 100 includes a column decoder 22, a write circuit 23, and a read circuit 24. These are provided to control the voltages of the bit line pair BL, / BL. Specifically, the column decoder 22 selects a column of the memory cell array 10 in accordance with a column address signal CA. Usually, multiple columns are selected at one time. The column decoder 22 electrically connects the bit line pair BL, / BL of the selected column to the write circuit 23 when writing data. The column decoder 22 electrically connects the bit line pair BL, / BL of the selected column to the read circuit 24 when reading data.

[0017] The write circuit 23 includes an input buffer and a write drive circuit, and when writing data, generates internal write data according to external write data DI. The write drive circuit drives one of the bit line pair BL, / BL of the selected column to H (High) level and the other to L (Low) level according to the internal write data. The read circuit 24 includes a sense amplifier circuit and an output buffer. When reading data, the sense amplifier detects and amplifies a potential difference occurring on the bit line pair BL, / BL of the selected column. The output buffer generates external read data DO based on the potential difference detected and amplified by the sense amplifier.

[0018] Furthermore, the SRAM circuit 100 includes power supply voltage reducer circuits (VDD REDN.) 30 to 32, and power supply voltage selector circuits (VDD SELECT) 34_0 to 34_m and 35. These circuits are used in the test mode.

[0019] Each of the power supply voltage reduction circuits 30-32 generates a reduced voltage VDD-α by reducing an external power supply voltage VDD supplied from the outside, and outputs the generated reduced voltage VDD-α to a voltage supply line 33. In the example of FIG. 1, the power supply voltage reduction circuits 30-32 and the voltage supply line 33 are arranged in the Y direction between the memory cell array 10 and the row decoder 21. The voltage supply line 33 is further arranged in the X direction between the memory cell array 10 and the column decoder 22. The power supply voltage reduction circuits 30 and 32 at both ends in the Y direction always operate in the test mode. The power supply voltage reduction circuit 31 operates selectively in the test mode. Although only one power supply voltage reduction circuit 31 is shown in FIG. 1 as a representative example, a plurality of power supply voltage reduction circuits are actually provided between the power supply voltage reduction circuits 30 and 32.

[0020] The power supply voltage selection circuits 34_1 to 34_m are disposed between the memory cell array 10 and the column decoder 22, one for each column of the memory cell array 10. In the following description, the power supply voltage selection circuits 34_1 to 34_m are collectively referred to as the power supply voltage selection circuit 34 when any one of them is indicated. Each power supply voltage selection circuit 34 selects one of the external power supply voltage VDD and the reduced voltage VDD-α supplied from the voltage supply line 33 as a power supply voltage. Each power supply voltage selection circuit 34 supplies the selected power supply voltage to the corresponding power supply line PL. Here, each power supply voltage selection circuit 34 selects the reduced voltage VDD-α for the memory cells MC of the corresponding column in the test mode and the data read mode. The power supply voltage selection circuit 34 selects the external power supply voltage VDD in other cases.

[0021] The power supply voltage selection circuit 35 is disposed between the memory cell array 10 and the row decoder 21. In FIG. 1, only one is shown as a representative example, but actually, a plurality of power supply voltage selection circuits are arranged in the Y direction. As shown in FIG. 1, the power supply voltage selection circuit 35 is disposed adjacent to the power supply voltage selection circuit 34 in the X direction. The power supply voltage selection circuit 35 selects one of the external power supply voltage VDD and the reduced voltage VDD-α supplied from the voltage supply line 33 as a power supply voltage. The power supply voltage selection circuit 35 supplies the selected power supply voltage to the power supply line 25 for the word line driver WD. As a result, the selected power supply voltage (i.e., VDD or VDD-α) is supplied to the word line WL of the row selected by the row decoder 21. Here, the power supply voltage selection circuit 35 selects the reduced voltage VDD-α as the power supply voltage in the test mode and the data write mode. The power supply voltage selection circuit 35 selects the external power supply voltage VDD in other cases.

[0022] Furthermore, the SRAM circuit 100 includes a controller () 20 that controls the above components as a whole. The controller 20 receives an address signal AD, a write enable signal WE, and a test mode signal TM as control signals from outside the SRAM circuit 100. The controller 20 generates a row address signal RA and a column address signal CA from the address signal AD. When the write enable signal WE is asserted, the mode is a data write mode, and when the write enable signal WE is negated, the mode is a data read mode. When the test mode signal TM is asserted, the mode is a test mode, and when the test mode signal TM is negated, the mode is a normal mode.

[0023] Figure 2 is a table showing the potentials of the word line WL and the power line PL according to the operation mode. As explained with reference to Figure 1, there are two modes (MODE): normal mode and test mode. Also, there are two operations (OPERATION) of the RAM: data write (WRITE) and data read (READ).

[0024] As shown in FIG. 2, in normal mode, both the word line potential (WL POTENTIAL) and the power line potential (PL POTENTIAL) are the external power supply potential VDD. In test mode and during a data write operation, the word line potential of the selected row is set to the reduced potential VDD-α. In this case, the power line potential for the memory cells MC remains at the external power supply potential VDD. In test mode and during a data read operation, the power line potential for the memory cells MC is set to the reduced potential VDD-α. In this case, the word line potential remains at the external power supply potential VDD. In the following description, unless a distinction is required, the potential and the voltage (potential difference with respect to a reference potential) are regarded as the same thing.

[0025] Next, the effect of applying the above-mentioned reduced voltage VDD-α to the power supply line PL and the word line WL will be explained. First, the configuration and basic operation of an SRAM memory cell will be briefly explained with reference to Fig. 3, and then the effect of applying the reduced voltage VDD-α will be explained. As will be explained in detail below, applying the reduced voltage VDD-α has the effect of tightening (i.e., reducing) the operating margin of the SRMM memory cell MC.

[0026] [Structure and basic operation of SRAM memory cells] 3, the memory cell MC0 is basically configured with a latch circuit made up of two CMOS (Complementary Metal Oxide Semiconductor) inverters. The memory cell MC0 further includes two NMOS (N-channel MOS) access transistors 45 and 46 connected to the latch circuit. The other memory cells MC have the same configuration.

[0027] The latch circuit is composed of a first CMOS inverter and a second CMOS inverter. The first CMOS inverter includes a PMOS (P-channel MOS) load transistor 41 and an NMOS drive transistor 43 connected in series between a power supply line PL0 and a ground VSS. The second CMOS inverter includes a PMOS load transistor 42 and an NMOS drive transistor 44 connected in series between a power supply line PL0 and a ground VSS. A connection node 47 between the load transistor 41 and the drive transistor 43 is connected to the gates of the load transistor 42 and the drive transistor 44. A connection node 48 between the load transistor 42 and the drive transistor 44 is connected to the gates of the load transistor 41 and the drive transistor 43.

[0028] The access transistor 45 is connected between a connection node 47 and a bit line BL0 (TRUE). The access transistor 46 is connected between a connection node 48 and a bit line / BL0 (BAR). The gates of the access transistors 45 and 46 are connected to a common word line WL.

[0029] Memory cell MC0 holds complementary voltages (one voltage is H level and the other is L level) at connection nodes 47 and 48. The procedure of the write operation will be briefly described below. For example, a case will be described in which connection node 47 holds a voltage of H level and connection node 48 holds a voltage of L level. In this case, first, the voltage of bit line BL0 is set to H level, and the voltage of bit line / BL0 is set to L level. Next, by holding the state in which the voltage of word line WL is changed from L level to H level for a predetermined time, the voltage of connection node 47 changes to H level, and the voltage of connection node 48 changes to L level.

[0030] Next, the procedure of the read operation will be briefly described. It is assumed that the voltage of the connection node 47 is preset to H level, and the voltage of the connection node 48 is preset to L level. First, the bit line pair BL0, / BL0 is precharged to the power supply voltage (VDD PRECHARGED). After that, when the voltage of the word line WL is changed from L level to H level, the voltage of the bit line BL connected to the connection node 47 holding the H level voltage does not change, whereas the voltage of the bit line / BL0 connected to the connection node 48 holding the L level voltage drops. The voltage difference between the bit lines BL0, / BL0 is amplified by a sense amplifier (not shown) provided in the read circuit 24, and the data held in the memory cell MC can be read out.

[0031] [Effect of applying reduced voltage VDD-α to the power supply line when reading data] Next, the effect of applying the reduced voltage VDD-α to the power supply line PL in the test mode (test mode signal TM=H level) and when reading data (write enable signal WE=L level) will be described. The voltage of the word line WL is not lowered from the external power supply voltage VDD.

[0032] Fig. 3 is a diagram for explaining the effect of applying a reduced voltage to the power supply line when reading data. Fig. 3 shows two memory cells MC0 and MC1 connected to the same word line WL, which is a selected row. Memory cell MC0 is a memory cell in a selected column (SELECTED COLUMN), and memory cell MC1 is a memory cell in a non-selected column (DESELECTED COLUMN). In each of memory cells MC0 and MC1, an H-level voltage is held at connection node 47, and an L-level voltage is held at connection node 48.

[0033] In the test mode (TM=H) and during data read (WE=L), the voltages of the power supply lines PL0 and PL1 are reduced from the external power supply voltage VDD to the reduced voltage VDD-α. In this case, in the memory cells MC0 and MC1, the connection node 48 is at the L level, so the load transistor 41 is turned on. As a result, the voltage of the wiring portion including the connection node 47 shown by the thick line in FIG. 3 becomes the reduced voltage VDD-α.

[0034] When reading data, the bit line pairs BL0, / BL0 and BL1, / BL1 are first precharged to the external power supply voltage VDD. Then, the external power supply voltage VDD is applied to the word line WL. This causes the access transistors 45, 46 in each of the memory cells MC0, MC1 to switch to a conductive state.

[0035] At this time, in the memory cell MC0 in the selected column, the drive transistor 44 may not be fully turned on because the voltage of the connection node 47 is the reduced voltage VDD-α. In this case, the discharge current 49 flowing from the bit line / BL0 through the drive transistor 44 to the ground VSS is limited. As a result, if the bit line / BL0 is not fully discharged (DISCHARGED) and the voltage difference between the bit line pair BL0, / BL0 is not sufficient, an error may occur in the detection by the read circuit 24. In other words, by applying the reduced voltage VDD-α to the power supply line PL0, the read margin of the memory cell MC0 in the selected column can be made slightly tighter.

[0036] The same is true for memory cell MC1 in an unselected column. Specifically, since the voltage of connection node 47 is the reduced voltage VDD-α, the drive transistor 44 may not be fully turned on, limiting the discharge of bit line / BL0. In this case, the voltage of connection node 48 hardly drops from the precharge voltage VDD. As a result, the load transistor 41 switches to a non-conductive state and the drive transistor 43 switches to a conductive state, thereby inverting the stored data in memory cell MC1 in an unselected column. In other words, by applying the reduced voltage VDD-α to the power supply line PL0, the static noise margin of memory cell MC1 in an unselected column can be made slightly tighter.

[0037] As will be described in detail later, a read test is performed with the operating margins tightened as described above. The read test checks whether the data already written is read correctly and whether data inversion occurs in the memory cells MC of the unselected columns. This allows a degradation prediction test to be performed to check whether a failure will occur in the future even if the memory cell is currently normal.

[0038] [Effect of applying reduced voltage VDD-α to the word line when writing data] Next, the effect of applying the reduced voltage VDD-α to the word line WL in the test mode (test mode signal TM=H level) and when writing data (write enable signal WE=H level) will be described. The voltage of the power line PL is not lowered from the external power supply voltage VDD.

[0039] 4 is a diagram for explaining the effect of applying a reduced voltage to a word line when writing data. In FIG. 4, a memory cell MC0 connected to a word line WL, which is a selected row, is shown. The memory cell MC0 is a memory cell in a selected column. Memory cells in unselected columns are not involved in the test.

[0040] In the memory cell MC0 before data is written, the connection node 47 holds a voltage of H level, and the connection node 48 holds a voltage of L level. In order to write a logical value opposite to the logical value of the held data to the memory cell MC0, the bit line BL0 is set to L level (VSS), and the bit line / BL0 is set to H level (VDD). In this state, a voltage of H level is supplied to the word line WL. In the test mode (TM=H) and during data writing (WE=H), the voltage of the word line WL is the reduced voltage VDD-α, so that the access transistor 45 may not be fully turned on. In this case, the discharge current 50 flowing from the connection node 47 through the access transistor 45 to the bit line BL0 is limited. As a result, the voltage of the connection node 48 hardly changes from the power supply voltage VDD, and no inversion of the stored data occurs. That is, by applying the reduced voltage VDD-α to the word line WL, the write margin of the memory cell MC0 in the selected column can be made slightly tighter.

[0041] As will be described in detail later, a write test is performed with the write margin set to be strict as described above. In the write test, data written to the memory cell MC is read to test whether the data is written correctly. This allows a degradation prediction test to be performed to check whether a failure will occur in the future even if the memory cell is currently normal.

[0042] [Example of a power supply voltage reduction circuit and a power supply voltage selection circuit] Fig. 5 is a circuit diagram showing an example of the circuit configuration of the power supply voltage reducing circuits and the power supply voltage selection circuit in Fig. 1. Hereinafter, an example of the circuit configuration of the power supply voltage reducing circuits 30 to 32 and the power supply voltage selection circuits 34 and 35 in Fig. 1 will be described with reference to Fig. 5.

[0043] 5 representatively shows the power supply voltage selection circuit 34 connected to the power supply line PL0, the power supply voltage selection circuits 34 connected to the other power supply lines PL have the same configuration. Also, in FIG. 5, the circuit configuration of the portion related to the control of the power supply voltage reducing circuits 30-32 and the power supply voltage selection circuits 34, 35 of the controller 20 in FIG. 1 is shown. Specifically, the controller 20 includes a flip-flop (FF) 80, inverters 81-87, NOR circuits 88, 89, and a NAND circuit 90. The configuration of these logic circuits is merely an example, and other configurations that provide similar functions may be used.

[0044] 5, each of the power supply voltage reducing circuits 30 to 32 includes PMOS transistors 60 and 61 connected in series to each other. The PMOS transistor 60 is connected between a power supply node (hereinafter referred to as a VDD node) to which an external power supply voltage VDD is applied and the voltage supply line 33. The PMOS transistor 61 is connected between the ground to which a reference voltage VSS is applied and the voltage supply line 33.

[0045] Here, the current supply capability of the PMOS transistor 60 is large, while the current supply capability of the PMOS transistor 61 is small. For example, the ratio W / L of the channel width W to the channel length L of the PMOS transistor 60 is set to be larger than the ratio W / L of the PMOS transistor 61. Due to this difference in current supply capability, when the PMOS transistors 60 and 61 are both on, a reduced voltage VDD-α, which is a voltage lower than the external power supply voltage VDD, is supplied to the voltage supply line 33.

[0046] In the case of the power supply voltage reduction circuits 30 and 32, a reference voltage VSS is input to the gate of the PMOS transistor 60, and a gate of the PMOS transistor 61 is connected to a signal line 66. A test mode signal TM is supplied to the signal line 66 via inverters 82, 83, and 84. Therefore, in the non-test mode (TM=L level), the PMOS transistor 60 is turned on, and the PMOS transistor 61 is turned off. In this case, the power supply voltage reduction circuits 30 and 32 supply the external power supply voltage VDD to the voltage supply line 33. On the other hand, in the test mode (TM=H level), both the PMOS transistors 60 and 61 are turned on. In this case, the power supply voltage reduction circuits 30 and 32 supply a reduced voltage VDD-α to the voltage supply line 33.

[0047] In the case of the power supply voltage reduction circuit 31, the gates of the PMOS transistors 60 and 61 are connected to a signal line 67. An OR operation result between a signal obtained by inverting the test mode signal TM by an inverter 82 and a signal obtained by inverting the control signal CNTL1 by an inverter 85 is input to the signal line 67. In the case of FIG. 5, the OR operation is realized by a series connection of a NOR circuit 89 and an inverter 87. Therefore, in the test mode (TM=H level) and when the control signal CNTL1 is at H level, the PMOS transistors 60 and 61 are in an ON state. In this way, the power supply voltage reduction circuit 31 is controlled so as to temporarily generate a reduced voltage VDD-α in response to the control signal CNTL1 during the test mode (TM=H level). In other cases, the power supply voltage reduction circuit 31 does not supply voltage.

[0048] The power supply voltage selection circuit 34 includes PMOS transistors 75 and 76, and an inverter 77. The PMOS transistor 75 is connected between the VDD node and a power supply line PL0. The PMOS transistor 76 is connected between the voltage supply line 33 and the power supply line PL0. A write enable signal WE is input to the gate of the PMOS transistor 75 via a flip-flop (FF) 80 and an inverter 81. A write enable signal WE is input to the gate of the PMOS transistor 76 via the flip-flop 80 and the inverters 81 and 77.

[0049] According to the above connection, during a write operation (WE=H level), the PMOS transistor 75 is turned on and the PMOS transistor 76 is turned off. Therefore, the external power supply voltage VDD is supplied to the power supply line PL0. On the other hand, during a read operation (WE=L level), the PMOS transistor 75 is turned off and the PMOS transistor 76 is turned on. Therefore, the voltage of the voltage supply line 33 is supplied to the power supply line PL0. The voltage of the voltage supply line 33 is the reduced voltage VDD-α during the test mode (TM=H level) and is the external power supply voltage VDD during the non-test mode (TM=L level).

[0050] The power supply voltage selection circuit 35 includes PMOS transistors 70 and 71, NAND circuits 72 and 73, and an inverter 74. The PMOS transistor 70 is connected between the VDD node and the power supply line 25 for the word line driver WD0. The PMOS transistor 71 is connected between the voltage supply line 33 and the power supply line 25. The gate of the PMOS transistor 70 receives a NAND operation result between the logic level of the signal line 68 and the logic level of the signal line 69. The gate of the PMOS transistor 71 receives a NAND operation result between the value obtained by inverting the logic level of the signal line 68 by an inverter 74 and the logic level of the signal line 69. The signal line 68 receives an OR operation result between the NAND operation result between the test mode signal TM and the write enable signal WE and the value obtained by inverting the control signal CNTL1 by an inverter 85. The OR operation in this case is realized by a series connection of a NOR circuit 88 and an inverter 86. The control signal CNTL2 is input to the signal line 69.

[0051] According to the above connection, when the control signal CNTL2 is at L level, both PMOS transistors 70 and 71 are turned off, so that no power supply voltage is supplied to the power supply line 25. On the other hand, when the control signal CNTL2 is at H level, the following control is performed.

[0052] (i) When the control signal CNTL1, the test mode signal TM, and the write enable signal WE are all at H level, the PMOS transistor 70 is turned off and the PMOS transistor 71 is turned on. Therefore, the reduced voltage VDD-α is supplied from the voltage supply line 33 to the power supply line 25 for the word line driver WD0.

[0053] (ii) When the control signal CNTL1 is at H level and at least one of the test mode signal TM and the write enable signal WE is at L level, the PMOS transistor 70 is turned on and the PMOS transistor 71 is turned off. Therefore, the external power supply voltage VDD is supplied to the power supply line 25 for the word line driver WD0.

[0054] (iii) When the control signal CNTL1 is at the L level, the PMOS transistor 70 is turned on and the PMOS transistor 71 is turned off. Therefore, the external power supply voltage VDD is supplied to the power supply line 25 for the word line driver WD0.

[0055] Although one test mode signal TM is used above for simplicity, a different test mode signal TM may be used for each region of the memory cell array 10. This makes it possible to apply the reduced voltage VDD-α to only a specific region while operating the SRAM circuit 100.

[0056] [Deterioration prediction test] Next, a method for performing a degradation prediction test on an SRAM circuit using the above-mentioned power supply voltage reducing circuits 30 to 32 and power supply voltage selection circuits 34 and 35 will be described.

[0057] 6 is a block diagram showing an overall configuration of a semiconductor device according to the first embodiment. Referring to FIG. 6, a semiconductor device (SEMICONDUCTOR DEVICE) 110 includes an SRAM circuit 100 and a field memory BIST circuit 102.

[0058] As described with reference to FIGS. 1 to 5, the SRAM circuit 100 includes power supply voltage reducing circuits 30 to 32 and power supply voltage selection circuits 34 and 35 for tightening the operating margin. Hereinafter, these circuits are collectively referred to as a test circuit (TEST CIRCUIT) 101. The SRAM circuit 100 is a conventional SRAM circuit to which the test circuit 101 has been added, but there is almost no increase in area overhead due to the incorporation of the test circuit 101. In addition, there is no need to reduce the power supply voltage supplied to the SRAM circuit 100 for the degradation prediction test, and the power supply voltage can be locally reduced by simply changing the mode.

[0059] BIST is an acronym for Built-In Self-Test. The BIST circuit includes a test pattern generating circuit and a test result evaluation circuit. In particular, the field memory BIST circuit 102 is capable of RUNTIME DIAGNOSTICS in addition to POWER-ON DIAGNOSTICS of the memory. The power-on diagnosis is to detect an abnormality immediately when the user starts using the semiconductor device 110. The runtime diagnosis is to detect an abnormality immediately while the semiconductor device 110 is operating.

[0060] 7 is a flowchart showing the procedure of power-on diagnosis. First, the field memory BIST circuit 102 performs an existing normal test such as a marching test (S101). In the normal test, the field memory BIST circuit 102 sets the test mode signal TM to an L level (negate). This causes the external power supply voltage VDD that is normally used by the user to be supplied to each power supply line PL and word line WL. If the total number of addresses is N, then the marching test requires 12N memory accesses (number of writes and reads).

[0061] Next, the field memory BIST circuit 102 judges whether the result of the normal test is PASS or FAIL (S102). If the result of the normal test is FAIL (FAIL in S102), the field memory BIST circuit 102 notifies the user of a WARNING (S103). In this case, the SRAM circuit 100 of the semiconductor device 110 cannot be used because it is broken.

[0062] 8 is a flowchart showing the procedure of the runtime diagnosis. First, the field memory BIST circuit 102 performs an existing normal test such as a marching test (S201). In the case of the normal test, the field memory BIST circuit 102 sets the test mode signal TM to the L level (negate).

[0063] Next, the field memory BIST circuit 102 judges whether the result of the normal test is pass or fail (S202). If the result of the normal test is fail (FAIL in S202), the field memory BIST circuit 102 notifies the user of a warning (S203) and ends the process. In this case, the SRAM circuit 100 of the semiconductor device 110 is broken, so the semiconductor device 110 cannot be operated any more.

[0064] On the other hand, if the result of the normal test is pass (PASS in S202), the field memory BIST circuit 102 performs a degradation prediction test (S204). In the degradation prediction test, the field memory BIST circuit 102 sets the test mode signal TM to an H level (asserted). This causes a reduced voltage VDD-α to be supplied to the word line WL or the power line PL in the test area. In the degradation prediction test, for example, a checkerboard test is performed. A detailed procedure of the degradation prediction test will be described later with reference to FIGS. 9A to 9D.

[0065] Next, the field memory BIST circuit 102 judges whether the result of the degradation prediction test is pass or fail (S205). If the result of the degradation prediction test is fail (FAIL in S205), the field memory BIST circuit 102 notifies the user of a warning (S206). In this case, since the SRAM circuit 100 of the semiconductor device 110 is not currently broken, there is no need to stop the operation of the semiconductor device 110.

[0066] Thereafter, the field memory BIST circuit 102 returns the process to the first step S201, and repeats the above steps periodically or in response to a request from a host system.

[0067] 9A to 9D are diagrams for explaining an example of the procedure for performing the degradation prediction test of FIG. 8. In each diagram, a column address CA, a row address RA, an operation (OPERATION) of the SRAM, write data, read data, and whether or not it is a test mode TM are described. The column address CA ranges from 0 to 7, and the row address RA ranges from 0 to 255. Therefore, the total number of addresses N is 2048. The operation of the SRAM includes write (WRITE) and read (READ). For the write data (WRITE DATA), "0000" and "1111" are alternately selected. The read data (READ DATA) is an expected value (EXPECTATION) when the SRAM circuit 100 is normal. During the degradation prediction test, the test mode signal TM is asserted to H level.

[0068] First, referring to Fig. 9A, the field memory BIST circuit 102 writes "0000" and "1111" alternately into the memory cells MC in the order of addresses. Next, referring to Fig. 9B, the field memory BIST circuit 102 reads out the data stored in each memory cell MC in the order of addresses. Here, the reason that the data of each row with the column address CA=0 is read out again at the end is to execute a read test for the case of the non-selected column.

[0069] Next, referring to Fig. 9C, the field memory BIST circuit 102 writes "1111" and "0000" alternately into the memory cells MC in the order of the addresses. Next, referring to Fig. 9D, the field memory BIST circuit 102 reads out the data stored in each memory cell MC in the order of the addresses. Here, the reason that the data of each row with the column address CA=0 is read out again at the end is to execute a read test for the case of the non-selected columns.

[0070] In this way, the number of accesses to the SRAM circuit 100 in the degradation prediction test is approximately 4N (N is the total number of addresses), so there is no significant increase in the number of memory accesses.

[0071] [Advantages of the First Embodiment] As described above, according to the semiconductor device 110 of the first embodiment, the reduced voltage VDD-α is applied to the power supply line PL when reading data, and the reduced voltage VDD-α is applied to the word line WL when writing data. This enables testing that predicts future deterioration of the operating margin of the SRAM.

[0072] The supply of the above-mentioned reduced voltage VDD-α is achieved by lowering the power supply voltage locally, rather than by changing the power supply voltage. This eliminates the need to implement and build an additional test power supply voltage control system on the product chip. In addition, future SRAM circuit failures can be detected in advance not only when the chip is powered on, but also while the chip is actually in use.

[0073] Fig. 10 is a diagram for explaining the effect of the first embodiment. The vertical axis of Fig. 10 represents the minimum power supply voltage VDDmin at which the SRAM circuit can operate. The horizontal axis of Fig. 10 represents time (TIME). The solid line in Fig. 10 represents the case where the test mode signal TM=L level, i.e., the case of normal operation. The dashed line in Fig. 10 represents the case where the test mode (TM=H) is in effect.

[0074] As shown by the solid line in FIG. 10, the operating margin deteriorates over time, so that the minimum power supply voltage VDDmin at which the SRAM circuit can operate rises. When the normal power supply voltage Vo used by the user becomes equal to the minimum power supply voltage VDDmin (time T2), it indicates that the SRAM circuit 100 has failed. The characteristics (dashed line) in the test mode (TM=H) correspond to the characteristics (solid line) in the normal use (TM=L) shifted upward. Therefore, in the test mode, the normal power supply voltage Vo used by the user becomes equal to the minimum power supply voltage VDDmin at time T1, which is before time T2, so that the occurrence of a future failure can be predicted.

[0075] <Second embodiment> In the second embodiment, a case where the degree of tightening of the operating margin of the SRAM circuit is adjusted will be described. Specifically, α of the reduced voltage VDD-α is changed in multiple stages. This makes it possible to specifically predict the time when a defect will occur in the SRAM circuit. Hereinafter, a detailed description will be given with reference to the drawings.

[0076] [Changes in SRAM circuit] Fig. 11 is a diagram showing an example of the configuration of a power supply voltage reducing circuit in an SRAM circuit 100A according to the second embodiment. The circuit diagram of the SRAM circuit 100A in Fig. 11 corresponds to the circuit diagram of the SRAM circuit 100 according to the first embodiment in Fig. 5.

[0077] 5 in that the power supply voltage reduction circuits 30-32 are replaced with power supply voltage reduction circuits 30A-32A. In the power supply voltage reduction circuits 30A-32A of FIG. 11, a PMOS transistor 62 is provided in parallel with a PMOS transistor 61. The current driving capability of the PMOS transistor 62 is smaller than that of the PMOS transistor 60, but larger than that of the PMOS transistor 61. As an example, the current driving capability of the PMOS transistor 62 is twice as large as that of the PMOS transistor 61.

[0078] Here, in the case of the power supply voltage reducing circuits 30A and 32A, the reference voltage VSS is input to the gate of the PMOS transistor 60. Therefore, the PMOS transistor 60 is always in an ON state. The gate of the PMOS transistor 61 is connected to a signal line 66. The test mode signal TM1 is supplied to the signal line 66 via inverters 82, 83, and 84. The gate of the PMOS transistor 62 is connected to a signal line 66A. The test mode signal TM2 is supplied to the signal line 66A via inverters 91, 92, and 93. Therefore, when the test mode signal TM1 is asserted to an H level, the PMOS transistor 61 is in an ON state. When the test mode signal TM2 is asserted to an H level, the PMOS transistor 62 is in an ON state.

[0079] In the case of the power supply voltage reduction circuit 31A, the gate of the PMOS transistor 61 is connected to a signal line 67, and the gate of the PMOS transistor 62 is connected to a signal line 67A. The gate of the PMOS transistor 60 receives the result of an AND operation of the gate signals of the PMOS transistors 61 and 62. This AND operation is realized by a series connection of a NAND circuit 63 and an inverter 64. Therefore, the PMOS transistor 60 is conductive when the gate signal of at least one of the PMOS transistors 61 and 62 is at an L level.

[0080] Here, the signal line 67 is supplied with the result of an OR operation between a signal obtained by inverting the test mode signal TM1 by an inverter 82 and a signal obtained by inverting the control signal CNTL1 by an inverter 85. This OR operation is realized by a series connection of a NOR circuit 89 and an inverter 87. Therefore, when the test mode signal TM1 is at H level and the control signal CNTL1 is at H level, the PMOS transistors 60 and 61 are turned on.

[0081] Similarly, the signal line 67A is supplied with the result of an OR operation between a signal obtained by inverting the test mode signal TM2 by an inverter 91 and a signal obtained by inverting the control signal CNTL1 by an inverter 85. This OR operation is realized by a series connection of a NOR circuit 95 and an inverter 94. Therefore, when the test mode signal TM2 is at H level and the control signal CNTL1 is at H level, the PMOS transistors 60 and 62 are turned on. When both the test mode signals TM1 and TM2 are at H level and the control signal CNTL1 is at H level, the PMOS transistors 60, 61 and 62 are all turned on.

[0082] Controller 20A in Fig. 11 differs from controller 20 in Fig. 5 in that inverters 91-94, 96 and NOR circuits 95, 97 are additionally provided. Inverters 91-94 and NOR circuit 95 have already been described, and therefore description thereof will not be repeated.

[0083] A write enable signal WE is input to a first input terminal of the NAND circuit 90, and an OR operation result of the test mode signals TM1 and TM2 is input to a second input terminal. This OR operation is realized by a series connection of a NOR circuit 97 and an inverter 96. Therefore, when the control signal CNTL1 and the write enable signal WE are at H level and at least one of the test mode signals TM1 and TM2 is at H level, a reduced voltage VDD-α is supplied to the power supply line 25. In this case, the PMOS transistor 70 of the power supply voltage selection circuit 35 is turned off and the PMOS transistor 71 is turned on. On the other hand, when the control signal CNTL1 is at H level and the write enable signal WE is at L level or when both the test mode signals TM1 and TM2 are at L level, an external power supply voltage VDD is supplied to the power supply line 25. In this case, the PMOS transistor 70 of the power supply voltage selection circuit 35 is turned on and the PMOS transistor 71 is turned off. In the above explanation, it is assumed that the control signal CNTL2 is at H level.

[0084] Other points in FIG. 11 are similar to those in FIG. 5, so the same or corresponding parts are given the same reference characters and descriptions thereof will not be repeated.

[0085] Fig. 12 is a diagram for explaining the magnitude of the reduced voltage according to the test mode signals TM1 and TM2. Referring to Fig. 12, in the reduced voltage VDD-α, the voltage value of α changes depending on whether the test mode signals TM1 and TM2 are asserted to the H level or not. Specifically, this is as follows.

[0086] (i) When the test mode signals TM1 and TM2 are both at the L level, the PMOS transistor 60 in Fig. 11 is turned on, but the PMOS transistors 61 and 62 are turned off. Therefore, α=0, and the external power supply voltage VDD is supplied to the voltage supply line 33, not the reduced voltage.

[0087] (ii) When the test mode signal TM1 is at H level and the test mode signal TM2 is at L level, the PMOS transistors 60 and 61 are on, but the PMOS transistor 62 is off. Therefore, the value of α, that is, the amount of decrease in the operating margin, is small (SMALL).

[0088] (iii) When the test mode signal TM1 is at L level and the test mode signal TM2 is at H level, the PMOS transistors 60 and 62 are on, but the PMOS transistor 61 is off. Therefore, the value of α, i.e., the amount of decrease in the operating margin, is medium. The current driving capability of the PMOS transistor 62 is assumed to be twice as high as that of the PMOS transistor 61.

[0089] (iv) When the test mode signals TM1 and TM2 are both at H level, the PMOS transistors 60, 61, and 62 are all turned on. Therefore, the value of α, that is, the amount of decrease in the operating margin, is the largest (LARGE).

[0090] [Deterioration prediction test] Next, a method of performing a degradation prediction test on an SRAM circuit using the power supply voltage reducing circuits 30A to 32A and the power supply voltage selection circuits 34 and 35 shown in FIG. 11 will be described.

[0091] Fig. 13 is a block diagram showing the overall configuration of a semiconductor device according to the second embodiment. Referring to Fig. 13, a semiconductor device 110A differs from the semiconductor device 110 of Fig. 6 in that it further includes a main controller (MAIN CONTROLLER) 103. The main controller 103 includes a processor, a memory (volatile memory and non-volatile memory), and a clock circuit (CLK) 104 for timekeeping. The processor may be realized as a CPU (Central Processing Unit) of a microcomputer, or may be realized by a FPGA (Field Programmable Gate Array). Alternatively, the processor may be realized by other dedicated circuits, or may be realized by a combination of a CPU and an FPGA, and is not particularly limited.

[0092] The main controller 103 requests the field memory BIST circuit 102 to start a test (TEST CALL). In response to this, the field memory BIST circuit 102 tests the SRAM circuit 100A and transmits the test results (TEST RESULTS) to the main controller 103. The test results include the results of the normal test and the degradation prediction test.

[0093] 14 is a flowchart showing the procedure of the runtime diagnosis in the second embodiment. First, the field memory BIST circuit 102 performs an existing normal test such as a marching test (S301). In the case of the normal test, the field memory BIST circuit 102 sets the test mode signals TM1 and TM2 to the L level (negate).

[0094] Next, the field memory BIST circuit 102 judges whether the result of the normal test is pass or fail (S302). If the result of the normal test is fail (FAIL in S302), the field memory BIST circuit 102 outputs the test result to the main controller 103 (RESULTS OUTPUT) (S303). In this case, the SRAM circuit 100A of the semiconductor device 110A is faulty, so the semiconductor device 110A cannot be operated any further. Therefore, the field memory BIST circuit 102 ends the process.

[0095] On the other hand, if the normal test is passed (PASS in S302), the field memory BIST circuit 102 minimizes the voltage reduction amount α and performs a degradation prediction test (S304). Specifically, the field memory BIST circuit 102 sets the test mode signal TM1 to an H level (asserted) and sets the test mode signal TM2 to an L level. In the degradation prediction test, for example, a checkerboard test is performed.

[0096] Next, the field memory BIST circuit 102 judges whether the result of the degradation prediction test is pass or fail (S305). If the result of the degradation prediction test is fail (FAIL in S305), the field memory BIST circuit 102 outputs the test result to the main controller 103 (S306). In this case, since the SRAM circuit 100A of the semiconductor device 110A is not broken at this time, there is no need to stop the operation of the semiconductor device 110A.

[0097] Next, the field memory BIST circuit 102 performs a degradation prediction test with a medium voltage reduction amount α (S307). Specifically, the field memory BIST circuit 102 sets the test mode signal TM1 to an L level and sets the test mode signal TM2 to an H level. In the degradation prediction test, for example, a checkerboard test is performed.

[0098] Next, the field memory BIST circuit 102 judges whether the result of the degradation prediction test is pass or fail (S308). If the result of the degradation prediction test is fail (FAIL in S308), the field memory BIST circuit 102 outputs the test result to the main controller 103 (S309).

[0099] Next, the field memory BIST circuit 102 sets the voltage reduction amount α to the largest value and performs a degradation prediction test (S310). Specifically, the field memory BIST circuit 102 sets both test mode signals TM1 and TM2 to the H level. In the degradation prediction test, for example, a checkerboard test is performed.

[0100] Next, the field memory BIST circuit 102 judges whether the result of the degradation prediction test is pass or fail (S311). If the result of the degradation prediction test is fail (FAIL in S311), the field memory BIST circuit 102 outputs the test result to the main controller 103 (S312).

[0101] Thereafter, the field memory BIST circuit 102 returns the process to the first step S301, and repeats the above steps periodically or in response to a request from the main controller 103. Note that the execution order of the above steps S304, S307, and S310 may be any order.

[0102] 13, the main controller 103 measures the time from when the semiconductor device 110A starts to be used until the test result becomes "fail" based on the received test result. Based on this measurement result, the main controller 103 predicts when a failure will occur in the SRAM circuit 100A, and outputs the prediction result to the outside (OUTPUT).

[0103] Fig. 15 is a diagram for explaining a method for predicting the time of failure of an SRAM circuit. The vertical axis of Fig. 15 represents the minimum power supply voltage VDDmin at which the SRAM circuit can operate. The horizontal axis of Fig. 15 represents time. The solid line in Fig. 15 represents the case where both test mode signals TM1 and TM2 are at L level, i.e., the case of normal operation. The dashed line in Fig. 15 represents the case where at least one of the test mode signals TM1 and TM2 is at H level.

[0104] 15, the minimum power supply voltage VDDmin at which the SRAM circuit can operate increases as the operating margin deteriorates over time. When the normal power supply voltage Vo used by the user becomes equal to the minimum power supply voltage VDDmin (time T4), this indicates that the SRAM circuit 100A has actually failed.

[0105] The test mode aging characteristics shown by the dashed line correspond to the case where the aging characteristics in normal use (TM1, TM2 = L) shown by the solid line are shifted upward. Specifically, in the case of Figure 15, when the amount of reduction in power supply voltage α is the largest (i.e., TM1 = TM2 = H), the test result is a fail at time T1. When the amount of reduction in power supply voltage α is medium (i.e., TM1 = L, TM2 = H), the test result is a fail at time T2. When the amount of reduction in power supply voltage α is the smallest (i.e., TM1 = H, TM2 = L), the test result is a fail at time T3. In this case, the measurement results at times T1, T2, and T3 can be used to estimate the time T4 at which a failure actually occurs.

[0106] Fig. 16 is a flow chart showing a procedure for the main controller to predict the failure time in the semiconductor device of Fig. 13. First, the main controller 103 measures the times T1, T2, and T3 until the test result becomes a failure according to the power supply voltage reduction amount α based on the test result output from the field memory BIST circuit 102 (S401). The main controller 103 stores the measured times T1, T2, and T3 in memory (MEASURE & STORE).

[0107] Next, the main controller 103 calculates (CALCULATE) the time T4 until the SRAM circuit 100A actually fails based on the above measurement results (S402). In this case, the time of failure may be experimentally estimated based on the relationship between the voltage reduction amount α and the times T1, T2, and T3 until the test result becomes unacceptable, or the remaining margin may be quantified from the voltage reduction amount α.

[0108] Next, the main controller 103 outputs the estimated time T4 until the occurrence of a failure to the outside (S403). For example, by outputting the result to a display device of the system equipped with the semiconductor device 110A, it is possible to urge the user to take measures such as replacing the board. Alternatively, the main controller 103 may output the failure estimation result to a data center via a network. In this case, it is possible for the data center to urge the system administrator to take measures such as replacing the board. Alternatively, when performing maintenance on the system equipped with the semiconductor device 110A, a maintenance worker may retrieve information on the failure estimation result stored in the non-volatile memory of the main controller 103.

[0109] [Effects of the second embodiment] As described above, according to the semiconductor device 110A of the second embodiment, the reduction amount α of the power supply voltage can be changed. This allows the memory test to be performed by changing the degree of reduction of the operating margin, so that the time when a defect will occur can be predicted from the period until the memory test result becomes a failure. In addition, since this prediction of the time when a defect will occur is executed by the main controller 103 inside the semiconductor device 110A, no separate processing system is required. Furthermore, since the time when a defect will occur can be predicted with a certain degree of accuracy before an actual failure occurs, it is possible to encourage the user to take action to prevent the occurrence of a failure.

[0110] The invention made by the inventor has been specifically described above based on an embodiment, but it goes without saying that the present invention is not limited to the above embodiment and can be modified in various ways without departing from the gist of the invention. [Explanation of symbols]

[0111] 10 memory cell array, 20 controller, 21 row decoder, 22 column decoder, 23 write circuit, 24 read circuit, 25 power line of word line driver, 30 to 32 power supply voltage reduction circuit, 33 voltage supply line, 34, 35 power supply voltage selection circuit, 41, 42 load transistor, 43, 44 drive transistor, 45, 46 access transistor, 47, 48 connection node, 49, 50 discharge current, 60, 61, 62 PMOS transistor, 100 SRAM circuit, 101 test circuit, 102 field memory BIST circuit, 103 main controller, 110 semiconductor device, BL, / BL bit line, CA column address signal, CNTL1, CNTL2 control signal, DI write data, DO external read data, MC memory cell, PL power line of memory cell, RA row address signal, TM test mode signal, VDD external power supply voltage, VDD-α reduced voltage, VSS reference voltage (ground), WD Word line driver, WE write enable signal, WL word line.

Claims

1. A semiconductor device including a static random access memory (SRAM) circuit that operates based on an external power supply voltage, The SRAM circuit includes: a first bit line pair extending in a first direction; a first word line extending in a second direction intersecting the first direction; a first word line driver that drives the first word line; a first memory cell electrically connected to the first bit line pair and the first word line; a first power supply line for supplying an operating voltage to the first memory cell; a power supply voltage reducing circuit for generating a reduced voltage by reducing the external power supply voltage; a first power supply voltage selection circuit that selects one of the external power supply voltage and the reduced voltage as a drive voltage for the first word line driver; a second power supply voltage selection circuit that selects one of the external power supply voltage and the reduced voltage as the operating voltage to be supplied to the first power supply line; an internal controller for controlling an operation of the SRAM circuit; the internal controller causes the first power supply voltage selection circuit to select the reduced voltage as a drive voltage for the first word line driver and to select the external power supply voltage as a voltage to be supplied to the first power supply line when writing test data to the first memory cell in a test mode; The semiconductor device, wherein when reading the test data from the first memory cell in the test mode, the internal controller causes the first power supply voltage selection circuit to select the external power supply voltage as the drive voltage of the first word line driver, and causes the second power supply voltage selection circuit to select the reduced voltage as the voltage to be supplied to the first power supply line.

2. The SRAM circuit includes: a second bit line pair extending in the first direction; a second memory cell electrically connected to the second bit line pair and the first word line; a second power supply line for supplying an operating voltage to the second memory cell; a third power supply voltage selection circuit that selects one of the external power supply voltage and the reduced voltage as the operating voltage to be supplied to the second power supply line; 2. The semiconductor device according to claim 1, wherein the internal controller causes the third power supply voltage selection circuit to select the reduced voltage as the voltage to be supplied to the second power supply line when the test data is read from the first memory cell in the test mode.

3. 2. The semiconductor device according to claim 1, wherein said power supply voltage reducing circuit is capable of selecting, as said reduced voltage, a first reduced voltage and a second reduced voltage that is lower than said first reduced voltage.

4. The semiconductor device further includes a BIST (Built-In Self-Test) circuit, 4. The semiconductor device according to claim 3, wherein the BIST circuit determines whether or not the test data written to the first memory cell in the test mode matches the test data read from the first memory cell after the test data is written in the test mode, and outputs a determination result.

5. The semiconductor device further includes a main controller that receives the determination result from the BIST circuit; 5. The semiconductor device according to claim 4, wherein said main controller records the elapsed time from the start of use of said semiconductor device until a mismatch occurs between said written test data and said read test data.

6. 6. The semiconductor device according to claim 5, wherein the main controller predicts a time when the SRAM circuit of the semiconductor device will fail based on a difference between the elapsed time when the first reduced voltage is selected as the reduced voltage and the elapsed time when the second reduced voltage is selected as the reduced voltage.

7. The semiconductor device according to claim 6 , wherein said main controller outputs said predicted failure time to an external device of said semiconductor device.

8. A semiconductor device including an SRAM (Static Random Access Memory) circuit that operates based on an external power supply voltage, The SRAM circuit includes: a first bit line pair extending in a first direction; a first word line extending in a second direction intersecting the first direction; a first word line driver that drives the first word line; a first memory cell electrically connected to the first bit line pair and the first word line; a first power supply line for supplying an operating voltage to the first memory cell; a power supply voltage reducing circuit for generating a reduced voltage by reducing the external power supply voltage; a first power supply voltage selection circuit that selects one of the external power supply voltage and the reduced voltage as a drive voltage for the first word line driver; a second power supply voltage selection circuit that selects one of the external power supply voltage and the reduced voltage as the operating voltage to be supplied to the first power supply line; The power supply voltage reduction circuit includes: a first transistor connected between a power supply node receiving the external power supply voltage and an output node outputting the reduced voltage; a second transistor connected between a ground node receiving a reference voltage and the output node; A semiconductor device, wherein a current driving capability of the first transistor is greater than a current driving capability of the second transistor.

9. The power supply voltage reduction circuit comprises: a first transistor connected between a power supply node receiving the external power supply voltage and an output node outputting the reduced voltage; a second transistor connected between a ground node receiving a reference voltage and the output node; a third transistor connected in parallel with the second transistor; a current driving capability of the first transistor is greater than a current driving capability of the second transistor and greater than a current driving capability of the third transistor; 4. The semiconductor device according to claim 3, wherein a current driving capability of said third transistor is greater than a current driving capability of said second transistor.

10. supplying a first reduced voltage obtained by reducing an external power supply voltage as a drive voltage to a first word line driver that drives a first word line connected to a first memory cell of the SRAM circuit, and writing first test data to the first memory cell while supplying the external power supply voltage to a first power supply line that supplies an operating voltage to the first memory cell; supplying the external power supply voltage as a drive voltage to the first word line driver and reading the written first test data from the first memory cell while supplying the first reduced voltage to the first power supply line; and determining whether the written first test data and the read first test data match.

11. supplying a second reduced voltage, which is lower than the first reduced voltage obtained by reducing the external power supply voltage, to the first word line driver as a drive voltage, and writing second test data to the first memory cell while supplying the external power supply voltage to the first power supply line; supplying the external power supply voltage as a drive voltage to the first word line driver and reading the written second test data from the first memory cell while supplying the second reduced voltage to the first power supply line; determining whether the written second test data and the read second test data match; measuring an elapsed time from a start of use of the SRAM circuit until a mismatch occurs between the first test data and the second test data; 11. The method of testing an SRAM circuit according to claim 10, further comprising: predicting a time when the SRAM circuit will fail based on the measured elapsed time.

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