Power supply semiconductor integrated circuit and power supply regulator circuit

Abstract

To provide a power source semiconductor integrated circuit capable of detecting occurrence of an open-circuit failure in any one or more loads of plural loads.SOLUTION: A power source semiconductor integrated circuit includes: an output transistor connected between a voltage input terminal, to which a dc voltage is inputted, and a voltage output terminal; and a control circuit that controls the output transistor according to a feedback voltage of an output. The power source semiconductor integrated circuit further includes: an open-circuit failure detection circuit that includes plural voltage comparison circuits each of which compares each voltage of threshold voltages on predetermined plural stages with a voltage proportional to a voltage at the voltage output terminal, and that detects an open-circuit condition of the voltage output terminal; and plural detection result output terminals through which a result of detection by the open-circuit failure detection circuit is outputted to outside. The threshold voltages on the plural stages are designated so that the open-circuit failure detection circuit can detect the open-circuit condition of some of the plural loads or all of the loads connected to the voltage output terminal.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a power supply semiconductor integrated circuit (power supply IC) constituting a DC power supply device such as a voltage regulator or a DC-DC converter that converts DC voltage, and in particular to a technology that is effective when used for open detection of an output terminal to which a multi-channel load is connected. [Background technology]

[0002] 2. Description of the Related Art A series regulator (hereinafter, abbreviated as regulator) is a power supply device that outputs a DC voltage of a desired potential by controlling a transistor provided between a DC voltage input terminal and an output terminal. In automobiles equipped with digital terrestrial (terrestrial digital television broadcasting) tuners, power is supplied to the vehicle's electronic devices, such as the antenna for digital terrestrial broadcasting, by an on-board regulator. In addition, in on-board digital terrestrial broadcasting tuners that support full-segment broadcasting, the tuner adjusts the reception sensitivity and switches between full-segment and one-segment broadcasting, and a diversity antenna, which is an equivalent antenna for 4ch (channels), is generally used as the antenna for digital terrestrial broadcasting to optimize reception conditions.

[0003] On the other hand, since in-vehicle tuners and antennas are connected to the in-vehicle regulator via a connector, vibrations of the vehicle body can cause the connector to come loose, opening the output terminal of the power supply or causing a short circuit inside the load. For this reason, some in-vehicle regulators are equipped with a function to detect such abnormal conditions. In view of this, an invention has been proposed relating to a semiconductor integrated circuit for a regulator (regulator IC) that is configured to include an open circuit anomaly detection comparator that detects the open state of the output terminal and a short circuit anomaly detection comparator that detects the short state, and to generate an anomaly detection signal and output it from the output terminal (e.g., Patent Documents 1 and 2). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2017-45096 A [Patent Document 2] JP 2018-55545 A Summary of the Invention [Problem to be solved by the invention]

[0005] In the past, in vehicle-mounted digital terrestrial broadcasting systems equipped with multiple antennas, it was common to supply power to the multiple antennas from a common regulator. In this case, even if any one of the 1ch antennas becomes open, the system will continue to operate without detecting the abnormality because it will receive signals on the other channels. On the other hand, it is also possible to provide a regulator with an open abnormality detection function for each antenna as a load so that it can detect when any one of the 1ch antennas becomes open. However, doing so requires multiple regulators, which poses the problem of significant increases in costs and mounting area.

[0006] The present invention has been made with attention to the problems described above, and an object of the present invention is to provide a semiconductor integrated circuit for a power supply and a regulator circuit for a power supply which can supply power to a plurality of loads and detect and output an open circuit abnormality even if an open circuit abnormality occurs in any one of the loads or in a plurality of the loads. [Means for solving the problem]

[0007] In order to achieve the above object, the present invention provides 1. A power supply semiconductor integrated circuit comprising: an output transistor connected between a voltage input terminal to which a DC voltage is input and a voltage output terminal; and a control circuit for controlling the output transistor in response to a feedback voltage of an output, an open circuit abnormality detection circuit having a plurality of voltage comparator circuits for comparing a voltage proportional to the voltage of the voltage output terminal with each of a plurality of predetermined threshold voltage levels, and for detecting an open circuit state of the voltage output terminal; a plurality of detection result output terminals for outputting a detection result by the open circuit abnormality detection circuit to an outside; The multiple-stage threshold voltages are configured to be set so that the open circuit abnormality detection circuit can detect an open circuit state of any of a plurality of loads connected to the voltage output terminal and an open circuit state of all of the loads.

[0008] According to the power supply semiconductor integrated circuit having the above-described configuration, power can be supplied from a single semiconductor integrated circuit to a plurality of loads connected to the voltage output terminal, thereby avoiding a significant increase in cost and mounting area, and the open circuit abnormality detection circuit can distinguish between an open circuit state of any of the plurality of loads connected to the voltage output terminal and an open circuit state of all of the loads.

[0009] Also, there is provided a power supply regulator circuit including an output transistor connected between a voltage input terminal to which a DC voltage is input and a voltage output terminal, and a control circuit that controls the output transistor in response to a feedback voltage of an output, an open circuit abnormality detection circuit having a plurality of voltage comparator circuits for comparing a voltage proportional to the voltage of the voltage output terminal with each of a plurality of predetermined threshold voltage levels, and for detecting an open circuit state of the voltage output terminal; A detection result by the open circuit abnormality detection circuit can be output to an external device. The multiple-stage threshold voltages may be configured to be set so that the open circuit abnormality detection circuit can detect an open circuit state of any of a plurality of loads connected to the voltage output terminal and an open circuit state of all of the loads. Effect of the Invention

[0010] According to the present invention, it is possible to provide a power supply semiconductor integrated circuit (regulator IC, IC for DC-DC converter) and a power supply regulator circuit that can supply power to a plurality of loads and detect and output an open circuit abnormality even if an open circuit abnormality occurs in any one of the loads or in a plurality of the loads. [Brief description of the drawings]

[0011] [Figure 1] 1 is a circuit configuration diagram showing an embodiment of a regulator IC to which the present invention is applied. [Diagram 2] FIG. 13 is a diagram showing the relationship between the current consumption of two channel antennas and the state of the output terminal when the variation a of the current consumption of one antenna is 33%. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. Fig. 1 shows an embodiment of a series regulator as a DC power supply device to which the present invention is applied. In Fig. 1, the part enclosed by the dashed line is formed as a semiconductor integrated circuit (regulator IC) 10 on a semiconductor chip such as single crystal silicon, and a capacitor Co is connected to the output terminal OUT of the regulator IC 10 to function as a DC power supply device that supplies a stable DC voltage.

[0013] In the regulator IC10 of this embodiment, as shown in FIG. 1, a voltage control transistor Q1 made of a P-channel MOS transistor is connected between a voltage input terminal IN to which a DC voltage VDD is applied and an output terminal OUT, and bleeder resistors R1 and R2 for dividing the output voltage Vout are connected in series between the output terminal OUT and a ground line to which a ground potential GND is applied.

[0014] The voltage VFB divided by the output voltage dividing resistors R1 and R2 is fed back to the non-inverting input terminal of an error amplifier 11, which serves as an error amplifier circuit that controls the gate terminal of the voltage control transistor Q1. The error amplifier 11 controls the voltage control transistor Q1 in accordance with the potential difference between the output feedback voltage VFB and a predetermined reference voltage Vref, so that the output voltage Vout becomes a desired potential. In the regulator IC10 of this embodiment, the characteristics and size of the voltage control transistor Q1 are designed so that even when two antennas ANT1 and ANT2 are connected as loads to the output terminal OUT, the required current can flow to each of the loads.

[0015] The regulator IC10 of this embodiment is also provided with a reference voltage circuit 12 for generating a reference voltage Vref to be applied to the inverting input terminal of the error amplifier 11, a bias circuit 13 for passing an operating current to the error amplifier 11 and the reference voltage circuit 12, a current limit circuit 14 connected to the gate terminal of the voltage control transistor Q1 for limiting the output current, and a thermal shutdown (TSD) circuit 15 for stopping the operation of the error amplifier 11 and turning off the transistor Q1 when the chip temperature rises above a predetermined temperature. CE is an external terminal to which a signal for turning the IC on and off is input.

[0016] The reference voltage circuit 12 can be composed of a band gap reference, a series resistor, a Zener diode, etc. The bias circuit 13 has a function of supplying or cutting off a bias current to the error amplifier 11 in response to a control signal input to an external terminal CE from an external microcomputer (CPU), etc. The current limit circuit 14 limits the output current Iout by clamping so that the drain current does not increase beyond a predetermined value when the output current Iout increases due to an abnormality in the load, the output voltage drops, and the error amplifier 11 tries to lower the gate voltage so that more current flows through the transistor Q1. This output current Iout flows as the consumption current Icc of the antennas ANT1 and ANT2, which serve as loads connected to the output terminal OUT.

[0017] Furthermore, in the regulator IC10 of this embodiment, transistors Q2, Q3, and Q4 are provided in parallel with the voltage control transistor Q1, forming a current mirror circuit with Q1, and the same voltage as that applied to the gate terminal of the voltage control transistor Q1 is applied to the gate terminals of these transistors Q2 to Q4 as control terminals. This allows a current proportional to the drain current of Q1 (1 / N current) to flow through Q2 to Q4 according to the size ratio N of the elements. When the transistor Q1 is configured by connecting N transistors of the same size in parallel and each of Q2 to Q4 is configured by one transistor, the current is set to flow in proportion to the number of elements.

[0018] In addition, the regulator IC10 of this embodiment is provided with an external terminal P1 for connecting a resistor Rop that performs current-to-voltage conversion outside the chip, and an external terminal P2 for connecting a resistor Rsc, and the drain terminal of the current mirror transistor Q2 is connected to the external terminal P1, and the drain terminal of the current mirror transistor Q3 is connected to the external terminal P2. Further, there are provided comparators CMP1 and CMP2 for detecting open anomalies, the inverting input terminal of which is connected to the external terminal P1 and the reference voltages Vop_1 and Vop_2 (Vop_1>Vop_2) are applied to the non-inverting input terminal, and a comparator CMP3 for detecting short anomalies, the non-inverting input terminal of which is connected to the external terminal P2 and the reference voltage Vsc is applied to the inverting input terminal. Although not particularly limited, the comparators CMP1 and CMP2 for detecting open anomalies and the comparator CMP3 for detecting short anomalies have hysteresis characteristics.

[0019] The resistance value of the external resistor Rop is set so that the voltage across both terminals of the resistor becomes the same as the reference voltages Vop_1 and Vop_2 when a relatively small detection current for an open circuit abnormality flows through the current mirror transistor Q2. How to set the reference voltages Vop_1 and Vop_2 will be explained in detail later. On the other hand, the resistance value of the external resistor Rsc is set so that the voltage across both terminals of the resistor becomes the same as the reference voltage Vsc when a relatively large detection current for a short circuit abnormality flows through the current mirror transistor Q3.

[0020] Therefore, if one of the two antennas connected to the output terminal OUT becomes disconnected or broken, reducing the current flowing through the voltage control transistor Q1 and the current mirror transistor Q2, the output OP_OUT1 of the comparator CMP1 changes from low level (L) to high level (H), and if both become disconnected and the current flowing through the voltage control transistor Q1 and the current mirror transistor Q2 decreases further, the outputs OP_OUT1 and OP_OUT2 of the comparators CMP1 and CMP2 both change from L to H, detecting an open abnormality. In this manner, in this embodiment, the current values ​​for detecting open and short abnormalities are set by the external resistors Rop and Rsc, so that the detection current value (threshold value) can be set arbitrarily according to the system used. Note that the same voltage value can be used as either the reference voltage Vop_1 or Vop_2 used in the comparator CMP1 or CMP2, and the reference voltage Vsc used in the comparator CMP3.

[0021] The regulator IC10 of this embodiment is also provided with a logic circuit 16 to which the outputs OP_OUT1, OP_OUT2 of the open circuit abnormality detection comparators CMP1, CMP2 and the output SC_OUT of the short circuit abnormality detection comparator CMP3 are input. Furthermore, there are provided N-channel MOS transistors Q5 and Q6 whose gate terminals receive the output of the logic circuit 16. The regulator IC is provided with external terminals P3 and P4 for outputting abnormality detection signals Err_1 and Err_2 to an external CPU or the like in an open-drain format, with the drain terminal of the transistor Q5 being connected to the external terminal P3 and the drain terminal of the transistor Q6 being connected to the external terminal P4.

[0022] Table 1 shows a truth table indicating the relationship between the state of the output terminal OUT, the outputs OP_OUT1, OP_OUT2, and SC_OUT of the comparators CMP1 to CMP3, and the abnormality detection signals Err_1 and Err_2. The logic circuit 16 is configured so that when OP_OUT1, OP_OUT2, and SC_OUT having the relationship shown in Table 1 are input, the logic circuit 16 outputs signals for driving the transistors Q5 and Q6 so that the abnormality detection signals Err_1 and Err_2 having the relationship shown in Table 1 are output. Note that the truth table in Table 1 is an example and is not limited to this. [Table 1]

[0023] As can be seen from Table 1 above, in the regulator IC10 of this embodiment, a one-channel open state in which one of the antennas ANT1 and ANT2 connected to the output terminal OUT is disconnected, a two-channel open state in which both of the antennas ANT1 and ANT2 are disconnected, and a short state in which a short circuit occurs in one of the antennas ANT1 and ANT2 can be distinguished and output using 2-bit abnormality detection signals Err_1 and Err_2, and can be notified to a CPU, etc. Therefore, when a circuit for detecting an open abnormality in the output terminal and a circuit for detecting a short abnormality in the output terminal are provided, the abnormality detection results can be distinguished and output with a small number of external terminals.

[0024] Next, a method for setting the reference voltages Vop_1, Vop_2 of the open circuit abnormality detection comparators CMP1, CMP2 in the regulator IC10 of this embodiment that performs the abnormality detection described above will be described. When using two comparators CMP1 and CMP2 to detect the 1 channel open state and the 2 channel open state, if there is a large variation in the consumption current Icc flowing through the antennas ANT1 and ANT2 as loads, it is difficult to distinguish between these abnormalities and detect them. Therefore, first consider the range of variation in the consumption current Icc required to distinguish between and detect the two open states.

[0025] Table 2 shows the relationship between the minimum (Min), median (Typ), and maximum (Max) current consumption when there is one antenna (1ch) and when there are two antennas (2ch), assuming that the variation in current consumption Icc for one antenna is ±a%. [Table 2] As shown in Table 2, when there are two antennas (2ch), the current consumption is twice as much as when there is one antenna (1ch).

[0026] Also, Figure 2 shows the relationship between the current consumption of the 2ch antenna and the state of the output terminal when the variation a of the current consumption of one antenna is 33%. As can be seen from Figure 2, if the maximum value (Icc+a%) of the current consumption when there is one antenna (1ch) is smaller than the minimum value (Icc-a%) × 2 when there are two antennas (2ch), then by setting a threshold value (Vop_1) at the voltage corresponding to the boundary between (Icc+a%) and (Icc-a%) × 2, it is possible to distinguish and detect whether the output terminal is in a normal state or an abnormal state in which one of the antennas is disconnected (1ch open). Specifically, a current that is 1 / N of the current flowing through the voltage control transistor Q1 flows through the current mirror transistor Q2, which has an external resistor Rop connected in series. Therefore, by setting Vop_1=Rop×(Icc+a%) / N, it is possible to distinguish between when the output terminal is normal and when 1ch is open.

[0027] Here, the above variation a is expressed by the following formula: Icc(1+a / 100)=Icc(1-a / 100)×2 By solving this, we obtain a = 100 / 3 ≒ 33.3%. From this, we can see that in the case of a 2-channel antenna, if the variation in current consumption Icc is within ±33.3%, it is possible to distinguish and detect whether the output terminal is in a normal state from an abnormal state in which one of the antennas is disconnected (1-channel open).

[0028] Also, from Figure 2, Vop_2 is set to a voltage corresponding to the current consumption (Icc-a%). Specifically, by setting Vop_2 = Rop × (Icc-a%) / N, it is possible to distinguish and detect an abnormal state in which one antenna is disconnected (1ch open) from an abnormal state in which both antennas are disconnected (2ch open). If the antenna used is changed and the antenna current consumption Icc changes, the resistance value of the external resistor Rop connected to the external terminal P1 can be adjusted to detect the open state of the output terminal using the same principle as described above.

[0029] Here, the above variation a ≒ 33.3% is for the case where there are two loads (antennas) connected to the output terminal OUT. When there are n antennas (nch), the following formula is used: a=100÷{n×(n+1)÷2} This formula shows that when there are three antennas (3ch), the variation range of current consumption in which an open anomaly can be distinguished is within approximately ±16.6%, and when there are four antennas (4ch), the variation range of current consumption in which an anomaly can be distinguished is within ±10%. In these cases, three and four comparators are required to detect open anomalies, respectively. It is also recommended that the anomaly detection signal be configured to be 3 or more bits and output.

[0030] Therefore, if the variation a in current consumption satisfies the above condition, any number of antennas with the same current consumption can be connected to the output terminal OUT of the regulator IC of this embodiment to pass current. This makes it possible to detect an open state caused by any one of the antennas being disconnected or an antenna being broken, while avoiding the increased cost that would accompany providing multiple regulator ICs corresponding to multiple antennas.

[0031] As described above, in the regulator IC10 of this embodiment, two antennas can be connected to the output terminal OUT to pass current, and a one-channel open state in which one of the two antennas is disconnected, a two-channel open state in which both of the two antennas are disconnected, and a short state in which a short circuit has occurred in one of the two antennas can be distinguished and output using 2-bit abnormality detection signals Err_1, Err_2 to notify a CPU, etc.

[0032] Therefore, while maintaining the function of detecting open and short abnormalities, it is possible to reduce costs, mounting area, and IC power consumption compared to providing a regulator for each antenna. Therefore, when configuring an in-vehicle 4-channel terrestrial digital antenna that supports full-segment broadcasting, it is sufficient to provide only two regulator ICs. In addition, because the three abnormal conditions can be distinguished by a 2-bit abnormality detection signal, the number of terminals provided on the regulator IC can be reduced, allowing the use of a small, inexpensive package and achieving cost reduction.

[0033] Incidentally, instead of providing comparators CMP1, CMP2 for detecting open abnormalities within the regulator IC, it is also possible to provide an A / D converter on the microcontroller side and supply the voltage of external terminal P1 to which resistor Rop is connected to the microcontroller so as to detect open abnormalities on the microcontroller side. However, by configuring to output 2-bit abnormality detection signals Err_1, Err_2 as in the above embodiment, there is no need to provide an A / D converter in the I / O section of the microcontroller, and there is no need to set a threshold value for discrimination, which has the advantage of facilitating system design.

[0034] Furthermore, when the load connected to the output terminal is an antenna connected to a terrestrial digital television broadcast tuner mounted in a vehicle, the antenna of the vehicle-mounted terrestrial digital tuner is relatively prone to coming off due to vibration of the vehicle body, so by supplying current to the antenna from a power supply device using the power supply semiconductor integrated circuit of the above embodiment, it is possible to distinguish and detect the open state of any of the multiple antennas and the open state of all the loads.

[0035] (Modification) In the regulator IC (FIG. 1) of the above embodiment, a 1-channel open state, a 2-channel open state, and a short state are detected, and the 2-bit abnormality detection signals Err_1 and Err_2 are used to distinguish and output the signals, but the short detection function (comparator CMP3) may be omitted. In addition, when the short detection function is omitted, the logic circuit 16 may be omitted, and the outputs of the comparators CMP1 and CMP2 for open abnormality detection may be directly input to the gate terminals of the transistors Q5 and Q6, or a simple circuit such as a delay circuit or a buffer may be provided instead of the logic circuit 16, and input to the gate terminals of Q5 and Q6.

[0036] Also, when the short circuit detection function is omitted, the logic circuit 16 may be configured to input the output TSD_OUT of the thermal shutdown (TSD) circuit 15, generate a signal that is logically combined with the outputs of the open circuit abnormality detection comparators CMP1 and CMP2, and output the signal as 2-bit abnormality detection signals Err_1 and Err_2. In this case, "short circuit" in Table 1 should be read as "TSD activated."

[0037] Furthermore, in the regulator IC (FIG. 1) of the above embodiment, an antenna is connected to the output terminal OUT as a load, and the regulator IC (FIG. 1) is configured as an in-vehicle power supply device for terrestrial digital broadcasting. However, the load is not limited to an antenna, and the regulator IC can be applied to a power supply device to which two or more loads with the same current consumption are connected. In addition, for example, in the case of two loads, if the condition that the minimum side of the variation in the total current consumption when the two loads are normally connected does not overlap with the maximum side of the variation in the current consumption when one of the loads is disconnected (including disconnection) is satisfied, the regulator IC can be used as a power supply device in which two loads of different types, i.e., two loads with different current consumption, are connected to the output terminal OUT.

[0038] Although the invention made by the present inventor has been specifically described based on the embodiment, the present invention is not limited to the above embodiment. For example, in the above embodiment, MOS transistors are used as transistors constituting the internal circuit of the regulator IC10, but bipolar transistors may be used instead of MOS transistors. In the above embodiment, the present invention is described as being applied to a regulator IC, but the present invention is not limited to regulator ICs and can also be applied to ICs that constitute an isolated DC-DC converter. [Explanation of symbols]

[0039] 10...regulator IC, 11...error amplifier, 12...reference voltage circuit, 13...bias circuit, 14...current limit circuit, 15...thermal shutdown circuit, 16...logic circuit, CMP1, CMP2...comparator for detecting open abnormality, CMP3...comparator for detecting short abnormality, Q1...transistor for voltage control (output transistor), Q2, Q3, Q4...current mirror transistor, Q5, Q6...transistor for outputting abnormality detection signal, P3, P4...external terminal (detection result output terminal)

Claims

1. A power supply semiconductor integrated circuit comprising: an output transistor connected between a voltage input terminal to which a DC voltage is input and a voltage output terminal; and a control circuit that controls the output transistor in response to a feedback voltage of an output, an open circuit abnormality detection circuit having a plurality of voltage comparator circuits for comparing a voltage proportional to the voltage of the voltage output terminal with each of a plurality of predetermined threshold voltage levels, and for detecting an open circuit state of the voltage output terminal; a plurality of detection result output terminals for outputting a detection result by the open circuit abnormality detection circuit to an outside; the multiple-stage threshold voltages are set so that the open circuit abnormality detection circuit can detect an open circuit state of any of a plurality of loads connected to the voltage output terminal and an open circuit state of all of the loads.

2. the plurality of loads connected to the voltage output terminal are two antennas, and the plurality of voltage comparison circuits are two; 2. The power supply semiconductor integrated circuit according to claim 1, wherein the multiple threshold voltage stages are set to two stages, one of the two voltage stages is a voltage corresponding to a value between a maximum current consumption value when there is one antenna and a minimum current consumption value when there are two antennas, and the other of the two voltage stages is a voltage corresponding to the minimum current consumption value when there is one antenna.

3. 3. The power supply semiconductor integrated circuit according to claim 2, wherein the antenna has a current consumption variation within ±33.3%.

4. a first transistor forming a current mirror circuit together with the output transistor; a resistive element connected in series with the first transistor; an external terminal to which the resistor element is connected as an external element; 4. The power supply semiconductor integrated circuit according to claim 1, wherein the plurality of voltage comparison circuits compare a voltage obtained by current-voltage conversion by the resistance element with each of the plurality of threshold voltage levels.

5. The plurality of detection result output terminals are two, a second transistor forming a current mirror circuit with the output transistor; a short circuit abnormality detection circuit that detects a short circuit state of the voltage output terminal based on a voltage of a resistor element connected in series with the second transistor; a logic circuit which receives the outputs of the two voltage comparators and the output of the short circuit abnormality detection circuit as inputs, and generates and outputs a two-bit signal which indicates one of four states, i.e., one channel open, two channel open, short, and normal; 5. The power supply semiconductor integrated circuit according to claim 1, wherein a 2-bit signal corresponding to the 2-bit output signal of the logic circuit is output from the plurality of detection result output terminals.

6. 6. The power supply semiconductor integrated circuit according to claim 1, wherein the load is an antenna connected to a tuner for terrestrial digital television broadcasting mounted on a vehicle.

7. A power supply regulator circuit comprising: an output transistor connected between a voltage input terminal to which a DC voltage is input and a voltage output terminal; and a control circuit that controls the output transistor in response to a feedback voltage of an output, an open circuit abnormality detection circuit having a plurality of voltage comparator circuits for comparing a voltage proportional to the voltage of the voltage output terminal with each of a plurality of predetermined threshold voltage levels, and for detecting an open circuit state of the voltage output terminal; A detection result by the open circuit abnormality detection circuit can be output to an external device. a power supply regulator circuit, characterized in that the multiple-stage threshold voltages are set so that the open circuit abnormality detection circuit can detect an open circuit state of any of a plurality of loads connected to the voltage output terminal and an open circuit state of all of the loads.

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