Chopper amplifier tracks multiple input offsets.

Abstract

To disclose herein a chopper amplifier with tracking of multiple input offsets.SOLUTION: In certain embodiments, a chopper amplifier includes chopper amplifier circuitry including an input chopping circuit, an amplification circuit, and an output chopping circuit, electrically connected along a signal path. The amplification circuit includes two or more pairs of input transistors, from which a control circuit chooses a selected pair of input transistors to amplify an input signal. The chopper amplifier further includes an offset correction circuit that senses the signal path to generate an input offset compensation signal for the amplification circuit. Furthermore, the offset correction circuit separately tracks an input offset of each of the two or more pairs of input transistors.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE Embodiments of the present invention relate to electronic systems, and more particularly, to amplifiers. [Background technology]

[0002] An amplifier, such as an operational amplifier or an instrumentation amplifier, may include a chopper circuit that helps compensate for the input offset voltage of the amplifier. For example, a chopper amplifier may include an input chopping circuit that may be used to chop the amplifier's input signal during an input chopping operation, thereby upshifting the frequency of the amplifier's input signal. The chopper amplifier may further include an amplifier circuit for amplifying the chopped input signal, and an output chopping circuit for downshifting the frequency of the amplified signal during an output chopping operation. By providing chopping in this manner, the amplifier's input offset voltage is separated in frequency from the chopped input signal and therefore may be filtered or otherwise attenuated. Summary of the Invention [Means for solving the problem]

[0003] A chopper amplifier that tracks multiple input offsets is disclosed herein. In a particular embodiment, the chopper amplifier includes a chopper amplifier circuit including an input chopping circuit, an amplifier circuit, and an output chopping circuit electrically connected along a signal path. The amplifier circuit includes two or more input transistor pairs from which a control circuit selects a selected input transistor pair for amplifying an input signal. The chopper amplifier further includes an offset correction circuit that senses the signal path and generates an input offset compensation signal for the amplifier circuit. Furthermore, the offset correction circuit separately tracks the input offset of each of the two or more input transistor pairs. Thus, the selected input transistor pair can be changed with little or no delay in the offset correction circuit that compensates for the input offset and suppresses chopping ripple. In particular, since the offset correction circuit separately tracks the input offset of each input transistor pair, the input offset compensation signal can be quickly updated to a signal value suitable for compensation in response to changing the selected input transistor pair.

[0004] In one embodiment, a chopper amplifier for tracking multiple input offsets is provided. The chopper amplifier includes a chopper amplifier circuit including an input chopping circuit configured to chop an input signal to generate a chopped input signal, an amplifier circuit configured to amplify the chopped input signal to generate an amplified signal, the amplifier circuit including two or more selectable input transistor pairs, an output chopping circuit configured to chop the amplified signal to generate a chopped output signal, and a control circuit configured to select a selected input transistor pair from the two or more input transistor pairs, the selected input transistor pair configured to amplify the chopped input signal. The chopper amplifier further includes an offset correction circuit configured to generate an input offset compensation signal for the chopper amplifier circuit, the offset correction circuit separately tracking the input offset of each of the two or more input transistor pairs.

[0005] In another aspect, a method of amplification is provided that includes chopping an input signal using an input chopping circuit to generate a chopped input signal, selecting an input transistor pair from two or more input transistor pairs of an amplifier circuit using a control circuit, amplifying the chopped input signal using the selected input transistor pair to generate an amplified signal, chopping the amplified signal using an output chopping circuit to generate a chopped output signal, and compensating the amplifier circuit using an input offset compensation signal generated by an offset correction circuit that includes separately tracking an input offset of each of the two or more input transistor pairs.

[0006] In another aspect, a chopper amplifier includes a pair of input terminals, an input chopping circuit including an input coupled to the pair of input terminals, an amplifier circuit including an input coupled to an output of the input chopping circuit, the amplifier circuit including two or more selectable input transistor pairs, an output chopping circuit including an input coupled to an output of the amplifier circuit, and a control circuit configured to select a selected input transistor pair from the two or more input transistor pairs to provide amplification. The chopper amplifier further includes an offset correction circuit configured to separately track an input offset of each of the two or more input transistor pairs and to generate an input offset compensation signal to compensate the amplifier circuit. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a schematic diagram of a chopper amplifier according to one embodiment. [Figure 2A] FIG. 13 is a schematic diagram of a chopper amplifier according to another embodiment. [Figure 2B] FIG. 13 is a schematic diagram of a chopper amplifier according to another embodiment. [Diagram 3] FIG. 13 is a schematic diagram of a chopper amplifier according to another embodiment. [Figure 4] FIG. 13 is a schematic diagram of a chopper amplifier according to another embodiment. [Diagram 5]FIG. 13 is a schematic diagram of a chopper amplifier according to another embodiment. [Figure 6] FIG. 13 is a schematic diagram of a chopper amplifier according to another embodiment. [Figure 7] FIG. 2 is a schematic diagram of one embodiment of an amplifier circuit of a chopper amplifier. [Figure 8] FIG. 2 is a schematic diagram of one embodiment of a chopping switch that can be used in a chopper amplifier. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] In the following detailed description of the embodiments, various descriptions of specific embodiments of the present invention are presented. However, the present invention can be embodied in a number of different ways. In this description, reference is made to the drawings, in which like reference numbers may indicate identical or functionally similar elements. It will be understood that the elements illustrated in the drawings are not necessarily drawn to scale. Furthermore, it will be understood that certain embodiments can include more elements than shown in the drawings and / or a subset of the elements shown in the drawings. Furthermore, some embodiments can incorporate any suitable combination of features from two or more drawings.

[0009] Without compensation, the amplifier may have an input offset voltage and / or low frequency noise, such as flicker noise or 1 / f noise, which has an associated noise power spectral density (PSD) that is greater at lower frequencies.

[0010] To reduce or eliminate the input offset voltage and / or low frequency noise, the amplifier may include a chopper circuit. An amplifier having a chopper circuit is referred to as a chopper amplifier. In one embodiment, the chopper amplifier includes an input chopping circuit that chops or modulates the amplifier's input signal during an input chopping operation, thereby upshifting the frequency of the amplifier's input signal. In addition, the chopper amplifier includes an amplification circuit that amplifies the chopped input signal, and an output chopping circuit that chops or demodulates the amplified signal during an output chopping operation. By providing chopping in this manner, the amplifier's input offset voltage and / or low frequency noise are separated in frequency from the desired signal and can therefore be filtered or otherwise attenuated.

[0011] In certain implementations, the chopper amplifier may further include an auto-zero circuit. Including both an auto-zero circuit and a chopper circuit in a chopper amplifier may further lower the overall input offset voltage and / or low frequency noise. The teachings herein are applicable not only to chopper amplifiers that provide chopping, but also to chopper amplifiers that combine chopping with auto-zeroing and / or other compensation schemes.

[0012] The chopping action of the amplifier may result in ripple appearing in the amplifier's output voltage. The chopping ripple may have a magnitude that varies in relation to the magnitude of the amplifier's input offset voltage and / or low frequency noise. Thus, chopping may result in the amplifier's input offset voltage and / or low frequency noise not being cancelled but instead being modulated by the chopping frequency to produce chopping ripple that disrupts the spectral integrity of the amplifier's output signal.

[0013] A low pass post-filter may be included after the output chopping circuit to filter chopping ripple associated with the modulated input offset voltage and / or modulated low frequency noise, although it may be desirable to reduce the input offset voltage and / or low frequency noise of the amplifier to avoid the need for a post-filter or to relax the design constraints of the post-filter. In another embodiment, a switched capacitor notch filter may be included after the output chopping circuit to provide attenuation of the chopping ripple.

[0014] Feedback and / or feed-forward correction paths can be used to provide input offset compensation and suppress chopping ripple. For example, such correction path(s) can be used to generate an input offset correction signal to compensate for the input offset before output chopping, thereby suppressing chopping ripple.

[0015] In certain applications, a chopper amplifier may include multiple input transistor pairs, each of which may be selected to amplify an input signal based on operating conditions and / or parameters. For example, a particular chopper amplifier may include multiple input transistor pairs for operating over a wide range of input common-mode voltages and therefore amplifying the input signal based on the detected input common-mode voltage. In particular, the chopper amplifier may include an n-type input transistor pair for amplifying the input signal over a high-voltage portion of the input common-mode voltage range and a p-type input transistor pair for amplifying the input signal over a low-voltage portion of the input common-mode voltage range. In contrast, a chopper amplifier having only a single input transistor pair may have insufficient voltage headroom to operate over a wide input common-mode voltage range, e.g., rail-to-rail operation.

[0016] When transitioning from one input transistor pair to another, the offset correction circuit of the chopper amplifier may have a delay in properly compensating for the input offset of the newly selected input transistor pair. For example, each input transistor pair of the chopper amplifier may have a different input offset voltage, and thus, when the selected input transistor pair changes, the input offset correction signal generated by the offset correction circuit may have a delay in settling to a suitable steady-state value to properly compensate the newly selected pair.

[0017] A chopper amplifier that tracks multiple input offsets is disclosed herein. In a particular embodiment, the chopper amplifier includes a chopper amplifier circuit including an input chopping circuit, an amplifier circuit, and an output chopping circuit electrically connected along a signal path. The amplifier circuit includes two or more input transistor pairs from which a control circuit selects a selected input transistor pair for amplifying an input signal. The chopper amplifier further includes an offset correction circuit that senses the signal path and generates an input offset compensation signal for the amplifier circuit. Furthermore, the offset correction circuit separately tracks the input offset of each of the two or more input transistor pairs.

[0018] Thus, the selected input transistor pair can be changed with little or no delay in the offset correction circuitry that compensates for the input offset and suppresses chopping ripple. In particular, because the offset correction circuitry tracks the input offset of each input transistor pair separately, the input offset compensation signal can be quickly updated to a signal value suitable for compensation in response to changing the selected input transistor pair.

[0019] In a particular implementation, the two or more input transistor pairs include a p-type input transistor pair and an n-type input transistor pair, and the control circuit determines whether to use the p-type input transistor pair or the n-type input transistor pair based on sensing the input common mode voltage of the chopper amplifier. For example, the control circuit can use the n-type input transistor pair over a first input common mode voltage range and the p-type input transistor pair over a second input common mode voltage range. As the input common mode voltage changes, the selection of the n-type input transistor pair or the p-type input transistor pair can also change. Furthermore, the input offset of the n-type input transistor and the input offset of the p-type input transistor are tracked separately, so that the input offset compensation signal can be quickly updated to an appropriate signal level when the selected input transistor pair changes. Thus, seamless or nearly seamless switching between the n-type input transistors and the p-type input transistors is achieved.

[0020] The input transistor pairs can correspond to a wide variety of transistor types, including, but not limited to, field effect transistors (FETs), such as metal oxide semiconductor (MOS) transistors. The MOS transistors can be associated with a wide variety of manufacturing processes, including bulk complementary MOS (CMOS) processes, as well as triple well CMOS processes, silicon on insulator (SOI) processes, double diffused MOS (DMOS) processes, as well as a wide range of other manufacturing processes. In a particular implementation, the two or more input transistor pairs include an n-type MOS (NMOS) transistor pair, such as n-type DMOS transistors, and a p-type MOS (PMOS) transistor pair, such as p-type DMOS transistors.

[0021] The offset correction circuit can be implemented in a wide variety of ways. In a particular implementation, the offset correction circuit includes digital circuitry used to separately track the input offsets of two or more input transistor pairs. The use of digital circuitry can provide several advantages.

[0022] In a first embodiment, the digital circuitry may include a non-volatile memory for storing digital data representative of the input offset voltages of each input transistor pair of the amplifier circuit. Thus, after a power cycle of the chopper amplifier in which the chopper amplifier is powered off and then power is restored, the chopper amplifier can quickly resume high precision amplification using any selected input transistor pair. In contrast, a chopper amplifier that does not have such a feature may have a long delay at start-up in settling to a steady-state signal value suitable for input offset compensation.

[0023] In a second embodiment, the digital circuitry is coupled to a digital interface (e.g., a serial or parallel interface of a semiconductor die or chip) allowing the digital data to be observed off-chip and / or loaded into the chopper amplifier after power-up to achieve input offset compensation with little or no delay.

[0024] In a third embodiment, the digital circuit can hold the input offset correction data indefinitely without having the chopping clock signal toggle. Thus, the user can stop and restart the chopping clock signal at any time and after any duration. Furthermore, a particular input transistor pair can remain unused for an extended period of time without affecting the ability of the digital circuit to store the input offset correction data for that pair. In contrast, analog circuits may suffer from leakage currents and / or noise that necessitate periodically running the analog circuit with the chopping clock signal to maintain proper input offset compensation.

[0025] The offset correction circuit herein can be used not only to compensate for the input offset voltage of two or more input transistor pairs of an amplifier circuit, but also to reduce or eliminate other low-frequency input noise sources, such as flicker noise, which in turn leads to reduced output chopping ripple, lower flicker noise current, and / or improved spectral output purity of a chopper amplifier.

[0026] 1 is a schematic diagram of a chopper amplifier 20 according to one embodiment. The chopper amplifier 20 includes a chopper amplifier circuit 1 and an offset correction circuit 2 for compensating for the input offset voltage of the chopper amplifier circuit 1 while suppressing output chopping ripple.

[0027] As shown in FIG. 1, a chopper amplifier 20 has a pair of differential input terminals V IN+ , V IN- The positive or non-inverting input voltage terminal V IN+ and the negative or inverting input voltage terminal V IN- The chopper amplifier 20 also receives a differential input signal between a pair of differential output terminals V OUT+ , V OUT- Positive or non-inverting output voltage terminal V IN+ and the negative or inverted output voltage terminal V IN- The differential output signal between the input and output terminals is output.

[0028] 1 illustrates a configuration in which chopper amplifier 20 produces a differential output signal, chopper amplifier 20 may be adapted to produce other output signals, including, for example, a single-ended output signal. In addition, although FIGURE 1 illustrates chopper amplifier 20 in an open-loop configuration, chopper amplifier 20 may be used in a closed-loop configuration.

[0029] In the illustrated embodiment, the chopper amplifier circuit 1 includes an input chopping circuit 3, an output chopping circuit 4, and an amplifier circuit 5, which are electrically connected in cascade along a signal path, with the amplifier circuit 5 being between the input chopping circuit 3 and the output chopping circuit 4. The chopper amplifier circuit 1 further includes a control circuit, which in this embodiment corresponds to a common mode detection circuit 6.

[0030] Although particular components of the chopper amplifier circuit 1 are shown, the chopper amplifier circuit 1 may include additional components or circuits, including, but not limited to, one or more additional amplification stages, output stages, feedforward paths, and / or feedback paths. Thus, other implementations are possible.

[0031] The input chopping circuit 3 operates to chop or modulate the differential input signal to generate a chopped differential input signal, which is amplified by the amplifier circuit 5 to generate an amplified differential signal. The chopping action of the input chopping circuit 3 upshifts the frequency of the differential input signal. For example, in a particular implementation, the chopping clock signal of the input chopping circuit 3 is a square wave that can be equivalently represented by a Fourier series of sine waves at the chopping frequency and its odd harmonics. By modulating the differential input signal by such a square wave, the frequency content of the differential input signal is upshifted. Thus, the chopped differential input signal includes signal content at the chopping frequency and its odd harmonics. The chopped differential input signal is therefore isolated in frequency from the input offset voltage and / or low frequency noise of the amplifier circuit 5.

[0032] 1, the amplifier circuit 5 includes a number of input transistor pairs, which in this embodiment correspond to an n-type input transistor pair 7 and a p-type input transistor pair 8. Each of the input transistor pairs is individually selectable by the control circuitry of the chopper amplifier circuit and can have a different input offset.

[0033] In certain implementations, the input chopping circuit 3 includes a separate set of input chopping switches for each input transistor pair of the amplifier circuit 5. In other implementations, a shared set of chopping switches is used for the input transistor pairs.

[0034] In the illustrated embodiment, the common mode detection circuit 6 generates a first enable signal N EN and a second enable signal P for selecting the p-type input transistor pair 8 for amplification. EN The common mode detection circuit 6, in this embodiment, selects the selected input transistor pair based on the sensed input common mode voltage. For example, due to limitations arising from supply voltage headroom, the n-type input transistor pair 7 may be biased against a high input common mode voltage (e.g., V DD The p-type input transistor pair 8 is well suited to providing amplification at low input common-mode voltages (e.g., V SS The NI 6111 is well suited to providing amplification in the vicinity of

[0035] Thus, in a particular implementation, the common mode detection circuit 6 activates the n-type input transistor pair 7 and deactivates the p-type input transistor pair 8 when the detected input common mode voltage is high, and activates the p-type input transistor pair 8 and deactivates the n-type input transistor pair 7 when the detected input common mode voltage is low. For a mid-band of input common mode voltages, the common mode detection circuit 6 can activate either the n-type input transistors 7 or the p-type input transistors 8, depending on the implementation.

[0036] The selected input transistor pair amplifies the chopped differential input signal to generate an amplified differential signal. The amplified differential signal is chopped by the output chopping circuit 4, which downshifts the signal frequency content. The chopped differential output signal can be output with or without further processing (e.g., amplification, filtering, and / or integration) to generate the differential output signal of the chopper amplifier 20.

[0037] The chopper amplifier 20 further includes an offset correction circuit 2 that senses the signal path through the chopper amplifier circuit 1 at one or more points or locations. In addition, the offset correction circuit 2 injects an input offset voltage compensation signal into the signal path of the chopper amplifier circuit 1 to compensate for the input offset voltage and suppress chopping ripple.

[0038] In the illustrated embodiment, offset correction circuit 2 separately tracks the input offset of each input transistor pair of amplifier circuit 5. In particular, offset correction circuit 2 includes a first tracking circuit 17 for tracking the input offset of n-type input transistor pair 7 and a second tracking circuit 18 for tracking the input offset of p-type input transistor pair 8. Although shown as separate components, first tracking circuit 17 and second tracking circuit 18 may share portions of offset correction circuit 2 used for particular circuits, e.g., sensing, amplification, chopping, and / or other processing.

[0039] As shown in FIG. 1, the offset correction circuit 2 receives a first enable signal N EN and a second enable signal P EN Receive the first enable signal N EN and a second enable signal P EN can be used to activate the tracking operation of the first tracking circuit 17 and the second tracking circuit 18, respectively. Thus, suitable input offset compensation and chopping ripple suppression can be provided for the selected input transistor pair of the amplifier circuit 5.

[0040] In a particular implementation, the input offset compensation signal is injected into a portion of the signal path of the chopper amplifier circuit 1 between the amplification circuit 5 and the output chopping circuit 4. By compensating for such low frequency noise prior to output chopping, the generation of chopping voltage ripple in the differential output signal is reduced or eliminated.

[0041] 2A is a schematic diagram of a chopper amplifier 30 according to another embodiment. The chopper amplifier 30 includes a chopper amplifier circuit 1 and an offset correction circuit 22.

[0042] The chopper amplifier 30 of Figure 2A is similar to the chopper amplifier 20 of Figure 1, except that the chopper amplifier 30 of Figure 2A includes a different implementation of an offset correction circuit. In particular, the offset correction circuit 22 of Figure 2A includes a sense amplifier 13, a resistor 15, a chopping circuit 16, an analog-to-digital converter (ADC) 23, a digital circuit 24, and a digital-to-analog converter (DAC) 25. In addition, the digital circuit 24 includes an n-type tracking circuit 27 and a p-type tracking circuit 28.

[0043] In the illustrated embodiment, the sense amplifier 13 includes differential inputs coupled to a sensing point along the signal path of the chopper amplifier circuit 1. In a particular implementation, the sensing point is along the signal path after the output chopping circuit 4. However, the teachings herein are applicable to offset correction circuits that sense input offsets in a wide variety of ways.

[0044] 2A, the output signal from the sense amplifier 13 is provided to a chopping circuit 16. In a particular implementation, the output signal from the sense amplifier 13 is a current that flows through a resistor 15 to generate an input voltage signal for the chopping circuit 16. The chopping circuit 16 generates an output signal that is digitized by an ADC 23 and processed by digital circuitry 24 to generate digital correction data.

[0045] The digital correction data is used by the DAC 25 to generate a differential input offset compensation signal that is provided to the chopper amplifier circuit 1. In a particular implementation, the differential input offset compensation signal is provided to the differential output of the amplifier circuit 5 to compensate for the input offset voltage of a selected pair of input transistors of the amplifier circuit 5.

[0046] Continuing with reference to FIG. 2A, the offset correction circuit 22 receives the first enable signal N EN and the second enable signal P EN and a first enable signal N EN and a second enable signal P EN are used to activate the tracking operations of the first tracking circuit 27 and the second tracking circuit 28, respectively.

[0047] Thus, when the common mode detection circuit 6 changes the selected input transistor pair from the p-type pair 8 to the n-type pair 7, or vice versa, a corresponding digital tracking circuit in the offset correction circuit 22 is activated. The digital correction data provided to the DAC 25 is thus updated such that the differential input offset compensation signal provided to the chopper amplifier circuit 1 is at a suitable signal level to compensate for the input offset of the selected input transistor pair. Thus, the selected input transistor pair can be switched with little or no delay and without affecting the ability of the chopper amplifier 30 to provide high precision amplification with low input offset.

[0048] 2B is a schematic diagram of a chopper amplifier 39 according to another embodiment. The chopper amplifier 39 includes the chopper amplifier circuit 1 and an offset correction circuit 36.

[0049] Chopper amplifier 39 of Figure 2B is similar to chopper amplifier 30 of Figure 2A, except that offset correction circuit 36 ​​of Figure 2B omits chopping circuit 16 shown in Figure 2A. In addition, offset correction circuit 36 ​​includes digital circuitry 37 that provides digital chopping 38. Any of the offset correction circuits herein can be adapted to operate with digital chopping.

[0050] 3 is a schematic diagram of a chopper amplifier 40 according to another embodiment. The chopper amplifier 40 includes a chopper amplifier circuit 1 and an offset correction circuit 32.

[0051] Chopper amplifier 40 of Figure 3 is similar to chopper amplifier 30 of Figure 2A, except that offset correction circuit 32 of Figure 3 includes digital circuitry 34 that includes non-volatile memory (NVM) 35. NVM 35 is used to store digital data indicative of the signal values ​​of the differential input offset compensation signal when tracking n-type input transistor pair 7 and when tracking p-type input transistor pair 8.

[0052] By including NVM 35, chopper amplifier 40 can quickly resume amplification after a power cycle. Such a power cycle can correspond to a ramp-down and ramp-up of the chopper amplifier's supply voltage, and / or a power-down signal (PWR_DN) can be used to turn chopper amplifier 40 on and off. By including NVM 35, data indicative of the signal value of the input offset compensation of each transistor pair is not lost during a power cycle. Thus, start-up delays in settling to a steady-state signal value for input offset compensation are avoided. Furthermore, either n-type input transistor pair 7 or p-type input transistor pair 8 can be used after a power cycle.

[0053] 4 is a schematic diagram of a chopper amplifier 50 according to another embodiment. The chopper amplifier 50 includes a chopper amplifier circuit 1 and an offset correction circuit 42.

[0054] The chopper amplifier 50 of Figure 4 is similar to the chopper amplifier 30 of Figure 2A, except that the offset correction circuit 42 of Figure 4 includes a digital circuit 44 coupled to a digital interface and including a memory 45, which may be volatile or non-volatile. The memory 45 is used to store digital data indicative of signal values ​​of a differential input offset compensation signal for tracking the n-type pair 7 and the p-type pair 8. The memory 45 may be read or written using a digital interface, which may correspond to a serial or parallel interface of the semiconductor chip on which the chopper amplifier 50 is fabricated.

[0055] Implementing digital circuitry 44 to communicate over a digital interface allows digital data to be observed off-chip and / or loaded into chopper amplifier 50 after power-up or power cycling to achieve input offset compensation with little or no delay.

[0056] 5 is a schematic diagram of a chopper amplifier 60 according to another embodiment. The chopper amplifier 60 includes a chopper amplifier circuit 1 and an offset correction circuit 52.

[0057] Chopper amplifier 60 of Figure 5 is similar to chopper amplifier 30 of Figure 2A, except that offset correction circuit 52 of Figure 5 further includes second sense amplifier 14. Thus, offset correction circuit 52 senses the signal path of chopper amplifier circuit 1 at multiple points or locations.

[0058] In the illustrated embodiment, the first sense amplifier 13 includes a differential input coupled to a first sensing point along the signal path of the chopper amplifier circuit 1, while the second sense amplifier 14 includes a differential input coupled to a second sensing point along the signal path of the chopper amplifier circuit 1. In a particular implementation, the first sensing point is before the input chopping circuit 3, while the second sensing point is after the output chopping circuit 4.

[0059] The first sense amplifier 13 and the second sense amplifier 14 can each include one or more stages. In a particular implementation, the input stage of the first sense amplifier 13 includes a replica of the n-type pair 7 and a replica of the p-type pair 8, with or without scaling.

[0060] 5, the output signal from the first sense amplifier 13 and the output signal from the second sense amplifier 14 are combined and then chopped using a chopping circuit 16 to generate a combined sense signal that is input to the ADC 23. In a particular implementation, the output signal from the first sense amplifier 13 and the output signal from the second sense amplifier 14 correspond to a current that flows through a resistor 15 to generate an input voltage signal for the chopping circuit 16.

[0061] The input offset correction circuits herein may be implemented using a wide variety of sensing configurations, including configurations that use one or more feedback paths, one or more feedforward paths, or a combination thereof.

[0062] 6 is a schematic diagram of a chopper amplifier 70 according to another embodiment. The chopper amplifier 70 includes a chopper amplifier circuit 61 and an offset correction circuit 62. The chopper amplifier 70 receives a differential input voltage V Sig A pair of differential input terminals V IN+ , V IN- and a single-ended output terminal V OUT and

[0063] In the illustrated embodiment, the chopper amplifier circuit 61 includes a common mode detection circuit 51, a chopping clock signal CLK CHOP an input chopping circuit 53 (controlled by a voltage source V OSP A p-type transconductance amplifier G including a p-type input pair having an input offset voltage represented by m1p , (voltage source V OSNAn n-type transconductance amplifier G including an n-type input pair having an input offset voltage represented by m1n , (chopping clock signal CLK CHOP (controlled by) an output chopping circuit 54, a second transconductance amplifier G m2 , the first resistor R CA1 , the second resistor R CA2 , the first capacitor C CA , and a second capacitor C CB Includes.

[0064] Continuing to refer to FIG. 6, the common mode detection circuit 51 has a pair of differential input terminals V IN+ , V IN- and based on the detected common-mode input voltage, a p-type transconductance amplifier G m1p or n-type transconductance amplifier G m1n The selected transconductance amplifier is enabled by a first enable signal N EN or the second enable signal P EN The selected transconductance amplifier is enabled using the differential signal current I m1 Output.

[0065] Although one embodiment of chopper amplifier circuit 61 has been shown, the teachings herein are applicable to chopper amplifier circuits implemented in a wide variety of ways. Thus, other implementations are possible.

[0066] With continued reference to FIG. 6, the offset correction circuit 62 may be implemented with or without scaling to provide an n-type transconductance amplifier G m1n A replica transconductance amplifier G corresponding to the replica of m1NRep The offset correction circuit 62 includes a p-type transconductance amplifier G m1p A replica transconductance amplifier G corresponding to the replica of m1PRep The offset correction circuit 62, with or without scaling, includes a first resistor R CA1and the second resistor R CA2 The first resistor R corresponds to a replica of the series combination with CARep Further includes:

[0067] The offset correction circuit 62 is connected to the first sense transconductance amplifier G mS1 , a second sense transconductance amplifier G mS2 , the second resistor R S , chopper circuit 55, comparator 56, (G m1n The first counter for 67, G m1p The digital circuit 57 further includes a digital circuit 57 (including a second counter 68 for , and a multiplexer 69), and a current DAC (iDAC) 58. The comparator 56 functions as a 1-bit ADC that generates up and down signals to control the state of the active counter of the digital circuit 57. The digital circuit 57 outputs digital correction data from either the first counter 67 or the second counter 68, as selected by the multiplexer 69. The digital correction data is used to calculate a differential correction current I Corr This is used by the current DAC 58 to generate

[0068] In the illustrated embodiment, chopping circuit 55 generates a chopping clock signal CLK CHOP while the comparator 56 is clocked by a comparator clock signal CLK COMP The digital circuit 57 is timed by a counter clock signal CLK COUNT In a particular implementation, the comparator clock signal CLK COMP and / or the counter clock signal CLK COUNT is the chopping clock signal CLK CHOP 6, the current DAC 58 is responsive to changes in the digital correction data rather than being driven by a clock signal. Although one embodiment of timing is shown, the offset correction circuit can be timed in a wide variety of ways.

[0069] Continuing to refer to FIG. 6, the first enable signal N EN and a second enable signal P EN is provided to the offset correction circuit 62 to assist in tracking the input offset of the selected input transistor pair. For example, the first enable signal N EN Using G m1NRep and selectively enabling the first counter 67 while the second enable signal P EN Using G m1PRep and the second counter 68. In addition, a multiplexer 69 selectively enables the first enable signal N EN and a second enable signal P EN is used to select which counter output is provided as the digital correction data for the current DAC 58.

[0070] As shown in FIG. 6, the offset correction circuit 62 detects the differential input to the input chopping circuit 53 and the S2P and V S2N The first resistor R CA1 and the second resistor R CA2 In addition, the offset correction circuit 62 senses the signal path of the chopper amplifier circuit 61 both across the series combination of Corr into the chopper amplifier circuit 61, and thus the differential correction current I Corr is the differential signal current I m1 is synthesized as follows.

[0071] The use of multiple sensing points provides several advantages, including providing low input offset voltage during chopping and excellent gain vs. frequency characteristics (including at the frequency used for chopping), however, the teachings herein are also applicable to implementations that use a single sensing point.

[0072] Thus, although one embodiment of offset correction circuit 62 is depicted, the teachings herein are applicable to offset correction circuits implemented in a wide variety of ways. Thus, other implementations are possible.

[0073] FIG. 7 is a schematic diagram of one embodiment of an amplifier circuit 130 for a chopper amplifier.

[0074] The amplifier circuit 130 includes an NMOS input transistor pair 101, a PMOS input transistor pair 102, a PMOS isolation switch pair 103a, an NMOS isolation switch pair 103b, a first input chopping switch 104a, a second input chopping switch 104b, a common mode detection circuit 105, a first group of current sources 107, 108a, and 108b, a second group of current sources 109, 110a, and 110b, a first cascode PMOS transistor 113a, a second cascode PMOS transistor 113b, a first cascode NMOS transistor 114a, a second cascode NMOS transistor 114b, a third group of current sources 115a and 115b, a fourth group of current sources 116a and 116b, a first voltage source 117, and a second voltage source 118. The amplifier circuit 130 further includes a pair of input terminals (IN+, IN-) and a pair of output terminals (OUT+, OUT-), and is connected to a high power supply voltage V DD and low power supply voltage V SS Powered by

[0075] In the illustrated embodiment, the NMOS input transistor pair 101 is connected together and receives a common bias current I N The input transistor 121 is implemented as a differential transistor pair including a first NMOS input transistor 121a and a second NMOS input transistor 121b, each including a source biased at I. In addition, the drain of the first NMOS input transistor 121a receives a bias current I from a current source 108a. N The drain of the second NMOS input transistor 121b is biased by I N Biased by / 2.

[0076] The PMOS isolation switch pair 103a includes a first PMOS isolation switch 123a and a second PMOS isolation switch 123b. The drains of the PMOS isolation switches 123a and 123b are connected to IN+ and IN-, respectively, while the sources of the PMOS isolation switches 123a and 123b are connected to the gates of the NMOS input transistors 121a and 121b, respectively, through the first input chopping switch 104a. The gates of the PMOS isolation switches 123a and 123b are connected to the first inverted enable signal N ENB is controlled by.

[0077] Continuing with reference to FIG. 7, the PMOS input transistor pair 102 is connected together and fed with a common bias current I P The input transistor 122 is implemented as a differential transistor pair including a first PMOS input transistor 122a and a second PMOS input transistor 122b, each including a source biased at I. Additionally, the drain of the first PMOS input transistor 122a receives a bias current I from the current source 110a. P The drain of the second PMOS input transistor 122b is biased by I P Biased by / 2.

[0078] NMOS isolation switch pair 103b includes a first NMOS isolation switch 124a and a second NMOS isolation switch 124b. The drains of NMOS isolation switches 124a and 124b are connected to IN+ and IN-, respectively, while the sources of NMOS isolation switches 124a and 124b are connected to the gates of PMOS input transistors 122a and 122b, respectively, through second input chopping switch 104b. The gates of NMOS isolation switches 124a and 124b are connected to the gates of PMOS input transistors 122a and 122b, respectively, through second input chopping switch 104b. EN is controlled by.

[0079] In the illustrated embodiment, the common mode detection circuit 105 is coupled to a pair of input terminals (IN+, IN-) to sense an input common mode voltage. Based on the sensed input common mode voltage, the common mode detection circuit 105 generates a first enable signal N EN 101, or the second enable signal P EN is used to select the PMOS input transistor pair 102. The selected input transistor pair amplifies the differential input signal received between IN+ and IN− after being chopped by the first input chopping switch 104a or the second input chopping switch 104b.

[0080] As shown in FIG. 7, the first input chopping switch 104a and the second input chopping switch 104b each receive a chopping clock signal CLK CHOP In the illustrated embodiment, separate sets of input chopping switches are used for the n-type input pair 101 and the p-type input pair 102. In other embodiments, a shared set of chopping switches is used. Any of the embodiments herein may use shared or separate input chopping switches. Similarly, any of the embodiments herein may use shared or separate output chopping switches.

[0081] When the NMOS input transistor pair 101 is in use, the common mode detection circuit 105 turns on the PMOS isolation transistor pair 103a and turns on the first group of current sources 107, 108a, and 108b. However, when the NMOS input transistor pair 101 is not in use, the common mode detection circuit 105 turns off the PMOS isolation transistor pair 103a and turns off the first group of current sources 107, 108a, and 108b.

[0082] 7, when the PMOS input transistor pair 102 is in use, the common mode detection circuit 105 turns on the NMOS isolation transistor pair 103b and turns on the second group of current sources 109, 110a, and 110b. However, when the PMOS transistor pair 102 is not in use, the common mode detection circuit 105 turns off the NMOS isolation transistor pair 103b and turns off the second group of current sources 109, 110a, and 110b.

[0083] The inclusion of PMOS isolation transistor 103a and NMOS isolation transistor 103b helps reduce the input capacitance, however, the teachings herein also apply to implementations without isolation transistors.

[0084] An embodiment of a folded cascode circuit is depicted as being coupled to an NMOS input transistor pair 101 and a PMOS input transistor pair 102. The folded cascode circuit illustrates one embodiment of a circuit suitable for providing output signals from the NMOS input transistor pair 101 and the PMOS input transistor pair 102 to a common output terminal pair (OUT+, OUT-). However, other implementations of the circuit are possible.

[0085] 8 is a schematic diagram of one embodiment of a chopping switch 210 that can be used in a chopper amplifier, however, the chopping switch can be implemented in other ways.

[0086] 8, the chopping switch 210 includes first and second inputs 201a, 201b operating as differential inputs, first and second outputs 202a, 202b operating as differential outputs, first to fourth switches 203a-203d, and a switch control circuit 204. As shown in FIG 8, the switch control circuit 204 generates a chopping clock signal CLK that can be used to control the states of the switches 203a-203d over time. CHOPAlthough shown as including a switch control circuit 204, in certain configurations, the switch control circuit 204 is omitted if one chooses to provide multiple clock signals to the chopping switch 210 (e.g., inverted and non-inverted versions of a chopping clock signal, with or without overlap).

[0087] The first input 201a is electrically connected to a first end of the first switch 203a and a first end of the second switch 203b. The second input 201b is electrically connected to a first end of the third switch 203c and a first end of the fourth switch 203d. The first output 202a is electrically connected to a second end of the second switch 203b and a second end of the third switch 203c. The second output 202b is electrically connected to a second end of the first switch 203a and a second end of the fourth switch 203d.

[0088] The chopping switch 210 may be used to chop a differential input signal received between a first input 201a and a second input 201b to generate a chopped differential signal between a first output 202a and a second output 202b. For example, a chopping clock signal CLK CHOP During the first clock phase of the chopping clock signal CLK, the switch control circuit 204 may close the second and fourth switches 203b, 203d and open the first and third switches 203a, 203c. CHOP During the second clock phase, the switch control circuit 204 may close the switches 203a, 203c of the first and third switches and open the second and fourth switches 203b, 203d.

[0089] The clock signals disclosed herein can be implemented in a wide variety of ways, including, for example, using any suitable clock generator. In certain implementations, a common clock signal is used to synthesize clock signals used for chopping the chopper amplifiers, auto-zeroing, digital processing, and / or other operations.

[0090] Purpose Devices employing the above schemes may be implemented in a variety of electronic devices, including but not limited to consumer electronics, electronic test equipment, communication systems, data converters, and the like.

[0091] conclusion The foregoing description may refer to elements or features as being "connected" or "coupled" together. As used herein, unless expressly stated otherwise, "connected" means that one element / feature is directly or indirectly connected to another element / feature, not necessarily mechanically. Similarly, unless expressly stated otherwise, "coupled" means that one element / feature is directly or indirectly coupled to another element / feature, not necessarily mechanically. Thus, while the various schematic diagrams depicted in the figures show example configurations of elements and components, additional intervening elements, devices, features, or components may be present in an actual embodiment (assuming the functionality of the depicted circuitry is not adversely affected).

[0092] Although specific embodiments have been described, these embodiments are presented as examples only and are not intended to limit the scope of the disclosure. Indeed, the novel apparatus, methods, and systems described herein may be embodied in a variety of other forms, and further, various omissions, substitutions, and changes in the forms of the methods and systems described herein may be made without departing from the spirit of the disclosure. For example, while the disclosed embodiments are depicted in a given configuration, alternative embodiments may perform similar functions using different components and / or circuit topologies, and some elements may be deleted, moved, added, subdivided, combined, and / or modified. Each of these elements may be implemented in a variety of different ways. Any suitable combination of elements and operations of the various embodiments described above may be used together to provide further embodiments. The scope of the present invention is therefore defined solely by reference to the appended claims.

[0093] Although the claims presented herein are in single dependent form for purposes of filing with the USPTO, it should be understood that any claim may be dependent on any preceding claim of the same type unless it is clearly technically impracticable. [Explanation of symbols]

[0094] 1 Chopper amplifier circuit 2 Offset correction circuit 3-input chopping circuit 4 Output chopping circuit 5 Amplification circuit 6 Common mode detection circuit 7 n-type input transistor pair 8 p-type input transistor pairs 17 First Tracking Circuit 18 Second Tracking Circuit 20 Chopper Amplifier

Claims

1. 1. A chopper amplifier for tracking multiple input offsets, comprising: an input chopping circuit configured to chop the input signal to generate a chopped input signal; an amplifier circuit configured to amplify the chopped input signal to generate an amplified signal, the amplifier circuit comprising two or more selectable input transistor pairs, the two or more input transistor pairs comprising an n-type input transistor pair and a p-type input transistor pair; an output chopping circuit configured to chop the amplified signal to generate a chopped output signal; and a control circuit configured to select a selected pair of input transistors from the two or more input transistor pairs, the selected pair of input transistors configured to amplify the chopped input signal, the control circuit configured to generate two or more enable signals, each operable to select a corresponding pair of input transistors from the two or more input transistor pairs; a chopper amplifier circuit comprising: an offset correction circuit configured to generate an input offset compensation signal for the chopper amplifier circuit, the offset correction circuit comprising a respective tracking circuit for tracking a corresponding one of the two or more input transistor pairs, the offset correction circuit receiving the two or more enable signals from the control circuit and configured to separately track an input offset of each of the two or more input transistor pairs via the respective tracking circuits, the two or more enable signals being used to activate a tracking operation of the respective tracking circuits; A chopper amplifier comprising:

2. 2. The chopper amplifier of claim 1, wherein the offset correction circuit comprises a digital circuit configured to generate digital correction data indicative of a value of the input offset compensation signal for each of the two or more input transistor pairs.

3. The chopper amplifier of claim 2 , wherein the digital circuitry comprises a non-volatile memory configured to store the digital correction data.

4. 3. The chopper amplifier of claim 2, wherein the digital circuitry comprises a memory configured to store the digital correction data, the digital circuitry being coupled to a digital interface operable to read and write to the memory.

5. 3. The chopper amplifier of claim 2, wherein the offset correction circuit comprises: an analog sense circuit configured to generate a sense signal based on sensing a signal path through the chopper amplifier circuit; an analog-to-digital converter configured to convert the sense signal to a digital input signal for the digital circuit; and a digital-to-analog converter configured to control the input offset compensation signal based on the digital correction data.

6. 6. The chopper amplifier of claim 5, wherein the analog-to-digital converter comprises a comparator and the digital circuitry comprises two or more counters each configured to track the input offset of a corresponding one of the two or more input transistor pairs.

7. 6. The chopper amplifier of claim 5, wherein the analog sense circuit comprises: a chopping circuit configured to output the sense signal; and a sense amplifier having an input coupled to the signal path and an output coupled to an input of the chopping circuit.

8. 2. The chopper amplifier of claim 1, further comprising: a first isolation switch pair coupled to the n-type input transistor pair and a second isolation switch pair coupled to the p-type input transistor pair, wherein the control circuit closes the first isolation switch pair and opens the second isolation switch pair when the selected input transistor pair corresponds to the n-type input transistor pair, and closes the second isolation switch pair and opens the first isolation switch pair when the selected input transistor pair corresponds to the p-type input transistor pair.

9. 2. The chopper amplifier of claim 1, further comprising a pair of input terminals configured to receive the input signal, and wherein the control circuit selects the selected pair of input transistors based on sensing an input common-mode voltage of the pair of input terminals.

10. 2. The chopper amplifier of claim 1, wherein the offset correction circuit is configured to generate the input offset compensation signal based on sensing a signal path through the chopper amplifier circuit at two or more signal points.

11. 11. The chopper amplifier of claim 10, wherein the two or more signal points include a first signal point before the input chopping circuit and a second signal point after the output chopping circuit.

12. The chopper amplifier of claim 10 , wherein the offset correction circuit is configured to provide the input offset compensation signal to an output of the amplifier circuit.

13. 1. A method of amplification comprising: chopping the input signal using an input chopping circuit to generate a chopped input signal; selecting, using a control circuit, an input transistor pair from two or more input transistor pairs of the amplifier circuit, the selecting including generating two or more enable signals each operable to select a corresponding input transistor pair of the two or more input transistor pairs, the two or more input transistor pairs including an n-type input transistor pair and a p-type input transistor pair; amplifying the chopped input signal using the selected pair of input transistors to generate an amplified signal; chopping the amplified signal using an output chopping circuit to generate a chopped output signal; compensating the amplifier circuit using an input offset compensation signal generated by an offset correction circuit, the offset correction circuit comprising a respective tracking circuit for tracking a corresponding one of the two or more input transistor pairs, the offset correction circuit receiving from the control circuit, the two or more enable signals, via the respective tracking circuits, separately tracking an input offset of each of the two or more input transistor pairs, the two or more enable signals being used to activate a tracking operation of the respective tracking circuits; The method includes:

14. 14. The method of claim 13, wherein compensating the amplifier circuit for the input offset comprises generating digital correction data indicative of a value of the input offset compensation signal for each of the two or more input transistor pairs.

15. 15. The method of claim 14, further comprising: storing the digital correction data in a non-volatile memory; performing a power cycle; and compensating the amplifier circuit for the input offset after the power cycle using the stored digital correction data.

16. The method of claim 13, further comprising selecting the selected input transistor pair based on an input common-mode voltage.

17. A chopper amplifier comprising: A pair of input terminals; an input chopping circuit including an input coupled to said pair of input terminals; an amplifier circuit including an input coupled to an output of the input chopping circuit, the amplifier circuit comprising two or more selectable input transistor pairs, the two or more input transistor pairs including an n-type input transistor pair and a p-type input transistor pair; an output chopping circuit including an input coupled to an output of the amplifier circuit; and a control circuit configured to select a selected input transistor pair from the two or more input transistor pairs for providing amplification, the control circuit configured to generate two or more enable signals each operable to select a corresponding input transistor pair from the two or more input transistor pairs; a chopper amplifier circuit comprising: an offset correction circuit configured to generate an input offset compensation signal for compensating the amplifier circuit, the offset correction circuit comprising a respective tracking circuit for tracking a corresponding one of the two or more input transistor pairs, the offset correction circuit receiving the two or more enable signals from the control circuit and configured to separately track an input offset of each of the two or more input transistor pairs via the respective tracking circuits, the two or more enable signals being used to activate a tracking operation of the respective tracking circuits.

18. 20. The chopper amplifier of claim 17, wherein the offset correction circuit comprises a digital circuit configured to generate digital correction data indicative of a value of the input offset compensation signal for each of the two or more input transistor pairs.

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