Nanowire-core ferroelectric field-effect transistors

Abstract

A ferroelectric field effect transistor (FeFET) is provided, which includes a buried oxide (BOX) layer, a nanowire layer including a nanowire core formed on the BOX layer in source and drain regions of the FeFET and extending over pads and recesses formed in the BOX layer between the pads, a metal electrode covering the nanowire core, a ferroelectric layer covering the metal electrode, an interfacial layer covering the ferroelectric layer, and a polysilicon layer formed over a channel region of the FeFET and covering the interfacial layer.

Description

Technical Field

[0001] The present disclosure generally relates to semiconductor-based electronic devices and methods of manufacturing semiconductor-based electronic devices. More specifically, the present application relates to ferroelectric gate field effect transistor (FeFET) devices including nanowire channels and methods of manufacturing the same.

Background Art

[0002] The endurance characteristics of FeFET devices can be a function of the large electric field within the interface layer (IL) when the polarization of the ferroelectric oxide in the ferroelectric layer switches. It would be desirable to improve the performance of the ferroelectric layer of FeFET devices.

Summary of the Invention

[0003] Embodiments of the present disclosure relate to ferroelectric field effect transistors (FeFETs). The FeFET includes a buried oxide (BOX) layer, a nanowire layer including a nanowire core extending over pads formed on the BOX layer in the source and drain regions of the FeFET and over a recess formed in the BOX layer between the pads, a metal electrode covering the nanowire core, a ferroelectric layer covering the metal electrode, an interface layer covering the ferroelectric layer, and a polysilicon layer formed over the channel region of the FeFET and covering the interface layer.

[0004] Other embodiments of the present disclosure relate to a method of manufacturing a ferroelectric field effect transistor (FeFET). The method includes forming a buried oxide (BOX) layer. The method includes forming a nanowire layer on the BOX layer that includes pads formed on the BOX layer in the source and drain regions of the FeFET and a nanowire core extending between the pads. The method further includes undercutting the BOX layer under the nanowire core to separate the nanowire core from the BOX layer, forming a metal electrode around the nanowire core, forming a ferroelectric layer around the metal electrode, forming an interface layer around the ferroelectric layer, and forming a polysilicon layer covering the interface layer over the channel region of the FeFET.

[0005] The above summary is not intended to describe every illustrative embodiment or any embodiment of the present disclosure.

Brief Description of the Drawings

[0006] The drawings included in this application are incorporated herein and form a part hereof. They illustrate embodiments of the present disclosure and, together with the description, explain the principles of the present disclosure. The drawings are only examples of certain embodiments and do not limit the present disclosure.

[0007]

Figure 1A

Figure 1B

Figure 2A

Figure 2B

Figure 3A

Figure 3B

Figure 4A

Figure 4B

Figure 5A

Figure 5B

Figure 6A

Figure 6B

Figure 6C

Figure 7

Figure 8

Figure 9

[0008] It should be recognized that the elements in the figures are shown for simplicity and clarity. Well-known elements that may be useful or necessary in commercially implementable embodiments may not be shown, for simplicity and to aid in the understanding of the exemplary embodiments.

Embodiments for Carrying Out the Invention

[0009] The present disclosure describes a semiconductor structure and a method of manufacturing the semiconductor structure. More specifically, the present application relates to a ferroelectric gate field effect transistor (FeFET) and a method of manufacturing an FeFET device. Generally, an FeFET is a type of field effect transistor that includes a ferroelectric material sandwiched between a gate electrode of the device and a source-drain conductive region. Due to the permanent electric field polarization of the ferroelectric material, this type of device can retain the state (on or off) of the transistor even in the absence of an electrical bias. The FeFET transistor can be used in an FeFET memory device, which is a type of non-volatile memory of a single transistor.

[0010] Various embodiments of the present disclosure are described herein with reference to the related drawings. Alternative embodiments can be devised without departing from the scope of the present disclosure. It should be noted that in the following description and drawings, various connections and positional relationships (e.g., above, below, adjacent, etc.) between elements are revealed. These connections or positional relationships or both may be direct or indirect, and the present disclosure is not intended to be limited in this regard. Accordingly, the coupling of entities can indicate either direct or indirect coupling, and the positional relationship between entities can be direct or indirect. As an example of an indirect positional relationship, in this description, a reference to forming layer "A" on layer "B" includes a situation where one or more intermediate layers (e.g., layer "C") are present between layer "A" and layer "B", provided that the relevant characteristics or functionality of layer "A" and layer "B" are not substantially changed by the intermediate layer(s).

[0011] The following definitions and abbreviations are used for the interpretation of the claims and this specification. As used herein, the terms "comprises", "comprising", "includes", "including", "has", "having", "contains" or "containing", or any other variations thereof, are intended to include non-exclusive inclusion. For example, a composition, mixture, process, method, article, or apparatus that includes a list of elements is not necessarily limited to those elements and may include other elements not expressly listed or inherent to the composition, mixture, process, method, article, or apparatus.

[0012] For the following description, the terms "upper", "lower", "right", "left", "vertical", "horizontal", "top", "bottom" and their derivatives shall be related to the structures and methods being described as adapted in the drawings. The terms "overlying", "atop", "on top", "positioned on" or "positioned atop" mean that a first element, e.g., a first structure, is present over a second element, e.g., a second structure, where intervening elements, e.g., an interface structure, can be present between the first and second elements. The term "direct contact" means that a first element, e.g., a first structure, and a second element, e.g., a second structure, are connected at the interface of the two elements without any intermediate conductor, insulator or semiconductor layer. It should be noted that the term "selective to", e.g., "a first element selective to a second element", means that the first element can be etched and the second element can function as an etch stop.

[0013] For the sake of brevity, the prior art related to semiconductor device and integrated circuit (IC) manufacturing may or may not be described in detail herein. Further, the various tasks and process steps described herein can be incorporated into more comprehensive procedures or processes having additional steps or functionality not described in detail herein. Specifically, the various steps in the manufacture of semiconductor devices and semiconductor-based ICs are well known, and for the sake of brevity, many conventional steps are only briefly mentioned herein or are completely omitted without providing details of well-known processes.

[0014] Generally, the various processes used to form the microchips that will be packaged into ICs are classified into four general categories: namely, film deposition, removal / etching, semiconductor doping, and patterning / lithography.

[0015] Deposition is any process of growing, coating, or otherwise transferring a material onto a wafer. Available techniques include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and, more recently, particularly atomic layer deposition (ALD). Another deposition technique is plasma-enhanced chemical vapor deposition (PECVD), which is a process that utilizes the energy in a plasma to induce reactions on the wafer surface that would otherwise require high temperatures in conventional CVD. Collisions of high-energy ions during PECVD deposition can also improve the electrical and mechanical properties of the film.

[0016] Etching / removal is any process that removes material from a wafer. Examples include etching processes (wet or dry), chemical mechanical planarization (CMP), etc. One example of a removal process is ion beam etching (IBE). Generally, IBE (or milling) refers to a dry plasma etching method that uses a remote broad beam ion / plasma source to remove substrate material by means of a physically inert gas, a chemically reactive gas, or both. Similar to other dry plasma etching techniques, IBE has advantages such as etching rate, anisotropy, selectivity, uniformity, aspect ratio, and minimization of substrate damage. Another example of a dry removal process is reactive ion etching (RIE). Generally, RIE uses a chemically reactive plasma to remove material deposited on a wafer. In RIE, the plasma is generated under low pressure (vacuum) by an electromagnetic field. High energy ions from the RIE plasma attack the substrate surface and react with it to remove the material.

[0017] Semiconductor doping is the changing of electrical properties, for example, in the source and drain of a transistor, generally by doping by diffusion, ion implantation, or both. Following these doping processes, furnace annealing or rapid thermal annealing ("RTA") is performed. Annealing functions to activate the implanted dopants. For FeFET devices, the ferroelectric layer of the device can be used to store information such as "0" or "1", and the RTA process can be used to create the ferroelectric film. Conductors (e.g., polysilicon, aluminum, copper, etc.) and insulators (e.g., various forms of silicon dioxide, silicon nitride, etc.) are used to connect and isolate transistors and their components. Selective doping of various regions of a semiconductor substrate enables the conductivity of the substrate to change upon application of a voltage. By creating structures of these various components, millions of transistors can be constructed and wired together to form the complex circuits of modern microelectronic devices.

[0018] Semiconductor lithography is to form a three-dimensional relief image or pattern on a semiconductor substrate for subsequent transfer of the pattern onto the substrate. In semiconductor lithography, the pattern is formed by a photosensitive polymer called photoresist. To construct the complex structures that make up transistors and the numerous wires that connect millions of transistors in a circuit, the lithography and etching / pattern transfer steps are repeated many times. Each pattern printed on the wafer is aligned with previously formed patterns, and gradually, conductors, insulators, and selectively doped regions are built to form the final device.

[0019] As briefly described above, the endurance characteristics of a FeFET device can be a function of the large electric field in the interface layer (IL) when the polarization state in the ferroelectric oxide material of the ferroelectric layer switches. Due to this large electric field, degradation of the IL may occur earlier than polarization fatigue, which may cause the endurance fatigue of the FeFET device. According to this embodiment, based on the geometric structure of the device, by adjusting (or reducing) the high electric field of the IL, it is possible to enable the FeFET device to achieve more robust performance characteristics (for example, the device can achieve more write / read cycles before endurance fatigue). In certain embodiments, the high electric field can be reduced by changing the geometric design of the device and placing the interface layer at a location where the electric field is not too strong.

[0020] Generally, the electric field of a conductive cylindrical structure (cylindrical shell) is a function of the radius of the cylinder. Specifically, the electric field of an infinite cylindrical conductor with a uniform linear charge density can be obtained by applying Gauss's law. Considering a cylindrical Gaussian surface at a radius r > R, the electric field has the same magnitude at every point on the cylinder and is directed outward. Therefore, the electric flux is the product of the electric field and the area of the cylinder. Further, considering that the electric field of the cylindrical structure is a function of the radius, the electric field in its outer part will be smaller. By adjusting the geometric shape of the structure of the FeFET device according to this embodiment by arranging an interface layer outside the ferroelectric layer, the inner ferroelectric layer will receive a relatively large electric field. Further, since the interface layer (IL) is formed outside the ferroelectric layer, the IL will receive a relatively small electric field. As described in this specification, since the degradation of the IL is related to the endurance fatigue of the FeFET and a high electric field may cause the degradation of the IL, arranging the IL outside the ferroelectric layer that will receive a smaller electric field can minimize the degradation of the IL and help extend the life of the FeFET device.

[0021] This technology provides a gate-all-around (GAA) nanowire ferroelectric field-effect transistor (FeFFT) and a method for manufacturing the same. This method is described using a silicon (Si) nanowire and Si processing. However, this technology can also be implemented using other semiconductor materials, such as germanium (Ge) or III-V semiconductors. When using a non-Si-containing semiconductor, the processing steps of this teaching are generally the same except that the growth temperature and the dopant species added are adapted to the specific semiconductor used. Semiconductor materials containing Si, such as Si, silicon-germanium (SiGe), Si / SiGe, silicon carbide (SiC), or silicon-germanium-carbide (SiGeC), etc., can be used.

[0022] Next, referring to the drawings in which like numerals represent like or similar elements, and initially to FIGS. 1A and 1B, a FeFET device 100 including a substrate 102 and a buried oxide (BOX) layer 104 according to an embodiment is shown. In a particular example, the substrate 102 can be a Si substrate, although other suitable materials can also be used. As shown in the cross-sectional view of FIG. 1B, the buried oxide layer 104 is formed on the underlying substrate 102. As shown in FIG. 1B, a nanowire 106 traverses the recessed portion 103 of the buried oxide layer 104. In a particular embodiment, the nanowire 106 can include Si or silicide, or any other suitable material. As shown in the top view of FIG. 1A, the nanowire 106 can include square pad portions 107 on both sides of the recessed portion 103 of the BOX layer 104 (e.g., the left source side and the right drain side). The patterned width dimension of the nanowire 106 can range, for example, from about 10 nm to about 30 nm. In a particular example, the patterning of the nanowire 106 can be performed by conventional lithography (e.g., optical or e-beam) followed by reactive ion etching (RIE). That is, the BOX layer 104 can be etched to recess the BOX layer 104 under the nanowire 106 to form the recessed portion 103, thereby suspending (separating from the BOX layer 104) the nanowire 106. Accordingly, the nanowire 106 forms a suspension bridge between different sides of the BOX layer 104. Recessing the BOX layer 104 can be achieved, for example, by dilute hydrofluoric acid (DHF) etching. DHF etching is an isotropic etching. Accordingly, the lateral component of the etching undercuts the BOX layer 104 under the narrow nanowire 106.

[0023] In certain embodiments, the suspended nanowire 106 is further processed to change the cross-sectional profile of the nanowire 106 from a generally square (or rectangular) shape to a generally circular cross-sectional shape (see also FIG. 6C). In certain embodiments, the diameter of the suspended portion of the nanowire 106 of a general gate-all-around (GAA) MOSFET structure is about 10 nm or less. In certain embodiments, a process for reliably obtaining highly uniform and smooth silicon nanowires in the range of 10 nm and below can include a manufacturing technique of continuous hydrogen annealing followed by high-temperature oxidation (when using a conventional CMOS process). In an exemplary process for manufacturing the nanowire 106, first the nanowire 106 is patterned using standard lithography techniques. Next, maskless thinning / smoothing of the nanowire 106 is 2 achievable by an annealing process. This annealing process can change the cross-sectional shape of the suspended portion of the nanowire 106 from a generally square (or rectangular) shape to a generally circular cross-sectional shape (see also FIG. 6C). In certain embodiments, the diameter of the nanowire 106 can be further reduced in size by an oxidation process. The oxidation process can further reduce the nanowire dimensions without measurable degradation of the line edge roughness (LER).

[0024] Next, referring to FIGS. 2A and 2B, top and cross-sectional views, respectively, of the FeFET device 100 of FIGS. 1A and 1B in the next stage of the manufacturing process are shown. As shown in FIGS. 2A and 2B, a metal electrode 108 (e.g., TiN, Ir, TaN, etc.) is deposited to cover the cylindrical portion of the suspended nanowire 106 and is further formed to extend up to one on the right side of the contact pad 107 of the nanowire 106. As shown in FIG. 2B, the thickness of the metal electrode 108 covering the suspended portion of the nanowire 106 is selected such that the amount of the recessed portion 103 of the BOX layer 104 still exists. In accordance with the generally cylindrical cross-sectional shape of the suspended portion of the nanowire 106, the suspended portion of the metal electrode 108 also has a cylindrical cross-sectional shape (see also FIG. 6C).

[0025] Next, referring to FIGS. 3A and 3B, top views and cross-sectional views in the next stage of the manufacturing process of the FeFET device 100 of FIGS. 2A and 2B are shown, respectively. As shown in FIGS. 3A and 3B, an insulator oxide layer 110 is formed over the right and left sides (i.e., the source side and the drain side) of the FeFET device 100. The insulator oxide layer 110 can include silicon dioxide (SiO 2 ), silicon oxynitride (SiON), hafnium oxide (HFO 2 ), or any other suitable high-k dielectric(s), and can be deposited over the pad 107 using physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or, in the case of SiO 2 and SiON, an oxidation furnace. The insulator oxide layer 110 can be considered a kind of spacer that enables separation of the active regions of the FeFET device 100.

[0026] Next, referring to FIGS. 4A and 4B, top views and cross-sectional views in the next stage of the manufacturing process of the FeFET device 100 of FIGS. 3A and 3B are shown, respectively. As shown in FIGS. 4A and 4B, after the formation of the insulator oxide layer 110, a ferroelectric oxide layer 112 is formed around the metal electrode 108. Following the suspended portion of the nanowire 106 and the generally cylindrical cross-sectional shape of the metal electrode 108, the ferroelectric oxide layer 112 also has a generally cylindrical cross-sectional shape (see also FIG. 6C). In certain embodiments, the ferroelectric oxide layer 112 can include, for example, HfO 2 . HfO 2 can be undoped or doped. Dopants for HfO 2 can include, for example, Si, Al, Zr, La, N, etc. The ferroelectric oxide layer 112 can be formed by atomic layer deposition (ALD) or any other suitable material deposition technique. In certain embodiments, the ferroelectric oxide layer 112 is in an orthorhombic layer and can have a thickness in the range of, for example, 1 nm to 30 nm.

[0027] Next, referring to FIGS. 5A and 5B, top views and cross-sectional views of the FeFET device 100 of FIGS. 4A and 4B, respectively, in the next stage of the manufacturing process are shown. As shown in FIGS. 5A and 5B, after the formation of the ferroelectric oxide layer 112, an interface layer 114 is formed around the ferroelectric oxide layer 112. In accordance with the generally cylindrical cross-sectional shape of the suspended portion of the nanowire 106, the metal electrode 108, and the ferroelectric oxide layer 112, the interface layer 114 formed here also has a generally cylindrical cross-sectional shape (see also FIG. 6C). The interface layer 114 can be formed by atomic layer deposition (ALD) or any other suitable material deposition technique. As described above, the interface layer 114 can usually be a source of degradation of the FeFET device 100 due to the application of a high level of electric field. However, in this embodiment, since the interface layer 114 is outside both the metal layer 108 and the ferroelectric oxide layer 112, it is disposed at a greater distance (i.e., at a greater radius) from the central axis of the nanowire 106. Accordingly, the interface layer 114 will receive a relatively small electric field and may be less susceptible to electric field degradation. Therefore, the durability characteristics of the FeFET device 100 can be improved. In a particular embodiment, the interface layer 114 can have a thickness in the range of, for example, 1 nm to 5 nm. The interface layer 114 can be composed of one or more of SiO 2 , SiON, SiN, etc.

[0028] Next, referring to FIGS. 6A, 6B, and 6C, there are shown, respectively, a top view, a cross-sectional view, and a cross-sectional view of the FeFET device 100 of FIGS. 5A and 5B at the next stage of the manufacturing process. As shown in FIGS. 6A and 6B, the polysilicon layer 116 is deposited on the pad portion 107 of the nanowire 106 and around the suspended cylindrical portion of the interface layer 114. Thus, the polysilicon layer is deposited to cover the channel region C of the FeFET device 100 that is between the source region S and the drain region, as shown in FIG. 6B. FIG. 6C is a cross-sectional view taken along line A-A of FIG. 6B, showing a concentric stack of the nanowire 106, the metal electrode 108, the ferroelectric oxide layer 112, the interface layer 114, and the polysilicon layer 116. In a particular embodiment, after the formation of the polysilicon layer 116, a CMP process can be performed on the FeFET device 100, which can flatten a particular upper portion of the polysilicon layer 116 (i.e., in contrast to the completely circular cross-sectional depiction of the polysilicon layer 116 shown in FIG. 6C).

[0029] Next, referring to FIG. 7, there is shown a cross-sectional view of the FeFET device 100 of FIG. 6B at the next stage of the manufacturing process. As shown in FIG. 7, the source region 710 and the drain region 712 are formed in the polysilicon layer 116. The source region 710 and the drain region 712 are regions where the polysilicon layer 116 is highly doped. Doping can be provided by methods such as ion implantation and subsequent annealing, or diffusion of dopants from a doping source. The doped polysilicon can further be selectively added to the source region 710 and the drain region 712 by various deposition methods.

[0030] Next, referring now to FIG. 8, a cross-sectional view of the FeFET device 100 of FIG. 7 in the next stage of the manufacturing process is shown. As shown in FIG. 8, a dielectric film 810 is deposited over the source region 710, polysilicon layer 116, and drain region 712. Next, vias reaching the source region 710, drain region 712, and gate (i.e., metal electrode 108) are opened in the dielectric film 810. Next, source contact 814, drain contact 816, and gate contact 818 are formed using a metal such as, for example, tungsten.

[0031] Next, referring to FIG. 9, this figure shows a method 900 for manufacturing a FeFET device according to an embodiment. As shown in FIG. 9, in operation 902, a substrate is prepared. As described above, the substrate can be a silicon substrate or can be composed of any other suitable material(s). In operation 904, a buried oxide (BOX) layer is formed on the substrate. In operation 906, a nanowire layer is formed. This nanowire layer includes pads above the source region side and the drain region side of the FeFET device and a nanowire core connecting the pads. Thus, at least initially, the nanowires have a general barb shape. It should be recognized that at this stage of the manufacturing process, the nanowire core has a generally square or rectangular cross-sectional area. Further, at this stage, the nanowire core is supported by the underlying BOX layer and is not yet suspended. Further, in operation 906, the nanowire core is separated from the BOX layer (i.e., a recess is formed in the BOX layer under the nanowire core), and as a result, the nanowire core is suspended in the hollow between the source region and the drain region of the FeFET device. In certain embodiments, as described above, after the nanowire core is separated from the BOX layer, the nanowire core can be further processed from a square shape to a circular (or generally circular) shape using annealing or oxidation or both (or any other suitable material removal process). In operation 908, a metal electrode is formed to cover the nanowire core. In operation 910, an insulator oxide layer is formed on at least a portion of the pads of the nanowire layer in the source and drain regions of the FeFET. In operation 912, a ferroelectric oxide layer is formed to cover the metal electrode. In operation 914, an interface layer is formed to cover the ferroelectric oxide layer. Thus, the interface layer is formed in the shape of a general cylindrical shell and is formed at a greater distance from the central axis of the nanowire core than the other layers described above. Thus, the magnitude of the electric field applied to the interface layer can be smaller compared to the other layers because the radius of this layer is large (see the discussion of Gauss's law above). In operation 916, source and drain electrodes are formed.In other embodiments, it should be recognized that these operations need not be in the same order as those described above with respect to FIG. 9, or may include additional intermediate operations, or both.

[0032] Although the description of the various embodiments has been presented for purposes of illustration, it is not intended to be exhaustive or to limit the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen in order to best explain the principles of the embodiments, the practical application, or technical improvement over technologies found in the marketplace, or to enable other practitioners of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A ferroelectric field effect transistor (FeFET), a buried oxide (BOX) layer; pads formed on the BOX layer at source and drain regions of the FeFET; a nanowire core extending over a recess formed in the BOX layer between the pads; a nanowire layer comprising: a metal electrode covering the nanowire core and extending to one of the pads; a ferroelectric layer covering the metal electrode; an interface layer covering the ferroelectric layer; a polysilicon layer formed on a channel region of the FeFET and covering the interface layer; A FeFET comprising:

2. The FeFET of claim 1 , wherein the nanowire core has a circular cross-sectional shape.

3. a dielectric oxide layer formed on the source and drain regions of the FeFET and configured to separate active regions of the FeFET; the polysilicon layer is also formed over at least a portion of the dielectric oxide layer. The FeFET according to claim 1 or 2.

4. The insulating oxide layer is made of silicon dioxide (SiO ２ ), silicon oxynitride (SiON), hafnium oxide (HfO ２ 4. The FeFET of claim 3, comprising at least one selected from the group consisting of: ZnO, FeNb, FeNbO, ZnO ...

5. The FeFET of any one of claims 1 to 4, wherein the nanowire layer comprises at least one of Si or a silicide.

6. The ferroelectric layer is made of HfO ２ The FeFET of any one of claims 1 to 5, comprising a base ferroelectric.

7. The FeFET of any one of claims 1 to 6, wherein the ferroelectric layer has a thickness in the range of 1 nm to 30 nm.

8. The interface layer is made of SiO ２ 8. The FeFET according to claim 1, comprising at least one selected from the group consisting of SiON and SiN.

9. The FeFET of any one of claims 1 to 8, wherein the interface layer has a cylindrical shell shape.

10. The FeFET of any one of claims 1 to 9, wherein the interface layer has a thickness in the range of 1 nm to 5 nm.

11. 1. A method for fabricating a ferroelectric field effect transistor (FeFET), comprising: forming a buried oxide (BOX) layer; pads formed on the BOX layer at source and drain regions of the FeFET; a nanowire core extending between the pads; forming a nanowire layer on the BOX layer, the nanowire layer comprising: undercutting the BOX layer beneath the nanowire core to space the nanowire core from the BOX layer; forming a metal electrode around the nanowire core and extending to one of the pads; forming a ferroelectric layer around the metal electrode; forming an interface layer around the ferroelectric layer; forming a polysilicon layer over a channel region of the FeFET, the polysilicon layer covering the interface layer; A method for fabricating an FeFET, comprising:

12. 12. The method of fabricating an FeFET as recited in claim 11, further comprising subjecting the nanowire core to at least one of an annealing process and an oxidation process to change the shape of the nanowire core to a cylindrical shape.

13. forming an insulator oxide layer on the source and drain regions of the FeFET and configured to separate active regions of the FeFET; the polysilicon layer is also formed over at least a portion of the dielectric oxide layer. A method for manufacturing an FeFET according to claim 11 or 12.

14. The insulating oxide layer is made of silicon dioxide (SiO ２ ), silicon oxynitride (SiON), hafnium oxide (HfO ２ 14. The method of fabricating the FeFET of claim 13, comprising at least one selected from the group consisting of: 1) a high-κ FeFET; 2) a high-κ FeFET; and any other suitable high-κ dielectric material.

15. The method for manufacturing an FeFET according to any one of claims 11 to 14, wherein the nanowire layer comprises at least one of Si or a silicide.

16. The ferroelectric layer is made of HfO ２ A method for manufacturing an FeFET according to any one of claims 11 to 15, comprising a base ferroelectric.

17. The method for manufacturing an FeFET according to any one of claims 11 to 16, wherein the ferroelectric layer has a thickness in the range of 1 nm to 30 nm.

18. The interface layer is made of SiO ２ The method for manufacturing the FeFET according to any one of claims 11 to 17, wherein the FeFET comprises at least one selected from the group consisting of SiON and SiN.

19. The method for manufacturing an FeFET according to any one of claims 11 to 18, wherein the interfacial layer has a cylindrical shell shape.

20. The method for manufacturing an FeFET according to any one of claims 11 to 19, wherein the interfacial layer has a thickness in the range of 1 nm to 5 nm.

Images