High Voltage Tunable Multilayer Capacitors

Abstract

A tunable multilayer capacitor is provided. The capacitor includes a first active electrode in electrical contact with a first active termination and a second active electrode in electrical contact with a second active termination. The capacitor includes a first DC bias electrode in electrical contact with a first DC bias termination and a second DC bias electrode in electrical contact with a second DC bias termination. A plurality of dielectric layers are provided between the first and second active electrodes and between the first and second bias electrodes. At least a portion of the dielectric layers include a tunable dielectric material that exhibits a variable dielectric constant in response to an applied DC voltage across the first and second DC bias electrodes. At least one of the plurality of dielectric layers has a thickness greater than about 15 micrometers. [Selection diagram] Figure 12

Description

Technical Field

[0001] Cross - Reference to Related Applications

[0001] This application claims the benefit of U.S. Provisional Patent Application No. 62 / 555,924, filed on September 8, 2017, the entire disclosure of which is hereby incorporated by reference.

Background Art

[0002]

[0002] Tunable capacitors have been proposed for various applications that rely on the variable permittivity of a dielectric. In the case of such capacitors, the capacitance at zero bias is typically close to its maximum value, and the capacitance decreases with the applied voltage. The change in capacitance enables these units to be used to form tunable circuits in filters, matching networks, resonant circuits, and other applications from audible to RF and microwave frequencies. Despite the benefits of such capacitors, the use of capacitors has been relatively limited, partly due to the relatively low capacitance values achieved at high power and voltage levels. Therefore, there is a current need for voltage - tunable capacitors with improved properties that can be utilized in a wider range of possible applications.

Summary of the Invention

Means for Solving the Problems

[0003] According to one embodiment of the present disclosure, a tunable multilayer capacitor is disclosed that includes a first active electrode in electrical contact with a first active terminal and a second active electrode in electrical contact with a second active terminal. The capacitor also includes a first DC bias electrode in electrical contact with a first DC bias terminal and a second DC bias electrode in electrical contact with a second DC bias terminal. The capacitor further includes a plurality of dielectric layers provided between the first and second active electrodes and between the first and second bias electrodes. At least a portion of the dielectric layer includes a tunable dielectric material that exhibits a variable dielectric constant upon application of an applied DC voltage across the first and second DC bias electrodes. At least one of the plurality of dielectric layers has a thickness greater than about 15 micrometers.

[0004] According to another embodiment of the present disclosure, a tunable multilayer capacitor is disclosed that includes a first active electrode in electrical contact with a first active terminal and a second active electrode in electrical contact with a second active terminal. The capacitor also includes a first DC bias electrode in electrical contact with a first DC bias terminal and a second DC bias electrode in electrical contact with a second DC bias terminal. The capacitor further includes a plurality of dielectric layers provided between the first and second active electrodes and between the first and second bias electrodes. At least a portion of the dielectric layer includes a tunable dielectric material that exhibits a variable dielectric constant upon application of an applied DC voltage across the first and second DC bias electrodes. The applied DC voltage is greater than about 100 V without exceeding about 50% of the breakdown voltage of the tunable dielectric material.

[0005] Other features and aspects of the present invention are described in further detail below.

[0006] A complete and enabling disclosure of the present invention, including the best mode thereof, to those skilled in the art, is set forth more particularly in the remaining part of the specification, which makes reference to the accompanying drawings.

Brief Description of the Drawings

[0006]

Figure 1

[0007] A graph showing the capacitance change achievable using the subject matter of the present disclosure over a range of normalized bias voltage changes.

Figure 2A

[0008] A cross-sectional view of an exemplary embodiment of a four-terminal bias-type multilayer capacitor according to the subject matter of the present disclosure.

Figure 2B

Figure 2C

Figure 2D

[0009] An overall side, top, and end perspective views of an assembled device according to the exemplary embodiments of FIGS. 2A - 2C.

Figure 2E

[0010] A representative diagram of a shunt configuration of the exemplary embodiments of FIGS. 2A - 2D.

Figure 2F

Figure 3A

[0011] A cross-sectional view of an exemplary embodiment of a four-terminal tunable cascade configuration multilayer capacitor according to the subject matter of the present disclosure.

Figure 3B

Figure 3C

Figure 3D

[0012] A representative diagram of a shunt configuration of the exemplary embodiments of FIGS. 3A - 3C.

Figure 3E

Figure 4A

[0013] A cross-sectional view of an exemplary embodiment of a four-terminal tunable partial bias configuration multilayer capacitor according to the subject matter of the present disclosure.

Figure 4B

Figure 4C

[0014] These are representative views of exemplary embodiments of FIGS. 4A and 4B herein.

Figure 5

[0015] FIGures showing exemplary embodiments of a chip manufacturing automated process (CMAP) according to the subject matter of the present disclosure, which can be used in the exemplary manufacturing apparatus embodiments disclosed together.

Figure 6

[0016] A cross-sectional view of an exemplary embodiment of a bias-type asymmetric multilayer capacitor according to the subject matter of the present disclosure.

Figure 7A

[0017] A cross-sectional view of an exemplary embodiment of a 1:1 ratio replicated symmetric design of a bias-type multilayer capacitor according to the subject matter of the present disclosure.

Figure 7B

Figure 7C

[0018] A cross-sectional view of another exemplary embodiment of a 1:1 ratio replicated symmetric design of a bias-type multilayer capacitor according to the subject matter of the present disclosure.

Figure 7D

Figure 8

[0019] A cross-sectional view of an exemplary embodiment of an 11:1 ratio unshielded asymmetric design of a bias-type multilayer capacitor according to the subject matter of the present disclosure.

Figure 9

[0020] A cross-sectional view of an exemplary embodiment of an 11:1 ratio shielded asymmetric design of a bias-type multilayer capacitor according to the subject matter of the present disclosure.

Figure 10

[0021] A cross-sectional view of an exemplary embodiment of a composition blend bias-type multilayer capacitor according to the subject matter of the present disclosure.

Figure 11

[0022] (a)-(c) are diagrams showing symmetric directions that can be used for active and bias terminations in an embodiment of the present invention.

Figure 12

[0023] A diagram showing an embodiment of a stacked capacitor array having a single lead and a lead frame attachment according to an aspect of the subject matter of the present disclosure.

Figure 13

[0024] A diagram showing the measured capacitance of an example of a stacked capacitor array according to an aspect of the present disclosure at an applied DC bias voltage level ranging from 0 V to 200 V.

DETAILED DESCRIPTION OF THE INVENTION

[0007]

[0025] The repeated use of reference numerals throughout this specification and the accompanying drawings is intended to represent the same or similar features, elements, or steps in this specification and the accompanying drawings.

[0026] This discussion is merely a description of exemplary embodiments and is not intended to limit the broader aspects of the invention, which should be understood by those skilled in the art to be embodied in exemplary structures.

[0008]

[0027] Generally speaking, the present invention is directed to a multilayer capacitor including a plurality of dielectric layers interposed between alternating active electrode layers. At least a portion of the dielectric layer includes a tunable material that exhibits a variable dielectric constant upon application of an applied voltage. More specifically, such materials typically have a "voltage tunability coefficient" in the range of from about 10% to about 90%, in some embodiments from about 20% to about 80%, and in some embodiments from about 30% to about 70%, and the "voltage tunability coefficient" is given by the following general formula: T = 100×(ε 0 -ε ν ) / ε 0 and is determined according to wherein T is the voltage tunability coefficient, ε 0 is the static dielectric constant of the material without an applied voltage, ε ν is the variable dielectric constant of the material after application of an applied voltage (DC).

[0009]

[0028] The static dielectric constant of the material typically ranges from about 100 to about 25,000, in some embodiments from about 200 to about 10,000, and in some embodiments from about 500 to about 9,000, as determined by ASTM D2149-13 at an operating temperature (e.g., 25°C) ranging from about -55°C to about 150°C and a frequency (e.g., 1 kHz) ranging from about 100 Hz to about 1 GHz. Of course, it should be understood that specific values of the static dielectric constant are generally selected based on the particular application in which the capacitor is utilized. When an increased DC bias is applied, the dielectric constant generally decreases within the above-described range. The tuning voltage applied to induce a desired change in the dielectric constant may generally vary with respect to the voltage (the "breakdown voltage") at which the dielectric composition begins to conduct upon application of an electric field, which can be determined by ASTM D149-13 at a temperature of 25°C. In most embodiments, the applied DC bias voltage is about 50% or less of the breakdown voltage of the dielectric composition, in some embodiments about 30% or less, and in some embodiments from about 0.5% to about 10%.

[0010]

[0029] Any of a variety of tunable dielectric materials may generally be utilized as is well known. Particularly suitable materials are dielectrics whose base composition includes one or more ferroelectric base phases, such as perovskites, tungsten bronzes materials (e.g., barium sodium niobate), layered structure materials (e.g., bismuth titanate), etc. Suitable perovskites may include, for example, barium titanate and related solid solutions (e.g., barium strontium titanate, barium calcium titanate, barium zirconate titanate, barium strontium zirconate titanate, barium calcium zirconate titanate, etc.), lead titanate and related solid solutions (e.g., lead zirconate titanate, lead lanthanum zirconate titanate), sodium bismuth titanate, etc. In one particular embodiment, for example, the formula Ba x Sr 1-x TiO 3Barium strontium titanate (“BSTO”) may be utilized, where x ranges from 0 to 1, in some embodiments from about 0.15 to about 0.65, and in some embodiments from about 0.25 to about 0.6. Other electronically tunable dielectric materials may be used, in whole or in part, in place of barium strontium titanate. For example, one example is Ba x Ca 1-x TiO 3 where x ranges from about 0.2 to about 0.8, and in some embodiments from about 0.4 to about 0.6. Other suitable perovskites include lead x Zr 1-x TiO 3 (“PZT”), lead lanthanum zirconate titanate (“PLZT”) where x ranges from about 0.05 to about 0.4, lead titanate (PbTiO 3 ), barium calcium zirconium titanate (BaCaZrTiO 3 ), sodium nitrate (NaNO 3 ), KNbO 3 , LiNbO 3 , LiTaO 3 , PbNb 2 O 6 , PbTa 2 O 6 , KSr(NbO 3 ) and NaBa 2 (NbO 3 ) 5 KHb 2 PO 4 may be included. Yet further complex perovskites may include A[B1 1 / 3 B2 2 / 3 O 3 materials, where A is Ba x Sr 1-x (where x can be a value from 0 to 1), B1 is Mg y Zn 1-y (where y can be a value from 0 to 1), and B2 is Ta z Nb 1-z(where z can be a value from 0 to 1). As illustrated in the exemplary embodiment of FIG. 10, a potential dielectric material of interest can be formed by combining two end-component compositions in alternating layers. Such end-component compositions may be chemically similar, but may differ in the ratio of A-site dopants as described above. For example, Composition 1 (132 in FIG. 10) may be a perovskite compound of the general formula (A1 x , A2 (1-x) )BO 3 , and Composition 2 (134) may be a perovskite of the general formula (A1 y , A2 (1-y) )BO 3 , where A1 and A2 are from Ba, Sr, Mg, and Ca, potential B-site members are Zr, Ti, and Sn, and "x" and "y" represent the mole fractions of the respective components. A specific example for Compound 1 may be (Ba 0.8 Sr 0.2 )TiO 3 , and Compound 2 may be (Ba 0.6 Sr 0.4 )TiO 3 . These two compounds may be combined in alternating layers in a sintered multilayer capacitor with a tunable electrode structure as illustrated in FIG. 10 such that the dielectric properties of each material are superimposed. Optionally, the perovskite material may also be doped with a rare earth oxide ("REO") in an amount of 5.0 mole percent or less, and more preferably from 0.1 to 1 mole percent. Suitable rare earth oxide dopants for this purpose may include, for example, scandium, yttrium, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, and lutetium.

[0011]

[0030] Regardless of the specific materials utilized, the use of tunable dielectric materials can enable the capacitance of the resulting capacitor to be tuned by applying a DC bias voltage through bias terminations. More specifically, the capacitor includes a first set of active electrodes in electrical contact with a first active terminal (e.g., an input terminal) and a second set of active electrodes in electrical contact with a second active terminal (e.g., an output terminal). The capacitor also includes a first set of DC bias electrodes in electrical contact with a first DC bias termination and a second set of DC bias electrodes in electrical contact with a second DC bias termination. When provided in a circuit, a DC power source (e.g., a battery, a constant voltage power supply, a multi-output power supply, a DC-DC converter, etc.) can provide a DC bias to the capacitor through first and second bias terminations that are typically bipolar in that they have opposite polarities. The electrodes and terminations may be formed from any of a variety of different metals, such as noble metals (e.g., silver, gold, palladium, platinum, etc.), base metals (e.g., copper, tin, nickel, etc.), and various combinations thereof, as is well known. The dielectric layers are interposed between the respective active electrodes and bias electrodes.

[0012]

[0031] Regardless of the specific configuration utilized, the inventors have discovered that through the selective control of the properties of the tunable dielectric material, the number of dielectric layers, and the thickness of the dielectric layers, a capacitor can be achieved that exhibits excellent tunability over a wide range of voltage and capacitance values. For example, such a capacitor may enable a higher applied DC bias voltage value and a higher capacitance with a smaller overall size than has previously been thought possible for a single capacitor (compared to a composite capacitor connected in parallel). In certain embodiments, for example, the applied DC bias voltage is greater than about 10V, in some embodiments greater than about 50V, in some embodiments greater than about 100V, in some embodiments greater than about 350V, in some embodiments greater than about 500V, in some embodiments greater than about 750V, in some embodiments greater than about 1000V, in some embodiments greater than about 1200V, and in some embodiments greater than about 1500V. For example, in some embodiments, the applied DC bias voltage may range from about 10V to about 1500V, in some embodiments from about 20V to about 1000V, in some embodiments from about 30V to about 750V, in some embodiments from about 40V to about 500V, and in some embodiments from about 50V to about 350V. The applied bias field may similarly range from about 0.2V / μm to about 50V / μm, in some embodiments from about 0.5V / μm to about 40V / μm, in some embodiments from about 0.5V / μm to about 25V / μm, and in some embodiments from about 1V / μm to about 7V / μm.

[0013]

[0032] The capacitance value may also be controlled within a wider range of values than has been conventionally thought possible. For example, as will be described later, a tunability may be constructed that has an initial capacitance value ranging from 0.5 to 50,000,000 picofarads (“pF”). Thus, the capacitor may be used in applications where a high capacitance is required, such as values of 100 pF or more, in some embodiments about 10,000 pF or more, in some embodiments from about 100,000 to about 10,000,000 pF, in some embodiments from about 200,000 to 5,000,000 pF, and in some embodiments from about 400,000 to about 3,500,000 pF. Similarly, in other embodiments, the capacitor may be used in applications where a low capacitance is required, such as values of less than 100 pF, in some embodiments about 50 pF or more, in some embodiments from about 0.5 to about 30 pF, and in some embodiments from about 1 to about 10 pF. The degree to which the capacitance can be tuned may vary as desired. For example, the capacitance may be adjusted by values from about 10% to about 100% of its initial value, in some embodiments from about 20% to about 95%, and in some embodiments from about 30% to about 80%. The capacitance may be determined using an Agilent 4294A impedance analyzer at a frequency of 1 kHz or 1 MHz, a temperature of about 25° C., and a fixed amplitude of 500 mV.

[0014]

[0033] In some embodiments, the dielectric layer may have a thickness ranging from about 5 micrometers (μm) to about 150 μm, in some embodiments from about 15 μm to about 100 μm, and in some embodiments from about 30 μm to about 70 μm, for example, about 50 μm. The electrode layer may have a thickness ranging from about 0.5 μm to about 3.0 μm, in some embodiments from about 1 μm to about 2.5 μm, and in some embodiments from about 1 μm to about 2 μm, for example, about 1.5 μm.

[0015]

[0034] The total number of active and bias electrode layers may vary. For example, in some embodiments, the total number of active electrode layers may range from 2 to about 10,000, in some embodiments from 2 to about 1,000, in some embodiments from about 10 to about 500, and in some embodiments from about 30 to about 120, for example, about 50. For example, in some embodiments, the total number of bias electrodes may range from 2 to about 10,000, in some embodiments from 2 to about 1,000, in some embodiments from about 10 to about 500, and in some embodiments from about 30 to about 120, for example, about 50. It should be understood that the number of electrodes and bias layers depicted in the figures and described herein are merely illustrative.

[0016]

[0035] The length of the capacitor may range, for example, from about 1 millimeter (mm) to about 50 mm, in some embodiments from about 2 mm to about 35 mm, in some embodiments from about 5 mm to about 15 mm, and in some embodiments from about 7 mm to about 14 mm. The width of the capacitor may range, for example, from about 1 mm to about 50 mm, in some embodiments from about 2 mm to about 35 mm, in some embodiments from about 5 mm to about 15 mm, and in some embodiments from about 7 mm to about 14 mm.

[0017]

[0036] The height of the capacitor may range, for example, from about 0.5 mm to about 14 mm, in some embodiments from about 0.75 mm to about 7 mm, in some embodiments from about 1 mm to about 5 mm, and in some embodiments from about 2 mm to about 5 mm, for example, about 3 mm. The ratio of the length of the capacitor to the height of the capacitor may range, for example, from about 1 to about 15, in some embodiments from about 2 to about 7, in some embodiments from about 3 to about 5, for example, about 4. The ratio of the width of the capacitor to the height of the capacitor may range, for example, from about 1 to about 15, in some embodiments from about 2 to about 7, in some embodiments from about 3 to about 5, for example, about 4.

[0018]

[0037] FIG. 1 illustrates, in graphical form, the change in capacitance that can be achieved over a range of normalized bias voltage changes. Specifically, the horizontal axis graphically shows the normalized bias voltage as a percentage of the rated voltage of the device, such as from 0% to 150%. As shown, the corresponding change in the effective capacitance of the device is graphically shown on the vertical axis as a percentage change from the capacitance value without any bias. As illustrated by such a graph of FIG. 1, an increase of 150% in the amount of normalized bias voltage approaches a decrease of 80% in the bias-free capacitance value along a relatively linear curve, as illustrated. Thus, the voltage-tunable capacitor device according to the subject matter of the present disclosure facilitates maximizing efficiency over a range of operating conditions.

[0019]

[0038] Referring now to FIGS. 2A - 2D, one particular embodiment of the capacitor 10 that can be formed in accordance with the present invention is described in further detail herein. As shown, the capacitor 10 includes a plurality of dielectric layers 12 that are alternately stacked with respect to two separate sets of active electrodes 14 and 20 and two separate sets of bias electrodes 22 and 26. The capacitor may be a hexahedron such as a rectangular parallelepiped. In the illustrated embodiment, a first active terminal 16 is electrically connected to the first active electrode 14, and a second active terminal 18 is electrically connected to the second active electrode 20. The first bias electrode 22 is electrically connected to a first DC bias (+) terminal 30 via an extension member 24 (e.g., a tab) that extends to the side of the capacitor 10. Similarly, the second bias electrode 26 is electrically connected to a second DC bias (-) terminal 32 via an extension member 28. Thus, the resulting capacitor 10 includes four separate terminals. In some embodiments, the active terminals 16, 18 may wrap around respective ends of the capacitor 10 to provide larger terminals 16, 18 for electrically connecting the capacitor 10 to a circuit. The DC bias terminals 30, 32 may be configured as strips that do not extend across the entire side of the capacitor 10. In other embodiments, however, the DC bias terminals 30, 32 may instead wrap around the side of the capacitor 10, and the active terminals 16, 18 may be configured as strips that do not extend along the entire end of the capacitor.

[0020]

[0039] FIGS. 2E and 2F illustrate, respectively, representative diagrams of a shunt configuration and a series configuration of the exemplary embodiment of FIGS. 2A - 2D. As shown, for the shunt configuration, it is illustrated that a ground 34 is also provided with respect to the bias input.

[0021]

[0040] In the above-described embodiments, the active electrodes are stacked such that each alternating electrode is connected to the opposite end. In certain embodiments, the alternating layers may be connected to the same end through the use of a "cascade" configuration in which each set of active electrodes is spaced laterally rather than stacked. One embodiment of such a cascade capacitor 49 is illustrated in FIGS. 3A - 3C. As depicted, capacitor 49 includes a plurality of dielectric layers 44 disposed with respect to two separate sets of active electrodes 36 and 40 and two separate sets of bias electrodes 46 and 50. In the illustrated embodiment, in this example, a first active terminal 38 is electrically connected to the first active electrode 36 and a second active terminal 42 is electrically connected to the second active electrode 40. The first bias electrode 46 is electrically connected to a first DC bias (-) terminal 54 via an extension member 48 that extends to the side of capacitor 49. Similarly, the second bias electrode 50 is electrically connected to a second DC bias (+) terminal 56 via an extension member 52. FIGS. 3D and 3E illustrate representative diagrams of a shunt configuration and a series configuration, respectively, of the exemplary embodiment of FIGS. 3A - 3C. As shown, for the shunt configuration, a ground 58 is also provided with respect to the bias input.

[0022]

[0041] Figures 4A - 4C illustrate another embodiment of a capacitor 59 that may be formed in a partial vertical stack configuration according to the present invention. The capacitor 59 is considered "partially vertical" because only a partial region 60 of the total active capacitance region is biased (see Figure 4A). The addition of a biased floating electrode as illustrated causes the application of an external voltage to vary the permittivity of the total capacitance that would otherwise be required by other factors and characteristics. As illustrated by such figures, a dielectric layer 62 may be alternately stacked with respect to first and second sets of active electrodes 64 and 66, first and second sets of bias electrodes 68 and 72, and a plurality of floating electrodes 76. The first active electrode 64 is electrically connected to a first active terminal 78, while the second active electrode 66 is electrically connected to a second active terminal 80. The first bias electrode 68 is electrically connected to a first DC bias (+) terminal 82 via an extension member 70 that extends to the side of the capacitor 59. Similarly, the second bias electrode 72 is electrically connected to a second DC bias (-) terminal 84 via an extension member 74. It should be understood that the number of electrode layers illustrated in Figure 4A is exemplary only. As described above, in some embodiments, the number of active electrodes may range from 2 to about 10,000. As described above, in some embodiments, the number of bias electrodes may range from 2 to about 10,000.

[0023]

[0042] Yet another embodiment according to aspects of the present disclosure is illustrated in Figures 7A and 7B. In this embodiment, first and second sets of active electrodes 114, 120 are stacked in an alternating 1:1 ratio pattern with first and second sets of bias electrodes 122, 126, respectively. Referring to Figure 7B, in some embodiments, leads 124, 128 of bias electrodes 122, 126 may be configured as protruding tabs. Conductive leads 124, 128 may contact DC bias terminals 30, 32 in a completed form as illustrated in Figure 2D. It should be understood that the number of electrode layers illustrated in Figures 7A and 7B is exemplary only.

[0024]

[0043] Another embodiment according to an aspect of the present disclosure is illustrated in FIGS. 7C and 7D. In this embodiment, the active electrodes 114, 120 may include respective lead wires 125 and 127 configured as protruding tabs. The lead wires 125, 127 may be electrically connected to respective active terminations 16, 18 illustrated in FIG. 7D. This configuration may provide an improved stack between the edges of the capacitor layers, specifically at the corners of the layers, resulting in a more robust capacitor. Additionally, this configuration may reduce the occurrence of delamination problems during manufacturing.

[0025]

[0044] Additionally, the respective widths of the tabs 124, 125, 126, 127 may be selected to advantageously provide greater electrical contact (e.g., having less resistance) to the respective electrodes 114, 120, 122, 126. Additionally, the widths of the tabs 124, 128 and the widths of the terminations 30, 32 associated with the DC bias electrodes 122, 126 may be selected to avoid contact between the bias electrode terminations 30, 32 and the signal electrode terminations 16, 18. For example, in some embodiments, the tabs 124, 125, 126, 127 may extend along more than 10% of the edge of the capacitor, in some embodiments more than 30%, and in some embodiments more than 60%. It should be understood that the number of electrode layers illustrated in FIGS. 7A - 7D is exemplary only. As described above, in some embodiments, the number of active electrodes may range from 2 to about 10,000. As described above, in some embodiments, the number of bias electrodes may range from 2 to about 10,000.

[0026]

[0045] In the above-described embodiments, the electrodes are generally utilized in a "symmetric" configuration in that the distance between the first and second active electrodes (or dielectric thickness) is the same as the distance between the first and second bias electrodes. In certain embodiments, however, it may be desirable to vary this thickness to achieve an "asymmetric" configuration. For example, the distance between the first and second active electrodes may be less than the distance between the first and second bias electrodes. In yet other embodiments, the distance between the first and second active electrodes may be greater than the distance between the first and second bias electrodes. In particular, this may increase the DC field applied for a given level of applied DC bias, which will increase the level of tunability for a given DC bias voltage. Such an arrangement may also allow for the use of materials with relatively greater tunability for relatively lower DC voltages as well as materials with modest tunability (potentially with lower losses and temperature / frequency variability). Such asymmetric configurations can be achieved in a variety of ways, but it is typically desirable to use additional "floating" bias electrodes between each pair of active electrodes. Referring to FIG. 6, for example, one embodiment of such an asymmetric capacitor is shown that includes first and second active electrodes 114 and 120, respectively, in combination with first and second bias electrodes 122 and 126, respectively.

[0027]

[0046] FIG. 8 illustrates another embodiment of an asymmetric capacitor that is an active electrode rather than a bias electrode for each 11th electrode (11:1 ratio design). In this case, each such respective active electrode (e.g., an AC electrode) may be surrounded by a pair of DC electrode bias electrodes having opposite polarities. Thus, a bias field may be generated across each AC electrode. Such a structure may provide capacitive coupling between the AC signal and both polarities of the DC bias voltage, and vice versa. Each AC electrode 214, 220 may be provided between a pair of bias electrodes 222, 226 having opposite polarities. The first set of bias electrodes 222 may all have the same polarity, and the second set of bias electrodes 226 (illustrated by the dashed line) may all have the respective polarities opposite to those of the first set of bias electrodes 222. This configuration may provide capacitive coupling between each of the AC electrodes 214, 220 and both DC bias polarities.

[0028]

[0047] FIG. 9 illustrates a cross-sectional view of an exemplary embodiment of an 11:1 ratio "shielded type" asymmetric design of a bias type multilayer capacitor according to the subject matter of the present disclosure. This example is similar to the example illustrated in FIG. 8 except that each AC electrode 314, 320 is surrounded by a pair of DC electrodes (322 or 326) having the same polarity. One set of bias electrodes 322 may all have the same polarity, and the other set of bias electrodes 326 (illustrated by the dashed line) may all have opposite polarities. The material between the two DC electrodes (322 or 326) having the same polarity may not provide tuning, but the material may potentially provide a shield for the AC signal and reduce associated noise. Such a structure may also provide coupling between each of the first set of AC electrodes 314 and only a single DC bias polarity. Similarly, such a structure may provide capacitive coupling between the second set of AC electrodes 320 and only the opposite DC bias polarity.

[0029]

[0048] It should be understood that the number of electrode layers illustrated in FIGS. 8 and 9 is exemplary only. As described above, in some embodiments, the number of active electrodes may range from 2 to about 10,000. As described above, in some embodiments, the number of bias electrodes may range from 2 to about 10,000.

[0030]

[0049] Although not necessarily required, it is typically desired that the active and DC bias terminations be provided symmetrically about the axis of the capacitor. For example, in one embodiment, the capacitor may include first and second end regions that are vertically spaced and opposed and first and side regions that are horizontally spaced and opposed. In one embodiment, the active terminations may be provided at respective end regions of the capacitor while the DC bias terminations may be provided at respective side regions of the capacitor. When arranged symmetrically, the active terminations and / or the DC bias terminations may be spaced equidistant from longitudinal and / or transverse axes extending through the geometric center of the capacitor. Referring to FIG. 11(a), for example, one embodiment of a capacitor 1000 is illustrated that includes a longitudinal axis "x" and a transverse axis "y" that are perpendicular to each other and extend through the geometric center "C". In this particular embodiment, the capacitor 1000 includes first and second active terminations 1100 and 1120 that are provided at respective end regions of the capacitor 1000 and centered about both axes "x" and "y". Similarly, the capacitor 1000 includes first and second bias terminations 1140 and 1160 that are provided at respective side regions of the capacitor 1000 and centered about both axes "x" and "y".

[0031]

[0050] In some embodiments, it may also be desirable to provide two or more terminals on the same side of the capacitor. In FIG. 11(b), for example, one embodiment of a capacitor 2000 is illustrated that includes a first active terminal 2100 and a second active terminal 2140 provided in the same side region. Capacitor 2000 also includes a first bias terminal 2160 and a second bias terminal 2120 that are both provided in another side region opposite the side region of the active terminals. Despite being provided only in the side region, the active terminals 2100 and 2140 are still symmetrically arranged in that they are both positioned equidistant from the axes “x” and “y”. Similarly, the bias terminals 2160 and 2120 are also provided equidistant from the axes “x” and “y”. In the embodiments described above, the first active terminal and the first bias terminal are positioned on the opposite sides of their respective second active terminal and second bias terminal. Of course, this is not at all essential. In FIG. 11(c), for example, a capacitor 3000 is illustrated that includes first and second active electrode terminals 3100 and 3160 provided in opposite side regions in a diagonal configuration, respectively. Still, the first active terminal 3100 and the second active terminal 3160 are still symmetrically arranged in that they are both positioned equidistant from the axes “x” and “y”. Similarly, capacitor 3000 also includes first and second bias terminals 3120 and 3140 provided in opposite side regions in a diagonal configuration that is also equidistant from the axes “x” and “y”.

[0032]

[0051] The subject matter of the present disclosure equally encompasses related and / or corresponding methods, including, for example, the use of a device in combination with an associated circuitry, in addition to the production of such improved voltage tunable devices. As a further example, FIG. 5 depicts a chip manufacturing automated process (CMAP) 86 that can be used in conjunction with the exemplary manufacturing apparatus embodiments disclosed together. As shown, process 86 may include several consecutive stages, which in some examples involve three ovens with intervening other steps / phases, such as the use of a ceramics station or a screen head or elevator and conveyor functions, as typically illustrated. One of ordinary skill in the art will understand that the exact provision of the consecutive steps will depend on which of the exemplary device embodiments (or modifications thereof) disclosed together are being produced. Also, the individual steps shown are only intended to represent steps of the type shown and do not indicate that the use of other aspects beyond the general nature of the steps shown is essential. For example, the screen head step may involve the use of a stainless steel screen with an electrode paste for screen printing of an electrode layer, or other techniques for such steps may be practiced. For example, more conventional steps of alternating stacking and laminating (with tape) may be implemented. In any process (or otherwise), one of ordinary skill in the art will recognize that the selected steps may be implemented to produce a particular design selected for a given application of the subject matter of the present disclosure.

[0033]

[0052] Referring to FIG. 12, a multilayer capacitor array 4000 may be formed by stacking individual capacitors 10 as illustrated in FIGS. 2A - 2D, for example. The multilayer capacitor array 4000 may provide increased capacitance compared to a single capacitor 10 and may enable easier manufacturing and assembly. The capacitors 10 may be connected in parallel. For example, a first lead frame 4002 may connect each first active terminal 16, and a second lead frame 4004 may connect each second active terminal 19. A first single lead 4006 may connect each first DC bias terminal 30, and a second single lead 4008 may connect each second DC bias terminal 32. As described above with respect to FIGS. 2A - 2D, in some embodiments, the structures of the active terminals 16, 18 and the DC bias terminals 30, 32 may be reversed. For example, the DC bias terminals 30, 32 may wrap around the capacitor 10 instead of the active terminals 16, 18 that wrap around the capacitor 10 as illustrated in FIG. 12. In some embodiments, the multilayer capacitor array 4000 may include 2 to 24 capacitors, in some embodiments 3 to 12 capacitors, and in some embodiments 4 to 6 capacitors. In other embodiments, the multilayer capacitor array 4000 may include more than 24 capacitors.

[0034]

[0053] The capacitors of the present invention can be utilized in a wide variety of applications, including, for example, circuits used in aircraft. For example, one application may include an AC circuit operating in a frequency range from about 200 Hz to about 1200 Hz, in some embodiments from about 300 Hz to about 1100 Hz, and in some embodiments from about 400 Hz to about 1000 Hz. In such an application, the capacitor may have a capacitance ranging from about 5 microfarads (μF) to about 15 μF, and in some embodiments from about 8 μF to about 12 μF, for example, about 10 μF. The applied bias voltage may range from about 100 V to about 300 V, in some embodiments from about 150 V to about 250 V, for example, 200 V.

[0035]

[0054] Further uses may include circuitry enabled to tune the oscillation frequency of a switched-mode power supply. Through the use of the capacitors of the present invention, materials with relatively modest tunability but potentially lower losses and lower temperature / frequency variability are enabled, while better tunability can be selectively obtained at high DC voltages (i.e., bias voltages). Other suitable uses may include, for example, waveguides, RF applications (e.g., delay lines), antenna structures, filters (e.g., load point filters and circuits), matching networks, resonant circuits, smoothing capacitors in variable load circuits, and other uses.

[0036] Examples

[0055] A stacked capacitor array including a plurality of tunable multilayer capacitors according to aspects of the present disclosure is illustrated. The stacked capacitor array was assembled as illustrated in FIG. 12 and included three tunable multilayer capacitors. The capacitor array had an overall length of about 12.7 mm (0.5 inches), an overall width of about 12.7 mm (0.5 inches), and an overall height of about 3.1 mm (0.12 inches).

[0037]

[0056] Each of the three capacitors in the array included a dielectric material including barium titanate. Each dielectric layer had a thickness of about 50 μm. There were 54 active electrodes and 55 bias electrodes alternating. The individual capacitors had a capacitance of about 1.8 μF.

[0038]

[0057] An AC sine wave signal having an amplitude of 1 V and a frequency of 1 kHz was applied across the active terminals 16, 19 (via the first and second lead frames 4002, 4004). Various DC bias voltage levels were applied across the DC bias terminals 30, 32 (via the first and second single leads 4006, 4008).

[0039]

[0058] FIG. 13 illustrates the measured capacitance of a stacked capacitor array across the first and second lead frames 4002, 4004 at DC bias voltage levels ranging from 0V to 200V. As shown in FIG. 13, the measured capacitance between the active terminals 16, 19 decreased from 5.47 μF at a DC bias voltage of 0V to approximately 3.66 μF at a DC bias voltage of 200V. The measured capacitance values and the applied DC bias voltages plotted in FIG. 13 are presented in the following table in addition to the "synchronization" parameter. The "synchronization" parameter was calculated as the measured capacitance at each DC bias voltage level divided by the initial capacitance (5.47 μF) at a DC bias voltage of 0V.

[0040]

Table 1

[0041]

[0059] These and other modifications and variations of the present invention can be made by those skilled in the art without departing from the spirit and scope of the present invention. In addition, it should be understood that aspects of various embodiments can be exchanged, wholly or in part. Furthermore, those skilled in the art will recognize that the above description is merely exemplary and is not intended to limit the present invention as further described in the appended claims.

Claims

1. a first active electrode in electrical contact with the first active termination; a second active electrode in electrical contact with the second active termination; a first DC bias electrode in electrical contact with the first DC bias termination; a second DC bias electrode in electrical contact with the second DC bias termination; a plurality of dielectric layers disposed between the first and second active electrodes and between the first and second DC bias electrodes, at least a portion of the dielectric layers comprising a tunable dielectric material that exhibits a variable dielectric constant upon application of an applied DC bias voltage across the first and second DC bias electrodes; a total number of the first and second active electrodes ranges from about 10 to about 100; A tunable stacked capacitor, wherein the thickness of said dielectric layers ranges from about 15 micrometers to about 150 micrometers.

2. 10. The capacitor of claim 1, wherein the applied DC bias voltage is from about 100V to about 1000V.

3. The capacitor of claim 1 , wherein the capacitor has a length of from about 7 mm to about 14 mm.

4. The capacitor of claim 1 , wherein the capacitor has a width of from about 7 mm to about 14 mm.

5. The capacitor of claim 1 , wherein the capacitor has a height of from about 2 mm to about 5 mm.

6. 10. The capacitor of claim 1, wherein a ratio of the length of the capacitor divided by the height of the capacitor ranges from about 3 to about 5.

7. The dielectric material has a voltage tunability factor of from about 10% to about 95%, the voltage tunability factor being within the following general formula: T=100×(e) ０ -e ν ) / e ０ is required according to During the ceremony, T is the voltage tunability factor, ε ０ is the static dielectric constant of the material with no applied voltage, ε ν is the variable dielectric constant of the material after application of an applied voltage (DC); The capacitor of claim 1 .

8. 8. The capacitor of claim 7, wherein the static dielectric constant of the dielectric material is from about 100 to about 10,000 as determined by ASTM D2149-13 at an operating temperature of 25° C. and a frequency of 1 kHz.

9. The capacitor of claim 1 , wherein the dielectric material comprises one or more ferroelectric base phases.

10. 10. The capacitor of claim 9, wherein the dielectric material is a perovskite, a tungsten bronze material, a layered structure material, or a combination thereof.

11. The capacitor of claim 1 , wherein the first and second active terminations and the first and second DC bias terminations are disposed symmetrically about the capacitor.

12. 2. The capacitor of claim 1, wherein the distance between the first and second active electrodes is approximately the same as the distance between the first and second DC bias electrodes.

13. The capacitor of claim 1 , wherein a distance between the first and second active electrodes is greater than a distance between the first and second DC bias electrodes.

14. The capacitor of claim 1 , wherein the capacitor is capable of being tuned to a capacitance value of about 5,000,000 pF or greater.

15. The capacitor of claim 1 , wherein the capacitor is capable of being tuned to a capacitance value of about 200,000 pF or less.

16. 2. The capacitor of claim 1 , wherein the first DC bias electrode includes a tab that extends to the first DC bias termination, the second DC bias electrode includes a tab that extends to the second DC bias termination, or a combination thereof.

17. 2. The capacitor of claim 1 , wherein the first active electrode includes a tab extending to the first active termination, the second active electrode includes a tab extending to the second active termination, or a combination thereof.

18. 10. A circuit comprising: a capacitor as recited in claim 1; and a power supply that provides a DC bias voltage to the capacitor through the first and second DC bias terminations.

19. 10. A stacked capacitor array comprising: a capacitor according to claim 1; a first lead frame connected with each of the first active terminations; and a second lead frame connected with each of the second active terminations.

20. 20. The stacked capacitor array of claim 19, further comprising a first single lead connected to each of the first DC bias terminations and a second single lead connected to the second DC bias termination.

Images