Signal processing circuit, digital coherent receiver, and digital coherent communication system

Abstract

To stably implement mode demultiplexing even under the influence of phase fluctuation and frequency offset while compensating for IQ imbalance between a transmitter and a receiver with a minimum required calculation amount.SOLUTION: A signal processing circuit 1 includes a first digital filter 10 which is used in a digital coherent receiver and has a plurality of butterfly filters, a second digital filter 20 having one or more butterfly filters, a third digital filter 30, and a fourth digital filter 40 having one or more two-parallel filters. The first digital filter 10, the second digital filter 20, the third digital filter 30 and the fourth digital filter 40 are connected in series in this order when viewed from the input side of an optical signal to the digital coherent receiver.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present disclosure relates to a signal processing circuit, a digital coherent receiver, and a digital coherent communication system. [Background technology]

[0002] A digital coherent receiver is composed of digital signal processing and a coherent optical receiver, and is widely used in long-distance optical fiber transmission systems. By using a high-order multilevel modulation method in a digital coherent receiver, the transmission capacity can be increased (for example, see Non-Patent Document 1). [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] Jens C. Rasmussen et al., "Digital Coherent Receiving Technology for 100 Gbps Optical Transmission Systems," September 2009, FUJITSU, vol. 60, 5, p. 476-483, Internet URL: http: / / img.jp.fujitsu.com / downloads / jp / jmag / vol60-5 / paper18.pdf Summary of the Invention [Problem to be solved by the invention]

[0004] However, in high-order multi-level modulation, the symbols are densely arranged on the constellation, so the effects of IQ imbalance, including IQ gain imbalance, IQ phase imbalance, and IQ skew, are serious. Furthermore, mode division multiplexing technology is available as a method for increasing transmission capacity. In mode division multiplexing systems, crosstalk occurs due to coupling between modes, so mode separation technology is essential to stably remove crosstalk. Therefore, it is necessary to realize digital signal processing technology that can stably perform IQ imbalance compensation and mode separation technology.

[0005] As a mode separation technique, a FIR (Finite Impulse Response) filter using complex tap coefficients has been proposed. This technique uses the LMS (Least Mean Square) algorithm, which performs mode separation using a training signal, and therefore minimizes crosstalk between signals and avoids the mode singularity problem specific to the CMA (Constant Envelope Algorithm). Using this technique, successful results have been reported in transmission experiments with fiber capacities of up to 10 Pbps. Real-time operation has also been confirmed.

[0006] However, this technology cannot compensate for IQ imbalance. On the other hand, by changing the mode separation section to a butterfly filter with real coefficients, it is possible to compensate for the IQ imbalance. However, under the influence of frequency offset, it is not possible to compensate for the transmitter IQ imbalance. This problem can be solved by connecting two real coefficient butterfly filters. However, since the phase estimator and the mode separator do not work together, it is necessary to adopt an unstable CMA as the mode separator. Therefore, when the number of modes multiplexed increases, mode separation cannot be performed. In addition, there is an issue with the calculation cost because butterfly filters with multiple taps must be connected in series.

[0007] On the other hand, digital signal processing technology has been proposed that can compensate for IQ imbalance while performing mode demultiplexing. However, in order to realize the transmitter IQ imbalance compensation function, it is necessary to quadruple the number of filters that perform mode demultiplexing, which is not effective in terms of calculation cost.

[0008] The present disclosure has been made in consideration of these circumstances, and its purpose is to provide a digital signal processing circuit that can achieve stable mode multiplexing / demultiplexing even under the influence of phase fluctuations and frequency offsets, while compensating for IQ imbalance in both the transmitter and receiver with a minimum amount of calculation. [Means for solving the problem]

[0009] In order to solve the above problems, a signal processing circuit according to an embodiment of the present invention is used in a digital coherent receiver. The signal processing circuit includes a first digital filter having a plurality of butterfly filters, a second digital filter having one or more butterfly filters, a third digital filter, and a fourth digital filter having one or more two parallel filters. The first digital filter, the second digital filter, the third digital filter, and the fourth digital filter are connected in series in this order when viewed from the input side of an optical signal to the digital coherent receiver.

[0010] Another aspect of the present invention is a digital coherent receiver. The digital coherent receiver includes a signal processing circuit, a coherent receiver, an AD converter, and a local light source. The signal processing circuit includes a first digital filter having a plurality of butterfly filters, a second digital filter having one or more butterfly filters, a third digital filter, and a fourth digital filter having one or more two parallel filters. The first digital filter, the second digital filter, the third digital filter, and the fourth digital filter are connected in series in this order when viewed from the input side of the optical signal to the digital coherent receiver.

[0011] Yet another embodiment of the present invention is a digital coherent communication system. The digital coherent communication system includes a transmitter and a digital coherent receiver. The digital coherent receiver includes a signal processing circuit, a coherent receiver, an AD converter, and a local light source. The signal processing circuit includes a first digital filter having a plurality of butterfly filters, a second digital filter having one or more butterfly filters, a third digital filter, and a fourth digital filter having one or more two parallel filters. The first digital filter, the second digital filter, the third digital filter, and the fourth digital filter are connected in series in this order when viewed from the input side of the optical signal to the digital coherent receiver.

[0012] Any combination of the above components, and conversion of the present disclosure into a method, device, system, recording medium, computer program, etc. are also valid aspects of the present disclosure. Effect of the Invention

[0013] According to the present disclosure, it is possible to realize stable mode demultiplexing even under the influence of phase fluctuations and frequency offsets while compensating for IQ imbalance in both the transmitter and the receiver with a minimum required amount of calculations. [Brief description of the drawings]

[0014] [Figure 1] FIG. 2 is a functional block diagram of an adaptive filter. [Diagram 2] FIG. 2 is a functional block diagram of a butterfly filter. [Diagram 3] 1 is a functional block diagram of a signal processing circuit according to a first embodiment. [Figure 4] FIG. 11 is a functional block diagram of a digital coherent receiver according to a second embodiment. [Diagram 5] FIG. 11 is a functional block diagram of a digital coherent communication system according to a third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] The present invention will be described below based on preferred embodiments with reference to the drawings. In the embodiments and modified examples, identical or equivalent components and parts are given the same reference numerals, and duplicated descriptions are omitted as appropriate. The dimensions of the parts in each drawing are enlarged or reduced as appropriate for ease of understanding. Some elements that are not important for explaining the embodiments are omitted in each drawing. Terms including ordinal numbers such as first and second are used to describe various components, but these terms are used only for the purpose of distinguishing one component from other components, and the components are not limited by these terms.

[0016] Before describing specific embodiments, a basic concept will be described. Figure 1 is a functional block diagram of a basic adaptive filter. An adaptive filter is a filter that self-adapts a transfer function according to an adaptive algorithm. As shown in Figure 1, the adaptive filter includes an adaptive algorithm and an FIR filter, and self-adapts based on an input signal.

[0017] An FIR filter is a filter in which the output signal y(n) is defined by the convolution of the input signal x(n) and a finite-time impulse response. The output signal y(n) is expressed by the following difference equation: y(n)=h 1 x(n)+h 2 x(n-1)+…+h N x(n-(N-1)) Here, x(k) is Z for x(k-1). -1 The signal is delayed by k = 2, 3, ..., N. The coefficient h 1 , h 2 , …, h N are called filter tap coefficients. The number N in this case is called the number of filter taps.

[0018] The filter tap coefficients are determined to optimal values ​​using an adaptive algorithm. Specifically, the adaptive algorithm determines the filter tap coefficients so that the error (also called error signal) e(n) = d(n) - y(n), defined as the difference between the output y(n) from the FIR filter and the target signal d(n), becomes 0. This improves the quality of the output signal. The adaptive algorithms used are broadly divided into CMA (constant envelope algorithm) and LMS (least mean square algorithm). CMA has the advantage of not interfering with the phase-frequency estimator, but the disadvantage of unstable operation when used for mode separation. In contrast, LMS has the disadvantage of interfering with the phase-frequency estimator, but the advantage of stable operation for mode separation.

[0019] Since the number of filter taps N is evaluated by the number of multipliers used in the filter, it is desirable to have as few as possible in terms of cost. However, when compensating for delay-related signal degradation factors (skew), the number of filter taps N needs to correspond to the amount of delay.

[0020] FIG. 2 is a functional block diagram of a butterfly filter as an example of an adaptive filter. This butterfly filter consists of four adaptive filters h xx-rr , h xx-ri , h xx-ir and h xx-ii The complex input signal is separated into a real part (I) and an imaginary part (Q). The real part of the input signal (I) is filtered by the adaptive filter h xx-rr and h xx-ir Similarly, the imaginary part of the input signal (Q) is processed by the adaptive filter h xx-ri and h xx-ii The adaptive filter h xx-rr and h xx-ri The outputs of the adaptive filter h xx-ir and h xx-iiThe outputs of the two are then combined. Finally, these combined outputs are further combined. The butterfly filter can be used to compensate for the IQ phase imbalance. The butterfly filter has the advantage of being able to separate the combined I and Q components, but it requires twice the computational cost of a non-coupled system.

[0021] Table 1 shows the configuration of an adaptive filter required to compensate for IQ imbalance for each type of IQ imbalance (IQ skew, IQ phase imbalance, and IQ gain imbalance). [Table 1] For IQ skew compensation, multiple filter taps (e.g., around eight) are required to compensate for the time delay difference between I and Q, but a two-parallel filter configuration is sufficient (second column of Table 1). For IQ phase imbalance compensation, the number of filter taps is sufficient as one, but a butterfly filter configuration (four parallel) is required (third column of Table 1). For IQ gain imbalance compensation, the number of filter taps is sufficient as one, and a two-parallel filter configuration is sufficient (fourth column of Table 1).

[0022] [First embodiment] 3 is a functional block diagram of the signal processing circuit 1 according to the first embodiment. The signal processing circuit 1 includes a signal processing unit 1x that processes signals in x mode (x polarization) and a signal processing unit 1y that processes signals in y mode (y polarization). The configurations and operations of the signal processing units 1x and 1y have much in common, so the following description focuses on the signal processing unit 1x. A redundant description of the signal processing unit 1y will be omitted.

[0023] 3, the signal processing unit 1x is configured to include four stages of digital filters. That is, the signal processing unit 1x includes a first digital filter 10 corresponding to the first stage, a second digital filter 20 corresponding to the second stage, a third digital filter 30 corresponding to the third stage, and a fourth digital filter 40 corresponding to the fourth stage. The first digital filter 10, the second digital filter 20, the third digital filter 30, and the fourth digital filter 40 are connected in series in this order when viewed from the signal input side.

[0024] The first digital filter 10 includes a first butterfly filter 11 and a second butterfly filter 12. The first butterfly filter 11 is an adaptive filter h xx-rr And, h xx-ri And, h xx-ir And, h xx-ii The second butterfly filter 12 includes an adaptive filter h xy-rr And, h xy-ri And, h xy-ir And, h xy-ii Includes:

[0025] The second digital filter 20 includes a butterfly filter 21. The butterfly filter 21 is an adaptive filter f x-rr And, f x-ri And, f x-ir And, f x-ii Includes:

[0026] The third digital filter 30 includes a filter 31. The filter 31 is an adaptive filter s x Includes.

[0027] The fourth digital filter 40 includes two parallel filters 41. The two parallel filters 41 include an adaptive filter t x-r And, t x-i Includes.

[0028] Filter h xx-rr , h xx-ri , h xx-ir , h xx-ii , h xy-rr , hxy-ri , h xy-ir , h xy-ii , f x-rr , f x-ri , f x-ir , f x-ii , s x , t x-r and t x-i is composed of FIR filters.

[0029] The first digital filter 10 performs mode dispersion compensation, mode coupling compensation, receiver side IQ phase imbalance compensation, receiver side IQ gain imbalance compensation, and receiver side IQ skew compensation. The second digital filter 20 performs transmitter side IQ gain imbalance compensation, transmitter side IQ phase imbalance compensation, and phase estimation. The third digital filter 30 performs frequency estimation. The fourth digital filter 40 performs transmitter side IQ skew compensation.

[0030] (Operation of the first digital filter 10) A complex input signal u in x mode x and a complex input signal u in y mode y are separated into real and imaginary parts. x The real and imaginary parts of the complex input signal u are input to a first butterfly filter 11 of a first digital filter 10. y The real and imaginary parts of are input to a second butterfly filter 12 of a first digital filter 10. The first digital filter 10 is composed of an FIR filter with multiple taps and real coefficients, and compensates for modal dispersion, mode coupling, receiver-side IQ phase imbalance, receiver-side IQ gain imbalance, and receiver-side IQ skew.

[0031] If the filter order is M, the input signal vector u(n) and the filter tap coefficient h are expressed as an (M+1)×1 vector as follows:

number

number

number

number

number

number

[0032] (Operation of the second digital filter 20) The output of the first digital filter 10 is input to the second digital filter 20. The second digital filter 20 performs transmitter-side IQ gain imbalance compensation, transmitter-side IQ phase imbalance compensation, and phase estimation using a butterfly filter, which is an FIR filter with a one-tap real coefficient. The transmitter-side IQ power imbalance and the transmitter-side IQ phase imbalance cannot be compensated for unless the phase noise and frequency offset are compensated for. In this embodiment, the transmitter-side IQ imbalance can be compensated for by simultaneously performing phase / frequency estimation and transmitter-side IQ imbalance compensation. Also, unlike the conventional technology, the transmitter-side IQ gain imbalance compensation and the transmitter-side IQ phase imbalance compensation are performed by the second digital filter 20, and the transmitter-side IQ skew compensation is performed by the fourth digital filter 40, thereby reducing the amount of calculation.

[0033] The update equation for the tap coefficients of the second digital filter 20 is shown below. f is given by:

number

number

number

[0034] (Operation of the third digital filter 30) The output of the second digital filter 20 is input to the third digital filter 30. The third digital filter 30 is composed of an FIR filter with one tap complex coefficient, and estimates the frequency and removes its offset. The output of the second digital filter 20 is input to the third digital filter 30. The third digital filter 30 and the third digital filter 30 are phase frequency estimators. These operate in cooperation with the first digital filter 10 to suppress the instability of the LMS algorithm.

[0035] The update equation for the tap coefficients of the third digital filter 30 is shown below. s is given by:

number

number

number

[0036] (Operation of the fourth digital filter 40) The output of the third digital filter 30 is input to the fourth digital filter 40. The fourth digital filter 40 is composed of an FIR filter with multiple tap real coefficients, and compensates for the IQ skew on the transmitter side. Since the frequency offset has already been compensated for at this point, the IQ skew on the transmitter side can be compensated for.

[0037] The update equation for the tap coefficients of the fourth digital filter 40 is shown below. tx (n) is given by:

number

number

number

[0038] The signal processing unit 1x involved in the signal processing in the x mode has been described above. Regarding the signal processing unit 1y involved in the signal processing in the y mode, the symbol x in the above description may be replaced with y.

[0039] (Evaluation of computational cost) Table 2 shows the results of comparing the signal processing circuit of this embodiment with a conventional signal processing circuit with respect to the number of filter taps. m is the tap length of the mode separation filter, N s is the tap length of the IQ skew compensation filter, and M is the number of modes. [Table 2] As shown in Table 2, this embodiment has succeeded in reducing the number of filter taps compared to conventional signal processing circuits. Furthermore, since this embodiment can use a stable LMS algorithm, it can be introduced into a multi-mode system.

[0040] As described above, according to this embodiment, it is possible to realize stable mode demultiplexing even under the influence of phase fluctuations and frequency offsets while compensating for IQ imbalance in both the transmitter and the receiver with a minimum required amount of calculations.

[0041] [Second embodiment]

[0042] FIG. 4 is a functional block diagram of a digital coherent receiver 2 according to a second embodiment. The digital coherent receiver 2 includes a coherent receiver 201, an AD converter 202, a signal processing circuit 1, and a local light source 203. The coherent receiver 201, the AD converter 202, and the local light source 203 can be realized using existing technology. The signal processing circuit 1 is the signal processing circuit 1 shown in FIG. 3. The coherent receiver 201 coherently detects an optical signal by utilizing interference with local light from the local light source 203. The AD converter 202 converts the coherently detected analog signal into a digital signal and inputs it to the signal processing circuit 1. The configuration and operation of the signal processing circuit 1 are as described above, and therefore detailed description will be omitted.

[0043] According to this embodiment, it is possible to realize a digital coherent receiver capable of signal processing with a minimum necessary amount of calculation.

[0044] [Third embodiment] Fig. 5 is a functional block diagram of a digital coherent communication system 3 according to a third embodiment. The digital coherent communication system 3 includes a transmitter 4 and a digital coherent receiver 2. The transmitter 4 can be realized using existing technology. The digital coherent receiver 2 is the digital coherent receiver shown in Fig. 4. Signal light from the transmitter 4 is received by the digital coherent receiver 2. The configuration and operation of the digital coherent receiver are as described above, and therefore detailed description will be omitted.

[0045] According to this embodiment, a low-cost, high-performance digital coherent communication system can be realized.

[0046] A signal processing circuit according to an embodiment of the present disclosure is a digital coherent receiver including a signal processing circuit, a coherent receiver, an AD converter, and a local light source, and the signal processing circuit includes a first digital filter including a plurality of butterfly filters, a second digital filter including one or more butterfly filters, a third digital filter, and a fourth digital filter including one or more two parallel filters. The first digital filter, the second digital filter, the third digital filter, and the fourth digital filter are connected in series in this order when viewed from the input side of an optical signal to the digital coherent receiver.

[0047] According to this embodiment, it is possible to realize stable mode demultiplexing even under the influence of phase fluctuations and frequency offsets while compensating for IQ imbalance in both the transmitter and the receiver with a minimum necessary amount of calculation.

[0048] A digital coherent receiver according to an embodiment of the present disclosure includes a signal processing circuit, a coherent receiver, an AD converter, and a local light source, and the signal processing circuit includes a first digital filter having a plurality of butterfly filters, a second digital filter having one or more butterfly filters, a third digital filter, and a fourth digital filter having one or more two parallel filters. The first digital filter, the second digital filter, the third digital filter, and the fourth digital filter are connected in series in this order when viewed from the input side of an optical signal to the digital coherent receiver.

[0049] According to this embodiment, it is possible to realize a digital coherent receiver capable of signal processing with a minimum necessary amount of calculation.

[0050] A digital coherent communication system according to an embodiment of the present disclosure includes a transmitter and a digital coherent receiver, the digital coherent receiver including a signal processing circuit, a coherent receiver, an AD converter, and a local light source, the signal processing circuit including a first digital filter including a plurality of butterfly filters, a second digital filter including one or more butterfly filters, a third digital filter, and a fourth digital filter including one or more two parallel filters. The first digital filter, the second digital filter, the third digital filter, and the fourth digital filter are connected in series in this order when viewed from the input side of an optical signal to the digital coherent receiver.

[0051] According to this embodiment, a low-cost, high-performance digital coherent communication system can be realized.

[0052] The present invention has been described above based on the embodiments. These embodiments are merely illustrative, and it will be understood by those skilled in the art that various modifications are possible in the combination of each component and each treatment process, and that such modifications are also within the scope of the present invention.

[0053] The signal processing circuit 1 in Fig. 1 processes polarized signals in two modes, x mode and y mode. However, the present invention is not limited to this, and the signal processing circuit of the embodiment may process signals in higher modes. According to this modification, multiplexed signals in multiple modes can be processed. [Explanation of symbols]

[0054] 1··signal processing circuit, 1x··signal processing section, 1y··signal processing section, 10··first digital filter, 20··second digital filter, 30··third digital filter, 40··fourth digital filter, 11··first butterfly filter, 12··second butterfly filter, 21··butterfly filter, 31··filter, 41··two parallel filters.

Claims

1. A signal processing circuit for use in a digital coherent receiver, comprising: a first digital filter comprising a plurality of butterfly filters; a second digital filter comprising one or more butterfly filters; a third digital filter; and a fourth digital filter comprising one or more two parallel filters; the first digital filter, the second digital filter, the third digital filter, and the fourth digital filter are connected in series in this order when viewed from an input side of an optical signal to the digital coherent receiver; the first digital filter performs mode dispersion compensation, mode coupling compensation, receiver-side IQ gain imbalance compensation, receiver-side IQ phase imbalance compensation, and receiver-side IQ skew compensation; the second digital filter performs transmitter-side IQ gain imbalance compensation, transmitter-side IQ phase imbalance compensation and phase estimation; The third digital filter performs frequency estimation; The signal processing circuit according to claim 1, wherein the fourth digital filter performs IQ skew compensation on a transmitter side.

2. 2. The signal processing circuit according to claim 1, wherein the first digital filter, the second digital filter, the third digital filter and the fourth digital filter are constituted by FIR filters.

3. the first digital filter is an FIR filter having real coefficients of a plurality of taps; the second digital filter is composed of a one-tap FIR filter having real coefficients; the third digital filter is composed of an FIR filter having one tap complex coefficient; 3. The signal processing circuit according to claim 2, wherein the fourth digital filter is composed of an FIR filter having multiple taps and real coefficients.

4. 4. The signal processing circuit according to claim 1, wherein filter tap coefficients of the first digital filter, the second digital filter, the third digital filter and the fourth digital filter are determined using an LMS algorithm.

5. A digital coherent receiver including a signal processing circuit, a coherent receiver, an AD converter, and a local light source, The signal processing circuit includes: a first digital filter comprising a plurality of butterfly filters; a second digital filter comprising one or more butterfly filters; a third digital filter; and a fourth digital filter comprising one or more two parallel filters; the first digital filter, the second digital filter, the third digital filter, and the fourth digital filter are connected in series in this order when viewed from an input side of an optical signal to the digital coherent receiver; the first digital filter performs mode dispersion compensation, mode coupling compensation, receiver-side IQ gain imbalance compensation, receiver-side IQ phase imbalance compensation, and receiver-side IQ skew compensation; the second digital filter performs transmitter-side IQ gain imbalance compensation, transmitter-side IQ phase imbalance compensation and phase estimation; The third digital filter performs frequency estimation; The digital coherent receiver according to claim 1, wherein the fourth digital filter performs IQ skew compensation on a transmitter side.

6. A digital coherent communication system comprising a transmitter and a digital coherent receiver, The digital coherent receiver includes a signal processing circuit, a coherent receiver, an AD converter, and a local light source, The signal processing circuit includes: a first digital filter comprising a plurality of butterfly filters; a second digital filter comprising one or more butterfly filters; a third digital filter; and a fourth digital filter comprising one or more two parallel filters; the first digital filter, the second digital filter, the third digital filter, and the fourth digital filter are connected in series in this order when viewed from an input side of an optical signal to the digital coherent receiver; the first digital filter performs mode dispersion compensation, mode coupling compensation, receiver-side IQ gain imbalance compensation, receiver-side IQ phase imbalance compensation, and receiver-side IQ skew compensation; the second digital filter performs transmitter-side IQ gain imbalance compensation, transmitter-side IQ phase imbalance compensation and phase estimation; The third digital filter performs frequency estimation; 2. A digital coherent communication system, comprising: a fourth digital filter for performing IQ skew compensation on a transmitter side;

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