Integrated Circuits and Memory Devices

Abstract

An etch stop is disclosed for integrated circuit applications having a set of contacts of varying heights, with a large height difference between the lowest and highest contacts. In one example, an etch stop is provided on a 3D NAND memory staircase structure. The structure is then planarized with an insulator material that can be etched selectively to the etch stop. Contact holes are etched that land on corresponding word lines of the staircase. Due to the nature of the staircase, the depth of the holes varies depending on which step of the staircase they land on. The etch stop below the shallowest holes remains intact, while the deepest holes are completely etched. Once all holes land on the etch stop, a further etch selective to the insulator material is performed to perforate the etch stop and expose the underlying word lines. Contacts are deposited into the holes.

Description

[Background technology]

[0001] In two-dimensional (2D) NAND memory technology, memory cells are arranged in a side-by-side layout, or array, on a single die. Storage capacity is determined by the number of cells in the array. In an effort to follow Moore's Law, manufacturers have been shrinking the size of memory cells to fit more cells on a given die. Eventually, a technological limit will be reached as to how much a cell can shrink. To this end, three-dimensional (3D) NAND memory technology is intended to address some of the challenges encountered in scaling 2D NAND memory technology. 3D NAND memory structures include multiple layers of memory cells stacked vertically, rather than a single layer of memory cells on a die. Thus, 3D NAND memory technology can be used to increase capacity in a given footprint without necessarily shrinking the memory cells. However, there are several non-trivial issues associated with 3D NAND memory technology, especially as the scaling of dimensions continues. [Brief description of the drawings]

[0002] [Figure 1] 1 illustrates an example 3D integrated circuit NAND memory staircase structure showing problematic penetration of a wordline by a corresponding contact (or via) that is relatively shorter than the highest contact that lands on a lower wordline in the staircase structure.

[0003] [Diagram 2] 1 illustrates an exemplary process for forming an etch stop for a 3D integrated circuit stair structure according to an embodiment of the present disclosure.

[0004] [Figure 3A] 3A-3C illustrate cross-sectional views of an exemplary 3D integrated circuit staircase structure formed at different times during the process of FIG. 2 in accordance with an embodiment of the present disclosure. [Figure 3B]3A-3C illustrate cross-sectional views of an exemplary 3D integrated circuit staircase structure formed at different times during the process of FIG. 2 in accordance with an embodiment of the present disclosure. [Figure 3C] 3A-3C illustrate cross-sectional views of an exemplary 3D integrated circuit staircase structure formed at different times during the process of FIG. 2 in accordance with an embodiment of the present disclosure. [Figure 3D] 3A-3C illustrate cross-sectional views of an exemplary 3D integrated circuit staircase structure formed at different times during the process of FIG. 2 in accordance with an embodiment of the present disclosure. [Figure 3E] 3A-3C illustrate cross-sectional views of an exemplary 3D integrated circuit staircase structure formed at different times during the process of FIG. 2 in accordance with an embodiment of the present disclosure. [Figure 3F] 3A-3C illustrate cross-sectional views of an exemplary 3D integrated circuit staircase structure formed at different times during the process of FIG. 2 in accordance with an embodiment of the present disclosure. [Figure 3G] 3A-3C illustrate cross-sectional views of an exemplary 3D integrated circuit staircase structure formed at different times during the process of FIG. 2 in accordance with an embodiment of the present disclosure. [Figure 3H] 3A-3C illustrate cross-sectional views of an exemplary 3D integrated circuit staircase structure formed at different times during the process of FIG. 2 in accordance with an embodiment of the present disclosure. [Figure 3I] 3A-3C illustrate cross-sectional views of an exemplary 3D integrated circuit staircase structure formed at different times during the process of FIG. 2 in accordance with an embodiment of the present disclosure.

[0005] [Figure 3J] 1 illustrates an exemplary configuration of an etch stop for a 3D integrated circuit stair structure according to an embodiment of the present disclosure. [Figure 3K] 1 illustrates an exemplary configuration of an etch stop for a 3D integrated circuit stair structure according to an embodiment of the present disclosure. [Figure 3L] 1 illustrates an exemplary configuration of an etch stop for a 3D integrated circuit stair structure according to an embodiment of the present disclosure. [Figure 3M] 1 illustrates an exemplary configuration of an etch stop for a 3D integrated circuit stair structure according to an embodiment of the present disclosure. [Figure 3N] 1 illustrates an exemplary configuration of an etch stop for a 3D integrated circuit stair structure according to an embodiment of the present disclosure.

[0006] [Figure 4] 1 is an exemplary computing system implemented with one or more of the 3D integrated circuit staircase structures disclosed herein, in accordance with embodiments of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] A non-conductive etch stop is disclosed for integrated circuit applications having a set of contacts or vias of various heights. The height difference between the lowest and highest contacts in the set is relatively large. The etch stop is particularly suitable for 3D NAND memory applications where contacts of various heights are formed on corresponding conductive layers (e.g., word lines) of a staircase structure, but it is clear that it may also be beneficial for other applications with a variety of contact heights across a given structure. In an embodiment, a non-conductive etch stop is provided on a 3D NAND memory staircase structure. After the etch stop is formed, the remaining open space of the staircase structure is filled with an insulating material (e.g., oxide) that can be selectively etched with respect to the etch stop or is otherwise planarized. Contact holes are then patterned and etched to land on corresponding conductive layers of the staircase structure. Due to the nature of the staircase structure, the height (depth) of the holes will be different depending on which step of the staircase structure they land on. To this end, according to an embodiment, the etch stop under the shallowest hole remains intact, while the deepest hole is etched to expose the etch stop underneath. Once all of the contact holes have landed on the underlying etch stop, a further etch selective to the insulator material (i.e., an etch that removes the etch stop but does not remove the insulator material) may be performed to perforate the etch stop and expose the underlying conductive layer. Conductive contacts may then be formed in the contact holes. In one such embodiment, a first contact on an upper step of the staircase structure has a first height and a second contact on a lower step of the staircase structure has a second height that is five or more times greater than the first height. As will be appreciated by consideration of the present disclosure, the etch stop prevents non-uniform etching of the conductive layer below the etch stop. In some such embodiments, the etch stop is a single layer composed of a material that has high etch selectivity to a given insulator material.In other embodiments, the etch stop is a bi-layer or multi-layer structure including a first and a second layer of a material with high etch selectivity to a given insulator material. In some exemplary embodiments, the etch stop includes at least one layer of a high-k dielectric (e.g., hafnium oxide or other high-k oxide). As will be appreciated by consideration of the present disclosure, the slow etch rate of the etch stop effectively protects the conductive layers (e.g., word lines) higher in the staircase structure from being etched or otherwise penetrated during the contact hole etching process to reach the conductive layers lower in the staircase structure. It is further noted that the non-conductive nature of the etch stop eliminates the risk of any shorts between word line layers. As will be appreciated, the term "contact" or "contact structure" as used herein generally refers to a hole filled with a conductive material (e.g., metal) and may be used interchangeably with "via" or "via structure." General Overview

[0008] As described above, there are several not inconsiderable unsolved problems associated with the continued downscaling of 3D NAND memory technology, particularly with respect to the need to form contacts to wordlines in 3D staircase structures. Briefly, the increase in the number of staircase levels results in more challenging etch applications, particularly with respect to staircase structure designs in which the higher contact holes on the lower steps of the staircase structure have height-to-width ratios of 20:1 or more. One minor problem that arises in such high aspect ratio etch applications is that the contact hole etch process for the shallower holes etches into (or through) the wordlines that are higher in the staircase structure because the etch process continues through the dielectric fill material to form deeper holes that land on the wordlines that are lower in the staircase structure. An etch stop can be used to help mitigate this problem, but the etch stop must account for the variability in the depth of the contact holes in the staircase structure, or the etch stop will fail.

[0009] For example, FIG. 1 illustrates an exemplary 3D integrated circuit NAND memory staircase structure that exhibits non-uniform contact hole etching across the staircase structure, resulting in variability in wordline thickness and potential defects. As can be seen, the staircase structure includes multiple alternating layers of oxide and wordline material over a substrate, with each step of the staircase structure including an oxide layer and a wordline layer. The lowest step in the staircase is more than five times lower than the upper steps of the staircase structure. An etch stop is provided on the staircase structure, and an oxide fill material is provided on the etch stop to planarize the staircase structure. As can be further seen, a series of contact holes are patterned and etched for wordline contacts. However, due to the ineffectiveness of the etch stop and the significant difference in hole depth between the shallowest hole (leftmost hole) and the deepest hole (rightmost hole), the etch may perforate the target wordline and etch into the wordline material underneath the target wordline (e.g., as can be seen in the leftmost hole in FIG. 1), ultimately resulting in a short between the two wordlines. It should be noted that even if such drilling did not occur, etching of the shallower contact holes would still penetrate the etch stop and etch further into the underlying wordlines, thereby causing uneven wordline recessing across a series of connected wordlines (as can be seen, for example, in the two middle holes in FIG. 1). The end result is a smaller, unexpected state of yield fallout in the event of a short, or a latent defect in which an overly thin wordline due to uneven wordline recessing eventually matures into a completely open wordline.

[0010] Thus, according to an embodiment of the present disclosure, a non-conductive etch stop is provided. The etch stop is particularly suitable for integrated circuit applications where the depths of contact holes etched in the same etch process are varied. For example, the etch stop may be provided on a 3D NAND memory staircase structure such as that shown in FIG. 1. The etch stop effectively protects the word line material in the 3D staircase structure during etch application by providing a suitable differential etch rate to the surrounding insulator fill material on the etch stop. Many variations and embodiments are understood in view of the present disclosure.

[0011] In some exemplary embodiments, the etch stop is a single layer structure that includes a high-k dielectric material. Exemplary high-k dielectric materials include, for example, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate, to name a few. In some specific such examples, the etch stop is aluminum oxide, hafnium oxide, or yttrium oxide. To improve etch selectivity, the high-k dielectric material may be annealed.

[0012] In other embodiments, the etch stop structure may include multiple layers. For example, in some such exemplary cases, the etch stop includes a bilayer structure composed of two compositionally distinct layers. In one such exemplary embodiment, the first layer on the step structure is aluminum oxide (Al x O y ), hafnium oxide (HfO x ), zirconium oxide (ZO x ), yttrium oxide (Y x O y), or other high-k materials, and the second layer (on the first layer) comprises a high-k dielectric material such as silicon nitride (Si x N y ), silicon oxynitride (SiO x N y ), or silicon oxide (SiO x ). Alternatively, in another embodiment, a first layer on the staircase comprises an oxide, nitride, or oxynitride, and a second layer on the first layer comprises a high-k dielectric material. In any such case, the second layer allows for a first delay period before reaching the first layer, and the first layer allows for a second delay period. These delays can be factored into the overall timing of the etching process to ensure that the high-k material is not completely consumed at any point before the drilling process.

[0013] It should be further noted that in any such embodiment, whether the etch stop structure is single layer or multilayer, one or more components of the etch stop may be graded. For example, in one exemplary case, the etch stop includes a single continuous layer that starts with a first outer phase or portion (e.g., silicon oxide) that transitions to a second inner portion (e.g., hafnium silicon oxide). In still other embodiments, the etch stop may include an inner layer that includes a stepped high-k dielectric material and a second separate outer layer having a first outer portion of silicon oxide that gradually transitions to a second inner portion of silicon oxynitride on the high-k dielectric material. In such a case, the etchant may first encounter the outer silicon oxide phase and consume that material in a relatively fast manner (especially if the fill insulator is also silicon oxide), but when it encounters the nitrogen component of the inner silicon oxynitride phase, the etch rate is slow. When it encounters the high-k electrical material layer, the etch rate is even slower. It should be further noted that the abruptness of the transition from one material or layer to the next may also vary. For example, in some cases, the grading of material concentrations is done in relatively coarse steps and the transition from one material to the next is relatively abrupt, so that the transition remains distinct and detectable as a separate layer of etch stop, however, in other cases, the grading may be performed in relatively much smaller increments and the transition from one material to the next is smooth or otherwise non-abrupt, so that the etch stop more closely resembles a single continuous layer having multiple phases or portions.

[0014] According to some embodiments, the thickness of the etch stop structure may vary from one embodiment to the next depending on factors such as the etch chemistry used, the etch selectivity between the insulator and etch stop materials used, as well as the depth difference between the shallowest and deepest holes formed during a given contact hole etch process. In some such exemplary cases, the total etch stop thickness ranges from 15 nm to 150 nm (e.g., 50 to 125 nm, such as 70 nm, or 80 nm, or 90 nm, or 100 nm, or 110 nm), but may be thinner or thicker depending on the factors described above. For example, in other embodiments, the etch stop thickness ranges from 2 nm to 15 nm (e.g., 5 nm, or 10 nm), and in still other embodiments, the etch stop ranges from 150 to 200 nm (e.g., 175 nm). As further described above, the etch stop structures may have different etch rates for each phase or layer of the overall structure, and the thickness of each such phase and / or layer may be set to achieve a globally timed etch process designed to etch all of the contact holes in a given staircase structure without prematurely perforating the etch stop.

[0015] In any such case, according to an embodiment, once an etch stop is deposited on the 3D staircase structure (or some other multi-depth structure), an insulator material is deposited on the etch stop to planarize the structure. The insulator fill material needs to be selectively etched with respect to the etch stop, and in some embodiments is silicon oxide or porous silicon oxide or polymer, to name a few. So, for example, for a given etch chemistry, the etch stop, including high-k dielectric materials and optionally materials such as nitrides and oxynitrides, etches relatively much slower than the oxide fill material. Holes for contacts can then be patterned and etched into the insulator fill up to the etch stop just above the respective word lines. During the etch of the insulator fill, the etch rate is generally uniform until the etch stop is encountered. From that point on in the corresponding contact hole, the etch rate of the exposed etch stop becomes much slower (e.g., 10 times slower or more) than the etch rate of the insulator fill in the deeper contact hole as the etching process continues to run. Here, the slow etch rate of the etch stop ensures that the wordline material or other material underneath the etch stop is protected from being unintentionally thinned or otherwise etched.

[0016] In certain embodiments, for example, for a given etch chemistry, the etch selectivity of the insulator material relative to the etch stop material is, on average, greater than 15:1, such that the etch stop (or at least a portion of the etch stop) etches 15 times slower than the insulator fill material. However, as will be appreciated, it should be noted that the etch selectivity may vary from one embodiment to the next depending on factors such as the materials selected for the etch stop and the insulator fill, the depth difference between the shallowest and deepest contact holes etched, and the etch chemistry utilized. In a more general sense, any etch selectivity may be used that allows for the etching of the insulator fill material to form the desired contact holes while consistently and reliably protecting the wordline material beneath the etch stop. Thus, in still other exemplary embodiments, the etch selectivity of the insulator fill material relative to the etch stop material ranges from about 5:1 to about 50:1, such as about 10:1, or about 20:1, or about 30:1, or about 40:1 or more. It should be noted that in the case of a multi-layer or multi-phase etch stop, the etch stop structure may have multiple etch rates that effectively provide a suitable overall etch rate (one or more etch rates for each of the different layers or phases of the etch stop). The overall overall etch rate may be, for example, an average or median etch rate contributing to all the etch rates that make up a given etch stop structure.

[0017] Thus, according to some embodiments, the differential etch rate of the etch stop on the 3D staircase structure allows etching of contact holes of varying depths while effectively preventing penetration of the etch stop and etching of word lines under shallower contact holes. Furthermore, the differential etch rate of the etch stop effectively eliminates non-uniform word line recesses and word line perforations across a series of word lines in some cases, thereby providing increased yields due to effective elimination of over-etch shorts. The differential etch rate also increases the number of contact holes of varying depths that can be etched using a single hard mask. This achieves improvements and efficiencies in the 3D NAND memory staircase contact process. Many other such advantages, as well as other configurations and embodiments, will be apparent.

[0018] Use of the techniques and structures provided herein may be detectable using tools such as electron microscopy, including scanning / transmission electron microscopy (SEM / TEM), scanning transmission electron microscopy (STEM), nanobeam electron diffraction (NBD or NBED), and reflection electron microscopy (REM); compositional mapping; X-ray crystallography or diffraction (XRD); energy dispersive X-ray spectroscopy (EDX); secondary ion mass spectrometry (SIMS); time-of-flight SIMS (ToF-SIMS); atom probe imaging or tomography; local electrode atom probe (LEAP) techniques; 3D tomography; or high-resolution physical or chemical analysis, to name a few suitable exemplary analytical tools. In particular, in some exemplary embodiments, such tools may reveal (e.g., by TEM cross-section) the presence of an etch stop structure comprising high-k dielectric material on a 3D NAND memory staircase structure, as well as word lines of uniform thickness under each contact (or via).

[0019] As used herein, compositionally distinct materials may refer to two materials that have different chemical compositions. This compositional difference may be due, for example, to elements that are present in one material but not in the other (e.g., SiGe is compositionally distinct from silicon), or one material may have all the same elements as a second material, but at least one of those elements is intentionally provided in one material at a different concentration than in the other (e.g., SiGe with 70 atomic percent germanium is compositionally distinct from SiGe with 25 atomic percent germanium). In addition to such chemical compositional variations, materials may also have distinct dopants (e.g., boron, silicon, gallium, and magnesium), or different concentrations of the same dopants. In still other embodiments, compositionally distinct may further refer to two materials that have different crystal orientations. For example, (110) silicon is distinct from (100) silicon. Creation of stacks of different orientations may be accomplished, for example, using blanket wafer layer transfer.

[0020] It should be noted that designations such as top or bottom, or uppermost or lowermost, or upper or lower, are not necessarily intended to suggest limitations to the orientation of the embodiments described herein, rather, such terms are merely used in a relative sense to consistently describe structures as they exist in any one particular orientation as shown herein.

[0021] The term high-k as used herein refers to a material having a dielectric constant greater than silicon dioxide (e.g., k value greater than about 3.9). Examples of high-k dielectric materials include, for example, hafnium oxide, hafnium silicon oxide, zirconium oxide, zirconium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. Any other high-k material may also be used. Furthermore, it should be noted that the stoichiometry of such high-k dielectric compounds may vary from one embodiment to the next, and such compounds expressed without stoichiometric coefficients or values ​​are intended to represent all forms of high-k dielectric compounds.

[0022] The term layer as used herein refers to a portion of a material that includes a region having a thickness. A monolayer is a layer consisting of a single layer of atoms of a given material. A layer may extend across an underlying or overlying structure, and may have an extent that is less than the extent of the underlying or overlying structure. A layer may extend horizontally, vertically, and / or along a tapered or non-linear surface. A layer may be conformal to a given surface (flat or curved) with a relatively uniform thickness across the layer, but need not be conformal or otherwise uniform. A monolayer may have graded components or multiple phases, and thus the layer is not homogeneous. methodology

[0023] FIG. 2 illustrates an exemplary process 200 for forming an etch stop for a 3D integrated circuit stair structure according to an embodiment of the present disclosure. FIG. 3A-3I illustrate cross-sectional views of an exemplary 3D integrated circuit stair structure formed when performing the process 200 of FIG. 2 according to an embodiment of the present disclosure. It is further understood that the operations described are provided only as examples, and other embodiments may include fewer separate operations (such as the exemplary case where 208 and 210 are performed in a single continuous deposition process where process knobs are adjusted to provide the desired material), and other embodiments may include operations not shown (such as planarization / polishing and cleaning operations). Many variations are apparent in light of the present disclosure. Explanation is facilitated by referring to FIG. 2 and FIG. 3A-3I simultaneously.

[0024] It should be noted that deposition of the materials variously described herein can be accomplished using any suitable deposition technique, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and / or molecular beam epitaxy (MBE). It should also be noted that etching of the materials variously described herein can be accomplished by any suitable etching technique, such as wet and / or dry etching processes that can be non-selective (e.g., etching all exposed materials at the same or similar rate) or selective (e.g., etching different exposed materials at different rates), isotropic (e.g., uniform etch rate in all directions) or anisotropic (e.g., orientation-dependent etch rate). It should further be noted that other processes, such as patterning or lithography, planarization or polishing (e.g., chemical mechanical planarization), doping (e.g., ion implantation, in situ doping), cleaning, annealing, etc., can be used to form the integrated circuit structures described herein, as will become apparent in view of the present disclosure.

[0025] Referring to FIG. 2, the process 200 begins at 202 with providing a substrate. FIG. 3A shows an exemplary substrate 302 according to an embodiment. Any number of suitable substrates may be used herein, including bulk substrates, semiconductor-on-insulator substrates (XOI, where X is a semiconductor material such as silicon, germanium, SiGe, gallium arsenide, or indium gallium arsenide), and multi-layer substrate structures. In a more general sense, any substrate on which a 3D NAND memory can be formed may be used. In one particular embodiment, the substrate 302 is a bulk silicon substrate.

[0026] The process 200 continues at 204 with depositing an alternating stack of insulator (e.g., oxide) and wordline material on the substrate to form a standard or proprietary stack. While any number of insulator and wordline materials may be used, one embodiment includes silicon oxide for the insulator layer and polysilicon for the wordline layer. FIG. 3B illustrates an exemplary alternating oxide and wordline stack comprised of an oxide layer 304 and a wordline layer 306, according to an embodiment. The oxide layer 304 and the wordline layer 306 may be deposited using any suitable deposition technique, such as ALD, CVD, PVD, or any combination of suitable deposition techniques. In one particular embodiment, each of the oxide layer 304 and the wordline layer 306 are deposited using CVD. It should be noted that while the structure illustrated in FIG. 3B includes an oxide deposited first, followed by a wordline material, an oxide, a wordline material, an oxide, etc., other embodiments may have a different stack, where the wordline material is deposited first, followed by an insulator material, a wordline material, etc.

[0027] Each oxide layer 304 in the stack may have the same thickness or may have different thicknesses. For example, in some embodiments, each oxide layer 304 has a thickness in the range of about 10 nm to about 100 nm. In one particular such embodiment, each oxide layer 304 has a thickness of about 20 nm to about 30 nm (e.g., 25 nm). Similarly, each wordline layer 306 in the stack may have the same thickness or may have different thicknesses. For example, in some embodiments, each wordline layer 306 has a thickness in the range of about 10 nm to about 100 nm. In one particular such embodiment, each wordline layer 306 has a thickness of about 30 nm to about 40 nm (e.g., 35 nm). In a more general sense, it will be understood that the thicknesses of the insulator layers 304 and the wordline layers 306 may vary widely.

[0028] The stack may include any number of alternating layers of oxide 304 and wordline 306 materials. For example, in some specific illustrative embodiments, the stack may include anywhere from 20 to 500 layers (counting both 304 and 306). In a more general sense, the number of alternating insulator and conductor layers or structures in the stack may vary widely depending on the particulars of the memory being formed, and it will be understood that the techniques provided herein may be used to advantage in any such configuration.

[0029] The process 200 continues at 206 with etching the stack to form a staircase structure on the substrate. FIG. 3C illustrates an exemplary staircase structure including alternating layers of oxide layers 304 and wordline layers 306 on a substrate 302 according to one such embodiment. The staircase structure generally includes two or more steps, with at least some of the risers of the steps including an insulator layer or structure 304 and a wordline layer or structure 306. It should be noted that in the illustrated exemplary embodiment, the top layer of each step in the staircase structure is a wordline 306, but in other embodiments, the top layer of each step may be an insulator 304. Thus, in some exemplary embodiments having 48-512 layers in the stack, the resulting staircase structure includes 24-256 steps (e.g., 32 steps, 64 steps, 96 steps, 128 steps). In a more general sense, the staircase may be comprised of any number of steps depending on the details of a given memory application.

[0030] The staircase structure may be formed with a standard staircase etch process or any other suitable etching process. For example, in one embodiment, a hard mask is provided on the stack of alternating layers of oxide layers 304 and wordline layers 306. The hard mask is then photo-patterned and etched to a single step depth to expose a riser including the top wordline layer 306 and oxide layer 304. The hard mask is then etched laterally to the tread width of the next step (sometimes called a pullback etch) and the next pair of wordlines 306 and oxide 304 is etched to a single step depth to form the riser of the next step. This process is repeated for each step of the staircase until the staircase is formed. The exemplary staircase structure of FIG. 3C shows four or five steps, but any number of steps may be provided as previously described.

[0031] The process 200 continues at 208 with depositing an etch stop layer over the staircase structure. FIG. 3D illustrates an exemplary etch stop 308 formed over the staircase structure, according to an embodiment. It should be noted that the etch stop 308 can have a number of configurations, as described with reference to FIGS. 3J-3N. In some embodiments, the etch stop is formed by conformally depositing a non-conductive high-k dielectric material that has high etch selectivity to a fill insulator used to fill or otherwise planarize the staircase structure. In some such embodiments, the high-k dielectric material of the etch stop is annealed to further improve etch selectivity. The etch stop 308 can be deposited using any suitable conformal deposition technique, such as ALD, CVD, PVD, or diffusion. In one particular embodiment, the etch stop 308 is deposited using PVD.

[0032] In some exemplary embodiments, the etch stop 308 is a single layer structure including a high-k dielectric material. Exemplary high-k dielectric materials include, for example, those previously provided herein. One such embodiment is shown in FIG. 3J, which shows a single layer having a single continuous phase. In some specific such examples, the single layer is aluminum oxide, hafnium oxide, zirconium oxide, or yttrium oxide. Another exemplary single layer embodiment is shown in FIG. 3K, which shows an etch stop including a single continuous layer starting with a first phase A that transitions to a second phase B. The transition from phase A to phase B is relatively gradual and is depicted using a dotted line. In one such exemplary case, the single continuous layer etch stop 308 includes a first phase A of silicon oxide that transitions to a second phase B of hafnium silicon oxide. In another exemplary such case, the single continuous layer etch stop 308 includes a first phase A of aluminum oxide that transitions to a second phase B of lanthanum aluminum oxide. It should be noted that while one or more phases of a single continuous layer may comprise high-k dielectric material, they need not all comprise a high-k dielectric.

[0033] In other embodiments, the etch stop 308 structure may include multiple layers. For example, in one exemplary case, the etch stop 308 includes a bilayer structure composed of two compositionally distinct layers. One such embodiment is shown in FIG. 3L. In one such exemplary case, layer 1 is a silicon nitride (Si x N y ), silicon oxynitride (SiO x N y ), or silicon oxide (SiO x ), and layer 2 (on the step) is aluminum oxide (Al x O y ), hafnium oxide (HfO x ), zirconium oxide (ZO x) or other high-k materials. It should be noted that, as previously described, layer 1 effectively allows for a first delay period before reaching the high-k material of layer 2, and layer 2 effectively allows for a second, longer delay period. As with the delays associated with a single successive layer, these delays can be factored into the overall timing of the etching process to ensure that the high-k material of layer 2 is not completely consumed at any point during the overall etching process. It should be noted that the layers including the high-k material need not be on a staircase. Specifically, in an alternative embodiment, layer 1 can include a high-k dielectric material, with the layers including an oxide, nitride, or oxynitride, as previously described.

[0034] In yet other embodiments, the etch stop 308 may include an inner layer comprising a stepped high-k dielectric material and a second separate outer layer having a first outer phase that gradually transitions to a second inner phase on layer 2. One such embodiment is shown in FIG. 3M. In one particular such exemplary case, layer 2 comprises a stepped high-k dielectric material (e.g., Al x O y ), where layer 1 has a first phase A of silicon oxide that gradually transitions to a second phase B of silicon oxynitride overlying the high-k dielectric material. As previously explained, in such cases the etchant may first encounter the outer silicon oxide phase A and consume that material in a relatively fast manner (especially if the fill insulator is also silicon oxide), but then the etch rate is slower when it encounters the nitrogen component of the inner silicon oxynitride phase B. When the high-k electrical material layer 2 is encountered, the etch rate is even slower.

[0035] 3N illustrates another exemplary multi-layer, multi-phase embodiment in which each separate layer of the bi-layered etch stop 308 includes a different phase. In one particular such exemplary case, layer 2 has a first phase A of aluminum oxide that gradually transitions to a second phase B of lanthanum aluminum oxide or hafnium oxide, and layer 1 has a first phase A of silicon oxide that gradually transitions to a second phase B of silicon oxynitride. As previously described, the overall contact etch sequence can include any number of timed etch sub-processes, each associated with a particular etch rate.

[0036] According to some embodiments, the thickness of the etch stop structure 308 may vary from one embodiment to the next depending on factors such as the etch chemistry used, the etch selectivity between the insulator and etch stop material used, the height difference between the tread of the top step and the tread of the bottom step in the staircase structure, etc. It should be noted that the height difference between the tread of the top step and the tread of the bottom step in the staircase structure effectively defines the major spread in the depth of the contact hole, as will be explained later. The techniques provided herein may be used on any staircase structure, but are particularly useful for structures in which the height difference between the respective contacts (or vias) on the top step and the bottom step is greater than 5 times. As previously discussed, the overall etch stop thickness can vary from one embodiment to the next, but in some cases ranges from 10 nm to 200 nm (e.g., 15 to 150 nm, or 25 to 125 nm, or 35 to 125 nm, or 45 to 125 nm, or 55 to 125 nm, or 65 to 125 nm, or 75 to 125 nm, or 85 to 115 nm, or 90 to 110 nm, or around 100 nm).

[0037] 2, according to an embodiment, the exemplary process 200 continues at 210 with depositing a dielectric fill material. Figure 3E illustrates an exemplary dielectric fill 310 formed over the etch stop 308 to planarize the integrated circuit structure, according to an embodiment. As previously described, the dielectric fill material 310 is selectively etched with respect to the etch stop 308, and in some embodiments, may be SiO x Or porous SiO x or other oxides or porous oxides. Thus, for example, for a given etch chemistry, the etch stop 308, including high-k dielectric materials, and optionally further including materials such as nitrides and oxynitrides, etches relatively much slower (e.g., 15 times slower or more) than the insulator fill material 310, which is comprised of an oxide. The insulator fill 310 may be deposited using any suitable deposition technique, such as ALD, CVD, PVD, or a combination of such techniques. In one particular embodiment, the insulator fill 310 is deposited using PVD. Any excess insulator fill 310 may be removed using, for example, a CMP process that planarizes the structure to a desired height (e.g., 50 nm to 500 nm above the top step of the staircase, or up to the top of the staircase). It should be noted that in some exemplary embodiments, the insulator fill 310 may be, but need not be, of the same composition as the oxide layer 304 in the staircase structure. Since the staircase structure itself provides a relatively high amount of structural integrity, it will be appreciated that the insulator fill 310 may be porous to improve etchability down to the etch stop 308 .

[0038] According to an embodiment, the process 200 continues at 212 with patterning and etching contact holes in the insulator filling 310, with each hole landing on the etch stop 308 of a corresponding step of the staircase. For example, in an embodiment, a hard mask for etching the holes is patterned and etched. FIG. 3F shows an example resulting hard mask 312 in one such embodiment. The hard mask 312 may be provided on the insulator filling 310 using any number of suitable processes. For example, in some embodiments, the hard mask 312 may be provided using standard photolithography that includes depositing one or more hard mask materials (such as, for example, silicon carbide, silicon dioxide, and / or silicon nitride, or other suitable hard mask materials), patterning a resist on the portions of the hard mask 312 that will remain temporarily to protect the areas underlying the insulator filling 310, etching (e.g., using a dry etch or other suitable hard mask removal process) to remove the unmasked (resist-free) portions of the hard mask 312, and then stripping the patterned resist material to leave the patterned hard mask 312. The pattern on the hard mask 312 provides a pattern for the contact holes to be formed. It will be apparent that any number of suitable mask configurations may be used.

[0039] Next, by using the patterned hard mask 312, the insulator fill 310 can be etched vertically to form contact holes. FIG. 3G illustrates exemplary holes 314 etched into the insulator fill 310, according to an embodiment. As can be seen, each of the holes lands on the etch stop 308 but does not penetrate through the etch stop 308. Although only four holes 314 are shown, it will be understood that any number of holes 314 may be provided. To etch the contact holes 314 down to the insulator fill 310, any number of dry and / or wet etching processes that are highly selective to the underlying etch stop 308 may be used. For example, in one particular embodiment, a dry etching process may be used that has an etch selectivity of the high-k dielectric material contained in the etch stop 308 to the insulator fill 310 that is 15:1 or greater. That is, the insulator fill 310 etches 15 times faster or greater than the high-k material of the etch stop 308. It should be noted that the etch stop 308 may be etched somewhat during the contact hole formation process, but is not penetrated by the etching process according to an embodiment. To this end, it should be further noted that the etch stop 308 prevents the formation of non-uniform recesses in the wordline layer 306, and thus further prevents unintentional perforation of the wordline layer 306.

[0040] The process 200 continues at 214 by etching the bottom etch stop of the contact hole 314, exposing the underlying wordline 306. FIG. 3H shows an exemplary resulting embodiment. In this portion of the etching process, the etch is selective to the insulator fill material 310 and the wordline 306 material, and more aggressively removes the etch stop 308 material. Thus, as will be appreciated, the etch utilized will depend on the materials used. In some exemplary embodiments, polysilicon and SiO xA selective wet and / or dry etch that is selective to may be used to remove the etch stop 308 from the bottom of the hole 314 .

[0041] For example, in one particular such embodiment, the etch stop 308 is Al x O y A single layer of polysilicon and SiO x A halide-based dry etch process that is selective to Al is used to selectively remove the etch stop 308 from the bottom of the hole 314. In another exemplary case, the etch stop 308 is a SiO2 ... x O y The outer layer of SiO x In such a case, a halide-based dry etch process that is selective to the insulator fill 310 may be used to remove the high-k outer layer of the etch stop 308, and a second dry etch process that is selective to the insulator fill 310 and polysilicon may be used to remove the SiO 2 of the inner layer of the etch stop 308. x It should be noted that in other such exemplary embodiments, the inner and outer layers of the etch stop 308 may be inverted, thereby reversing the order in which the primary and secondary etchants are applied. It should further be noted that a similar etching scheme may be used for an etch stop 308 having a single layer including a first phase and a second phase (rather than first and second separate layers). As will be further appreciated, specific examples herein include polysilicon wordlines, SiO x Filling material, and Al x O y Many other material systems may be used that include high-k layers / portions but provide the etch selectivity variously described herein.

[0042] In yet another particular embodiment, Al x O yAssuming a single layer or phase etch stop 308 containing Al, a hydrofluoric acid-based (HF-based) wet etch that is selective to polysilicon and dielectric fill 310 can be used to selectively remove etch stop 308. x O y and an outer layer or portion comprising SiO x In the case of a two-layer or two-phase etch stop 308 that includes an inner layer or portion comprising polysilicon, a HF-based wet etch that is selective to the dielectric fill 310 may be used to selectively remove the high-k outer layer or portion of the etch stop 308, and a secondary dry etch process that is selective to polysilicon and the dielectric fill 310 may be used to selectively remove the SiO 2 of the etch stop 308. x It should be noted that, again, the inner and outer layers of the etch stop 308 may be reversed, thereby reversing the order in which the primary and secondary etchants are applied, and that other material systems may be used that provide the etch selectivity variously described herein.

[0043] With further reference to FIG. 2, process 200 continues at 216 with depositing a conductive material into the hole to form a contact on the polysilicon wordline. FIG. 3I shows hole 314 filled with conductive material to form contact (or via) 316, according to an embodiment. The conductive material may be deposited using any suitable deposition technique, such as ALD, CVD, PVD, or a combination of such techniques. As generally shown in FIG. 3I, any excess deposited conductive material may be etched or planarized (e.g., by CMP) to make the top surface of the conductive material at contact 316 flush (or substantially flush) with the top surface of hard mask 312. It should be noted that in other embodiments, hard mask 312 may also be removed during such a CMP process. Exemplary conductive materials include polysilicon, tungsten, aluminum, nickel, silver, and copper, to name a few. It should be noted that in some exemplary embodiments, the contact 316 may include multiple components or layers, such as a barrier layer or liner (e.g., titanium or titanium nitride, or tantalum or tantalum nitride) to prevent migration of the core contact material (e.g., copper, aluminum, tungsten, etc.) into the fill material 310.

[0044] While the techniques provided herein may be used for any staircase structure, they are particularly useful with respect to structures in which the height difference between the contacts (or vias) 316 of the top and bottom steps ranges from 5x to 80x. In some such embodiments, the height difference between the lowest and highest contacts 316 is about 10x or 20x or 30x or 40x or 50x or 60x or 70x or 80x. For example, in one particular such exemplary embodiment, the lowest contact 316 is about 200nm to 300nm high (e.g., about 250nm) and the highest contact 316 is about 9 microns to 10 microns high (e.g., about 9.8 microns), thereby providing a height difference in the range of about 30x to about 50x (e.g., about 39x).

[0045] The diameter or width of the contact 316 may also vary, but in some embodiments, ranges from about 75 nm to 350 nm. It should be noted that the shape of the contact hole 314 (and contact 316) may vary from one embodiment to the next, depending on factors such as the mask shape and the hole etching process, but in some cases the hole 314 (and contact 316) is circular. Other hole / via shapes may include, for example, an oval shape or a trench shape or a rectangular shape or a square shape or any other shape suitable for a given application. It should further be noted that the width may vary along the height of the contact hole, such as when the hole tapers from a first width near the bottom of the hole to a relatively larger width at the top of the hole.

[0046] It should be further understood that the height-to-width aspect ratio of the best contacts 316 (or holes 314) can be very high, such as 20:1 or more. For example, for contact holes 314 (or contacts 316) having diameters in the range of 100 nm to 300 nm (e.g., about 200 nm) and heights in the range of 9 microns to 10 microns (e.g., about 9.5 microns) in length, the height-to-width aspect ratio is in the range of 30:1 to 100:1 (e.g., about 48:1).

[0047] Contacts 316 bring the wordlines 306 to the top of the structure. The contacts 316 may be further routed by interconnect structures (one or more metallization layers) to connect them back down again to integrated circuits such as CMOS logic on the substrate 302 and / or elsewhere in the integrated circuit structure. Interconnect processing may be completed as needed. Such additional processing may include completing back-end (BEOL) processes such as vias and interconnects for 3D NAND memory manufacturing. Exemplary System

[0048] 4 is an exemplary computing system 400 implemented using one or more of the 3D integrated circuit structures disclosed herein, according to an embodiment of the present disclosure. As can be seen, the computing system 400 houses a motherboard 402. The motherboard 402 may include multiple components, including but not limited to a processor 404 and at least one communication chip 406, each of which is physically and electrically coupled to or otherwise integrated with the motherboard 402. As will be appreciated, the motherboard 402 may be any printed circuit board, such as, for example, a mainboard, a daughterboard attached to the mainboard, or the only board of the system 400.

[0049] Depending on its applications, the computing system 400 may include one or more other components that may or may not be physically and electrically coupled to the motherboard 402. These other components may include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., read-only memory (ROM)), graphics processors, digital signal processors, cryptographic processors, chipsets, antennas, displays, touch screen displays, touch screen controllers, batteries, audio codecs, video codecs, power amplifiers, global positioning system (GPS) devices, compasses, accelerometers, gyroscopes, speakers, cameras, and mass storage devices (such as hard disk drives, compact discs (CDs), digital versatile discs (DVDs), etc.). Any of the components included in the computing system 400 may include one or more integrated circuit structures or devices configured in accordance with the disclosed techniques according to exemplary embodiments (e.g., an etch stop including high-k provided on a staircase or other integrated circuit structure having a diverse set of contact hole depths (or contact heights) that are etched simultaneously in a timed etch process as variously described herein). In some embodiments, multiple functions may be integrated into one or more chips (e.g., note that the communications chip 406 may be part of or otherwise integrated into the processor 404).

[0050] The communications chip 406 enables wireless communications to transfer data to and from the computing system 400. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., capable of communicating data using modulated electromagnetic radiation over a non-solid medium. The term does not imply that the associated devices are completely wire-free, although in some embodiments this may not be the case. The communications chip 406 may implement any of a number of wireless standards or protocols, including, but not limited to, Wi-Fi (Institute of Electrical and Electronics Engineers (IEEE) 802.11 family), worldwide interoperability for microwave access (WiMAX) (IEEE 802.16 family), IEEE 802.20, long-term evolution (LTE), 1x evolution-data optimized (Ev-DO), high-speed packet access (HSPA+), high-speed downlink packet access (HSDPA+), high-speed uplink packet access (HSUPA+), enhanced data rates for GSM evolution (EDGE), global system for mobile communication (GSM), general packet radio service (GPRS), code division multiple access (CDMA), time division multiple access (TDMA), digital enhanced cordless telecommunications (DECT), Bluetooth, and derivatives thereof, as well as any other wireless protocols specified for 3G, 4G, 5G and beyond. The computing system 400 may include multiple communications chips 406. For example, a first communications chip 406 may be dedicated to short-range wireless communications such as Wi-Fi® and Bluetooth®, and a second communications chip 406 may be dedicated to long-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX®, LTE, Ev-DO, and others.In some embodiments, the communications chip 406 may include one or more 3D stair structures having an etch stop that includes a high-k dielectric material, as variously described herein.

[0051] The processor 404 of the computing system 400 includes an integrated circuit die packaged within the processor 404. In some embodiments, the processor's integrated circuit die includes on-board circuitry implemented in one or more integrated circuit structures or devices formed using techniques such as those variously described herein. The term "processor" may refer to any device or part of a device that processes electronic data from, for example, registers and / or memory and converts the electronic data into other electronic data that can be stored in registers and / or memory.

[0052] The communications chip 406 may also include an integrated circuit die packaged within the communications chip 406. According to some such exemplary embodiments, the communications chip's integrated circuit die includes one or more integrated circuit structures or devices formed using techniques as variously described herein. As will be understood in light of the disclosure, it is noted that multi-standard wireless functionality may be integrated directly into the processor 404 (e.g., rather than having separate communications chips, the functionality of any chip 406 is integrated into the processor 404). It is further noted that the processor 404 may be a chipset having such wireless functionality. In short, any number of processors 404 and / or communications chips 406 may be used. Similarly, any one chip or chipset may have multiple functions integrated therein.

[0053] In various implementations, computing system 400 may be a laptop, netbook, notebook, smartphone, tablet, personal digital assistant (PDA), ultra-mobile PC, mobile phone, desktop computer, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, digital video recorder, or any other electronic device that processes data or employs one or more integrated circuit structures or devices formed using the techniques as variously described herein. Further exemplary embodiments

[0054] The following examples relate to further embodiments from which numerous variations and configurations will be apparent.

[0055] Example 1 includes an integrated circuit comprising: a memory staircase structure, each of a first step and a second step included in the staircase structure including an insulating material layer and a conductive material layer; an etch stop on the staircase structure, the etch stop including a high-k dielectric material; an insulating fill material on the etch stop; a first contact passing through the etch stop and on the conductive material layer of the first step, the first contact having a first height; and a second contact passing through the etch stop and on the conductive material layer of the second step, the second contact having a second height that is at least five times greater than the first height.

[0056] Example 2 shows that the high-k dielectric material is aluminum oxide (Al x O y ) or otherwise including the subject matter of Example 1.

[0057] Example 3 shows that the high-k dielectric material is hafnium oxide (HfO x ) or otherwise containing the subject matter of Examples 1 or 2.

[0058] Example 4 shows that the high-k dielectric material is yttrium oxide (Y x O y ), or otherwise including the subject matter of any of the above examples.

[0059] Example 5 shows that the high-k dielectric material is zirconium oxide (ZO). x ), or otherwise including the subject matter of any of the above examples.

[0060] Example 6 includes the subject matter of any of the above examples, where the etch stop is a multi-layer structure, a first layer of the etch stop includes oxygen and one or both of silicon and nitrogen, and a second layer of the etch stop includes a high-k dielectric material.

[0061] Example 7 includes the subject matter of Example 6, where the second layer is on the first layer, and the first layer is on the conductive material layer of each step.

[0062] Example 8 includes the subject matter of Example 6, where the second layer is on the conductive material layer of each step and the first layer is on the second layer.

[0063] Example 9 includes the subject matter of any of examples 6-8, wherein the high-k dielectric material includes aluminum and oxygen. In other examples, the high-k dielectric material includes oxygen and one or more of hafnium, aluminum, zirconium, and yttrium.

[0064] Example 10 includes the subject matter of any of the above examples, where the etch stop is a multi-phase structure, a first phase of the etch stop includes oxygen and one or both of silicon and nitrogen, and a second phase of the etch stop includes a high-k dielectric material.

[0065] Example 11 includes the subject matter of Example 10, where the second phase is adjacent to the first phase, which is adjacent to the conductive material layer of each step.

[0066] Example 12 includes the subject matter of Example 10, where the second phase is adjacent to the conductive material layer of each step and the first phase is adjacent to the second layer.

[0067] Example 13 includes the subject matter of any of examples 10 to 12, wherein the high-k dielectric material includes aluminum and oxygen. In other examples, the high-k dielectric material includes oxygen and one or more of hafnium, aluminum, zirconium, and yttrium.

[0068] Example 14 includes the subject matter of any of the above examples, where the etch stop is a multi-layer structure including a first layer and a second layer, and one or both of the first layer and the second layer include multiple phases.

[0069] Example 15 includes the subject matter of Example 14, wherein the first layer is on the conductive material layer of the respective step and includes a first phase and a second phase, each of the first phase and the second phase including oxygen and at least one of silicon and nitrogen, and the second layer is on the first layer and includes a high-k dielectric material.

[0070] Example 16 includes the subject matter of Examples 14 or 15, wherein the first layer is on the conductive material layer of the respective step and includes a high-k dielectric material, and the second layer is on the first layer and includes a first phase and a second phase, each of the first phase and second phase including oxygen and at least one of silicon and nitrogen.

[0071] Example 17 includes the subject matter of any of Examples 14 to 16, wherein the first layer is on the conductive material layer of the respective step and includes oxygen and one or both of silicon and nitrogen, and the second layer is on the first layer and includes a first phase and a second phase, one of the first phase and the second phase includes a high-k dielectric material and the other of the first phase and the second phase includes a different high-k dielectric material.

[0072] Example 18 includes the subject matter of any of Examples 14 to 17, wherein the first layer is on the conductive material layer of the respective step and includes a first phase and a second phase, one of the first phase and the second phase includes a high-k dielectric material and the other of the first phase and the second phase includes a different high-k dielectric material, and the second layer is on the first layer and includes oxygen and one or both of silicon and nitrogen.

[0073] Example 19 includes the subject matter of any of the above examples, where the first and second step conductive material layers include polysilicon. Other examples may include, for example, copper, aluminum, tungsten, nickel, titanium, silicide, germanide, or some alloy of any of these.

[0074] Example 20 includes the subject matter of any of the above examples, where the etch selectivity of the high-k dielectric material relative to the dielectric fill material is 15 times or more, such that for a given etch process, the dielectric fill material etches 15 times or more faster than the high-k dielectric material.

[0075] Example 21 includes the subject matter of any of the above examples, wherein the etch stop has a thickness in the range of 80 nm to 120 nm.

[0076] Example 22 includes the subject matter of any of the above examples, wherein the second contact has a second height that is 10 times greater than the first height. Or, 12.5 times or more, or 15 times or more, or 17.5 times or more.

[0077] Example 23 includes the subject matter of any of the above examples, wherein the second contact has a second height that is 20 times greater than the first height. Or, 22.5 times or more, or 25 times or more, or 27.5 times or more.

[0078] Example 24 includes the subject matter of any of the above examples, wherein the second contact has a second height that is 30 times greater than the first height. Or, 32.5 times greater, or 35 times greater, or 37.5 times greater.

[0079] Example 25 includes the subject matter of any of the above examples, wherein the second contact has a second height that is 35 times greater than the first height. Or, 37.5 times greater, or 40 times greater, or 42.5 times greater.

[0080] Example 26 includes the subject matter of any of the above examples, where the high-k dielectric material includes aluminum and oxygen, the insulator fill material includes silicon and oxygen, the insulator material layer includes silicon and oxygen, the conductive material layer includes polysilicon or a metal, and the first and second contacts include a metal. In other examples, the high-k dielectric material includes oxygen and one or more of hafnium, aluminum, zirconium, and yttrium.

[0081] Example 27 includes the subject matter of any of the above examples, wherein the first contact and the second contact include a metal and one or more nitrides.

[0082] Example 28 includes the subject matter of any of the above examples, wherein the first contact and the second contact have a width or diameter in the range of 100 nm to 300 nm.

[0083] Example 29 includes the subject matter of any of the previous examples, wherein the second contact has a height-to-width aspect ratio of 35:1 or greater.

[0084] Example 30 includes the subject matter of any of the previous examples, wherein the second contact has a height-to-width aspect ratio of 45:1 or greater.

[0085] Example 31 includes the subject matter of any of the previous examples, wherein the second contact has a height-to-width aspect ratio of 75:1 or greater.

[0086] Example 32 includes the subject matter of any of the previous examples, wherein the second contact has a height-to-width aspect ratio of 90:1 or greater.

[0087] Example 33 is a memory device or printed circuit board (PCB) that includes the integrated circuit of any of the above examples.

[0088] Example 34 includes the subject matter of example 33, wherein the memory device or PCB includes a NAND memory.

[0089] Example 35 includes the subject matter of example 33 or 34, wherein the memory device is part of a processor. The processor can be mounted on a PCB.

[0090] Example 36 includes an integrated circuit comprising: a memory staircase structure, each of a first step and a second step included in the staircase structure comprising an insulator layer and a conductive layer; an etch stop on the staircase structure, the etch stop comprising a high-k dielectric material; an oxide fill material on the etch stop; a first contact passing through the oxide fill material and the etch stop and on the conductive layer of the first step, the first contact having a first height; and a second contact passing through the oxide fill material and the etch stop and on the conductive layer of the second step, the second contact having a second height that is 25 times greater than the first height, wherein an etch selectivity of the high-k dielectric material relative to the oxide fill material is 15 times or greater, such that for a given etch process, the oxide fill material etches 15 times faster than the high-k dielectric material.

[0091] Example 37 includes the subject matter of Example 36, where the etch stop is a multi-layer structure, a first layer of the etch stop includes oxygen and one or both of silicon and nitrogen, and a second layer of the etch stop includes a high-k dielectric material.

[0092] Example 38 includes the subject matter of Example 37, where the second layer is on the first layer, and the first layer is on the conductive layer of each step.

[0093] Example 39 includes the subject matter of Example 37, where the second layer is on the conductive layer of each step and the first layer is on the second layer.

[0094] Example 40 includes the subject matter of any of Examples 36 to 39, wherein the etch stop is a multi-phase structure, a first phase of the etch stop includes oxygen and one or both of silicon and nitrogen, and a second phase of the etch stop includes a high-k dielectric material.

[0095] Example 41 includes the subject matter of Example 40, where the second phase is adjacent to the first phase, and the first phase is adjacent to the conductive layer of each step.

[0096] Example 42 includes the subject matter of Example 40, where the second phase is adjacent to the conductive layer of each step and the first phase is adjacent to the second layer.

[0097] Example 43 includes the subject matter of any of Examples 36-42, wherein the etch stop is a multi-layer structure including a first layer and a second layer, and one or both of the first layer and the second layer include multiple phases.

[0098] Example 44 includes the subject matter of Example 43, wherein the first layer is on the conductive layer of the respective step and includes a first phase and a second phase, each of the first phase and the second phase including oxygen and at least one of silicon and nitrogen, and the second layer is on the first layer and includes a high-k dielectric material.

[0099] Example 45 includes the subject matter of Examples 43 or 44, wherein a first layer is on the conductive layer of the respective step and includes a high-k dielectric material, and a second layer is on the first layer and includes a first phase and a second phase, each of the first phase and the second phase including oxygen and at least one of silicon and nitrogen.

[0100] Example 46 includes the subject matter of any of Examples 43 to 45, wherein a first layer is on the conductive layer of the respective step and includes oxygen and one or both of silicon and nitrogen, and a second layer is on the first layer and includes a first phase and a second phase, one of the first phase and the second phase includes a high-k dielectric material and the other of the first phase and the second phase includes a different high-k dielectric material.

[0101] Example 47 includes the subject matter of any of Examples 43 to 45, wherein the first layer is on the conductive layer of each step and includes a first phase and a second phase, one of the first phase and the second phase includes a high-k dielectric material and the other of the first phase and the second phase includes a different high-k dielectric material, and the second layer is on the first layer and includes oxygen and one or both of silicon and nitrogen.

[0102] Example 48 includes an integrated circuit comprising: a 3D NAND memory staircase structure, each of a first step and a second step included in the staircase structure comprising an oxide layer and a polysilicon layer; an etch stop on the staircase structure, the etch stop comprising aluminum oxide and having a thickness in a range of 50 nm to 150 nm; an oxide fill material on the etch stop; a first contact passing through the oxide fill material and the etch stop and on the polysilicon layer of the first step, the first contact having a first height; and a second contact passing through the oxide fill material and the etch stop and on the polysilicon layer of the second step, the second contact having a second height that is 35 times greater than the first height and having a height-to-width aspect ratio of 25:1 or greater; an etch selectivity of the high-k dielectric material to the oxide fill material is 15 times or greater, and for a given etch process, the oxide fill material etches 15 times faster than the high-k dielectric material.

[0103] Example 49 is a memory device including the integrated circuit of example 48.

[0104] Example 50 includes the subject matter of example 49, wherein the memory device is part of a processor or a printed circuit board (PCB).

[0105] The above description of exemplary embodiments of the present disclosure has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the present disclosure to the precise forms disclosed. Many modifications and variations may be made in light of the present disclosure. It is intended that the scope of the present disclosure be limited not by this detailed description, but rather by the claims appended hereto. [Item 1] 1. An integrated circuit comprising: a memory staircase structure, each of a first step and a second step of the memory staircase structure including a layer of insulating material and a layer of conductive material; an etch stop on the memory staircase structure, the etch stop comprising a high-k dielectric material; and a dielectric fill material on said etch stop; a first contact passing through the etch stop and on the conductive material layer of the first step, the first contact having a first height; a second contact passing through the etch stop and on the conductive material layer of the second step, the second contact having a second height that is at least five times greater than the first height; 1. An integrated circuit comprising: [Item 2] 2. The integrated circuit of claim 1, wherein the etch stop is a multi-layer structure, a first layer of the etch stop comprising oxygen and one or both of silicon and nitrogen, and a second layer of the etch stop comprising the high-k dielectric material. [Item 3] 3. The integrated circuit of claim 2, wherein the second layer is on the first layer, and the first layer is on the conductive material layer of each of the steps. [Item 4] 3. The integrated circuit of claim 2, wherein the second layer is on the conductive material layer of each of the steps and the first layer is on the second layer. [Item 5] 5. The integrated circuit of any one of claims 2 to 4, wherein the high-k dielectric material comprises aluminum and oxygen. [Item 6] 6. The integrated circuit of claim 1, wherein the etch stop is a multi-phase structure, a first phase of the etch stop comprising oxygen and one or both of silicon and nitrogen, and a second phase of the etch stop comprising the high-k dielectric material. [Item 7] 7. The integrated circuit of claim 6, wherein the second phase is adjacent to the first layer, and the first phase is adjacent to the conductive material layer of each of the steps. [Item 8] Item 6, which is a reference to item 2, wherein the second phase is adjacent to the conductive material layer of each of the steps and the first phase is adjacent to the second layer. [Item 9] 9. The integrated circuit of any one of claims 6 to 8, wherein the high-k dielectric material comprises aluminum and oxygen. [Item 10] Item 1 , the integrated circuit of item 1 , wherein the etch stop is a multi-layer structure including a first layer and a second layer, one or both of the first layer and the second layer including multiple phases. [Item 11] 11. The integrated circuit of claim 10, wherein the first layer is on the conductive material layer of each of the steps and includes a first phase and a second phase, each of the first phase and the second phase including oxygen and at least one of silicon and nitrogen, and the second layer is on the first layer and includes the high-k dielectric material. [Item 12] 12. The integrated circuit of claim 10 or 11, wherein the first layer is on the conductive material layer of each of the steps and comprises the high-k dielectric material, and the second layer is on the first layer and comprises a first phase and a second phase, each of the first phase and the second phase comprising oxygen and at least one of silicon and nitrogen. [Item 13] 13. The integrated circuit of any one of items 10 to 12, wherein the first layer is on the conductive material layer of each of the steps and comprises oxygen and one or both of silicon and nitrogen, and the second layer is on the first layer and comprises a first phase and a second phase, one of the first phase and the second phase comprising the high-k dielectric material and the other of the first phase and the second phase comprising a different high-k dielectric material. [Item 14] 14. The integrated circuit of any one of claims 10 to 13, wherein the first layer is on the conductive material layer of each of the steps and comprises a first phase and a second phase, one of the first phase and the second phase comprising the high-k dielectric material and the other of the first phase and the second phase comprising a different high-k dielectric material, and the second layer is on the first layer and comprises oxygen and one or both of silicon and nitrogen. [Item 15] Item 15. The integrated circuit of any one of items 1 to 14, wherein the etch stop has a thickness in the range of 80 nm to 120 nm, and the first contact and the second contact have a width or diameter in the range of 100 nm to 300 nm. [Item 16] Item 16. The integrated circuit of any one of items 1 to 15, wherein the second contact has a second height that is at least 20 times greater than the first height. [Item 17] 17. A memory device comprising an integrated circuit according to any one of items 1 to 16. [Item 18] Item 18. The memory device of item 17, wherein the memory device comprises a NAND memory. [Item 19] 20. The memory device of claim 18, wherein the memory device is part of a processor. [Item 20] 1. An integrated circuit comprising: a memory staircase structure, each of a first step and a second step included in the memory staircase structure includes an insulating layer and a conductive layer; an etch stop on the memory staircase structure, the etch stop comprising a high-k dielectric material; an oxide fill material on said etch stop; a first contact passing through the oxide fill material and the etch stop and on the conductive layer of the first step, the first contact having a first height; a second contact passing through the oxide fill material and the etch stop and on the conductive layer of the second step, the second contact having a second height that is at least 25 times greater than the first height; an etch selectivity of the high-k dielectric material relative to the oxide fill material is 15 times or more, such that for a given etch process, the oxide fill material etches 15 times faster than the high-k dielectric material. [Item 21] 21. The integrated circuit of claim 20, wherein the etch stop is a multi-layer structure, a first layer of the etch stop comprising oxygen and one or both of silicon and nitrogen, and a second layer of the etch stop comprising the high-k dielectric material. [Item 22] 22. The integrated circuit of claim 20 or 21, wherein the etch stop is a multi-phase structure, a first phase of the etch stop comprising oxygen and one or both of silicon and nitrogen, and a second phase of the etch stop comprising the high-k dielectric material. [Item 23] 21. The integrated circuit of claim 20, wherein the etch stop is a multi-layer structure including a first layer and a second layer, one or both of the first layer and the second layer including multiple phases. [Item 24] 1. An integrated circuit comprising: a 3D NAND memory staircase structure, wherein each of a first step and a second step included in the memory staircase structure includes an oxide layer and a polysilicon layer; an etch stop on the memory staircase structure, the etch stop comprising aluminum oxide and having a thickness in the range of 50 nm to 150 nm; an oxide fill material on said etch stop; a first contact passing through the oxide fill material and the etch stop and on the polysilicon layer of the first step, the first contact having a first height; a second contact passing through the oxide fill material and the etch stop and on the polysilicon layer of the second step, the second contact having a second height that is at least 35 times greater than the first height and having a height-to-width aspect ratio of at least 25:1; an etch selectivity of the high-k dielectric material relative to the oxide fill material is 15 times or more, such that for a given etch process, the oxide fill material etches 15 times faster than the high-k dielectric material. [Item 25] 25. A memory device comprising the integrated circuit of claim 24, wherein the memory device is part of a processor.

Claims

1. 1. An integrated circuit comprising: a memory staircase structure, each of a first step and a second step included in the memory staircase structure includes a layer of insulating material and a layer of conductive material; an etch stop on the memory staircase structure, the etch stop comprising a high-k dielectric material; a dielectric fill material on said etch stop; a first contact passing through the etch stop and on the conductive material layer of the first step, the first contact having a first height; a second contact passing through the etch stop and on the conductive material layer of the second step, the second contact having a second height that is at least five times greater than the first height; Equipped with the etch stop is a multi-layer structure, a first layer of the etch stop comprising silicon and one or both of oxygen and nitrogen, and a second layer of the etch stop comprising the high-k dielectric material; At least one of the first layer and the second layer of the etch stop is a multi-phase structure. Integrated circuits.

2. 2. The integrated circuit of claim 1, wherein a first phase of the etch stop comprises silicon and one or both of oxygen and nitrogen, and a second phase of the etch stop comprises the high-k dielectric material.

3. 3. An integrated circuit as claimed in claim 1 or 2, wherein the second layer is on the first layer, and the first layer is on the conductive material layers of the first and second steps, respectively.

4. 3. The integrated circuit of claim 1, wherein the second layer is on the conductive material layers of the first and second steps, and the first layer is on the second layer.

5. The integrated circuit of claim 1 , wherein the high-k dielectric material comprises aluminum and oxygen.

6. 3. The integrated circuit of claim 2, wherein the second phase is adjacent to the first layer, and the first phase is adjacent to the conductive material layers of the first and second steps.

7. 3. The integrated circuit of claim 2, wherein the second phase is adjacent to the conductive material layers of each of the first and second steps, and the first phase is adjacent to the second layer.

8. 8. The integrated circuit of claim 6 or 7, wherein the high-k dielectric material comprises aluminum and oxygen.

9. 1. An integrated circuit comprising: a memory staircase structure, each of a first step and a second step included in the memory staircase structure includes a layer of insulating material and a layer of conductive material; an etch stop on the memory staircase structure, the etch stop comprising a high-k dielectric material; a dielectric fill material on said etch stop; a first contact passing through the etch stop and on the conductive material layer of the first step, the first contact having a first height; a second contact passing through the etch stop and on the conductive material layer of the second step, the second contact having a second height that is at least five times greater than the first height; Equipped with the etch stop is a multi-layer structure including a first layer and a second layer, one or both of the first layer and the second layer including multiple phases; Integrated circuits.

10. the first layer is on the conductive material layer of each of the first and second steps and includes a first phase and a second phase, each of the first phase and the second phase including silicon and at least one of oxygen and nitrogen; the second layer is on the first layer and comprises the high-k dielectric material; 10. The integrated circuit of claim 9.

11. the first layer is on the conductive material layer of each of the first step and the second step and includes the high-k dielectric material; the second layer is on the first layer and includes a first phase and a second phase, each of the first phase and the second phase including silicon and at least one of oxygen and nitrogen; 11. An integrated circuit according to claim 9 or 10.

12. the first layer is on the conductive material layer of each of the first step and the second step, and includes silicon and one or both of oxygen and nitrogen; the second layer is on the first layer and comprises a first phase and a second phase, one of the first phase and the second phase comprising the high-k dielectric material and the other of the first phase and the second phase comprising a different high-k dielectric material; 12. An integrated circuit according to any one of claims 9 to 11.

13. the first layer is on the conductive material layer of each of the first and second steps and includes a first phase and a second phase, one of the first phase and the second phase including the high-k dielectric material and the other of the first phase and the second phase including a different high-k dielectric material; the second layer is on the first layer and comprises silicon and one or both of oxygen and nitrogen; 13. An integrated circuit according to any one of claims 9 to 12.

14. 14. The integrated circuit of claim 1, wherein the etch stop has a thickness in the range of 80 nm to 120 nm, and the first and second contacts have widths or diameters in the range of 100 nm to 300 nm.

15. 15. The integrated circuit of claim 1, wherein the second contact has a second height that is at least 20 times greater than the first height.

16. A memory device comprising an integrated circuit according to any one of claims 1 to 15.

17. The memory device of claim 16 , wherein the memory device comprises a NAND memory.

18. The memory device of claim 17 , wherein the memory device is part of a processor.

19. 1. An integrated circuit comprising: a memory staircase structure, each of a first step and a second step included in the memory staircase structure includes an insulating layer and a conductive layer; an etch stop on the memory staircase structure, the etch stop comprising a high-k dielectric material; an oxide fill material on said etch stop; a first contact passing through the oxide fill material and the etch stop and on the conductive layer of the first step, the first contact having a first height; a second contact passing through the oxide fill material and the etch stop and on the conductive layer of the second step, the second contact having a second height that is at least 25 times greater than the first height; Equipped with an etch selectivity of the high-k dielectric material relative to the oxide fill material is 15 times or more, such that for a given etch process, the oxide fill material etches 15 times faster than the high-k dielectric material; the etch stop is a multi-layer structure, a first layer of the etch stop comprising silicon and one or both of oxygen and nitrogen, and a second layer of the etch stop comprising the high-k dielectric material; At least one of the first layer and the second layer of the etch stop is a multi-phase structure. Integrated circuits.

20. 20. The integrated circuit of claim 19, wherein a first phase of the etch stop comprises silicon and one or both of oxygen and nitrogen, and a second phase of the etch stop comprises the high-k dielectric material.

21. 1. An integrated circuit comprising: a memory staircase structure, each of a first step and a second step included in the memory staircase structure includes an insulating layer and a conductive layer; an etch stop on the memory staircase structure, the etch stop comprising a high-k dielectric material; an oxide fill material on said etch stop; a first contact passing through the oxide fill material and the etch stop and on the conductive layer of the first step, the first contact having a first height; a second contact passing through the oxide fill material and the etch stop and on the conductive layer of the second step, the second contact having a second height that is at least 25 times greater than the first height; Equipped with an etch selectivity of the high-k dielectric material relative to the oxide fill material is 15 times or more, such that for a given etch process, the oxide fill material etches 15 times faster than the high-k dielectric material; the etch stop is a multi-layer structure including a first layer and a second layer, one or both of the first layer and the second layer including multiple phases; Integrated circuits.

22. 1. An integrated circuit comprising: a 3D NAND memory staircase structure, wherein each of a first step and a second step included in the memory staircase structure includes an oxide layer and a polysilicon layer; an etch stop on the memory staircase structure, the etch stop comprising aluminum oxide and having a thickness in the range of 50 nm to 150 nm; an oxide fill material on said etch stop; a first contact passing through the oxide fill material and the etch stop and on the polysilicon layer of the first step, the first contact having a first height; a second contact passing through the oxide fill material and the etch stop and on the polysilicon layer of the second step, the second contact having a second height that is at least 35 times greater than the first height and having a height-to-width aspect ratio of at least 25:1; an etch selectivity of the high-k dielectric material relative to the oxide fill material is 15 times or more, such that for a given etch process, the oxide fill material etches 15 times faster than the high-k dielectric material; the etch stop is a multi-layer structure, a first layer of the etch stop comprising silicon and one or both of oxygen and nitrogen, and a second layer of the etch stop comprising the high-k dielectric material; At least one of the first layer and the second layer of the etch stop is a multi-phase structure. Integrated circuits.

23. 23. The integrated circuit of claim 22, wherein a first phase of the etch stop comprises silicon and one or both of oxygen and nitrogen, and a second phase of the etch stop comprises the high-k dielectric material.

24. 1. An integrated circuit comprising: a 3D NAND memory staircase structure, wherein each of a first step and a second step included in the memory staircase structure includes an oxide layer and a polysilicon layer; an etch stop on the memory staircase structure, the etch stop comprising aluminum oxide and having a thickness in the range of 50 nm to 150 nm; an oxide fill material on said etch stop; a first contact passing through the oxide fill material and the etch stop and on the polysilicon layer of the first step, the first contact having a first height; a second contact passing through the oxide fill material and the etch stop and on the polysilicon layer of the second step, the second contact having a second height that is at least 35 times greater than the first height and having a height-to-width aspect ratio of at least 25:1; an etch selectivity of the high-k dielectric material relative to the oxide fill material is 15 times or more, such that for a given etch process, the oxide fill material etches 15 times faster than the high-k dielectric material; the etch stop is a multi-layer structure including a first layer and a second layer, one or both of the first layer and the second layer including multiple phases; Integrated circuits.

25. 25. A memory device comprising an integrated circuit according to any one of claims 19 to 24, said memory device being part of a processor.

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