Systems and methods for reducing degeneracy in quantum processors

Abstract

Degeneracy in analog processor operation is alleviated through the use of floppy qubits or regions of floppy qubits, thereby significantly increasing hardware performance for some problems. In one embodiment, samples are drawn from an analog processor. A device including the analog processor is evaluated for floppiness. A normalized floppiness metric is calculated, and an offset is added to advance the device during annealing. Degeneracy in a hybrid computing system including a quantum processor is mitigated by determining the magnetic susceptibility of the qubits and tuning the tunneling rate of the qubits based on a tunneling rate offset determined based on the magnetic susceptibility. The quantum annealing evolution is controlled by pausing the evolution for a determined pause duration.

Description

[Technical field]

[0001] Field The present disclosure relates generally to quantum processors and related systems, devices, methods and articles. [Background technology]

[0002] background Quantum Devices Quantum devices are structures in which quantum mechanical effects are observable. Quantum devices include circuits in which current transport is governed by quantum mechanical effects. Such devices include spintronics and superconducting circuits. Both spin and superconductivity are quantum mechanical phenomena. Quantum devices may be used in measurement instruments in computing machines and the like.

[0003] quantum computing A quantum computer is a system that directly exploits at least one quantum mechanical phenomenon, such as superposition, tunneling, or entanglement, to perform operations on data. The elements of a quantum computer are qubits. Quantum computers may provide speedups for some classes of computational problems, such as computational problems, by mimicking quantum physics.

[0004] Quantum Annealing Quantum annealing is a computational method that can be used to find a low-energy state of a system (usually, preferably the ground state of the system). Conceptually similar to classical simulated annealing, the method is based on the fundamental principle that natural systems tend to move toward lower energy states because lower energy states are more stable. While classical annealing exploits classical thermal fluctuations to drive a system to a lower energy state, quantum annealing may exploit quantum effects such as quantum tunneling as a source of delocalization to reach energy minima more precisely and / or quickly than classical annealing.

[0005] Quantum processors can be designed to perform quantum annealing and / or adiabatic quantum computation. An evolution Hamiltonian proportional to the sum of a first term proportional to the problem Hamiltonian and a second term proportional to the delocalization Hamiltonian can be constructed as follows: H E ∝A(t)H P +B(t)H D Here, H E is the evolutionary Hamiltonian, H P is the problem Hamiltonian, H D is the delocalized Hamiltonian, where A(t), B(t) are coefficients that control the evolution rate and can typically be in the range [0,1].

[0006] In some embodiments, a time-varying envelope function may be placed on the problem Hamiltonian. A suitable delocalized Hamiltonian is given by:

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[0007] The general problem Hamiltonian includes a first component proportional to the diagonal single-qubit terms and a second component proportional to the diagonal multi-qubit terms, and may be of the following form:

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number

[0008] Where:

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[0009] Throughout this specification, the terms "problem Hamiltonian" and "final Hamiltonian" are used interchangeably unless the context dictates otherwise. Some states of the quantum processor are energetically favored or simply favored by the problem Hamiltonian. These include ground states, but may include excited states.

[0010] H in the above two equations D and H P Each of the Hamiltonians, e.g., can be physically realized in a wide variety of ways. Particular examples are realized by embodiments of superconducting qubits.

[0011] Superconducting quantum processor for quantum annealing Superconducting quantum processors may be designed for quantum annealing (and / or adiabatic quantum computing; see below) components that may be used to implement the present systems and methods. A superconducting quantum processor may have multiple superconducting qubits and tunable control between the qubits.

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[0012] A quantum processor may include multiple interfaces used to configure and control the state of the quantum processor, each of which may be implemented with a respective inductive coupling structure as part of the programming subsystem and / or the evolution subsystem.

[0013] During operation of the quantum processor, the interface couples a flux signal to each compound Josephson junction of the qubit, thereby adjusting the tunable term (Δ i terms) into the system Hamiltonian. This coupling is x These magnetic flux signals are examples of "delocalized signals".

[0014] Similarly, the interface couples a flux signal into the qubit loop of each of the qubits, thereby i can be used to realize terms in the system Hamiltonian. This coupling is done by the diagonal σ z In addition, the interface couples the flux signal into a coupler, which provides the ij can be used to realize the terms in the stem Hamiltonian. This coupling is

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[0015] The quantum processor may include a readout device that reads out the final state of the qubit. Examples of superconducting qubits include superconducting flux qubits, superconducting charge qubits, etc.

[0016] Adiabatic Quantum Computing One model of quantum computing is adiabatic quantum computing. Adiabatic quantum computing may be suitable for solving, for example, hard optimization problems. Adiabatic quantum computing may be considered a special case of quantum annealing. In adiabatic quantum computing, a system ideally begins and remains in its ground state through adiabatic evolution. Those skilled in the art will understand that quantum annealing systems and methods may be implemented generally on adiabatic quantum computers. Throughout this specification and the appended claims, any reference to quantum annealing is intended to encompass adiabatic quantum computing, unless the context requires otherwise.

[0017] Hybrid Computing System Including Quantum Processors A hybrid computing system may include a digital computer communicatively coupled to an analog computer, hi some embodiments, the analog computer is a quantum computer and the digital computer is a classical computer.

[0018] A digital computer may include a digital processor that may be used to perform the classical digital processing tasks described in the present systems and methods. A digital computer may include at least one system memory that may be used to store various sets of computer or processor readable instructions, application programs and / or data.

[0019] A quantum computer may include a quantum processor that includes programmable elements such as qubits, couplers, and other devices. The qubits may be read out via a readout system, and the results may be communicated to a digital computer. The qubits and couplers may be controlled by a qubit control system and a coupler control system, respectively. In some embodiments, the qubit and coupler control systems may be used to perform quantum annealing on an analog computer.

[0020] Degeneracy In a quantum mechanical system, an energy level is said to be degenerate if it can correspond to two or more different measurable states. Two or more different states of a quantum mechanical system are said to be degenerate if they can correspond to the same energy level. A quantum binary number known as a qubit is a two-state quantum mechanical system. The two states are said to be degenerate if flipping the qubit from the first of the two states to the second has no effect on the energy of the system.

[0021] Degeneracy operations in quantum bits Dickson and Amin (arXiv 1104.2349) describe a way to avoid perturbative crossings by adding ancillary qubits (i.e., constraints) to the Hamiltonian. Dickson and Amin prove that "a simple adiabatic quantum algorithm based on penalizing clusters of path minima by tuning single-qubit tunneling energies can be effective at eliminating perturbative crossings that result in minimum gaps."

[0022] Dickson and Amin explain how corresponding eigenstates can repel each other and deviate from the final ground state if the final ground state is degenerate. If degeneracy in the final ground state can be introduced without significantly affecting the excited states, the ground state energy can deviate from that of the excited states.

[0023] Boixo et al. (arXiv 1212.1739) describe a 17-fold degenerate ground state Hamiltonian that can be constructed from a ferromagnetic four-cycle by imposing auxiliary constraints on each of the four original qubits. Summary of the Invention [Means for solving the problem]

[0024] overview A method for reducing degeneracy in a hybrid computing system including a quantum processor and a digital processor, the quantum processor and the digital processor being communicatively coupled to each other, the quantum processor including a plurality of devices and operated as a sample generator to provide samples, the method may be summarized as including: sending a problem to the quantum processor; until a termination criterion is satisfied: drawing a plurality of samples by the quantum processor; returning the plurality of samples to the digital processor; initializing a sample counter; until the sample counter reaches a predetermined sample limit: initializing a device counter; until the device counter reaches a first predetermined device limit: determining whether a device indexed by the device counter is floppy; incrementing the device counter; incrementing the sample counter; initializing the device counter; until the device counter reaches a second predetermined device limit: calculating a normalized floppiness metric for the device indexed by the device counter; adding an offset to advance the device during annealing; incrementing the device counter.

[0025] The method may further include determining whether a termination condition is satisfied. Determining whether a termination condition is satisfied may include one of completing a predetermined number of iterations, reaching a predetermined upper limit of an allowed computation time, or determining that a change in energy of a solution to the problem between successive iterations is less than a predetermined threshold. Reducing degeneracy in a hybrid computing system including a quantum processor may include reduc- ing degeneracy in a hybrid computing system including a superconducting quantum processor. Determining whether a device indexed by the device counter is floppy may include determining whether a superconducting qubit indexed by the device counter is floppy. Determining whether a superconducting qubit indexed by the device counter is floppy may include determining that a change in energy of a solution to the problem is less than a predetermined threshold when a state of the superconducting qubit is flipped. Determining whether a superconducting qubit indexed by the device counter is floppy may include determining a prevalence of zero net bias from neighboring devices. Calculating a normalized floppyness metric for a device indexed by a device counter may include summing the number of times the device was determined to be floppy and dividing this by a predetermined sample limit. The first predetermined device limit may be the same as the second predetermined device limit. Drawing a plurality of samples by the quantum processor may include drawing at least 1000 samples by the quantum processor. Determining whether a device indexed by the device counter is floppy may include determining whether a region of qubits indexed by the device counter is floppy. The region of qubits includes a plurality of coupled qubits. Sending the problem to the quantum processor may include sending the hard problem to the quantum processor.

[0026] The hybrid computing system includes at least one quantum processor including a plurality of devices and a readout subsystem; at least one digital processor-based device communicatively coupled to the at least one quantum processor; and at least one non-transitory computer-readable storage medium storing processor-executable instructions for mitigating degeneracy, the at least one non-transitory computer-readable storage medium, when executed, causing the at least one processor-based device to: send a problem to the quantum processor; until a termination criterion is satisfied; withdraw a plurality of samples by the quantum processor; return the plurality of samples to the digital processor via the readout system; initialize a sample counter; and and repeatedly repeating: initializing a device counter until the sample counter reaches a predetermined sample limit; determining whether the device indexed by the device counter is floppy until the device counter reaches a first predetermined device limit; and incrementing the device counter; incrementing the sample counter; initializing the device counter; until the device counter reaches a second predetermined device limit: calculating a normalized floppyness metric for the device indexed by the device counter; adding an offset to advance the device during annealing; and incrementing the device counter.

[0027] The quantum processor may be a superconducting quantum processor, and the plurality of devices may include a plurality of superconducting qubits, and the quantum processor may further include a plurality of coupling devices, each coupling device providing a controllable transfer coupling between a respective pair of superconducting qubits in the plurality of superconducting qubits. The at least one processor device may determine whether a superconducting qubit indexed by the device counter is floppy based at least in part on whether a change in energy of a solution to a problem is less than a predetermined threshold when a state of the superconducting qubit is flipped. The at least one processor device may determine whether a superconducting qubit indexed by the device counter is floppy based at least in part on a prevalence of zero net bias from neighboring devices. The normalized floppyness metric may be the number of times the device is determined to be floppy divided by a predetermined sample limit. The first predetermined device limit may be the same as the second predetermined device limit. The plurality of samples may include at least 1000 samples. The termination criteria may include at least one of completing a predetermined number of iterations, reaching a predetermined upper limit of the allowable computation time, or determining that a change in energy of a solution to the problem between successive iterations is less than a predetermined threshold. The device may be a field of qubits including a plurality of coupled qubits, and to determine whether the device indexed by the device counter is floppy, the at least one processor may determine whether the field of qubits indexed by the device counter is floppy. The problem may be a hard problem.

[0028] A method of reducing degeneracy in a hybrid computing system including a quantum processor and a digital processor, the quantum processor and the digital processor being communicatively coupled to one another, the quantum processor including a plurality of qubits and operated as a sample generator to provide samples. The method may be summarized as including: receiving a computational problem by the quantum processor; generating one or more samples based on the problem by the quantum processor; determining a magnetic susceptibility for each of one or more qubits of the plurality of qubits based on the one or more samples; determining a tunneling rate offset for at least one qubit of the one or more qubits based on the magnetic susceptibility of the one or more qubits; and tuning the tunneling rate of the at least one qubit based on the tunneling rate offset.

[0029] The method may further include determining a subset of the plurality of qubits to be tuned based on the target susceptibility, where the susceptibility of each qubit in the subset differs from the target susceptibility by more than a threshold amount; at least one qubit comprises the subset. Determining the susceptibility of each of the one or more qubits includes measuring a magnetization response of each of the one or more qubits to a flux bias. Determining the susceptibility of each of the one or more qubits may include, for each of the one or more qubits: generating one or more estimates of the qubit based on the one or more samples; refining the one or more estimates of the qubit; determining the susceptibility of the qubit based on the one or more estimates of the qubit.

[0030] Refining one or more estimates of a qubit may include generating an initial estimate and iteratively generating another estimate based on at least one of the initial estimate and one or more previously generated estimates. Iteratively generating the another estimate may include generating the another estimate based on a mean-field model. Each another estimate may include an estimate of at least one of a qubit current and a qubit flux, and generating the another estimate based on the mean-field model may include generating at least one estimate based on an expectation value of an isolated-qubit current based on the qubit flux.

[0031] Determining the magnetic susceptibility of each of the one or more qubits of the plurality of qubits may include determining a derivative of a flux-current relationship of each of the one or more qubits based on at least one of the one or more estimates. Determining a tunneling rate offset for the at least one qubit may include, for each of the at least one qubit: determining a target tunneling rate where the isolated qubit model predicts a predicted magnetic susceptibility corresponding to the magnetic susceptibility of the qubit; determining a tunneling rate offset based on the target tunneling rate.

[0032] Determining the target tunneling rate may include determining a sample target tunneling rate for each sample and determining the target tunneling rate based on a measure of the sample target tunneling rates. Determining the target tunneling rate based on the measure of the sample target tunneling rates may include determining an average value of the sample target tunneling rates.

[0033] For each of the at least one qubit, a tunneling rate offset may be determined based on a difference between a target tunneling rate of the qubit and a measure of the multiple target tunneling rates. The measure of the multiple target tunneling rates may be a median of the multiple target tunneling rates. For each of the at least one qubit, determining the target tunneling rate may include reducing a magnitude of the target tunneling rate below that predicted by the isolated qubit model.

[0034] A method of operating a digital processor to tune the annealing rate of at least one quantum bit of a quantum processor may be summarized as including: receiving an encoding of a problem, the encoding including one or more quantum bits; modifying the encoding by representing one of the one or more quantum bits as a logical quantum bit to generate a modified encoding of the problem, the logical quantum bit including a plurality of internal quantum bits of the quantum processor coupled by internal couplings, the logical quantum bit having a reduced effective tunneling rate compared to the tunneling rate of the quantum bit before the modification; and causing the quantum processor to compute the problem based on the modified encoding. The method may include selecting at least one of a number of internal quantum bits and an internal coupling strength of the logical quantum bits such that the effective tunneling rate approximates a target tunneling rate. The quantum bit may include an initial logical quantum bit. The method may further include selecting a topology for the logical quantum bit to affect the effective tunneling rate. Selecting the topology may include selecting the topology from a plurality of topologies based on a minimum internal coupling strength associated with each of the plurality of topologies.

[0035] The method may include modifying an effective tunneling rate of the logical qubit by determining a tunneling rate offset based on a characteristic of the logical qubit, and modifying the effective tunneling rate of the logical qubit by applying the tunneling rate offset to the anneal schedule. The logical qubit may have a chain topology, and the characteristic of the logical qubit may include a chain length. Determining the tunneling rate offset may include determining a scaling factor and scaling the offset value by the scaling factor. The offset value may be based on the following formula: 2^(k-1) / (k-1) where k is the length of the chain topology of logical qubits. The encoding may include a multiplication circuit that embeds the factorization problem.

[0036] The characteristics may include a position of the logical qubit in the graph relative to one or more other qubits. The graph may include an embedded graph. Determining the tunneling rate offset may include determining a distance between the logical qubit and an origin and / or a distance between the logical qubit and an edge of the graph, and determining the tunneling rate offset based on the distance. The tunneling rate offset may be determined based on a gradient defined for at least a portion of the graph. The gradient may include a radial gradient having a first region proximate to the origin, and the annealing schedule is advanced relative to the annealing schedule in a second region. The second region is farther from the origin compared to the first region.

[0037] The effective tunneling rate of a logical qubit can be determined based on an annealing sub-schedule specific to the logical qubit and an annealing schedule defined across the plurality of qubits, at least one of which is not included in the logical qubit.

[0038] Selecting a topology from the plurality of topologies based on a minimum internal coupling strength may include selecting a topology based on a correspondence between a minimum internal coupling strength and a number of internal qubits that couple with qubits outside the logical qubit.

[0039] A method of operating a hybrid computing system including a quantum processor and a digital processor, the quantum processor and the digital processor being communicatively coupled to each other, the quantum processor including a plurality of quantum bits, the method may be summarized as including: receiving as input by the digital processor via a user interface a pause start and a pause duration; controlling by the digital processor a quantum annealing evolution performed by the quantum processor, the control including starting the quantum annealing evolution; pausing the quantum annealing evolution for the pause duration upon reaching the pause start; and completing the quantum annealing evolution; and reading out the states of the plurality of quantum bits by the hybrid computing system.

[0040] Receiving the pause initiation may include receiving a measure of progress through the quantum annealing evolution. Receiving the pause initiation and the pause duration may include receiving the pause initiation and the pause duration via an application programming interface. Controlling the quantum annealing evolution performed by the quantum processor with the digital processor may include controlling the quantum annealing evolution performed by the plurality of superconducting flux qubits with the digital processor.

[0041] Pausing the quantum annealing evolution for a pause duration may include selecting a subset of qubits, pausing the quantum annealing evolution for one or more qubits that are not in the subset of qubits, and reverse annealing the subset of qubits while the one or more qubits are paused. The method may include forward annealing the subset of qubits after reverse annealing the subset of qubits and before completing the quantum annealing evolution.

[0042] A method of operating a digital processor to mitigate degeneracy in a hybrid computing system including a quantum processor, where the quantum processor and the digital processor are communicatively coupled to each other, and the quantum processor includes a plurality of quantum bits and is operated as a sample generator to provide samples, the method may be summarized as including: sending a problem for computation to the quantum processor; receiving one or more samples generated by the quantum processor based on the problem; determining a magnetic susceptibility for each of one or more quantum bits of the plurality of quantum bits based on the one or more samples; determining a tunneling rate offset for at least one quantum bit of the one or more quantum bits based on the magnetic susceptibility of the one or more quantum bits; and tuning the tunneling rate of the at least one quantum bit based on the tunneling rate offset.

[0043] A method of operating a hybrid computing system including a digital processor communicatively coupled to a physical quantum annealer including a plurality of quantum bits may be summarized as including: encoding a computational problem into a first subset of the plurality of quantum bits by the digital processor; weakly coupling a second subset of the plurality of quantum bits disjoint from the first subset to the first subset; determining a magnetic resonant tunneling (MRT) peak width by the quantum bits of the second subset; and adjusting an annealing schedule of the physical quantum annealer based at least in part on the MRT peak width.

[0044] Encoding the computational problem into a first subset of the plurality of quantum bits by the digital processor may include encoding the computational problem into a first plurality of superconducting quantum bits by the digital processor, and weakly coupling a second subset of the plurality of quantum bits to the first subset may include weakly coupling the second plurality of superconducting quantum bits.

[0045] A method of operating a hybrid computing system including a digital processor communicatively coupled to a physical quantum annealer may be summarized as including: collecting one or more energy statistics by parallel tempering with the physical quantum annealer; evaluating an expected result by the digital processor; and determining a preferred annealing rate and a preferred annealing trajectory by the digital processor based at least in part on the one or more energy statistics and the expected result.

[0046] The method may further include iteratively determining, by a digital processor, a preferred annealing rate and a preferred annealing trajectory based at least in part on one or more energy statistics and expected results until a change in the preferred annealing rate and the preferred annealing trajectory between iterations is less than a predetermined threshold.

[0047] Determining a preferred annealing rate may include inverting a cumulative distribution. Determining a preferred annealing trajectory may include performing a local search. Collecting one or more energy statistics by parallel tempering with a physical quantum annealer may include collecting one or more energy statistics by parallel tempering with a superconducting quantum processor.

[0048] A method of operating a hybrid computing system including a digital processor communicatively coupled to a quantum processor may be summarized as including: sending a computational problem by the digital processor to the quantum processor; generating one or more samples by the quantum processor; collecting one or more samples by the digital processor; determining by the digital processor whether a quantum bit is floppy with respect to the sample; upon determining that the quantum bit is floppy with respect to the sample, incrementing a count of the floppy quantum bits by the digital processor; calculating a metric by the digital processor based at least in part on the count of the floppy quantum bits; defining an ancillary quantum bit in the quantum processor by the digital processor; and coupling the ancillary quantum bit to at least one of the floppy quantum bits in the quantum processor by the digital processor.

[0049] Sending the computational problem to the quantum processor may include sending the computational problem to a superconducting quantum processor. Sending the computational problem to a superconducting quantum processor may include sending the computational problem to a physical quantum annealer. Determining by the digital processor whether a qubit is floppy with respect to a sample may include determining by the digital processor whether a superconducting qubit is floppy. Computing by the digital processor a metric based at least in part on the count of floppy qubits may include computing a normalized floppyness metric that describes a portion of the one or more samples in which the qubit is floppy. Coupling by the digital processor to at least one of the floppy qubits in the quantum processor may include selecting a strength of coupling between the floppy qubit and the ancillary qubit to adjust a tunneling amplitude of the floppy qubit.

[0050] A method of operating a hybrid computing system including a digital processor communicatively coupled to a quantum processor including a plurality of quantum bits may be summarized as including: receiving a first bias value for a first quantum bit of the plurality of quantum bits; coupling an ancillary quantum bit to the first quantum bit; determining whether a modulus of the first bias value is less than or equal to a predetermined threshold; upon determining that the modulus of the first bias value is less than or equal to the predetermined threshold: providing a second bias value to the ancillary quantum bit, the second bias value being a negative bias value and having a modulus greater than a modulus of the first bias value; setting a strength of coupling between the first quantum bit and the ancillary quantum bit to be approximately equal to the first bias value; and setting a zero bias on the first quantum bit.

[0051] Receiving a first bias value for a first qubit of the plurality of qubits may include receiving a bias value for a superconducting qubit. Coupling an ancillary qubit to the first qubit may include coupling the superconducting qubit to the first qubit. Determining whether a modulus of the first bias value is less than or equal to a predetermined threshold may include determining whether a modulus of the first bias value is less than or equal to one.

[0052] A method of operating a hybrid computing system including a quantum processor and a digital processor, the quantum processor and the digital processor being communicatively coupled to each other, the quantum processor including a plurality of quantum bits, the method may be summarized as including: receiving an annealing schedule by the digital processor; controlling by the digital processor a quantum annealing evolution performed by the quantum processor, the controlling including initiating the quantum annealing evolution, performing the quantum annealing evolution based at least in part on the annealing schedule, and completing the quantum annealing evolution; and reading out states of the plurality of quantum bits by the hybrid computing system, the receiving of the annealing schedule by the digital processor including receiving, for each quantum bit of the plurality of quantum bits, at least one of a respective tunneling velocity or a respective persistent current as a single-valued function of time.

[0053] Receiving the annealing schedule by the digital processor may include receiving a first annealing schedule for qubits of a first subset of the plurality of qubits, where receiving the first annealing schedule includes receiving at least one of a first tunneling rate or a first persistent current as a single-valued function of time for each qubit of the first subset of qubits, and receiving a second annealing schedule for qubits of a second subset of the plurality of qubits, where receiving the second annealing schedule includes receiving at least one of a second tunneling rate or a second persistent current as a single-valued function of time for each qubit of the second subset of qubits, and performing quantum evolution at least in part based on the annealing schedule includes performing quantum evolution of the first subset of qubits at least in part based on the first annealing schedule and performing quantum evolution of the second subset of qubits at least in part based on the second annealing schedule. In some embodiments, each of the qubits of the first and second subsets may include a respective first and second logical qubit.

[0054] Receiving the annealing schedule by the digital processor may include receiving a vector as a single-valued function of time. Receiving the annealing schedule by the digital processor may include receiving lateral and vertical energy measures as single-valued functions of time. Receiving the annealing schedule by the digital processor may include receiving a piecewise linear annealing schedule.

[0055] A method of operating a hybrid computing system including a quantum processor and a digital processor, the quantum processor and the digital processor being communicatively coupled to each other, the quantum processor including a plurality of quantum bits and a plurality of coupling devices, each of the plurality of coupling devices selectively communicatively coupling a pair of quantum bits, the method may be summarized as including: receiving an annealing schedule by the digital processor; controlling by the digital processor a quantum annealing evolution performed by the quantum processor, the control including initiating the quantum annealing evolution, performing the quantum annealing evolution based at least in part on the annealing schedule, and completing the quantum annealing evolution; and reading out states of the plurality of quantum bits by the hybrid computing system, the receiving of the annealing schedule by the digital processor receiving a respective local bias as a single-valued function of time for each quantum bit of the plurality of quantum bits and receiving a respective coupling strength as a single-valued function of time for each coupling device of the plurality of coupling devices.

[0056] A method for selecting an annealing schedule for a problem in a hybrid computing system including a quantum processor and a digital processor, the quantum processor and the digital processor being communicatively coupled to each other. The quantum processor includes a plurality of qubits. The method may be summarized as including: generating one or more annealing schedules; receiving an input annealing schedule and selecting an annealing schedule from the one or more annealing schedules based on an objective function that provides a measure of at least one characteristic of the input annealing schedule; transmitting the problem by the digital processor to the quantum processor; and executing the problem on the quantum processor according to the annealing schedule.

[0057] The method may include selecting an objective function from a set of one or more objective functions. Generating the one or more annealing schedules may include performing an optimization algorithm based on the objective function. The optimization algorithm may include parallel tempering. The objective function may measure at least one of models and chains linking the models generated by applying parallel tempering to the problem modified by the input annealing schedule. The objective function may include calculating at most a threshold number of parallel tempering iterations. The threshold number may be less than the number of iterations to solve the problem.

[0058] The optimization algorithm may include Bayesian optimization. The objective function may measure the ground state distribution of the problem according to an input annealing schedule. The objective function may provide at least one of a measure of similarity between the ground state distributions and a characteristic of one or more outliers of the ground state distributions. The objective function may measure the entropy of the ground state distribution, the distance of the ground state distribution from a uniform distribution according to a distance metric, the Gini coefficient of the ground state distribution, and / or the ratio of the maximum probability to the minimum probability of the ground state distribution.

[0059] Selecting an annealing schedule from the one or more annealing schedules may include determining that an annealing schedule provides optimal results compared to the one or more annealing schedules. Generating one or more annealing schedules may include generating a plurality of annealing schedules, selecting an interim annealing schedule based on an objective function, and generating one or more annealing schedules based on the interim annealing schedule.

[0060] A method for mitigating sample bias in a hybrid computing system including an analog processor and a digital processor, the analog processor and the digital processor being communicatively coupled to each other, the analog processor including a plurality of quantum bits, the method may be summarized as including: sending a computational problem by the digital processor to the analog processor; generating a first set of one or more samples by the analog processor; collecting the first set of one or more samples by the digital processor; identifying one or more valleys based on the first set of one or more samples, each valley including a set of equal-energy samples; selecting one of the one or more valleys based on a valley selection criterion; for each quantum bit in the valley: determining a degeneracy metric for the quantum bit; determining an annealing schedule for the quantum bit based on the degeneracy metric; collecting a second set of one or more samples by the analog processor based on the annealing schedule for the quantum bits in the valley.

[0061] Identifying one or more valleys may include determining that the plurality of qubits are related by a series of equal-energy qubit flips. Identifying one or more valleys may include determining membership of the plurality of qubits based on an equal-energy Hamming distance metric. Selecting a valley from the one or more valleys may include selecting a valley that has at least as many samples as each other valley of the one or more valleys based on a sample number of one or more samples within the valley. The degeneracy metric may include a normalized floppyness metric. Determining a degeneracy metric for a qubit may include determining a normalized floppyness metric for a qubit based on a number of times the qubit was floppy within samples of the valley.

[0062] Determining an annealing schedule for a qubit based on a degeneracy metric may include determining that an annealing offset is proportional to the degeneracy metric. Determining an annealing schedule for a qubit based on a degeneracy metric may include advancing the qubit to a start of annealing. Advancing the qubit to a start of annealing may include delaying at least one other qubit such that the at least one other qubit begins annealing after the qubit completes its anneal. Determining an annealing schedule for a qubit based on a degeneracy metric may include delaying the qubit to an end of annealing. At least one qubit in a valley may include a region of the qubit.

[0063] The method of claim 101 may include identifying one or more other valleys, each comprising a set of equal-energy samples, based on the one or more samples of the second set; selecting a different valley from the one or more other valleys based on a valley selection criterion; for each quantum bit in the different valley: determining a different degeneracy metric for the quantum bit; determining a different annealing schedule for the quantum bit based on the degeneracy metric; and collecting by the analog processor a third set of one or more samples based on the different annealing schedule for the quantum bits in the different valley.

[0064] Determining an annealing schedule for the qubit based on the degeneracy metric may include generating a plurality of annealing schedules and selecting an annealing schedule from the plurality of annealing schedules based on one or more selection criteria. Generating the plurality of annealing schedules may include generating a first annealing schedule and generating a plurality of scaled annealing schedules based on a plurality of scaling factors.

[0065] A method for controllably simulating noise in an annealing schedule used in a hybrid computing system, the hybrid computing system including an analog processor and a digital processor, the analog processor and the digital processor communicatively coupled to each other, the method may be summarized as including: receiving an input annealing schedule at the digital processor; generating pseudo-noise; modifying the input annealing schedule based on the pseudo-noise to generate an output annealing schedule; and providing the output annealing schedule to the analog processor.

[0066] Generating the pseudo-noise may include pseudo-randomly generating one or more modifications to apply to the input annealing schedule. Generating the pseudo-noise may include generating one or more annealing pauses and one or more annealing ramps. The one or more annealing pauses and ramps may be sequenced as alternating pairs of pauses and ramps.

[0067] Generating the pseudo-noise may include applying one or more modifications to the pseudo-noise based on one or more constraints. The one or more constraints may include requiring that the output annealing schedule deviate from the input annealing schedule by no more than a threshold amount. The threshold amount may vary over time and may be based on the time-dependent amplitude of the input annealing schedule. The threshold amount may be a predetermined constant. Applying the one or more modifications may include, for each modification, pseudo-randomly determining at least one of an amplitude of the modification and a duration of the modification according to the one or more constraints.

[0068] BRIEF DESCRIPTION OF THE DRAWINGS In the accompanying drawings, like reference numbers identify similar elements or acts. The dimensions and relative positions of elements in the accompanying drawings are not necessarily drawn to scale. For example, the shapes and angles of various elements are not necessarily drawn to scale, and some of these elements have been arbitrarily enlarged and positioned to improve legibility of the drawings. Furthermore, the particular shapes of the depicted elements are not necessarily intended to convey any information regarding the actual shape of the particular elements, but rather have been selected for ease of recognition in the accompanying drawings. [Brief description of the drawings]

[0069] [Figure 1A] 1 is a flowchart illustrating an exemplary method of operation of a hybrid computing system including a quantum processor for reducing degeneracy via "floppy qubits" in accordance with the present systems, devices, articles and methods. [Figure 1B] 1 is a flowchart illustrating an exemplary method of operation of a hybrid computing system including a quantum processor for reducing degeneracy via "floppy qubits" in accordance with the present systems, devices, articles and methods. [Diagram 2] 1 is a flowchart illustrating an example method of operation of a hybrid computing system including a quantum processor for reducing degeneracy via magnetic susceptibility in accordance with the present systems, devices, articles and methods. [Diagram 3] 13 is a plot showing advancing or retarding the per-qubit annealing schedule by tuning the tunneling rate Δi. [Figure 4] 1 is a flowchart illustrating an example method of operation of a hybrid computing system including a quantum processor for mitigating degeneracy via evolving measurements of qubits in accordance with the present systems, devices, articles and methods. [Diagram 5] 1 is a flow chart illustrating an exemplary method for determining magnetic susceptibility. [Figure 6] 1 is a plot illustrating comparative results of an exemplary implementation of degeneracy mitigation in a quantum processor in accordance with the present systems, devices, articles and methods. [Figure 7] 1 is a plot illustrating comparative results of an exemplary implementation of degeneracy mitigation in a quantum processor in accordance with the present systems, devices, articles and methods. [Figure 8] 1 is a plot illustrating comparative results of an exemplary implementation of degeneracy mitigation in a quantum processor in accordance with the present systems, devices, articles and methods. [Figure 9] 1 is a plot illustrating comparative results of an exemplary implementation of degeneracy mitigation in a quantum processor in accordance with the present systems, devices, articles and methods. [Figure 10] 1 is a plot illustrating comparative results of an exemplary implementation of degeneracy mitigation in a quantum processor in accordance with the present systems, devices, articles and methods. [Figure 11A] 1 is a graph illustrating an example annealing scenario with no pause in the annealing schedule. [Figure 11B] 1 is a graph illustrating an example annealing scenario with a pause in the annealing schedule. [Figure 11C] 1 is a graph illustrating an example annealing scenario having intermediate annealing ramps in an annealing schedule. [Figure 11D] 1 is a graph illustrating an example annealing scenario with an annealing schedule operation that includes intermediate annealing pauses and intermediate annealing ramps within the annealing schedule. [Figure 11E] 1 is a graph illustrating an example annealing scenario in which the local bias h of a qubit is changed during evolution. [Figure 11F] 13 is a graph illustrating an example annealing scenario in which the coupling strength J of a coupling device between a pair of qubits is altered during evolution. [Figure 12] 1 is a flowchart illustrating an exemplary method of operating a hybrid computer to adjust a quantum annealing schedule. [Figure 13] 1 is a flow chart illustrating an exemplary method for adjusting an annealing schedule based on equilibrium energy statistics. [Figure 14]1 is a flowchart illustrating an example method for mitigating the effects of degeneracy using ancillary qubits. [Figure 15] 1 is a flowchart illustrating an example method for mitigating h / J mismatch using an ancillary qubit. [Figure 16] FIG. 1 is a schematic diagram of an exemplary hybrid computing system including a digital computer coupled to an analog computer. [Figure 17] FIG. 1 is a schematic diagram of a portion of an example superconducting quantum processor designed for quantum annealing (and / or adiabatic quantum computing) components that may be used to implement the present systems and devices. [Figure 18] FIG. 13 is a schematic diagram of an example gradient defined on a graph including a Chimera structured group of qubits in accordance with the present systems, devices, articles and methods. [Figure 19] 1 is a flow chart illustrating an exemplary method of operating an annealing schedule for a logical qubit in accordance with the present systems, devices, articles, and methods. [Figure 20] 4 is a flowchart illustrating an example method for selecting an annealing schedule for a problem based on an objective function. [Figure 21] 1 is a flowchart illustrating an example method for mitigating sampling bias. [Figure 22] 1 is a graph illustrating an exemplary annealing scenario in which noise is controllably simulated and added to the input annealing schedule. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0070] General Comments In the following description, some specific details are included to provide a thorough understanding of various disclosed embodiments. However, one of ordinary skill in the art will recognize that the embodiments may be practiced without one or more of these specific details, or with other methods, components, materials, etc. In other examples, well-known structures related to quantum processors, such as quantum devices, couplers, and control systems including microprocessors and driver circuits have not been shown or described in detail so as not to unnecessarily obscure the description of the method embodiments. Throughout this specification and the appended claims, the terms "element" and "elements" are used to encompass, without limitation, all such structures, systems, and devices related to quantum processors and their associated programmable parameters.

[0071] Unless the context otherwise requires, throughout the following specification and claims, the term "comprises" and its variations are intended to be interpreted in their open and inclusive sense, i.e., "including but not limited to."

[0072] References throughout this specification to "one embodiment," "an embodiment," "another embodiment," "one example," "an example," "another example," etc. mean that the particular referenced feature, structure, or characteristic described with respect to that embodiment or example is included in at least one embodiment or example. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" or "in another embodiment," etc. in various places throughout this specification do not necessarily all refer to the same embodiment or example. Furthermore, particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments, examples, or implementations.

[0073] It should be noted that, as used in this specification and the appended claims, singular and indefinite articles include plural references unless the content clearly dictates otherwise. Thus, for example, a reference to a problem-solving system that includes a "quantum processor" includes a single quantum processor or two or more quantum processors. It should also be noted that the term "or" is typically used in its sense to include "and / or" unless the content clearly dictates otherwise.

[0074] The subheadings provided herein are for convenience only and do not interpret the scope or meaning of the embodiments.

[0075] Tunneling speed and degeneracy At least some quantum processors exploit the tunneling behavior of qubits to find lower energy states of a problem encoded on the processor. i The tunneling rate Δ i Typically, θ decreases over the course of the anneal, reaching a low value where the qubit is highly resistant to changing its state during the course of the evolution, and therefore ceases to interact with the problem. This behavior is called "freezing," and the frozen qubit can be thought of as effectively fixed for the remainder of the evolution.

[0076] Different qubits may be frozen at different times, and individual qubits may exhibit different tunneling behavior in different problems. Typically, the slow tunneling speed Δ i A qubit with iWhen different qubits in the same problem have different tunneling rates, the problem tends to exhibit degeneracy-related behavior that tends to reduce the optimality of the generated solutions. This behavior may include, for example, small-gap avoided level crossings and / or Landau-Zener transitions.

[0077] The techniques described in this application are techniques that can mitigate degeneracy by either directly or indirectly tuning the tunneling speed, which, in favorable circumstances, can significantly boost hardware performance for problems that are vulnerable to degeneracy and / or improve hardware performance for a more general set of problems.

[0078] Impact of degradation on hardware performance For low precision problem sets, experiments have shown a strong dependence of hardware performance on the parity of the degree of qubits (i.e., the number of active couplers per qubit). In particular, for a large population of low precision problem sets, even at C2 scale, the performance data can exhibit "fat tails". The phrase "fat tail" refers to a portion of the low precision problem set that is particularly challenging for the hardware. Fat tails can include problem instances that produce low energy solutions slowly and / or problems that cannot produce low energy solutions.

[0079] The behavior of problem sets in fat tails appears to be strongly related to degeneracy: specifically, problems with low degenerate ground states and highly degenerate first excited states appear to be at least partially responsible for the fat tail.

[0080] One approach is to reduce the problem energy measure of the hard problems. For C2 and C4 scale problems, reducing the energy measure of the applied J by a factor of 2× to 5× can improve hardware performance for hard problems.

[0081] Unfortunately, reducing the problem energy scale of a hard problem can have adverse effects. For example, reducing the energy scale can increase the effects of analog control errors, some of which do not scale down with the problem scale. Reducing the energy scale can also increase the effective temperature of a bathtub to which qubits are coupled. These effects, and others, can reduce hardware performance at some processor scales. Additionally, reducing the energy scale can reduce desirable quantum behavior.

[0082] At least some embodiments of the techniques described in this application provide techniques that can significantly boost hardware performance on fat-tail problems as well as improve hardware performance on more general problem sets.

[0083] Reducing degeneracy via 'floppy qubits' A "floppy qubit" is a qubit whose state can be flipped without any change in energy. Similarly, a floppy region is a set of multiple coupled qubits that can all be flipped in unison or simultaneously without any change in energy. In the remainder of this specification, the term "floppy qubit" includes floppy qubits or floppy regions unless the context dictates otherwise.

[0084] For some problem instances, such as "fat-tail" problem instances, there may be large iso-energy clusters of excited states that differ from each other by only a small number of qubit flips (e.g., one qubit flip or two qubit flips). The qubits responsible for movement around such iso-energy clusters are called "floppy" qubits. The techniques described in this application use a local major bias digital-to-analog converter (DAC) to advance (or retard) the floppy qubit relative to the rest of the working graph during quantum annealing. In one embodiment, the local major bias DAC may bias the qubit compound-compound Josephson junction (CCJJ) major loop.

[0085] 1A and 1B are flow charts illustrating an exemplary method 100 of operation of a hybrid computing system including a quantum processor to mitigate degeneracy in accordance with the present systems, devices, articles and methods. Figure 1A is a flow chart illustrating a first portion 100a of the exemplary method 100, and Figure 1B is a flow chart illustrating a second portion 100b of the exemplary method 100. Control of the method 100 may be transferred from the first portion 100a to the second portion 100b, or vice versa.

[0086] The method of operation 100 illustrated by Figures 1A and 1B includes a number of acts. One or more of these acts may be performed by (or via) one or more circuits, such as, for example, one or more processors (e.g., digital processors), analog processors such as quantum processors, or hybrid computers including both digital and analog processors. For purposes of the description of Figures 1A and 1B, it is assumed that the acts are performed by a hybrid computer including a quantum processor. The first portion 100a and second portion 100b of the method 100 are exemplary, and one of ordinary skill in the art will recognize that alternative implementations may omit some acts and / or include additional acts.

[0087] Referring initially to FIG. 1A, a first portion 100a of method 100 begins at 105, e.g., in response to submission of a problem or in response to a call by another routine. At 110, the hybrid computer sends the problem to the hardware. For purposes of this example, the hardware is a quantum processor communicatively coupled to a digital computer. At 115, the hybrid computer collects a number of samples. In some embodiments, the number of samples, N, is about 1000. In other embodiments, the number of samples, N, is 10. At acts 120-145 (inclusive), the hybrid computer records which of the M qubits in the quantum processor are floppy for each of the N samples.

[0088] At 120, the hybrid computer initializes sample indices, and at 125, the hybrid computer initializes qubit indices.

[0089] At 130, the hybrid computer determines whether the qubit or region of qubits is floppy (i.e., whether the state of the qubit or region of qubits can be flipped without changing the energy). In response to determining at 130 that the qubit or region of qubits is floppy ("yes"), control in first portion 100a proceeds to 135, where the floppy qubit or region of floppy qubits is recorded. In response to determining at 130 that the qubit or region of qubits is not floppy ("no"), control in first portion 100a proceeds to 140.

[0090] At 140, the hybrid computer determines whether there is another qubit or region of qubits to check for floppiness. In response to determining at 140 that there is another qubit ("yes"), control in first portion 100a returns to 130. The loop of 130-145 is repeated until there are no more qubits or regions of qubits to check for floppiness.

[0091] This process may repeat while there are additional qubits or regions of qubits to check for floppiness. In response to determining at 140 that there are no more qubits or regions of qubits to check for floppiness ("NO"), control of first portion 100a passes to 145, where the hybrid computer checks whether there is another sample. In response to determining at 145 that there is another sample ("YES"), control of first portion 100a passes back to 125. The loop from 125 to 145 is repeated until there are no more samples.

[0092] In response to determining at 145 that no more sample is present ("NO"), control of method 100 proceeds to a second portion 100b of FIG. 1B.

[0093] At 150, the hybrid computer initializes the qubit indices. At 155, the hybrid computer calculates a normalized floppiness metric for the current qubit or a region of current qubits. The normalized floppiness metric μ for the i th qubit is i An exemplary definition of is as follows:

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[0094] At 160, the hybrid computer advances the current qubit or region of qubits during quantum annealing based on the normalized floppiness metric. Advancing a qubit (or region of qubits) may be done in any of a number of ways, as described in further detail elsewhere herein. As an example, in some embodiments, advancing a qubit or region of qubits includes adding an offset to the main loop (anneal) DAC that is proportional to the normalized floppiness metric. If it is a region of qubits, the offset is applied to all member qubits of the region of qubits. In an exemplary embodiment where the qubit is a flux qubit, the offset is μ i ×2.5mΦ 0 is equal to.

[0095] At 165, the hybrid computer determines whether there is another qubit or region of qubits to which an offset should be applied. In response to determining at 165 that there is another qubit or region of qubits ("yes"), control in second portion 100b returns to 155. The loop from 155 to 165 is repeated until there are no more qubits or regions of qubits to which an offset should be applied.

[0096] In response to determining at 165 that the qubit or region of qubits is no longer present ("NO"), control of second portion 100b passes to 170. At 170, the hybrid computer determines whether a termination criterion has been satisfied. The termination criterion may be a single criterion or a combination of two or more criteria. Exemplary criteria may include thresholds based on the diversity of samples, the energy of samples, the degree or rate of convergence, and the number of unique ground states or first excited states. Exemplary criteria may also include thresholds based on computation time and number of iterations.

[0097] In response to determining at 170 that the termination criteria have been met ("YES"), method 100 ends at 175. In response to determining at 170 that the termination criteria have not been met ("NO"), control of method 100 returns to 115 of first portion 100a of FIG. 1A.

[0098] In some embodiments, the hybrid computer advances only a subset of the floppy qubits. In general, a qubit or region of qubits will either be floppy in a percentage of samples drawn, rarely be floppy in any samples, or rarely be floppy in all samples. A floppyness metric (described above) may be utilized to determine which qubits or regions of qubits are floppy and which qubits should be advanced. In some embodiments, qubits or regions of qubits that exceed a threshold for the floppyness metric may be advanced. In other embodiments, other criteria may be used by themselves or in conjunction with the floppyness metric to determine which qubits or regions of qubits should be advanced.

[0099] In some embodiments, the hybrid computer may take an iterative approach in which qubits or regions of qubits are stepped and repeated in a small subset. In some embodiments, the hybrid computer may choose to step only the floppiest qubits or regions of qubits in each iteration. In other embodiments, the hybrid computer may perform a suitable combination of the foregoing embodiments to step qubits or regions of qubits. The benefit of stepping and repeating a small number of qubits or regions of qubits is that this approach may reduce overcorrection.

[0100] In some embodiments, the offset applied to each qubit or region of qubits may be the same. In other embodiments, the offset applied to various qubits or regions of qubits may vary from qubit to qubit. For example, a hybrid computer may choose to apply a larger offset to one qubit or region of one qubit rather than another qubit or region of another qubit.

[0101] Relief of degeneracy via magnetic susceptibility In some embodiments, a qubit may be advanced or retarded during quantum annealing based on the qubit's magnetic susceptibility (denoted as χ, and sometimes referred to herein simply as "susceptibility"). Magnetic susceptibility χ is a property of some types of qubits (including flux qubits) that describes the degree of magnetization of the qubit in response to an applied magnetic field. This response may vary in various circumstances (e.g., depending on the strength and topology of its couplings with other qubits and the flux bias of the other qubits). Thus, the magnetic susceptibility χ of a qubit may be different for different problems. In some embodiments, the magnetic susceptibility χ of one or more qubits for a particular problem is measured and / or inferred, and at least one of the one or more qubits is advanced or retarded based on its magnetic susceptibility χ. For convenience, references in this disclosure to "determining" a magnetic susceptibility include measuring the magnetic susceptibility and / or estimating the magnetic susceptibility.

[0102] The inventors have determined that the magnetic susceptibility χ of a quantum bit is proportional to the tunneling speed Δ i We have determined through experiments that the qubits that freeze early during evolution (i.e., low Δ i qubits that freeze later in the evolution (i.e., low Δ i qubits (qubits that reach χ slowly) tend to have relatively low magnetic susceptibility χ.

[0103] Figure 2 shows the tunneling speed Δ i2 is a flow chart illustrating an exemplary method 200 for tuning a . The method 200 illustrated by FIG. 2 includes a number of acts. One or more of these acts may be performed by (or via) one or more circuits, such as, for example, one or more processors (e.g., digital processors), analog processors such as quantum processors, or hybrid computers including both digital and analog processors. For purposes of the description of FIG. 2, it is assumed that the acts are performed by a hybrid computer including a quantum processor. The method 200 is exemplary. Those skilled in the art will recognize that alternative implementations may omit some acts and / or include additional acts.

[0104] At 202, a problem is received by the hybrid computer and encoded on a quantum processor. At 204, the hybrid computer collects one or more samples based on the encoded problem. The hybrid computer may collect any number of samples depending on the requirements of various other acts of method 200 (e.g., depending on the number of samples needed to determine the susceptibility of one or more qubits at 206). For example, in some embodiments, the number of samples collected is 1. As another example, in other embodiments, the number of samples collected is 1000.

[0105] At 206, the magnetic susceptibility χ of one or more qubits is determined by the hybrid computer. Various approaches to determining the magnetic susceptibility χ of each qubit may be taken. For example, the magnetic susceptibility χ of each qubit may be measured by directly measuring the magnetization response of each qubit to a magnetic flux bias. As another example, the magnetic susceptibility χ of each qubit may be inferred based on a numerical method applied to one or more samples (and / or other data). Several approaches to determining the magnetic susceptibility χ of each of one or more qubits are discussed in more detail below, although one of ordinary skill in the art will understand that other approaches may be utilized alternatively or additionally.

[0106] In some embodiments, the magnetic susceptibility χ is measured directly. This can be done, for example, by having a quantum processor perform the evolution of the first set in question and simultaneously measure the flux bias Φ of one or more qubits. X This can be done in situ by instructing the system to perform an evolution of a second set of problems in which the second set is changed. The resulting difference in magnetization response of one or more qubits between the first and second sets can then be measured to determine a magnetic susceptibility χ of each of the one or more qubits. For example, the magnetic susceptibility χ can be determined by the change in the flux bias Φ between the first and second set of evolutions. X of the persistent current I P where each of the first and second sets of evolutions includes multiple evolutions, thereby providing multiple sample measurements, and the persistent current I P (or other estimators) of and / or the flux bias Φ X For example, the magnetic susceptibility χ of a qubit may be determined based on the following formula:

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[0107] Flux bias Φ of the qubit XSince modifying the flux bias Φ of just one qubit per evolution will likely provide a result that more accurately describes the original problem, modifying fewer qubits per evolution is likely to provide a result that more accurately describes the original problem. X is changed in each set of evolutions, thus requiring multiple sets of evolutions (and thus more time) to determine the magnetic susceptibility χ of the multiple qubits. In some embodiments, the flux bias set {Φ X} is varied in a given evolution, thereby reducing the number of evolution sets required (but potentially losing precision compared to single qubit measurements). In some embodiments, a global flux bias Φ is applied uniformly to all qubits of the processor in the second set of evolutions.

[0108] The first and second sets of evolutions may occur in any order and may optionally be interleaved (e.g., the second set of evolutions occur between the first set of evolutions and / or vice versa). In some embodiments, each of the first and / or second sets of evolutions comprises a single evolution. In some embodiments, each of the first and / or second sets of evolutions comprises multiple evolutions. The first and second sets of evolutions may comprise different numbers of evolutions.

[0109] In some embodiments, the magnetic susceptibility χ is estimated, for example, via post-processing techniques. For example, in some embodiments, the magnetic susceptibility χ of one or more qubits is estimated via a mean field method (e.g., via some embodiments of the magnetic susceptibility estimation method of FIG. 5).

[0110] At 208, a subset D of one or more qubits is optionally identified for tuning. Such a subset D may be, for example, a subset having a target susceptibility χ T may include each of one or more qubits having a magnetic susceptibility χ that differs by more than a threshold amount T. That is, a qubit X having a magnetic susceptibility χ may be included in the subset D if the following inequality is satisfied: |χ-χT |>T

[0111] In some embodiments, the target magnetic susceptibility χ T is based on the magnetic susceptibility χ of one or more qubits. For example, the target magnetic susceptibility χ T T may be determined to be the mean, median or mode of the magnetic susceptibility χ of one or more qubits. T may be a predetermined and / or user-provided value. Alternatively or in addition, T may be the mean, median or mode of the magnetic susceptibility χ of one or more qubits and / or the target magnetic susceptibility χ T For example, T can be determined based on the target magnetic susceptibility χ T can be a constant fraction of (e.g., 0.1χ T , 0.5χ T , 1.0χ T or any other suitable value).

[0112] As another example, the subset D may be the set of N qubits with the highest limiting magnetic susceptibility χ (e.g., |χ−χ T This can be determined by identifying the N qubits (where N is some positive integer) for which | is maximized.

[0113] In some embodiments, only qubits that are to be advanced are included in subset D. In some embodiments, only qubits that are to be delayed are included in subset D.

[0114] At 210, a Δtuning offset ω is determined for each qubit in D. This offset may be determined in a variety of ways, such as Δ i In some embodiments, the qubit has approximately equal tunneling rate Δ i , so that the qubits are frozen nearly in unison (such qubits are said to be "synchronized"). In some embodiments, the Δtuning offset ω for a particular qubit X is determined by the magnetic susceptibility χ of qubit X and the threshold magnetic susceptibility χ TFor example, the Δtuning offset ω may be determined according to the following equation:

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[0115] In 212, the tunneling rate Δ i is tuned according to the qubit's associated Δtuning offset ω. As discussed elsewhere herein, Δ can be adjusted by, for example, modifying digital-to-analog converter (DAC) offsets for the qubit's compound-compound Josephson junctions (CCJJs), forming logical qubits, etc. i There are various ways to tune the tunneling rate Δ i is scaled proportionally to the Δtuning offset ω. For example, an offset ω=0.2 scales the Δ i (thus slowing down the annealing rate of the qubit and delaying freezing), while an offset of ω=0.1 reduces the qubit's Δ i (thus speeding up the annealing rate of the qubits and accelerating freezing). For example, each qubit in the subset D receives a new Δ i Can be given: Δ new =(1+ω)Δ old Here, Δ old is the Δ of the qubit prior to Δ-tuning i And Δ new is the Δ of the qubit after Δ tuning i It is.

[0116] 3 shows a chart illustrating an exemplary Δ-tuning scenario. The vertical axis corresponds to the instantaneous tunneling speed Δ of a given qubit. The horizontal axis corresponds to time, and in particular to the progress in evolution (represented in s). Line 302 corresponds to the tunneling speed of an exemplary qubit (not shown), and point 304 corresponds to the initial tunneling speed Δ of the qubit. i Line 310 corresponds to a scenario in which the evolution of an example qubit is slowed by applying an offset 312 (which may be represented by a positive number, for example), and the initial tunneling velocity Δ i Line 320 corresponds to a scenario in which the evolution of an exemplary qubit has been advanced by applying an offset 322 (which may be represented, for example, by a negative number), resulting in an initial tunneling velocity Δ i In the scenario of line 310, the qubit evolution freezes later than the evolution could originally be frozen (i.e., in the pre-Δ-tuning scenario corresponding to line 302). In the scenario of line 320, the qubit evolution freezes earlier than the evolution could originally be frozen.

[0117] Returning to FIG. 2, at 214, the hybrid computer performs calculations on the problem (possibly modified by the delta tuning operation of 212) and determines a solution.

[0118] Estimation of magnetic susceptibility In some embodiments, the magnetic susceptibility of a qubit is estimated by inferring one or more properties of the qubit and using a model to estimate the magnetic susceptibility of the qubit based on those properties. Such an estimate of the magnetic susceptibility may be used, for example, in 206 of method 200. As discussed in more detail below, models that may be used in such an estimate include, but are not limited to, mean-field models.

[0119] 5 is a flow chart illustrating an exemplary method 500 for determining magnetic susceptibility.

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[0120] At 504, an initial guess or guess regarding one or more characteristics of the qubit is sampled.

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[0121] At 505, the initial estimate is refined to generate a refined estimate by circuitry. For example,

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[0122] In some embodiments, the estimate may be refined by exploiting an explicit relationship between the magnetic flux Φ applied to the superconducting quantum processor and the resulting current I flowing within the device. For example, for at least some superconducting quantum processors, the equilibrium state of the processor may be the following set of coupled equations:

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[0123] In some embodiments,

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[0124] In some embodiments,

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[0125] In some embodiments,

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[0126] In some embodiments,

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[0127] Based on the above, the inventors have concluded that in such an embodiment, the isolated quantum bit (〈I p The expectation value of the persistent current of (>) can be determined based on the following formula:

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[0128] In some embodiments, the temperature T is modeled as a limit close to zero. This can be done, for example, by omitting the tanh term from the above equation. Temperature may be considered separately (e.g., via a subsequent adjustment step) or not at all.

[0129] In some embodiments,

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[0130] Magnetic susceptibility of each qubit

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[0131] In 506, the estimated magnetic susceptibility

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[0132] In some embodiments, the estimated problem susceptibility

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[0133] The inferred problem susceptibility of a particular qubit

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[0134] To understand the above relationship, it may be helpful to consider one possible derivative.

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[0135] In some embodiments, method 500 may output the guessed susceptibility generated as described above, and method 500 may end. In some embodiments, method 500 may repeat acts 502-506 to generate multiple guessed susceptibility per qubit using circuitry. The multiple guesses may be combined into a composite guess for each qubit.

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[0136] At 508, a target tunneling rate for each qubit j is determined.

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[0137] Since magnetic susceptibility can vary with magnetic flux / current (which, as noted above, is a related property), the isolated qubit model can also be based on magnetic flux and / or current. For example, Δ j The value of may be determined according to the following formula:

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[0138] Tunneling Speed

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[0139] Optionally, at 510, acts 502-508 include determining the tunneling rate (e.g., based on another sample received from the hardware).

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[0140] Tunneling Speed

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[0141] In 514, the tunneling rate Δ of one or more qubits i Adjustments to (e.g., Δtuning offsets) can be made to one or more target tunneling rates.

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[0142] In some embodiments, the Δtuning offset ω j is multiple target tunneling speed

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[0143] In some embodiments, the reduced offset ω j (i.e., an offset having a reduced magnitude compared to that described above) is used. In some circumstances, such a reduction may be j For example, the offset ω can help compensate for nonlinear and dispersion effects encountered in adjusting j may be determined as above and then reduced by a constant factor (e.g., ω j may be halved), may be exponentially reduced, and / or may be reduced in other ways.

[0144] Optionally, method 500 further comprises: j In some embodiments, the qubit tunneling rate may be adjusted to an offset ω j In some embodiments, another hardware sample is not necessarily received at 502, but instead (or in addition) a corrected sample is received based on the hardware sample previously received at 502 and the offset ω j and the tunneling speed Δ j Changes and samples

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[0145] Another iteration may include further homogenization at 514, which results in an offset ω jis refined over multiple iterations.

[0146] At 518, the offset ω j is output by the circuitry. Such an output may be, for example, a function of the tunneling rate Δ of one or more qubits as described elsewhere herein. j offset ω j Based on the offset ω j The offset ω can be returned by software via the communication link. j , and the offset ω j to the user and / or otherwise offset ω j to a hardware and / or software interface.

[0147] Reducing degeneracy through evolutionary measurements In some embodiments, the states of the qubits are measured during the evolution prior to completion. Such measurements may provide information about the time-dependent quantum annealing dynamics over the course of the evolution (e.g., approximate freeze-up time, correlation of states as a function of time, and / or other information). Such information may be used to manipulate the annealing process via (for example) Δ-tuning. In some embodiments, a flux detector is used to measure the expectation value of one or more qubits one or more times during the evolution, and the flux detector measurements result in one or more Δ-tuning of one or more of the one or more qubits. i Used to tune the

[0148] Figure 4 shows the tunneling speed Δ i4 is a flow chart illustrating an example method 400 of tuning a . The method 400 illustrated by FIG. 4 includes a number of acts. One or more of these acts may be performed by (or via) one or more circuits, such as, for example, one or more processors (e.g., digital processors), analog processors such as quantum processors, or hybrid computers including both digital and analog processors. For purposes of the description of FIG. 4, it is assumed that the acts are performed by a hybrid computer including a quantum processor. Method 400 is exemplary, and one of ordinary skill in the art will recognize that alternative implementations may omit some acts and / or include additional acts.

[0149] At 402, a problem is received by the hybrid computer and encoded on a quantum processor. At 404, the hybrid computer couples a flux detector to a quantum bit (referred to herein as a "problem qubit"). The problem qubit may be an individual hardware qubit or a logical qubit that includes multiple hardware qubits. Method 400 may include any number of flux detectors and problem qubits. Although this disclosure generally refers to a "problem qubit" and a "flux detector," it is understood that multiple flux detectors and problem qubits may be measured and / or tuned in unison and / or sequentially according to method 400.

[0150] The flux detector may be any quantum flux parametron that can be annealed separately from the problem qubit. For example, the flux detector may include a qubit that is adjacent to (i.e., shares a coupler with) the problem qubit. As another example, the flux detector may be a calibration device provided by the processor and configured to measure the problem qubit. The strength J of the coupling between the flux detector and the problem qubit may be problem dependent. In general, the coupling strength J should be strong enough to reliably replicate the qubit state to the flux detector, but weak enough so as not to perturb the dynamical properties of the problem qubit. Determining the appropriate strength will depend in part on the coupling of the problem qubit with other qubits.

[0151] At 406, the quantum processor begins an evolution that includes annealing the problem qubit and the flux detector. In some embodiments, the problem qubit and the flux detector begin annealing approximately in unison. In some embodiments, the flux detector begins annealing after the problem qubit begins annealing.

[0152] At 408, the flux detector is rapidly annealed relative to the qubit of interest, e.g., via any suitable method described herein or otherwise known (now or future) to ensure that the flux detector has a low tunneling rate Δ i Thus, the flux detector completes its annealing process before the evolution is complete, and potentially before the problem qubit is frozen. By the end of the flux detector anneal, the expectation of the state of the problem qubit over the course of the flux detector anneal is replicated into the flux detector.

[0153] The states of the flux detectors are read at 410. In some embodiments, the states of the flux detectors are stored in a buffer and multiple states are read out together.

[0154] At 412, the hybrid computer determines whether to take another measurement of the problem qubit. In some embodiments, the hybrid computer continues to take measurements of the problem qubit until the evolution is complete. In some embodiments, the hybrid computer takes a predetermined number of measurements and then ceases taking such measurements. In some embodiments, the hybrid computer ceases taking measurements of the problem qubit after determining that the problem qubit is frozen (e.g., based on the measurement information read from the flux detector). In some embodiments, the hybrid computer ceases taking measurements of different problem qubits at different times.

[0155] If the hybrid computer determines that another measurement should be taken, method 400 returns to 408. The hybrid computer may optionally introduce a delay at 412 and / or 408 so that a predetermined amount of time elapses between measurements. The hybrid computer may return to 408 one or more times over the course of the evolution to obtain measurements of the problem qubit at various times during the evolution.

[0156] If the hybrid computer determines that no further measurements of the problem qubit should be performed during this evolution, the hybrid computer continues to 414. At 414, the quantum processor completes the evolution.

[0157] At 416, the information read from the flux detectors at 410 is processed to determine (at least approximately) information about the evolving behavior of the problem qubit. For example, an approximate freeze time for the problem qubit may be determined by observing an approximate time at which the expectation of the qubit's state stops changing between measurements (and / or, in some embodiments, stops changing by more than a threshold amount). As another example, avoided level crossings may be identified based on changes in state expectations between measurements.

[0158] At 418, a Δtuning offset ω is determined for the problem qubit based at least in part on the information determined at 416. For example, based on the approximate freeze times determined at 416, the evolution of the problem qubits may be advanced or retarded to approximately synchronize their freeze times (e.g., as described elsewhere herein). Alternatively or additionally, the tunneling rate Δ i may be modified to reduce the occurrence of level-crossing avoidance, for example, by slowing down the problem qubits. In some embodiments, the global annealing rate of the processor may be slowed to reduce the occurrence of level-crossing avoidance (e.g., problem qubits that have experienced a level-crossing avoidance are not frozen prior to the synchronous freezing time).

[0159] Acts 420 and 422 correspond generally to 212 and 214, respectively, of Figure 2. At 420, the problem qubit is tuned according to the Δ-tuning offset ω determined in 418. At 422, the hybrid computer performs a computation on the problem (possibly modified by the Δ-tuning operation of 420) and determines a solution.

[0160] Logical qubit strategy As noted elsewhere herein, the per-qubit annealing schedule Δ i At least some techniques for modifying Δt can correct the problem so that it is effectively calculated. For example, modifying the persistent current of a flux qubit can reduce the annealing schedule Δt of the qubit. i , but also generally modifying the flux of the qubits, thereby altering the problem so that it is solved.

[0161] In some embodiments, Δ tuning (e.g., at 160 and / or 212) may be performed by changing the encoding of the problem so that the problem is effectively solved (even though the problem may be represented differently by the processor). For flux qubit-based systems, such embodiments may involve tuning the persistent current (and / or other parameters that define the problem) and the tunneling rate Δ i It can be said that this provides orthogonal control with respect to the

[0162] In some embodiments, the persistent current and the tunneling velocity Δ i Orthogonal control with is provided by encoding the problem in an intermediate form that employs "logical" qubits. A logical qubit comprises multiple qubits (referred to herein as "inner" qubits) that are concatenated to effectively behave as a single qubit. A logical qubit represents a single variable of the problem. Techniques for forming logical qubits (e.g., as qubit chains) are described, for example, in U.S. Patent Nos. 7,984,012, 8,244,662, and 8,174,305.

[0163] Each internal qubit in a logical qubit has a tunneling rate Δ i and persistent current. The logical qubit itself has its own associated qubit parameters, such as effective tunneling rate Δ eff and the effective persistent current I eff The effective qubit parameters of a logical qubit may be determined by the qubit parameters of the internal qubits, the number of internal qubits in the logical qubit, and the coupling between the internal qubits, J i (herein referred to as the "internal coupling strength"), by the internal topology of the logical qubit (i.e., the topology of the internal qubits and the couplings between the internal qubits), and by the strength and arrangement of couplings between the internal qubits and qubits that are not within the logical qubit. Thus, these parameters of a logical qubit affect the desired (or "target") effective tunneling rate Δ eff may be selected to obtain

[0164] For example, there are N superconducting qubits and N-1 couplings J i The effective tunneling speed Δ of a logical qubit with a chain topology having eff (Each individual qubit is Δ i and the processor operates in a perturbation region with Δ≪J) is given by:

number

number

[0165] Logical qubits with different topologies can exhibit different behaviors. For example, the effective tunneling speed Δ eff can also (or alternatively) be achieved by increasing the number of internal couplers and / or the internal coupling J i Importantly, this can be suppressed by increasing the strength of the Δ eff However, the Δ i can be suppressed (i.e., tuned to advance annealing) without necessarily modifying the effective persistent current I eff (The persistent current I P Δ eff Provides control over

[0166] Thus, in some embodiments, Δ-tuning of a particular qubit is performed by modifying the representation of the problem on the processor such that the qubit is represented as a logical qubit. Then, a per-qubit annealing schedule Δ eff can be scaled proportionally to the number of qubits, the strength of the couplings, and the topology of the logical qubits.

[0167] In some embodiments, the qubits to be tuned may already be represented as logical qubits, and the Δ-tuning of the logical qubits may be determined by the per-qubit annealing schedule Δ eff This may involve modifying the number of qubits, the strength of the couplings, and / or the topology of the logical qubits to delay

[0168] In some embodiments, the topology of a logical qubit is determined based on its connectivity to external qubits (i.e., qubits outside the logical qubit). For example, if only a single internal qubit couples to one or more external qubits, then any coupling strength J i may be provided for the internal coupling (i.e., the coupler has its coupling strength J i A full range of coupling strengths J (usually from zero to some maximum coupling strength) may be used. However, if multiple internal qubits couple to the external qubit, then a problem-dependent minimum internal coupling strength J must be maintained to prevent the logical qubit from "corrupting" (i.e., to prevent the internal qubits from taking on different values). min In some embodiments, the topology of the logical qubits is selected such that only one internal qubit couples to one or more external qubits. This topology may be selected in preference to other topologies (where multiple internal qubits couple to one or more external qubits).

[0169] Depending on the problem and / or processor topology, the minimum internal coupling strength J of the logical qubits mincan be reduced by selecting a particular topology of the logical qubits. For example, a topology can be selected that reduces the number of internal qubits that couple to external qubits.

[0170] Auxiliary qubit strategy In one approach, results can be obtained using a C2 graph configured to form a 32-qubit 4-regular graph. The hybrid computer can submit a 1BOP (1 bit of precision) problem with zero local qubit bias to the hardware. The 1BOP problem is one with coupling strength J=±1. Some couplers can also be disabled by making them "unavailable". While such problems are generally easy, the hybrid computer can find 100 hard instances, for example, by first generating 17,000 instances with two ground states and over 400 first excited states, and then taking the 100 instances with the lowest hardware probability of success (usually less than 5%). Using the structure of C2 embedded in a larger graph, an auxiliary qubit can be attached to each of the 32 qubits.

[0171] The hybrid computer may apply an iterative method to realize this approach. First, the hybrid computer may derive a number of samples (e.g., 1,000 samples) by using hardware. Then, the hybrid computer may apply auxiliary constraints to qubits that are rarely floppy within the number of samples and that do not yet have an auxiliary qubit attached. The auxiliary constraint may be to point away from the current average spin (or magnetization). The hybrid computer may repeat this process, and the chance of success may change between iterations. Other variations of this approach may be used, such as adding a local bias to the qubits instead of an auxiliary constraint.

[0172] A method for eliminating perturbative crossings may be based on adding ancillary qubits to increase the degeneracy of the global minimum compared to the degeneracy of the competing minima (see, for example, U.S. Patent Application Publication No. 2015 / 0032994).

[0173] Advancing qubits during quantum annealing Another approach modifies the energy spectrum by using local CCJJ (Compound-Compound Josephson Junction) DACs (Digital-to-Analog Converters) to advance some of the qubits relative to others during quantum annealing. This may cause degradation of the persistent current balance across the C2 ensemble, but the primary primary effect may be to modify the transverse magnetic fields of some of the qubits during quantum annealing.

[0174] Example comparison results of degeneracy reduction Degeneracy reduction is related to area freezing. Area freezing is usually correlated to degeneracy reduction, although the relationship is generally not one-to-one.

[0175] 6-10 are plots illustrating comparative results of exemplary implementations of degeneracy mitigation in a quantum processor according to the present systems, devices, articles and methods. The methodology used to generate FIGS. 6-10 was as follows: 1. Program a difficult C2 problem instance. 2. Pull 1000 samples from the hardware. 3. For a given sample, for each qubit, calculate the net bias from its neighbors as follows:

number

[0176] 6-10 were generated using the method described above (acts 1-7) and a particular variation of that method described below with reference to FIGS. 6-10.

[0177] Figure 6 is a histogram of the probability of finding the ground state for selected hard problem instances. The problems were run using a variation of the method described above with 10 samples in act 2 instead of 1000 samples. The problems were run without local CCJJ DAC tuning. This is the baseline case (i.e., no shrinkage mitigation). The median is about 0.04.

[0178] Figure 7 shows the effect of degeneracy reduction. Even with only 10 samples, the chance of finding the ground state is significantly increased compared to the baseline case as a result of degeneracy reduction. The median value in Figure 7 is about 0.49.

[0179] Figure 8 shows a histogram of the probability of finding the ground state for selected hard problem instances. The problem was run using the method described above with 1000 samples. Figure 8 shows the effect of using more samples in reducing degeneracy. The chance of finding the ground state is increased compared to the 10 sample case in Figure 7. The median value in Figure 8 is about 0.66.

[0180] Figure 9 shows a histogram of the probability of finding the ground state for selected hard problem instances. i A variation of the above method was performed that advances five random qubits rather than the qubit with the maximum prevalence of =0. The results are similar to the baseline case, indicating that random degeneracy mitigation can have little or no positive impact on the chance of finding the ground state. The results reinforce the importance of selecting qubits to advance according to criteria such as those described in the above method. The median value in Figure 9 is about 0.03.

[0181] Figure 10 is a histogram of the probability of finding the ground state for selected hard problem instances. The problems were run using the method described above but by retarding the qubits by making an inverse CCJJ DAC adjustment instead of advancing the qubits. The results of this example show the adverse effect on the chance of finding the ground state compared to the baseline case with no degeneracy mitigation. The results show the importance of advancing the qubits rather than retarding them. The median value in Figure 10 is approximately 0.001.

[0182] In some embodiments, another suitable metric may be used to determine floppyness, such as a metric that may be used with a non-zero bias value. For example, instead of summing the bias values, the method may determine for a given qubit whether the energy of a given state changes when the state of the qubit is flipped. If the method determines that the energy of the given state does not change, the qubit may be counted as a floppy qubit.

[0183] The present technique improves performance by algorithmically (and iteratively) modifying the annealing trajectory. Although the use of a set of initial samples to guide the modification to the annealing trajectory has been theoretically proposed, the present technique is believed to be the first practical embodiment. In addition, the present system and method can be implemented to improve sampling diversity (e.g., diversity of ground state and / or excited state samples).

[0184] A benefit of this technique is that the hardware sample probability distribution can be made to be closer to the Boltzmann distribution (which may be desirable for sampling).

[0185] The present technique is not limited to the floppyness metric: other metrics could be used, for example to identify one or more "frozen" regions of a qubit (regions where the qubit is locked into the same configuration over many samples) and then slow the regions down during quantum annealing.

[0186] Intermediate annealing pause It may be beneficial to implement breaks in the annealing schedule.

[0187] FIG. 11A shows a chart 1100a illustrating an example annealing scenario with no pause in the annealing schedule. The horizontal axis 1110 corresponds to time. The vertical axis 1112 corresponds to the persistent current i P The tunneling speed of the quantum bit, Δ i can be tuned according to the qubit's associated Δtuning offset ω. As discussed elsewhere herein, Δ i can be tuned by modifying the persistent current of the qubit. Line 1115 shows the variation of the persistent current over time for the duration of the anneal. In the example shown, the persistent current varies linearly with time.

[0188] FIG. 11B shows a chart 1100b illustrating an example annealing scenario with a pause in the annealing schedule. The horizontal axis 1120 corresponds to time. The vertical axis 1122 corresponds to the persistent current i P Corresponds to.

[0189] Lines 1125, 1130, 1135 show the time variation of the persistent current over the duration of the anneal. Line 1125 shows the increase in persistent current until the onset of pause. Line 1130 shows the onset of pause. The onset of pause is the s P For example, if the pause starts in the middle of the anneal, it starts at s P =0.5.s P The pause in begins at time t 1 The pause corresponds to t P After the pause duration, time t 2 Line 1135 shows the increase in persistent current from the end of the dwell to the end of the anneal.

[0190] In some embodiments, the annealing schedule has a single pause, while in other embodiments, the annealing schedule has two or more pauses.

[0191] In some embodiments, the user may select the start of a pause via a user interface. P and the duration of the pause t P The user interface may be a graphic user interface, a remote interface, and / or an application programming interface. For example, to implement a 100 μs pause in the middle of an anneal, the user may specify P =0.5 and t P = 100 μs.

[0192] During testing, applicants have observed improvements in quantum annealing performance due to implementing pauses in the annealing schedule. For example, for a quantum processor containing 16 qubits, an approximately 30-fold improvement in performance can be achieved in a 10 μs annealing schedule by incorporating a 100 μs pause at a suitable stage of the anneal during a total annealing time of 110 μs. The same improvement without a pause would require an annealing time of approximately 1000 μs.

[0193] Fast and / or slow annealing The annealing time may be adjusted. In some embodiments of the systems and methods described herein, a user may specify a desired annealing time. The annealing time may be provided via a user interface (e.g., an application programming interface) (API). The annealing time may be faster or slower than a pre-adjusted annealing time.

[0194] Intermediate Annealing Lamp In some embodiments of the systems and methods described herein, the annealing schedule may include intermediate annealing ramps. A standard anneal (e.g., a linear increase in persistent current) may be interrupted at some point during the evolution by a sudden acceleration of the anneal by a steep increase in persistent current.

[0195] 11C shows a chart 1100c illustrating an example annealing scenario with an intermediate annealing ramp 1150 in the annealing schedule. The horizontal axis 1140 corresponds to time. The vertical axis 1142 corresponds to the persistent current i P The annealing schedule begins with a standard anneal 1145 followed by an intermediate anneal ramp 1150.

[0196] In some embodiments, parameters defining the intermediate annealing lamps may be provided via a user interface (eg, an API).

[0197] Annealing schedule operation In some embodiments of the systems and methods described herein, the annealing schedule may include any suitable combination of one or more intermediate annealing pauses and / or one or more intermediate annealing ramps.

[0198] FIG. 11D shows a chart 1100d illustrating an example annealing scenario having an annealing schedule operation that includes intermediate annealing pauses and intermediate annealing ramps within the annealing schedule. The horizontal axis 1160 corresponds to time. The vertical axis 1162 corresponds to the persistent current i P Corresponds to.

[0199] The annealing schedule begins with a standard anneal 1165, followed by a first intermediate annealing ramp 1170. The annealing schedule proceeds with a first intermediate annealing pause 1175 and then a second intermediate annealing ramp 1180, this time in the opposite direction (sudden drop in persistent current). Ramp 1180 is followed by a second intermediate annealing pause 1185 and a third ramp 1190.

[0200] In some embodiments, the annealing schedule operation may be provided via a user interface (e.g., an API). Parameters defining the annealing schedule operation may be, for example, the start and duration of each segment of the schedule. The start of the first intermediate annealing ramp 1170 may be defined by a measure of evolutionary progress. The timing of other ramps and pauses may be defined, for example, by duration.

[0201] 11A to 11D, the persistent current i P As described elsewhere herein, it is possible in at least some circumstances to vary the tunneling rate of one or more qubits orthogonally to the variations in the persistent current. Thus, it will be understood that the intermediate annealing pauses, intermediate annealing ramps, and fast annealing operations of the annealing schedules described herein may be achieved by any suitable technique (or combination of techniques) for varying the tunneling rate.

[0202] Generalized Annealing Schedules Figure 11D shows a chart 1100d illustrating an exemplary annealing scenario having an annealing schedule operation that includes intermediate annealing pauses and intermediate annealing ramps within the annealing schedule. Although Figure 11D shows an exemplary annealing schedule, one of ordinary skill in the art will recognize that other annealing schedules may be used to achieve the desired evolution.

[0203] The annealing schedule may be expressed using a single-valued function of suitable time. The function may be linear or non-linear. The function may be injective or non-injective. The function may be expressed as a series of segments, each having the same or different single-valued functions of suitable time.

[0204] Piecewise Linear Annealing Schedules A piecewise linear annealing schedule is one example of an annealing schedule. A piecewise linear annealing schedule includes one or more segments, each of which is a linear function of time. FIG. 11D is an example of a piecewise linear annealing schedule. In the example of FIG. 11D, the persistent current i p varies in piecewise linear segments, each of which is a linear function of time or linear as a function of progress through the evolution s. For example, the first linear segment is a ramp 1165. The schedule has five other linear segments 1170, 1175, 1180, 1185, 1190, respectively. Those skilled in the art will recognize that any suitable sequence of linear segments may be combined to generate the annealing schedule.

[0205] Annealing schedule manipulation using programmable parameters As mentioned above, quantum processors can be designed to perform quantum annealing and / or adiabatic quantum computation. An evolution Hamiltonian proportional to the sum of a first term proportional to the problem Hamiltonian and a second term proportional to the delocalized Hamiltonian can be constructed as follows: H E ∝A(t)H P +B(t)H D

[0206] In some embodiments, a time-varying envelope function may be placed on the problem Hamiltonian. A suitable delocalized Hamiltonian is given by:

number

number

number

[0207] The general problem Hamiltonian includes a first component proportional to the diagonal single-qubit terms and a second component proportional to the diagonal multi-qubit terms, and may be of the form:

number

number

[0208] During operation of the quantum processor, the interface couples a flux signal into each compound Josephson junction of the qubit, thereby adjusting the tunable term (Δ i terms) into the system Hamiltonian. This coupling is x terms, and these flux signals are examples of "delocalized signals".

[0209] Similarly, the interface couples a flux signal into the qubit loop of each of the qubits, thereby i can be used to realize terms in the system Hamiltonian. This coupling is done by the diagonal σ z In addition, the interface couples the flux signal into a coupler, which provides the J ij can be used to realize terms in the system Hamiltonian. This coupling is

number

[0210] In one approach to quantum annealing, the system adjusts a programmable parameter h to advance or retard qubits, logical qubits, chains and / or regions of qubits. i , J ij For example, the system may provide delays on programmable parameters separately or in combination with each other and in combination with the transverse magnetic field.

[0211] At the end of the annealing, when the transverse magnetic field becomes zero, the programmable parameter h i , J ij achieve their final values. In the approach described here, the envelope functions A(t), B(t) are the Hamiltonian and its associated parameter Δ i , h i , J ij The system can be flexible with respect to annealing schedules (e.g., h i , J ij is fixed, and Δ i can be evolved). Other schemes may produce similar results. In some cases, one approach to manipulating the annealing schedule may produce better results than another approach.

[0212] In one exemplary embodiment, the envelope function A(t) is fixed for each qubit, and the bias value h i is fixed, and bond J ij can be set to zero, and the envelope function B(t) is J to perform annealing. ij This may be changed at any time. i , B i , B ij The per-qubit value of each qubit q i These can be used to advance or retard the evolution of a gene.

[0213] In another example, A i , B i can be the same for all qubits, and B ij is the bond J at the center of the graph. ij and bond J, which is farther from the center. ijA related technique is described elsewhere in this application and is called annealing schedule operations based on the position of the qubits in the graph. More generally, B ij is the number of bonds J starting from a selected position in the graph or processor topology. ij may be used to gradually advance or retard.

[0214] In another example, B i Term and B ij Both terms can be manipulated to achieve the same effect.

[0215] In another exemplary implementation of quantum annealing, the system anneals a set of bonds J relative to other bonds in the graph. ij may advance or retard clusters, regions and / or chains of qubits by advancing or retarding.

[0216] FIG. 11E shows a chart 1100e illustrating an exemplary annealing scenario in which the local bias h of a qubit is altered during evolution.

[0217] Horizontal axis 1191 corresponds to time. Vertical axis 1192 corresponds to qubit bias h. The value of qubit bias h over time is represented by line 1193.

[0218] FIG. 11F shows a chart illustrating an exemplary annealing scenario in which the coupling strength J of a coupling device between a pair of qubits is altered during evolution.

[0219] Horizontal axis 1194 corresponds to time. Vertical axis 1195 corresponds to coupling strength J. The value of coupling strength J over time is represented by line 1196.

[0220] Annealing schedule operation of logical qubits In some embodiments of the systems and methods described herein, an annealing schedule for a logical qubit, which includes multiple hardware qubits, is determined based on characteristics of the logical qubit. The logical qubit has an effective tunneling rate (Δ eff ) has been observed elsewhere herein. As explained elsewhere, one strategy is to eff or manipulating these properties to obtain an approximation thereof.

[0221] In some embodiments, the Δ eff is manipulated based on one or more of the properties of the logical qubits (which may or may not involve modifying the properties themselves). For example, in embodiments having logical qubits with chain topologies (described elsewhere herein), chains that are significantly shorter than other chains will have a smaller Δ eff A potentially useful heuristic for the dynamics of logical qubits is the length of the chain (i.e., the number of constituent qubits), since it is likely that eff can be modified based on the length of the chain (with or without taking into account any other properties of the chain).

[0222] As explained elsewhere herein, Δ eff The modification of can be accomplished through one or more strategies. For example, Δ eff can be increased by lengthening the chain (thus delaying it during annealing) or can be decreased by shortening the chain (thus advancing it during annealing). Alternatively or in addition, the Δ eff may be modified by modifying the flux biases and / or coupling strengths of its constituent qubits and / or couplers, by modifying DAC parameters (such as a CCJJ DAC), or by any other available strategy.

[0223] In some embodiments, for problems that are embedded using a representation that includes multiple variable length strings, the Δ eff The values ​​can be synchronized by modifying their annealing schedules as described herein. In some embodiments, the Δ eff Harmony occurs by synchronizing the annealing schedules. Through experimentation, the inventors have found that this modified strategy can produce impressive results in some circumstances. For example, a 100-fold increase in solution speed has been observed in several instances of factoring 2n-bit half-primes into distinct n-bit primes (compared to attempting to solve the same problems without modifying the annealing schedule).

[0224] Example of logical qubit annealing schedule operation An example of such an experiment is shown as method 1900 in FIG. 19. At 1905, a factorization problem (e.g., find a solution (a, b) for a×b=35) is generated. At 1910, an embedding for a multiplication circuit that encodes the problem is generated (e.g., as described in U.S. Pat. No. 8,700,689). Optionally, at 1915, one or more scaling coefficients are selected. For example, multiple scaling coefficients in the range [0,1] may be selected (such as a set of coefficients {0,0.1,0.2,...1}). More or fewer scaling coefficients may be selected.

[0225] At 1920, an annealing schedule offset strategy is generated based on one or more scaling factors. Any suitable offset may be selected. Strands of different lengths may be assigned different offsets to synchronize their dynamics at a particular energy scale. In at least the exemplary experiment, the CCJJ offset was selected based on the following formula:

number

number

[0226] At 1925, the quantum processor executes the problem and generates a sample solution. 1925 may be repeated with the same and / or different scaling factors (e.g., each scaling factor may have multiple corresponding runs). Optionally, method 1900 may return to 1915 to generate additional scaling factors. Alternatively (or in addition), method 1900 may generate multiple scaling factors at 1915 and not necessarily return to 1915 from 1925.

[0227] Optionally, at 1930, the results generated at 1925 may be compared, for example, by applying a performance metric and ranking the scaling factors with respect to that metric. For example, scaling factors with a high success rate and / or short time to a solution may be ranked higher than scaling factors with a relatively low success rate and / or long time to a solution. One or more of the highest-ranked scaling factors may be stored and later recalled for use with similar problems.

[0228] It is understood that method 1900 may be performed with other anneal scheduling strategies described herein and may utilize any available annealing offset technique (manipulation of logical qubit characteristics, manipulation of programmable parameters, etc.).

[0229] Annealing schedule operations based on the position of the qubits in the graph In some embodiments of the systems and methods described herein, an annealing schedule for a qubit and / or set of qubits may be determined based on the position of the qubit and / or set of qubits relative to one or more other qubits. For example, one or more qubits located on or near the outer edge of a graph of qubits may be advanced or delayed relative to other qubits in the graph. The graph may be, for example, a working graph of hardware qubits, a virtual graph that mimics a particular working graph of hardware qubits (e.g., as described in U.S. Provisional Patent Application No. 62 / 375,785), and / or an embedded graph of logical qubits, where each logical qubit corresponds to one or more hardware qubits.

[0230] For example, the annealing schedule may be modified according to a gradient defined on the graph. Figure 18 shows an example gradient 1800 defined on a graph 1810 including Chimera structured groups 1812 of qubits 1814a, 1814b, etc. (collectively and individually "qubits 1814"). Due to the large number of groups 1812 and qubits 1814 in graph 1800, most of their labels are omitted for clarity of explanation. It is understood that the systems and methods described herein are not limited to Chimera structured graphs, and that graph 1810 is example and non-limiting.

[0231] Gradient 1800 associates a value with each qubit 1814 (visually depicted by shading intensity corresponding to legend 1820). The qubits 1814 in the first region 1802 are advanced upon annealing (e.g., by applying a Δ offset as described elsewhere herein), the qubits 1814 in the third region 1806 are retarded upon annealing (e.g., by applying a Δ offset having the opposite polarity of the Δ offset applied in the first region), and the qubits 1814 in the second region 1804 are not advanced or retarded, and / or are advanced or retarded by a small amount compared to the qubits 1814 in the first and third regions 1802, 1806. In some embodiments, gradient 1800 only advances (or retards) qubits 1814, but different qubits 1814 may be advanced (or retarded) by different amounts and / or some qubits 1814 may not be advanced (or retarded).

[0232] The inventors have observed that for at least some problems executable on at least some quantum processors, qubits 1814 near the outer edge tend to freeze earlier than other qubits 1814 located relatively far from the edge of the graph. In some embodiments, a gradient is defined that corresponds to an annealing schedule modification that retards qubits 1814 near the outer edge of graph 1810 and advances qubits 1814 far from the outer edge of graph 1810. Gradient 1800 is a non-limiting example of such a gradient, but it is understood that other gradients that have this behavior can be defined (e.g., gradients in which each qubit 1814 has an annealing offset determined by its distance from the outer edge (larger distances correspond to faster anneal times)).

[0233] Gradient 1800 is an exemplary radial gradient. Each qubit 1814 is associated with an offset value that falls in proportion to the distance of the qubit 1814 from point 1822. Other gradients are possible. For example, the gradient may be a linear gradient in which each qubit 1814 is associated with an offset value based on the distance from a line defined across graph 1810 (e.g., based on the distance between qubit 1814 and one edge (such as edge 1822) of graph 1810). In some embodiments, the gradient spans the entire graph 1810. In alternative or additional embodiments, the gradient is defined over a portion of graph 1810.

[0234] One or more gradients may be defined on the graph 1810. When multiple gradients are defined, the multiple gradients may be disjoint and / or overlapping. A qubit 1814 for which multiple gradients are defined may have an annealing schedule defined by a combination of associated values ​​of the overlapping gradients of the qubit 1814. For example, the annealing schedule of the qubit 1814 may be based on a sum, product, or other function of the overlapping gradient associated values.

[0235] Annealing schedule operations within logical qubits In some embodiments of the systems and methods described herein, the annealing schedule of a logical qubit may be manipulated such that the qubits that make up the logical qubit have the same or different annealing schedule offsets. For example, all qubits within a logical qubit may have the same annealing offsets, qubits with external coupling may be assigned a different offset (and / or may be assigned an offset based on different criteria) than qubits with only internal coupling, and / or qubits with different positions in the graph may be assigned different offsets (and / or may be assigned an offset based on different criteria). This annealing schedule manipulation may be in addition to (or alternative to) other annealing schedule manipulation strategies described elsewhere herein. Logical qubit-level schedules are sometimes referred to as "sub-schedules" to distinguish them from wide (e.g., processor-wide) annealing schedules.

[0236] For example, in some embodiments where the broad annealing schedule is directional, logical qubits may follow a directional annealing sub-schedule that modifies the broad annealing schedule. For example, given an annealing schedule based on a linear gradient across logical qubits in an embedded graph (e.g., such that a qubit anneals earlier compared to other qubits when it is along an axis across the embedded graph), a corresponding gradient may be determined within the logical qubit. Constituent qubits (which may be hardware qubits) of a logical qubit may anneal earlier compared to other qubits within the same logical qubit based on the gradient. The logical qubit-level gradient may have a different slope than the gradient of the broader annealing schedule (e.g., qubits within a logical qubit may anneal relatively more closely in time than similarly adjacent qubits elsewhere in the graph that are not part of the same logical qubit).

[0237] Selective Annealing In some embodiments of the systems and methods described herein, a subset of qubits is annealed while another subset of qubits is not annealed. The subset of qubits may include hardware qubits, logical qubits, and / or any other qubit representation. For example, the subset of qubits may be selected for annealing, an annealing schedule may be assigned to those qubits, and the remaining qubits may be clamped or otherwise prevented from changing their dynamical properties (e.g., by programming their corresponding CCJJ DAC biases). Such prevention is referred to herein as "pausing" the remaining qubits. The selected qubits may then be annealed according to their annealing schedule. The remaining qubits may then be unpaused (i.e., allowed to resume annealing).

[0238] For example, a subset of qubits may be selected for reverse annealing at some point in the evolution. The remaining qubits may be paused and the subset may be reverse annealed (e.g., as described in U.S. Patent Application Publication No. 2015 / 363708). The remaining qubits may then be allowed to anneal once the qubits return to the point in the anneal they occupied before the reverse anneal occurred, while the remaining qubits remain paused and before the selected qubits forward anneal again. Alternatively or additionally, some or all of the remaining qubits may be allowed to anneal after the reverse anneal is finished and before the selected qubits forward anneal again.

[0239] Intentional De-Tuning of Annealing Schedules Another embodiment of the disclosed system and method for advancing (or retarding) qubits during annealing identifies constraints and propagates them back throughout the logic circuit, e.g., from the circuit output toward the circuit input. For example, qubits closer to the circuit output may be frozen early in the evolution. This may be accomplished by starting to reduce the tunneling amplitude of a subset of qubits earlier than another subset of qubits, or by reducing the tunneling amplitude at a faster rate. For example, a time-dependent gradient of the tunneling amplitude may be established throughout the logic circuit. The gradient of the tunneling amplitude may correspond to an annealing schedule.

[0240] The modified annealing schedule may be generated by intentionally detuning the tunneling amplitudes and problem Hamiltonian energy measures of a selected subset of qubits, in one embodiment, as described elsewhere in this disclosure, detuning is accomplished by adjusting qubit parameters via DACs in the quantum processor, such as CCJJ DACs.

[0241] Controllably simulating noise in annealing schedules Analog processors tend to be vulnerable to noise, and considerable effort is typically made in existing systems to reduce the amount and impact of such noise. For example, at least some analog processors are operated in cryogenic environments (e.g., below 1° K) to reduce thermal noise. However, even in such environments, noise can get in. For example, communication lines connecting supercooled analog processors may also connect to devices in much warmer (e.g., room temperature) environments, thereby introducing potential paths for noise to affect the analog processor.

[0242] However, in at least some circumstances, further noise reduction can negatively impact some performance metrics of the analog processor. For example, in at least some cases, the inventors have observed that operating an analog processor even at subnormal temperatures results in sample diversity and / or the optimization success rate of some problems is reduced compared to the same metrics when the same problems are run at higher temperatures (and thus with more noise).

[0243] One potential effect of noise is that it can cause small and random (and / or quasi-random) variations in the annealing schedule. For example, in at least some quantum processors, noise on the annealing control lines can cause small, short-term increases and / or decreases in the persistent current, resulting in some jitter in the annealing schedule of the qubits.

[0244] In some embodiments, noise may be controllably simulated by a digital computer by applying short ramps and pauses to an annealing schedule run by an analog computer relative to the problem. FIG. 22 shows a chart 2200 illustrating an exemplary annealing scenario in which noise is controllably added to the anneal. The horizontal axis 2202 corresponds to time. The vertical axis 2204 corresponds to the tunneling rate Δ. As explained elsewhere herein, the tunneling rate can vary depending on one or more of several techniques (e.g., persistent current i P may be judged or influenced in accordance with (e.g., changing

[0245] Line 2210 corresponds to an example input annealing schedule. The input annealing schedule may be, for example, an ideal noise-free annealing schedule for the qubits in the problem. As another example, the input annealing schedule may already include some noise (either intentionally or unintentionally). In the illustrated example, line 2210 is shown as a dashed line that matches a portion 2222 of line 2220 (and is therefore partially obscured).

[0246] Line 2220 corresponds to an exemplary output annealing schedule. The output annealing schedule is generated by a digital computer based on the input annealing schedule and a controllable noise addition algorithm. For example, the output annealing schedule corresponding to line 2220 may be determined by applying a dithering technique to the input annealing schedule 2210.

[0247] In some embodiments, the output annealing schedule is determined by a digital computer by modifying the input annealing schedule by adding intermediate annealing ramps and pauses. For example, line 2220 includes portion 2222 that coincides with line 2210, thus showing the period of annealing when the input annealing schedule and the output annealing schedule are the same. At portion 2224 of line 2220, a ramp is added, causing line 2220 to deviate from line 2210 (in this case the deviation corresponds to an advance of the output annealing schedule relative to the input annealing schedule). At portion 2226 of line 2220, a pause is added, causing line 2220 to reduce its deviation from line 2210.

[0248] In the illustrated example of Figure 22, the pause in portion 2226 is long enough to cause line 2220 to intersect line 2210 at intersection 2230. The pause may end at intersection 2230, causing line 2220 to realign with line 2210 (similar to portion 2222), or the pause may continue, causing line 2220 to deviate from line 2210 again (e.g., as shown in Figure 22). A subsequent ramp may cause line 2220 to reintersect line 2210, for example, as shown by portion 2228 of line 2220. In some embodiments, pauses or ramps may be added that reduce the deviation from the input annealing schedule but that end before the input and output annealing schedules intersect.

[0249] Other modifications are possible. For example, the output annealing schedule may include a portion where reverse annealing occurs. As another example, the output annealing schedule may include a non-piecewise linear modification. For example, the output annealing schedule may be based on the product of the input annealing schedule with a low amplitude sinusoid and / or some other continuous function. As another example, fast and / or slow anneals may be provided instead of (or in addition to) ramps and / or pauses, respectively. For example, the output annealing schedule may anneal slowly during a period corresponding to some or all of portion 2226 (which would be graphically shown as portion 2226 having a positive slope less than the slope of line 2210). Thus, lines 2210 and 2220 would intersect at a point in time later than intersection point 2230 unless further modifications were added to hasten the intersection of lines 2210 and 2220.

[0250] In some embodiments, the modifications to the input annealing schedule (such as pauses and ramps) are applied randomly and / or pseudo-randomly by a digital computer. In some embodiments, the pauses and ramps (and / or slow and fast anneals) are applied in alternating pairs (e.g., first a pause, then a ramp, followed by either a pause-ramp pair or a ramp-pause pair). In some embodiments, the duration and amplitude of the modifications are determined randomly or pseudo-randomly.

[0251] In some embodiments, the modifications are applied to the output annealing schedule by the digital computer according to one or more constraints. For example, one or both of the duration and amplitude of the modifications may be constrained such that the modifications and / or deviations of the output annealing schedule from the input annealing schedule do not exceed a threshold. As an example, each 0.1 millisecond period of annealing may randomly (and / or pseudo-randomly) apply a modification, thereby constraining each modification to 0.1 milliseconds. Optionally, some periods may not have any modifications.

[0252] As another example, the duration and / or amplitude of one or more modifications may be randomly or pseudo-randomly selected by a digital computer subject to the constraint that "each modification must not cause the output annealing schedule to deviate from the input annealing schedule by more than a threshold amount." For example, the amplitude of the output annealing schedule may be constrained to deviate from the input annealing schedule by more than an amount proportional to the amplitude of the input annealing schedule at the same point in time of the input annealing schedule (e.g., within 1%, 5%, etc.). Alternatively or additionally, the amplitude of the output annealing schedule may be constrained to deviate from the input annealing schedule by more than a fixed amount (e.g., by an amount corresponding to 0.1%, 0.5%, 1%, etc. of the maximum persistent current).

[0253] The correction pseudo-noise may be applied on a per-qubit and / or multi-qubit basis. For example, an initial set of corrections may be determined and applied uniformly to the annealing schedule of all qubits on an analog processor (and / or all qubits in question). Another set of corrections may be determined and applied to each qubit individually. An intermediate set of corrections may be determined and applied to groups of qubits (e.g., by grouping qubits that together receive an annealing control signal on a shared annealing line and applying the intermediate set of corrections uniformly to the group).

[0254] Reducing sampling bias The techniques of the present disclosure for manipulating annealing schedules are not limited to optimization problems. For example, the techniques of the present disclosure may also be applied to improve the performance of analog processors (and / or hybrid computers) during sampling operations. As will be familiar to those skilled in the art, analog processors may be used to draw samples from a distribution defined by an input problem.

[0255] Particular problems may be vulnerable to sampling biases in which certain groups of solutions are sampled more frequently than others. For example, problems with highly degenerate ground states and / or initially excited states may exhibit strong sampling biases, resulting in "valleys" with high degeneracy being sampled more frequently than others (perhaps even to the extent that samples from highly degenerate valleys tend to dominate samples from other valleys). A "valley" is a group of one or more solutions (or samples) that occupy a low-energy region of the energy landscape defined by the problem's Hamiltonian between which an analog processor (and / or hybrid computer) may transition during annealing without a change in energy. That is, a valley is a low-energy, isoenergetic cluster of solutions (or samples).

[0256] In some embodiments of the disclosed systems and methods, sampling bias is mitigated by modifying the annealing schedule in question, thereby allowing samples of other valleys to be taken with greater frequency.

[0257] A flowchart illustrating an example method 2100 for mitigating sampling bias in an analog processor is shown in Figure 21. At 2105, a problem is received by a processor (e.g., a digital processor). At 2110, N samples are collected from the analog processor (e.g., as described above with respect to Figure 1).

[0258] At 2115, the N samples are analyzed and one or more valleys are identified. Valleys may be identified by a digital processor, for example, by grouping samples into clusters based on equal-energy qubit flips. For example, two samples may occupy the same valley if there is a sequence of qubit flips that can be applied to one sample to obtain the other sample without any flips causing a change in energy (or causing a change beyond a threshold in energy). Each qubit flip may include flipping one or more qubits. In some embodiments, only samples related to each other by no more than a determined (e.g., predetermined) number of equal-energy qubit flips are grouped as identified valleys. Such embodiments may be said to use equal-energy Hamming distance as a metric of valley membership.

[0259] In some embodiments, all valleys are identified by the digital processor at 2115. In some embodiments, only a subset of the valleys are identified. For example, valleys with more than a certain number of degenerate states, valleys for which at least a threshold number of samples have been collected, the subset including the valleys with the largest integer v, valleys with less than a minimum energy, and / or other valleys may be identified.

[0260] At 2120, the valley v i is selected from one or more valleys by a digital processor. For example, the most probable valley (i.e., the valley from which the greatest number of samples were drawn) may be selected.

[0261] At 2125, quantum bit q i is selected from the selected valley by the digital processor. i The degenerate metric μ i The degeneracy metric is determined for the qubit q i gives a measure of the contribution of the imay include a normalized floppyness metric as described with respect to act 130 of method 100 (see FIG. 1). For example, the normalized floppyness metric may be determined according to the following formula: μ i =n i / S where n i is the quantum bit q i Gaya V i is the number of times that the S samples were floppy.

[0262] Acts 2125, 2130 may be performed by a digital processor for a plurality of qubits (eg, all available qubits, all qubits in a region of interest, etc.), thereby generating a plurality of degeneracy metrics corresponding to the plurality of qubits.

[0263] At 2135, an annealing schedule is determined by the digital processor for each qubit based on its corresponding degeneracy metric. In some embodiments, the annealing schedule is determined based on the degeneracy metric μ i Based on the qubit q i The annealing offset ω determined for each i In some embodiments, the offset ω i is the degenerate metric μ i For example, for each quantum bit q i offset ω i =μ i A may be assigned, where A is a constant annealing offset factor (which, in at least some embodiments, is the maximum offset that may be assigned during one iteration of method 2100). The annealing factor A may represent either an advance or a retardation of the qubit during annealing, and thus may be positive or negative, in at least some embodiments.

[0264] As explained elsewhere herein, the term "qubit" may refer to a single quantum bit or a region of quantum bits (a quantum bit may be a hardware device, a logical quantum bit, etc.). i If x corresponds to a region of qubits, then the annealing offset can be applied to each qubit in the same region. For example, i Each qubit in has the same offset ω i Alternatively or additionally to applying an annealing schedule to the qubits in the region, as described elsewhere herein, may be used.

[0265] In some embodiments, the corresponding degeneracy metric μ greater than a threshold T (and / or equal to or greater than T) i A qubit q i Only with non-zero annealing offset ω i In some embodiments, Δ i is each such quantum bit q i is the same for

[0266] In some embodiments, the valley v i Each qubit in i In the annealing schedule, q is advanced to the beginning of the anneal or delayed to the end of the anneal. For example, the determined annealing schedule may i For example, qubit q may terminate annealing before at least some other qubits have begun their annealing and / or begin annealing after at least some other qubits have completed their annealing. i can be advanced (delayed) before (after) every other qubit. i may be advanced (delayed) ahead of (behind) only other qubits that have not already been advanced or delayed by method 2100. In some embodiments, the selected valley v i One or more other qubits that are not within the selected valley v before the other qubits begin their annealing.i is delayed to allow the qubit to complete its anneal.

[0267] Optionally, act 2135 comprises generating, by a digital processor, a quantum bit, q i For example, act 2135 may include determining a plurality of annealing schedules for each quantum bit q i one or more annealing schedules that advance the qubit q i Additionally or alternatively, act 2135 may include generating a plurality of annealing schedules by first determining one or more annealing schedules and then applying a set of scaling factors to each of the one or more annealing schedules. For example, the annealing schedules may be determined as described above, and then the products of the annealing schedules and each of the scaling factors {α i ,α 2 ,...,α n}(eg{0.1,0.2,...,1}). For example, act 2135 may determine qubit q i Annealing offset ω i and furthermore, generating the qubit q i multiple scaled annealing offsets, {α i ω i ,α 2 ω i ,...,α n ω i}.

[0268] Act 2135 may include selecting one of the multiple determined annealing schedules by the digital processor based on one or more selection criteria, such as an objective function and / or one or more constraints. For example, the annealing schedule may be selected based on avoiding conflicts, minimizing floppiness, and / or some other criteria.

[0269] At 2140, an additional M samples are collected by running the problem with an analog processor having the determined annealing schedule of act 2135. Optionally, method 2100 may be repeated by returning to act 2115 and performing acts 2115-2135 based on the M samples, thereby refining the determined annealing schedule. In such an embodiment, act 2120 selects valleys v that were not selected during a previous iteration of method 2100. i In some embodiments, the same valley v selected in the previous iteration may be selected. i may be used. The iterations may be terminated upon satisfying a termination criterion. For example, method 2100 may be repeated until the results converge, until a threshold number of iterations have been completed, until all valleys have been iterated through, until no eligible valleys remain (where "eligible valley" refers to a valley that may be selected in act 2120), and / or until some other criterion is met.

[0270] At 2145, the one or more samples generated by method 2100 are returned by at least one of a digital processor and an analog processor. In some embodiments, the M samples collected in the last iteration of method 2100 are returned. In some embodiments, samples collected in multiple iterations are returned. For example, all samples collected by method 2100 may be returned. In some embodiments, a set of annealing schedules determined in one iteration of act 2135 is selected based on an optimality metric (e.g., an objective function of an optimization algorithm), and the M samples generated according to these annealing schedules are returned.

[0271] Detecting quantum fluctuations using a probe qubit To determine an improved or optimized annealing schedule, it may be beneficial to measure the quantum fluctuations at different times during the annealing. Quantum fluctuations tend to be high or maximal near the quantum phase transition, and it may be beneficial to slow down the annealing at the point where quantum fluctuations become high.

[0272] The systems and methods of the present disclosure include techniques in which quantum fluctuations are measured directly via hardware and the results are used to improve or optimize the annealing schedule. In one embodiment, determining the improved or optimized annealing schedule is based on Macroscopic Resonant Tunneling (MRT) noise measurements of quantum fluctuations.

[0273] In one embodiment, the one or more computational problems of interest are encoded in a first subset of qubits available in the quantum processor. The qubits in the first subset are known as computation qubits. A second subset of qubits (disjoint with the qubits in the first subset) includes probe qubits operable to make MRT noise measurements of quantum fluctuations during annealing. The probe qubits may be weakly coupled to the computation qubits, and signals from the computation qubits detected by the probe qubits may be noise-like.

[0274] The width of the MRT peak measurable by each of the probe qubits may depend on the integral of the noise spectrum and may vary according to the quantum fluctuations arising from the computation qubits. As discussed above, quantum fluctuations may increase near a phase transition point or near a many-body localization point. Increased quantum fluctuations of the computation qubit coupled to the probe qubit may broaden the MRT peak measurable by the probe qubit.

[0275] The annealing schedule can be adjusted based at least in part on the width of the MRT peak.

[0276] FIG. 12 is a flow chart illustrating an exemplary method 1200 of operation of a hybrid computer to adjust a quantum annealing schedule. The method 1200 illustrated by FIG. 12 includes a number of acts. One or more of these acts may be performed by (or through) one or more circuits, such as, for example, one or more processors (e.g., digital processors), analog processors such as quantum processors, or a hybrid computer including both digital and analog processors. For purposes of the description of FIG. 12, it is assumed that the acts are performed by a hybrid computer including a quantum processor. The method 1200 describes an exemplary embodiment. Those skilled in the art will recognize that alternative implementations may omit some acts and / or include additional acts.

[0277] At 1205, method 1200 begins. At 1210, the hybrid computer encodes a computational problem in a first subset of qubits in a quantum processor. In one embodiment, the qubits are superconducting flux qubits. At 1220, the hybrid computer allocates a second subset of qubits as probe qubits. The probe qubits may be weakly coupled to the first subset of qubits. At 1230, the hybrid computer measures MRT peak widths. At 1240, the hybrid computer adjusts an annealing schedule based at least in part on one or more measurements of the MRT peak widths. Method 1200 ends at 1245, e.g., until called again.

[0278] Selection of annealing schedules using equilibrium energy statistics The annealer (such as a physical quantum annealer) may proceed according to an annealing schedule through a series of models between a prepared model and a target model. The prepared model may be, for example, a uniform superposition of states or a uniform distribution over classical states. The target model may be, for example, a distribution about a minimum of an energy function or a Boltzmann distribution at low system temperatures. Physical (or Markov Chain Monte Carlo (MCMC)) dynamics may modify the states during annealing.

[0279] The goal of annealing is usually to sample from a final distribution that is as close as possible to the distribution of the target model. If the target distribution is a Boltzmann distribution described by an energy function E(x) or by an energy operator (classical or quantum), it may be beneficial to choose an annealing schedule that can improve or maximize the closeness of the final distribution to the target distribution.

[0280] The annealing schedule selected in this way is usually problem-specific. However, there may be many large-scale problems that share statistical characteristics such that a single schedule may be good enough (in practice) for more than one problem. It may be useful to determine an improved or optimal schedule for a group of problems of interest. Alternatively, a set of schedules may be presented to an expert user from which the user may select based on evaluation. The methodology may also be adapted to select a suitable model for a multicanonical MCMC procedure (a discrete set of preferred or optimized intermediate models for parallel tempering).

[0281] A thermal annealer can be programmed with a classical Hamiltonian H(x) and a set of inverse temperatures β. The function Γ(t) can be used to describe the time dependence of β, where Γ(0)=β min is the initial state and Γ(1)=1 is the goal state.

[0282] The quantum annealer is a Hamiltonian operator

number

[0283] The classical Hamiltonian can be defined for either the classical, semiclassical, or quantum case as follows: H(x)=Γ T Φ(x)

[0284] Φ(x) is a vector when the schedule has more than one component. In the quantum case, the classical Hamiltonian can be constructed by the Trotter slice trick. In the quantum (or semiclassical) case, the first component Φ i (x) is a classical energy statistic, conjugate to the energy measure (E), and models the variables that are diagonal components in the operator equation. The second component Φ 2 (x) is the quantum energy function since it is conjugate with logΔ and does not exist in the diagonalized operator.

[0285] The equilibrium energy distribution along the path in the trajectory can be evaluated. The distribution can be approximated by a Gaussian distribution and modeled by a mean and covariance Σ. The quality of the schedule can be judged by the integral of the energy fluctuations along the trajectory multiplied by the speed at which the annealer proceeds along the trajectory. One approach is to maximize the following objective function subject to boundary conditions:

number

[0286] In cases where Γ(t) is a scalar or a function of one parameter (eg, the classical case presented), there may be a simple and clear solution to the above equation, for example using:

number

[0287] In cases where Γ(t) is a vector or a function of two or more parameters (e.g., the quantum case presented), one approach is to perform a local search method to find Γ. Another approach tries to optimize a weighted combination of functions that satisfy the boundary conditions.

[0288] The Gaussian approximation may be suitable for a wide variety of distributions because the distributed errors may accumulate over many steps or iterations, and the central limit theorem applies to the accumulation of errors.

[0289] If the target model has zero transverse field (or a large energy scale), the Gaussian approximation may no longer be applicable. Optimization of at least part of the schedule may be possible. Once the energy distribution is close enough to zero, the schedule can be terminated by quenching (i.e. by proceeding very quickly) and the above procedure is not required at this stage.

[0290] The energy statistics used in model optimization may be collected, for example, by annealed importance sampling or parallel tempering.

[0291] Energy dispersion can be used to determine a schedule for thermal annealing (see, for example, Kone and Kofke, 2005). The systems and methods of the present disclosure address the challenge of determining a schedule for quantum annealing.

[0292] The energy statistics of the physical quantum annealer can be inferred. In one embodiment, the quantum hardware can be modeled as stoquastic (i.e., a function of transverse magnetic field, energy scale, and physical temperature). In this case, the equilibrium properties of the hardware can be measured using quantum Monte Carlo techniques.

[0293] Hardware dynamics may affect the degree of success. The disclosed system and method is likely to produce beneficial results for many problem classes using the optimized schedules as described above. The degree of success may be measured, for example, by generating two different schedules, predicting the quality of many problem samples, and determining whether there is a positive correlation with the quality of the output samples. The quality of the output samples may be measured, for example, using KL divergence, ground state frequency, or another suitable metric.

[0294] Benefits of the disclosed systems and methods may include some or all of the following: • Selection of a suitable Hamiltonian annealing schedule that can be implemented without reliance on dynamic insight; • Selection of annealing schedule based on estimated equilibrium energy statistics; ●Selection of an annealing schedule for a physical quantum annealer based on input from a quantum simulation.

[0295] 13 is a flow chart illustrating an example method 1300 of adjusting an annealing schedule based on equilibrium energy statistics. At 1305, the method 1300 begins. At 1310, a hybrid computer collects energy statistics by parallel tempering for a classical Hamiltonian, Hamiltonian operator, or classical approximation to a Hamiltonian operator of the problem. The problem may be a particular problem or a problem chosen to represent a family of problems.

[0296] At 1320, the hybrid computer evaluates the fixed Γ expression to determine the expected quality of the results for a selected problem or group of problems. At 1330, the hybrid computer determines a preferred or optimized velocity (given a fixed trajectory in Γ) by inverting the cumulative distribution function. At 1340, the hybrid computer determines a preferred or optimized trajectory by performing a local search. As discussed above, the local search at 1340 can be replaced by a method that seeks to optimize a weighted combination of functions that satisfy boundary conditions.

[0297] At 1345, the hybrid computer determines whether to repeat acts 1330 and 1340. If it is determined at 1345 that there is to be a repeat, the method 1300 proceeds to 1330. If it is determined at 1345 that there is not to be a repeat, the method 1300 proceeds to 1350, e.g., until called again, at which point the method ends. The repeat is optional, as indicated by the dashed lines in FIG.

[0298] Selection of annealing schedule based on objective function In some embodiments, an annealing schedule for a problem that is executable by an analog processor is selected by a digital processor based on an objective function. An example of such a selection method 2000 is shown as a flow chart in Figure 20. At 2005, a problem is received by the digital processor for which an annealing schedule is generated.

[0299] In 2010, an objective function is selected by the digital processor. The objective function may be determined (e.g., predetermined (considered a type of selection in this disclosure)), selected by a user, selected in response to characteristics of the problem, selected based on another act in the method (e.g., techniques applied in 2015 and / or 2020), and / or otherwise selected. The objective function may at least in part measure one or more characteristics of the annealing schedule and provide different measures to the different annealing schedules based on these characteristics (although the different annealing schedules do not necessarily receive the same measures in every instance).

[0300] For example, the objective function may provide a measure of the extent to which an annealing schedule improves, deteriorates, or otherwise changes the performance of a problem as it is executed. For example, the objective function may provide a measure of sample quality (where the problem is related to sampling), computational success rate (e.g., the problem is associated with constraints that may be violated due to the analog nature of the computation), computational efficiency (e.g., a time vs. solution metric), and / or some other measure related to the performance of a problem executed according to a candidate annealing schedule.

[0301] In 2015, one or more annealing schedules are generated by the digital processor. For example, the set of candidate annealing schedules may be generated by a user or a remote computing system and received by the digital processor, and / or the set of candidate annealing schedules may be generated according to a series of calculations performed by the digital processor. In some embodiments, the annealing schedules are generated by the computing system by performing an optimization algorithm based on an objective function. An exemplary implementation of method 2000 using such an optimization algorithm is described in further detail below.

[0302] In 2020, an annealing schedule is selected by the digital processor based on the objective function. For example, in 2020, an annealing schedule may be selected from a set of candidate annealing schedules by determining which of the annealing schedules in the group provides an optimal result (in this disclosure, "optimal" is used to mean "best of the choices considered," not necessarily the single most ideal annealing schedule possible). For example, if the objective function provides a measure of solution versus time, an annealing schedule that minimizes the objective function may be selected. In some embodiments, an annealing schedule that maximizes the objective function may be selected. In some embodiments, act 2020 may select an annealing schedule, which may then be used in 2015 to generate another annealing schedule, which may result in a different annealing schedule being selected thereafter.

[0303] In at least some embodiments, generating and selecting an annealing schedule may be performed sequentially by a digital processor via a single act or operation, as interleaved or overlapping acts or operations, and / or in other ways. For example, method 2000 may include performing an optimization algorithm that includes selectively generating and evaluating iterative annealing schedules to generate an optimized annealing schedule. Thus, acts 2015 and 2020 are not necessarily clearly separated in some embodiments. For convenience, acts 2015 and 2020 may be referred to together as act 2022, whether or not acts 2015 and 2020 are considered separately in a particular embodiment.

[0304] An annealing schedule may be selected for its measure of optimality relative to other candidate annealing schedules, but not necessarily for providing better computational results than each of the other candidate annealing schedules (e.g., where the objective function provides a heuristic measure that is not perfectly correlated to the quality of the computational results). For example, an objective function that is relatively easy to compute and provides relatively consistent improvements to the computational results may in some circumstances be preferable over an objective function that is relatively expensive to compute and provides only slight (and / or inconsistent) other improvements.

[0305] In 2025, the optimal annealing schedule (selected in 2020) is returned. The optimal annealing schedule may then be used by the analog processor in the course of computing the problem received in 2005 and / or related problems.

[0306] The inventors have identified through experiment and theory several combinations of optimization algorithms and objective functions that provide annealing schedules that tend to produce improvements over the computation of their corresponding problems in at least some circumstances and for at least some problems. Examples of these include optimization to avoid phase transitions (e.g., via parallel tempering) and Bayesian optimization, embodiments of which are described in further detail below.

[0307] In some embodiments, the objective function selected in 2010 measures the ability of the annealing schedule to reduce floppiness and / or avoid phase transitions during annealing. The objective function may measure the ability to avoid phase transitions directly (e.g., by running the problem with the annealing schedule many times and determining the frequency of phase transitions) and / or indirectly (e.g., by measuring a property of the annealing schedule that is a proxy for its ability to avoid phase transitions during annealing).

[0308] For example, the objective function may describe a number of models (also called replicas) and / or chains linking the models to be generated by a parallel tempering algorithm (e.g., a quantum parallel tempering algorithm) in 2022. Parallel tempering may be performed on the problem (modified by the described annealing schedule) by a digital processor, thereby generating a number of models linked by chains.

[0309] Parallel tempering algorithms are sometimes described as placing models along paths that exist in a two-dimensional space whose dimensions are an energy measure and temperature. Annealing schedules that tend to reduce floppiness and / or avoid phase transitions tend, at least in some circumstances, to require fewer models toward the ends of the paths in higher energy regions of this space to obtain a certain efficiency between adjacently placed models. Such annealing schedules may thus result in a parallel tempering algorithm that generates fewer models overall. Thus, at least in some circumstances, an annealing schedule that minimizes an objective function that describes the many models (and / or chains linking the models) generated by the parallel tempering algorithm tends to reduce floppiness and / or avoid phase transitions during annealing.

[0310] The objective function based on the placement of the model in the parallel tempering algorithm can be calculated relatively efficiently by performing a limited number of iterations (or "sweeps") of the parallel tempering algorithm. It is understood that the parallel tempering algorithm can be used to directly solve the problem received in 2005, but this may require many iterations (often hundreds of thousands or millions of iterations). However, finding an efficient placement of the model typically requires much fewer iterations (on the order of thousands or tens of thousands of iterations in at least some cases). Therefore, a modified (partial) parallel tempering algorithm may be used that terminates after fewer iterations than may be performed to solve the problem.

[0311] In some embodiments, act 2022 includes Bayesian optimization. In some such embodiments, the objective function selected in 2010, when performed by the digital processor, provides a measure of the ground state distribution of the problem (as modified by the measured annealing schedule). Such a measure may correlate with the uniformity of the distribution and / or characteristics of outliers within the distribution. For example, the objective function may provide an entropy measure of the ground state distribution, the distance of the ground state distribution from a uniform distribution, the Gini coefficient of the ground state distribution, the width of the ground state distribution (e.g., the ratio of the minimum probability to the maximum probability), and / or some other measure of the ground state distribution. In at least some embodiments, the Bayesian optimization algorithm aims to maximize the entropy-based objective function and minimize the other above-mentioned objective functions.

[0312] Any suitable acquisition function and surrogate model may be used. In some embodiments, a Bayesian optimization algorithm is performed by using an expected improvement acquisition function and a Gaussian process for the surrogate model. Alternative (or additional) acquisition functions include the probability of improvement and a confidence upper bound. Alternative (or additional) surrogate models include linear models, regression trees and random forests, and neural networks. Once a suitable objective function, acquisition function and surrogate model are selected, a Bayesian optimization may be performed to generate and select an optimal annealing schedule.

[0313] Auxiliary qubit delta tuning Advancing or retarding a floppy qubit or a floppy region of a qubit during quantum annealing can mitigate the effects of degeneracy and improve hardware performance. Mitigation can be achieved by using a local CCJJ DAC bias. Advancing or retarding a floppy qubit can reduce the tunneling rate Δ q In quantum hardware that reduces h, persistent currents can be desynchronized, leading to errors in the qubit biases and coupling terms (h, J, respectively). Although the errors can be corrected once during the quantum annealing process, advancing or retarding a floppy qubit can result in time-dependent errors in h and J in the device being reduced. As a result, the final Hamiltonian can be distorted by the reduction process.

[0314] The disclosed systems and methods include another approach to mitigation that uses an auxiliary qubit instead of a local CCJJ DAC bias. In this approach, a qubit in a quantum processor may have an associated ancillary qubit that may be tunably coupled to the strength J. In one embodiment, the ancillary qubit is a dedicated ancillary device associated with the processor qubit. In another embodiment, the ancillary qubit is a processor qubit that is reserved for use as an auxiliary qubit, rather than being used as a computation qubit.

[0315] A floppy qubit or floppy region may be identified using a small number of samples via the initial Hamiltonian. An ancillary qubit may be coupled to the floppy qubit or region by a coupling strength J designed to modify the dynamics of the floppy qubit or region. In some cases, the coupling strength J is designed to slow down the dynamics of the floppy qubit or region.

[0316] Coupling a floppy qubit with an ancillary qubit may modify the tunneling amplitude of the floppy qubit as follows:

number

[0317] In one embodiment, the auxiliary device is on a separate annealing line to the floppy qubit. In another embodiment, the CCJJ DAC in the quantum processor is ancilla This can be used to further modify the dynamic characteristics of the auxiliary device by reducing Δ floppy and |I p Orthogonal control with | can be achieved in this way by eliminating or at least reducing the time-dependent errors in h and J.

[0318] FIG. 14 is a flow chart illustrating an example method 1400 for mitigating the effects of degeneracy using ancillary qubits. The method 1400 illustrated by FIG. 14 includes a number of acts. One or more of these acts may be performed by (or through) one or more circuits, such as one or more processors (e.g., digital processors) and analog processors, such as quantum processors, or hybrid computers including both digital and analog processors. For purposes of the description of FIG. 14, it is assumed that the acts are performed by a hybrid computer including a quantum processor. The method 1400 describes an example embodiment. Those skilled in the art will recognize that alternative implementations may omit some acts and / or include additional acts.

[0319] Method 1400 begins at 1405. At 1410, the hybrid computer sends a computational problem to the quantum hardware. At 1415, the hybrid computer collects a set of samples from the quantum hardware. At 1420, the hybrid computer determines whether a qubit (or a region of a qubit) is floppy in the samples by flipping the qubit state and determining whether it changes the energy of the sample.

[0320] At 1425, the hybrid computer determines whether another sample exists. If the hybrid computer determines at 1425 that another sample exists, then method 1400 returns to 1420. If the hybrid computer determines at 1425 that another sample does not exist, then method 1400 proceeds to 1430.

[0321] At 1430, the hybrid computer calculates a “normalized floppyness metric” μ that describes the fraction of samples for which a qubit is floppy. i is generated as follows: μ i =n i / N where n iis the number of times a qubit is floppy, and N is the number of samples used to generate the metric.

[0322] The floppyness metric is an exemplary metric that may be used. In other embodiments, another suitable metric is used. More generally, the disclosed systems and methods may include collecting samples and processing the samples to determine which quantum bit to advance (or retard) next and by how much. The processing is not limited to determining floppyness or a floppyness metric. Another suitable processing method may be used to determine which quantum bit to advance (or retard) and by how much.

[0323] In 1435, the hybrid computer adds an ancillary qubit to the floppy qubit and then combines it with the strength J to modify the tunneling amplitude as described above. In one embodiment, an ancillary qubit is added for every floppy qubit. In another embodiment, an ancillary qubit is added for every subset of the floppy qubits. In one embodiment, Δ floppy ≒Δ q (1-μ i ).

[0324] At 1440, the hybrid computer determines whether another quantum bit is present. If the hybrid computer determines at 1440 that another quantum bit is present, then method 1400 returns to 1420. If the hybrid computer determines at 1440 that another quantum bit is not present, then method 1400 proceeds to 1445.

[0325] At 1445, the hybrid computer determines whether to collect another set of samples. If the hybrid computer determines at 1445 that it will collect another set of samples, then method 1400 returns to 1415. If the hybrid computer determines at 1445 that it will not collect another set of samples, then method 1400 proceeds to 1450.

[0326] Compensating for the h / J mismatch using an auxiliary qubit Quantum annealing may involve evolving a time-dependent Hamiltonian from a simple superposition to a useful classical problem. A drawback of quantum annealing is that the annealer may be biased toward an undesired state if the state is unfavorable for the final Hamiltonian but still favorable for intermediate Hamiltonians further along in the anneal. This may occur, for example, if both h (qubit bias) and J (coupling) terms are used. The bias term can be given relatively higher priority than the coupling term early in the anneal. This may result in a time-dependent h / J mismatch that pushes the annealer toward an unfavorable subspace (or valley in the energy landscape). To find the favorable or correct solution, the annealer tunnels from the unfavorable subspace to another valley.

[0327] The mismatch can occur because the coupling terms in the Ising Hamiltonian are typically weighted by a product of at least two Pauli matrices whose expectation values ​​are small in magnitude early during the anneal. In contrast, the bias terms are typically weighted by a single Pauli matrix that has a higher expected magnitude early during the anneal than the coupling terms, as follows:

number

[0328] The systems and methods of the present disclosure provide a technique for mitigating the above-mentioned h / J mismatch. This technique involves applying a local bias h i This involves shifting the qubit q to the auxiliary qubit. i and the input bias h i = x, the auxiliary qubit q' i can be added, resulting in a large negative bias (e.g., h' i =-2) is the auxiliary quantum bit q' i The bias can typically be provided to the ancillary qubit q' iThe bias on q is chosen to be large enough so that it is not disturbed in the ground state. i and the auxiliary qubit q' i The coupling between qubits is set to x and qubit q i The upper bias can be set to 0. If the input bias |x|≦1, then this is within the range of acceptable combiner values.

[0329] In one embodiment, if |x|<<1, the qubit and ancillary qubit may be coupled by a coupler having a value of −1, and the bias on x may be adjusted to the ancillary qubit (h′ i = x). In another embodiment, if |x|<<1, the state is treated in the same manner as described in the previous paragraph for the general case of |x|.

[0330] If |x|>1, the bias h i A part of the auxiliary qubit q' i In one embodiment, a portion of the bias is shifted to a coupling of a single ancillary qubit. In another embodiment, a portion of the bias is shifted to two or more ancillary qubits.

[0331] FIG. 15 is a flow chart illustrating an example method 1500 for mitigating h / J mismatch using ancillary qubits. The method 1500 illustrated by FIG. 15 includes a number of acts. One or more of these acts may be performed by (or through) one or more circuits (e.g., one or more processors (e.g., digital processors) and analog processors such as quantum processors, or hybrid computers including both digital and analog processors). For purposes of the description of FIG. 15, it is assumed that the acts are performed by a hybrid computer including a quantum processor. Method 1500 describes an example embodiment. Those skilled in the art will recognize that alternative implementations may omit some acts and / or include additional acts.

[0332] Method 1500 begins at 1505. At 1510, the hybrid computer receives a bias for the qubit. At 1515, the hybrid computer adds an ancillary qubit. At 1520, the hybrid computer determines whether the bias is less than or equal to 1. If the hybrid computer determines at 1520 that the bias is less than or equal to 1, method 1500 proceeds to 1525. At 1525, the hybrid computer determines whether the bias is much less than 1. If the hybrid computer determines at 1525 that the bias is much less than 1, method 1500 proceeds to 1530. At 1530, the hybrid computer combines the qubit and the ancillary qubit with a combiner of value -1. At 1535, the hybrid computer applies the qubit bias to the ancillary qubit and method 1500 proceeds to 1540.

[0333] If the hybrid computer determines at 1525 that the bias is not significantly less than one, method 1500 proceeds to 1545. At 1545, the hybrid computer applies a large negative bias (e.g., −2) to the ancillary qubit. At 1550, the hybrid computer sets the coupling between the qubit and the ancillary qubit to the input bias value. At 1555, the hybrid computer sets the bias of the qubit to zero and method 1500 proceeds to 1540.

[0334] If the hybrid computation determines at 1520 that the bias is greater than one, then method 1500 proceeds to 1560. At 1560, the hybrid computer transfers a portion of the input bias onto the connection to the ancillary qubit, and method 1500 proceeds to 1540.

[0335] At 1540, the hybrid computer determines whether there is another qubit for which bias adjustment can be made. If the hybrid computer determines at 1540 that there is another qubit for which bias adjustment can be made, method 1500 returns to 1510.

[0336] If the hybrid computer determines at 1540 that there is no other qubit for which bias adjustment can be made, then method 1500 proceeds back to 1565. At 1565, method 1500 ends.

[0337] Hybrid Computing System Including Quantum Processors 16 illustrates an exemplary hybrid computing system 1600 including a digital computer 1605 coupled to an analog computer 1651. In some embodiments, the analog computer 1651 is a quantum computer and the digital computer 1605 is a classical computer. The exemplary digital computer 1605 includes a digital processor that can be used to perform classical digital processing tasks described in the present systems and methods. Those skilled in the art will appreciate that the present systems and methods can be implemented with other digital computer configurations including portable devices, multiprocessor systems, microprocessor-based or programmable consumer electronics devices, personal computers (PCs), network PCs, minicomputers, mainframe computers, etc. when properly configured or programmed to form a dedicated machine and / or communicatively coupled to control an analog computer (e.g., a quantum computer).

[0338] Although digital computer 1605 will be referred to in the singular herein, this is not intended to limit the application to a single digital computer. The present system and method may also be practiced in a distributed computing environment where tasks or sets of processor-readable instructions are performed or executed by remote processing devices that are linked through a communications network. In a distributed computing environment, computer or processor-readable instructions (sometimes known as program modules), application programs and / or data may be located in both local and remote storage devices (e.g., non-transitory computer or processor-readable media).

[0339] The digital computer 1605 may include at least one digital processor (such as a central processing unit) 1610, at least one system memory 1620, and at least one system bus 1617 coupling various system components including the system memory 1620 to the digital processor 1610.

[0340] The digital processor(s) 1610 may be any logical processing unit having, for example, one or more cores (e.g., one or more central processing units (CPUs), graphics processing units (GPUs), digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs). Unless otherwise noted, the structure and operation of the various blocks illustrated in FIG. 16 are of conventional design. As a result, such blocks need not be described in further detail herein as they will be understood by those skilled in the art.

[0341] The digital computer 1605 may include a user input / output subsystem 1611. In some embodiments, the user input / output subsystem includes one or more user input / output components, such as a display 1612, a mouse 1613, and / or a keyboard 1614. The system bus 1617 may employ any known bus structure or architecture, including a memory bus, a peripheral bus, or a local bus with a memory controller. The system memory 1620 may include non-volatile memory, such as read-only memory (ROM), static random access memory (SRAM), flash NAND, and volatile memory, such as random access memory (RAM) (not shown). All of these are examples of non-transitory computer or processor readable media. A basic input / output system (BIOS) 1621, which may form part of the ROM, contains the basic routines that help transfer information between elements within the digital computer 1605, such as during start-up.

[0342] The digital computer 1605 may also include other non-volatile memory 1615. The non-volatile memory 1615 may take a variety of forms including a hard disk drive for reading from and writing to a hard disk, an optical disk drive for reading from and writing to a removable optical disk, and / or a magnetic disk drive for reading from and writing to a magnetic disk. All of these are examples of non-transitory computer or processor readable media. An optical disk may be a CD-ROM or DVD, while a magnetic disk may be a magnetic floppy disk or diskette. The non-volatile memory 1615 may communicate with the digital processor via a system bus 1617 and may include a suitable interface or controller 1616 coupled to the system bus 1617. The non-volatile memory 1615 may serve as long-term storage of computer or processor readable instructions, data structures, or other data (also referred to as program modules) of the digital computer 1605.

[0343] Although the digital computer 1605 has been described as employing hard disks, optical disks, and / or magnetic disks, those skilled in the art will appreciate that other types of non-volatile computer readable media may be employed, such as magnetic cassettes, flash memory cards, flash, ROM, smart cards, and the like. All of these are other examples of non-transitory computer or processor readable media. Those skilled in the art will appreciate that some computer architectures combine volatile and non-volatile memory. For example, data in volatile memory may be cached to non-volatile memory; or solid-state disks employing integrated circuits to provide non-volatile memory. Some computers place data traditionally stored on disks in memory. Similarly, some media traditionally considered volatile may have a non-volatile form (e.g., a non-volatile dual in-line memory module that is a variation of a dual in-line memory module).

[0344] Various sets of computer or processor readable instructions (also referred to as program modules), application programs, and / or data may be stored in the system memory 1620. For example, the system memory 1620 may store an operating system 1623 and a set of computer or processor readable server instructions (i.e., server modules) 1625. In some embodiments, the server modules 1625 include instructions for communicating with remote clients and scheduling the use of resources, including resources on the digital computer 1605 and the analog computer 1651. For example, a web server application and / or a web client or browser application to enable the digital computer 1605 to exchange data with sources over the Internet, a corporate intranet, or other networks, as well as with other server applications running on server computers.

[0345] In some embodiments, the system memory 1620 may store other sets of computer or processor readable instructions 1627, such as computational instructions, analog computer interface instructions, and the like.

[0346] Although shown in FIG. 16 as being stored in system memory 1620, the illustrated modules and other data may also be stored elsewhere, including in non-volatile memory 1615 or in one or more other non-transitory computer- or processor-readable media.

[0347] Analog computer 1651 may be provided in an isolated environment (not shown). For example, if analog computer 1651 is a quantum computer, the environment shields the internal elements of the quantum computer from heat, magnetic fields, etc. and other external noise (not shown) and / or cools the analog processor to a temperature below which the circuitry of the analog processor becomes superconductive (i.e., a critical temperature). In contrast, digital computer 1605 typically operates at a much higher temperature (e.g., room temperature) where superconductivity does not occur and / or digital computer 1605 may employ materials that do not superconduct even below a critical temperature. Analog computer 1651 includes analog processor 1640. Examples of analog processor 1640 include quantum processors such as those described below with reference to FIG. 13.

[0348] The quantum processor includes programmable elements such as qubits, couplers, and other devices. The qubits are read out via readout system 1660. These results are sent to various sets of computer or processor readable instructions in digital computer 1605, including server module 1625 or other modules 1627, stored in non-volatile memory 1615, returned over a network, etc. The qubits are controlled via qubit control system 1665. The couplers are controlled via coupler control system 1670. In some embodiments, qubit control system 1665 and coupler control system 1670 are used to implement quantum annealing on analog processor 1640 as described herein.

[0349] In some embodiments, the digital computer 1605 may operate in a networked environment using logical connections to at least one client computer system. In some embodiments, the digital computer 1605 is coupled to at least one database system via logical connections. These logical connections may be formed using any means of digital communication over a network, such as a local area network (LAN) or a wide area network (WAN), including the Internet. The networked environment may include wired or wireless enterprise-wide computer networks, intranets, extranets, and / or the Internet. Other embodiments may include other types of communication networks, such as telecommunications networks, cellular networks, paging networks, and other mobile networks. Information transmitted or received over the logical connections may or may not be encrypted. When used in a LAN networking environment, the digital computer 1605 may be connected to the LAN through an adapter or network interface card (NIC), communicatively coupled to the system bus 1617. When used in a WAN networking environment, the digital computer 1605 may include devices such as an interface and modem (not shown) or a NIC for establishing communications over the WAN. Non-network communications may also or alternatively be employed.

[0350] An exemplary superconducting quantum processor for quantum annealing FIG. 17 is a schematic diagram of a portion of an exemplary superconducting quantum processor 1700 designed for quantum annealing (and / or adiabatic quantum computing) components that may be used to implement the present systems and devices. The portion of the superconducting quantum processor 1700 shown in FIG. 17 includes two superconducting qubits 1701, 1702. Also shown is a tunable coupling (diagonal coupling) between the qubits 1701, 1702 (i.e., providing two-local interaction) via a coupler 1710. Although the portion of the quantum processor 1700 shown in FIG. 17 includes only two qubits 1701, 1702 and one coupler 1710, one skilled in the art will recognize that the quantum processor 1700 may include any number of qubits and any number of couplers that couple information between them.

[0351] The portion of quantum processor 1700 shown in FIG. 17 may be implemented to physically realize quantum annealing and / or adiabatic quantum computing. Quantum processor 1700 includes a number of interfaces 1721-1725 that are used to configure and control the state of quantum processor 1700. Each of interfaces 1721-1725 may be realized with a respective inductive coupling structure as shown as part of a programming subsystem and / or evolution subsystem. Such programming and / or evolution subsystems may be separate from quantum processor 1700 or may be included locally (i.e., on-chip with quantum processor 1700).

[0352] During operation of quantum processor 1700, interfaces 1721, 1724 each couple a flux signal into compound Josephson junctions 1731, 1732 of qubits 1701, 1702, respectively, thereby generating a tunable tunneling term (Δ i terms) into the system Hamiltonian. This coupling is x terms, and these flux signals are examples of "delocalized signals".

[0353] In some embodiments, the tunneling term is selected to make a first portion of qubits on a quantum processor classical relative to a second portion of qubits. For example, qubit 1701 is a hidden unit in a Boltzmann machine and may have a small tunneling term relative to qubit 1702.

[0354] Similarly, interfaces 1722, 1723 may be used to apply flux signals into the qubit loops of each of qubits 1701, 1702, respectively, thereby realizing hi terms in the system Hamiltonian. This coupling is represented by the diagonal σ z In addition, interface 1725 couples the flux signal into coupler 1710, which provides the J ij can be used to realize terms in the system Hamiltonian. This coupling is

number

[0355] In Figure 17, the contributions of each of the interfaces 1721-1725 to the evolution Hamiltonian are shown in boxes 1721a-1725a, respectively. As shown, in the example of Figure 17, boxes 1721a-1725a are elements of a time-varying Hamiltonian for quantum annealing and / or adiabatic quantum computing.

[0356] Throughout this specification and the appended claims, the term "quantum processor" is used to generally describe a collection of physical qubits (e.g., qubits 1701, 1702) and couplers (e.g., coupler 1710). The physical qubits 1701, 1702 and coupler 1710 are referred to as the "programmable elements" of quantum processor 1700, and their corresponding parameters (e.g., qubit h i value, coupler J ijThe programmable parameters (values) are referred to as the "programmable parameters" of the quantum processor. In the context of quantum processors, the term "programming subsystem" is used generally to describe the interfaces (e.g., "programming interfaces" 1722, 1723, 1725) used to apply the programmable parameters to the programmable elements and other associated control circuitry and / or instructions of the quantum processor 1700.

[0357] As described above, the programming interface of the programming subsystem may communicate with other subsystems that may be separate from the quantum processor or may be included locally on the quantum processor. As described in more detail below, the programming subsystem may be configured to receive and execute machine program instructions of the quantum processor to program the programmable elements according to the program instructions. Similarly, in the context of a quantum processor, the term "evolution subsystem" is used to generally describe the interfaces (e.g., "evolution interfaces" 1721 and 1724) used to evolve the programmable elements of the quantum processor 1700 and other associated control circuitry and / or instructions. For example, the evolution subsystem may include interfaces (1721, 1724) to annealing signal lines and their corresponding qubits (1701, 1702).

[0358] Quantum processor 1700 also includes readout devices 1751, 1752. Readout device 1751 is associated with qubit 1701, and readout device 1752 is associated with qubit 1702. In some embodiments, such as that shown in FIG. 17, each of readout devices 1751, 1752 includes a DC-SQUID inductively coupled to a corresponding qubit. In the context of quantum processor 1700, the term "readout subsystem" is used generally to describe readout elements 1751, 1752 that are used to read out the final states of qubits (e.g., qubits 1701 and 1702) in the quantum processor to generate a bit string. The readout subsystem may also include other elements, such as routing circuitry (e.g., latch elements, shift registers, or multiplexer circuits), and / or be arranged in alternative configurations (e.g., an XY-addressable array, an XYZ-addressable array, etc.). Qubit readout can also be performed using alternative circuitry such as that described in PCT Patent Application WO2012064974.

[0359] 17 shows only two physical qubits 1701, 1702, one combiner 1710, and two readout elements 1751, 1752, a quantum processor (e.g., processor 1700) may employ any number of qubits, combiners, and / or readout elements, including large numbers (e.g., hundreds, thousands, or more) of qubits, combiners, and / or readout elements. Application of the teachings herein to processors having different (e.g., greater) numbers of computer components should be readily apparent to one of ordinary skill in the art.

[0360] Examples of superconducting qubits include superconducting flux qubits, superconducting charge qubits, etc. In superconducting flux qubits, the Josephson energy exceeds or is equal to the charge energy. In charge qubits, this is the opposite. Examples of flux qubits that may be used include rf-SQUIDs, which contain a superconducting loop interrupted by one Josephson junction, persistent current qubits, which contain a superconducting loop interrupted by three Josephson junctions, etc.

[0361] The qubits and coupling devices in a quantum processor may be arranged in a topology based on the architecture such that a certain number of qubits may be arranged in a sub-topology of qubits (hereinafter simply "sub-topology"). A sub-topology is a portion of a quantum processor topology that includes qubits and coupling devices. Multiple sub-topologies may be repeated or tiled (or otherwise directly communicatively coupled to one another) across the area of ​​the quantum processor to generate a quantum processor topology.

[0362] In some embodiments, each sub-topology within a topology is identical to every other sub-topology within the same topology, while in other embodiments, one or more sub-topologies within a topology include a different configuration of qubits and coupling devices than another sub-topology within the same topology.

[0363] The above description of the illustrated embodiments, including those described in the Abstract, are not intended to be exhaustive or to limit the embodiments to the precise forms disclosed. For illustrative purposes, specific embodiments and examples have been described herein; however, various equivalent modifications may be made without departing from the spirit and scope of the disclosure, as will be recognized by those skilled in the art. The teachings described herein of the various embodiments may be applied to other analog processors, and not necessarily only to the exemplary quantum processor outlined above.

[0364] The various embodiments described above may be combined to provide further embodiments.Unless inconsistent with the specific teachings and definitions herein, all of the U.S. patent application publications, U.S. patent applications, U.S. patents, foreign patents, and foreign patent applications referenced herein and / or listed in the Application Data Sheets that are commonly assigned to D-Wave Systems, Inc., are hereby incorporated by reference in their entirety, including, but not limited to, the following patents: U.S. Patent No. 7,984,012; U.S. Patent No. 8,244,662; U.S. Patent No. 8,174,305; U.S. Patent No. 8,670,807; U.S. Patent No. 8,700,689; PCT Patent Application Publication WO 2012064974; U.S. Patent Application No. 2015 / 0032994; U.S. Provisional Patent Application No. 62 / 247,085, filed October 27, 2015; U.S. Provisional Patent Application No. 62 / 324,210, filed April 18, 2016; U.S. Provisional Patent Application No. 62,331,288, filed May 3, 2016; U.S. Provisional Patent Application No. 62 / 399,764, filed September 26, 2016; U.S. Provisional Patent Application No. 62 / 375,785; and enclosed file U.S. Provisional Patent Application No. 62 / 399,683 (Attorney Docket No. 240105.581P1) entitled "SYSTEMS, METHODS AND DEVICES FOR SAMPLING FROM A SAMPLING SERVER." Aspects of the embodiments may be modified, as necessary, to employ systems, circuits and concepts of various patents, applications and publications to provide further embodiments.

[0365] These and other changes can be made to the above-described embodiments in light of the above detailed description. Generally, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by this disclosure.

Claims

1. 1. A method of operating a hybrid computing system including a quantum processor and a digital processor, the quantum processor and the digital processor being communicatively coupled to each other, the quantum processor including a plurality of qubits, the method comprising: receiving a pause start and a pause duration as input by said digital processor via a user interface; Controlling the quantum annealing evolution performed by the quantum processor by the digital processor, initiating the quantum annealing evolution; When the pause start is reached, pausing the quantum annealing evolution for the pause duration; controlling the quantum annealing evolution, including completing the evolution; reading out the states of the plurality of qubits by the hybrid computing system after completing the quantum annealing evolution.

2. The method of claim 1 , wherein receiving a pause initiation comprises receiving a measure of progress through the quantum annealing evolution.

3. The method of claim 1 , wherein receiving the pause start and pause duration comprises receiving the pause start and pause duration via an application programming interface.

4. 2. The method of claim 1 , wherein controlling a quantum annealing evolution performed by the quantum processor with the digital processor comprises controlling a quantum annealing evolution performed by a plurality of superconducting flux qubits with the digital processor.

5. 2. The method of claim 1 , wherein pausing the quantum annealing evolution for the pause duration comprises selecting a subset of qubits; pausing the quantum annealing evolution for one or more qubits that are not in the subset of qubits; and reverse annealing the subset of qubits while the one or more qubits are paused.

6. 6. The method of claim 5, further comprising forward annealing the subset of qubits after reverse annealing the subset of qubits and before completing the quantum annealing evolution.

7. 1. A hybrid computing system, comprising: a quantum processor including a plurality of qubits; a digital processor communicatively coupled to the quantum processor; a user interface communicatively coupled to the digital processor; at least one non-transitory computer-readable storage medium storing processor-executable instructions; The processor-executable instructions, when executed, cause the digital processor to: receiving a pause start and a pause duration as input via the user interface; Controlling a quantum annealing evolution performed by the quantum processor, comprising: initiating the quantum annealing evolution; When the pause start is reached, pausing the quantum annealing evolution for the pause duration; controlling the quantum annealing evolution, including completing the evolution; reading out the states of the plurality of qubits after completing the quantum annealing evolution.

8. The hybrid computing system of claim 7 , wherein the pause initiation includes a measure of progress through the quantum annealing evolution.

9. The hybrid computing system of claim 7 , wherein the user interface is an application programming interface, and the pause start and the pause duration are received as input via the application programming interface.

10. The hybrid computing system of claim 7 , wherein the plurality of qubits comprises a plurality of superconducting flux qubits.

11. 8. The hybrid computing system of claim 7, wherein pausing the quantum annealing evolution for the pause duration comprises selecting a subset of qubits, pausing the quantum annealing evolution for one or more qubits that are not in the subset of qubits, and reverse annealing the subset of qubits while the one or more qubits are paused.

12. 12. The hybrid computing system of claim 11, wherein after reverse annealing the subset of qubits and before completing the quantum annealing evolution, the subset of qubits is forward annealed.

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