Differential Analog Input Buffer

Abstract

A differential signal input buffer (200) is disclosed. The differential signal input buffer (200) receives a differential signal including a first signal and a second signal and may be divided into a first section (260) and a second section (261). The first section (260) may buffer and / or amplify the first signal based on a first level-shifted second signal. The second section (261) may buffer and / or amplify the second signal based on the first level-shifted first signal. In some implementations, the first section (260) may buffer and / or amplify the first signal based on a second level-shifted second signal. Also, in some implementations, the second section (261) may buffer and / or amplify the second signal based on the second level-shifted first signal.

Description

[Technical field]

[0001] Aspects of the present disclosure relate generally to analog input buffers, and more particularly, to differential analog input buffers with improved noise rejection. [Background technology]

[0002] background Many modern circuits receive one or more analog signals for processing, filtering, amplification, etc. For example, the analog signals may be buffered for sampling by an analog-to-digital converter (ADC). Analog signals are often distributed in a differential format including two complementary signals, with the electrical difference between these signals representing the analog signal. Analog signals are typically received through an input buffer to provide isolation and possible gain prior to further processing. In some cases, power supply noise may affect the performance of the input buffer by directly affecting the input buffer output signal. Therefore, an input buffer with increased power supply noise rejection is highly desirable. Summary of the Invention [Means for solving the problem]

[0003] overview This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter. Additionally, the systems, methods, and devices of the present disclosure each have several innovative aspects, no one of which is solely responsible for the desirable attributes disclosed herein.

[0004] One innovative aspect of the subject matter described in this disclosure may be used to buffer a differential signal. In some implementations, the differential signal buffer may include a first buffer circuit configured to receive a first level-shifted differential signal and a second buffer circuit configured to receive a second level-shifted differential signal. The first buffer circuit may include a first NMOS transistor and a first PMOS transistor, where the drain of the first NMOS transistor is coupled to the drain of the first PMOS transistor. The first buffer circuit may also include a first power regulator coupled to the source of the first PMOS transistor and configured to receive the second level-shifted differential signal. The second buffer circuit may include a second NMOS transistor and a second PMOS transistor, where the drain of the second NMOS transistor is coupled to the drain of the second PMOS transistor. The second buffer circuit may also include a second power regulator coupled to the source of the second PMOS transistor and configured to receive the first level-shifted differential signal. The differential signal buffer is configured to buffer the first level-shifted differential signal based on the second level-shifted differential signal and to buffer the second level-shifted differential signal based on the first level-shifted differential signal.

[0005] Another innovative aspect of the subject matter described in this disclosure may be implemented as a method for buffering a differential input signal. In some implementations, the method may include receiving the differential input signal, generating a first current based on the first level-shifted differential signal, generating a second current based on the second level-shifted differential signal, and generating a differential output signal based at least in part on the first current and the second current.

[0006] BRIEF DESCRIPTION OF THE DRAWINGS Exemplary implementations described herein are illustrated by way of example and are not intended to be limited by the figures of the accompanying drawings. Like numbers refer to like elements throughout the drawings and specification. It should be noted that relative dimensions in the following figures may not be drawn to scale. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a simplified circuit diagram of a conventional input buffer. [Diagram 2] 1 is a simplified circuit diagram of a differential input buffer according to some implementations. [Diagram 3] 1 is a simplified circuit diagram of an example first section of a differential input buffer according to some implementations. [Figure 4] FIG. 2 is a simplified circuit diagram of an exemplary second section of a differential input buffer. [Diagram 5] 4 is a simplified circuit diagram of another example section of a differential input buffer according to some implementations. [Figure 6] 4 is a simplified circuit diagram of another implementation of another example section of a differential input buffer according to some implementations. [Figure 7] 5 is an example flowchart illustrating example operations for operating a differential input buffer according to some implementations. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Detailed Description Aspects of the disclosure may be used to buffer differential analog signals. In some implementations, one or more power regulators may be used with an analog buffer circuit to provide an input buffer with improved power supply noise rejection that may be used to buffer the differential signal. In some implementations, the power regulator may also increase common mode signal rejection of the differential signal. In some aspects, the power regulator may provide a voltage and / or current to a first buffer circuit configured to buffer a first differential signal and may adjust the voltage and / or current provided to the first buffer circuit based on a second differential signal. In some other aspects, the power regulator may adjust the voltage and / or current provided to the analog buffer circuit based at least in part on a power supply voltage or a ground voltage.

[0009] In the following description, numerous specific details are set forth, such as examples of specific components, circuits, and processes, to provide a thorough understanding of the present disclosure. The term "coupled" as used herein means directly coupled or coupled through one or more intervening components or circuits. Also, in the following description, for purposes of explanation, specific nomenclature and / or details are set forth to provide a thorough understanding of the exemplary implementations. However, it will be apparent to one skilled in the art that these specific details may not be required to practice the exemplary implementations. In other instances, well-known circuits and devices are shown in block diagram form so as not to obscure the present disclosure. Any of the signals provided through the various buses described herein may be time-shared with other signals and provided through one or more common buses. In addition, the interconnections between circuit elements or software blocks may be shown as buses or as single signal lines. Each of the buses may alternatively be a single signal line, each of the single signal lines may alternatively be a bus, and a single line or bus may represent any one or more of a myriad of physical or logical mechanisms for communication between components. The example implementations should not be construed as being limited to the particular examples described herein, but rather as including within their scope all implementations defined by the appended claims.

[0010] 1 shows a simplified circuit diagram of a conventional input buffer 100. The input buffer 100 may include transistors 101 and 102, resistors 110 and 111, and level shifters 120 and 121. As shown, the input buffer 100 may receive an input signal VIN and generate an output signal VOUT. In some implementations, the input buffer 100 may be used to buffer a differential signal. For example, the input buffer 100 may be instantiated twice such that each instantiation can buffer one-half of the differential signal.

[0011] In some implementations, transistor 101 may be a PMOS transistor, transistor 102 may be an NMOS transistor, and input buffer 100 may operate as a CMOS buffer or an inverter. As shown, the drain terminals of transistor 101 and transistor 102 may be coupled together. The source of transistor 101 may be coupled to a power supply (VSUPPLY), and the source of transistor 102 may be coupled to ground. The gate of transistor 101 may be coupled to an output terminal of a first level shifter 120, and the gate of transistor 102 may be coupled to an output terminal of a second level shifter 121.

[0012] In other implementations, transistors 101 and 102 may be any possible transistor type. For example, transistor 101 may be an NMOS transistor and transistor 102 may be a PMOS transistor. In some other implementations, transistors 101 and 102 may be the same transistor type (e.g., both NMOS transistors or both PMOS transistors). In addition, input buffer 100 may include additional transistors that are not shown for simplicity. For example, one or more additional transistors may be used to provide bias currents and / or voltages for input buffer 100. Also, in other implementations, other terminals of transistors 101 and 102 may be coupled together.

[0013] Resistor 110 may be an input resistor, and resistor 111 may be a feedback resistor. As shown, resistor 110 may receive an input signal VIN and provide the input signal VIN to the gates of transistors 101 and 102 via level shifter 120 and level shifter 121, respectively. In some implementations, resistors 110 and 111 may determine at least a portion of the gain of input buffer 100. For example, the gain of input buffer 100 may be determined by the ratio between the resistance value of resistor 111 and the resistance value of resistor 110. Thus, in some implementations, input buffer 100 may provide a positive gain, a negative gain, or a unity gain based on the ratio or configuration of the resistance values ​​of resistors 110 and 111.

[0014] Level shifters 120 and 121 may move, shift, or "level shift" the input signal V to the appropriate voltage for operation of transistors 101 and 102. Thus, level shifter 120 may level shift the voltage of V for operation of transistor 101, and level shifter 121 may level shift the voltage of V for operation of transistor 102. Level shifters are well known in the art and will not be described in detail herein.

[0015] Power to input buffer 100 may be provided by VSUPPLY and returned to ground. Thus, VSUPPLY is coupled to the drain of transistor 101, and ground is coupled to the drain of transistor 102. In other implementations, power (VSUPPLY and ground) may be coupled to other terminals and / or devices.

[0016] The output signal of input buffer 100 may be expressed as a polynomial that is a function of the input voltage and the power supply. For example, the output current IOUT of input buffer 100 may be expressed as:

[0017]

number

[0018] In the formula, a 0 ~a n is a constant, and x is the combination of the input voltage VIN and the power supply voltage VSUPPLY.

[0019] Thus, x can be expressed as:

[0020]

number

[0021] Also, x 2 can be expressed as follows:

[0022]

number

[0023] x 3 Similar expressions can be defined for V and higher order terms not shown or described here for simplicity. Thus, the supply voltage V can be expressed as follows (e.g., a 1 ) linearly, and (for example, 2 Term and a 3 The input buffer circuit 100 may nonlinearly affect the output current IOUT (as shown in the paragraph 14). Thus, compensating or adjusting the output current IOUT based on the power supply voltage may reduce the power supply related noise in the output current. Similar equations not expressed here may show a similar reduction in the power supply related noise in the output voltage (VOUT) of the input buffer circuit 100.

[0024] 2 shows a simplified circuit diagram of a differential signal buffer 200 according to some implementations. The differential signal buffer 200 may receive a differential input signal and generate a differential output signal based on the differential input signal. The differential input signal may include complementary input signals VIN_P and VIN_N, and the differential output signal may include complementary output signals VOUT_P and VOUT_N. The differential signal buffer 200 may include transistors 201-204, resistors 210-213, level shifters 220-223, and power regulators 230-233.

[0025] Differential signal buffer 200 may be divided into a first section 260 (left of the dashed line) and a second section 261 (right of the dashed line). First section 260 may be configured substantially similarly to second section 261. For first section 260, transistors 201 and 202 are configured to provide a first output signal VOUT_P, and are coupled in series between power regulator 230 and power regulator 231, with a gate of transistor 201 coupled to an output terminal of level shifter 220 and a gate of transistor 202 coupled to an output terminal of level shifter 221. Level shifter 220 may generate a level-shifted input signal 240 for the gate of transistor 201, and level shifter 221 may generate a level-shifted input signal 241 for the gate of transistor 202. The commonly coupled drains of transistors 201 and 202 may be coupled to resistor 211. Resistor 210 may receive an input signal VIN_P and provide the input signal VIN_P to level shifters 220 and 211 as well as to resistor 211 .

[0026] For the second section 261, transistors 203 and 204 are configured to provide a second output signal VOUT_N, and are coupled in series between power regulator 232 and power regulator 233, with a gate of transistor 203 coupled to an output terminal of level shifter 222 and a gate of transistor 204 coupled to an output terminal of level shifter 223. Level shifter 222 may generate a level-shifted input signal 242 for the gate of transistor 203, and level shifter 223 may generate a level-shifted input signal 243 for the gate of transistor 204. The commonly coupled drains of transistors 203 and 204 may be coupled to resistor 213. Resistor 212 may receive input signal VIN_N and provide input signal VIN_N to level shifters 222 and 223 and also to resistor 213.

[0027] Each of power regulators 230-233, depicted as voltage tracking op-amps, may provide power (e.g., voltage and / or current) based at least in part on a corresponding input signal. For example, power regulator 230 provides power to a source of transistor 201 based on a level shifted input signal 242 provided by level shifter 222, power regulator 231 provides power to a source of transistor 202 based on a level shifted input signal 243 provided by level shifter 223, power regulator 232 provides power to a source of transistor 203 based on a level shifted input signal 240 provided by level shifter 220, and power regulator 233 provides power to a source of transistor 204 based on a level shifted input signal 241 provided by level shifter 221.

[0028] In some implementations, power regulator 230 may operate as a current source and provide current to transistors 201 and 202 based on level-shifted input signal 242, and power regulator 231 may operate as a current source and provide current to transistors 201 and 202 based on level-shifted input signal 243. Similarly, power regulator 232 may operate as a current source and provide current to transistors 203 and 204 based on level-shifted input signal 240, and power regulator 233 may operate as a current source and provide current to transistors 203 and 204 based on level-shifted input signal 241.

[0029] 3 shows a simplified circuit diagram of a first section 300 of a differential input buffer according to some implementations. The first differential input buffer section 300 of FIG. 3 may be an implementation of the first section 260 of the differential signal buffer 200 of FIG. 2. Thus, the first differential input buffer section 300 may include transistors 201 and 202, resistors 210 and 211, and level shifters 220 and 221 as described with respect to the differential signal buffer 200 of FIG. 2. The first differential input buffer section 300 may also include power regulators 310 and 311 and a current source 320. The power regulators 310 and 311 may be implementations of the power regulators 230 and 231, respectively.

[0030] Power regulator 310 may supply or synchronize power (e.g., current and / or voltage) to or from transistors 201 and 202. For example, power regulator 310 may provide an output current or an output voltage to transistors 201 and 202. In some implementations, power regulator 310 may include transistors 330-333 and a capacitor 340. In the example of FIG. 3, transistors 330-332 are shown as PMOS transistors and transistor 333 is shown as an NMOS transistor. In other implementations, transistors 330-333 may be any feasible type of transistor. Capacitor 340 is coupled between the source and drain terminals of transistor 333 to provide a high frequency path that may improve high frequency response of output current IOUT1.

[0031] Transistor 330 may have a source coupled to a power supply voltage (VSUPPLY), a drain coupled to a source of transistor 332, and a gate coupled to a drain of transistor 331 and a drain of transistor 333. The source of transistor 331 may be coupled to the power supply voltage, and the drain of transistor 331 may be coupled to the gate of transistor 330 and the drain of transistor 333. The source of transistor 333 may be coupled to the drain of transistor 332 and to the current source 320. In some implementations, the gate of transistor 332 may receive a level-shifted input signal 242, and transistor 332 may control the output current IOUT1 provided to transistors 201 and 202 based at least in part on the level-shifted input signal 242.

[0032] The gate of transistor 331 receives a first bias voltage V1, and the gate of transistor 333 receives a second bias voltage V2. The bias voltages V1 and V2 may be generated by any feasible device or procedure. In some implementations, transistors 331 and 333 are biased to enable transistors 330 and 332 to provide an output current IOUT1 based on the level-shifted input signal 242. In some aspects, transistors 330 and 332 may isolate the output current IOUT1 from voltage disturbances from the supply voltage, thereby increasing power supply noise rejection. Additionally, controlling the output current IOUT1 at least in part using the level-shifted input signal 242 (provided by another section of the differential output buffer) may increase common-mode signal rejection.

[0033] Power regulator 311 may also supply or synchronize power to or from transistors 201 and 202. In some implementations, power regulator 311 may include transistors 334-337 and a capacitor 341. In the example of Figure 3, transistors 334-336 are shown as NMOS transistors and transistor 337 is shown as a PMOS transistor. In other implementations, transistors 334-337 may be any feasible type of transistor.

[0034] The transistor 334 may have a source coupled to ground, a drain coupled to a source of the transistor 336, and a gate coupled to a drain of the transistor 335 and a drain of the transistor 337. The source of the transistor 335 may be coupled to ground, the drain of the transistor 335 may be coupled to the drain of the transistor 337, and the gate of the transistor 335 may be coupled to a third bias voltage V3. The source of the transistor 337 may be coupled to the drain of the transistor 336, and the gate of the transistor 337 may be coupled to a fourth bias voltage V4. The source of the transistor 336 may be coupled to the drain of the transistor 334, and the gate of the transistor 336 may be coupled to the level-shifted input signal 243. In some implementations, the transistor 336 may control the output current IOUT2 ​​received by the transistors 201 and 202.

[0035] The bias voltages V3 and V4 may be generated by any feasible device or procedure. In some implementations, the transistors 335 and 337 are biased to enable the transistors 334 and 336 to provide the output current IOUT2 ​​based on the level-shifted input signal 243. In some aspects, the transistors 334 and 336 may isolate the output current IOUT2 ​​from voltage disturbances from ground, thereby increasing power supply (ground in this case) noise rejection. Additionally, controlling the output current IOUT2 ​​at least in part with the level-shifted input signal 243 (provided by another section of the differential output buffer) may increase common-mode signal rejection.

[0036] Current source 320 may include transistors 338 and 339 and may enable current reuse by linking current to or from power regulator 310 with current to or from power regulator 311. In some implementations, a gate of transistor 338 may be coupled to a fifth bias voltage V5 and a gate of transistor 339 may be coupled to a sixth bias voltage V6.

[0037] 4 shows a simplified circuit diagram of a second section 400 of a differential input buffer according to some implementations. The second differential input buffer section 400 may be one implementation of the second section 261 of the differential signal buffer 200 of FIG. 2. Thus, the second differential input buffer section 400 may include the transistors 203 and 204, the resistors 212 and 213, and the level shifters 222 and 223 as described with respect to FIG. 2. The second differential input buffer section 400 may also include power regulators 410 and 411, and a current source 420.

[0038] Power regulator 410 may be an implementation of power regulator 232 of FIG. 2 and may be similar to power regulator 310 of FIG. 3. In some implementations, power regulator 410 may include transistors 430-433 and capacitor 440. Transistors 430-433 and capacitor 440 may be configured in a manner similar to that of transistors 330-330 and capacitor 340 of FIG. 3, respectively. Thus, transistors 430 and 432 may provide current IOUT3 to transistors 203 and 204 based at least in part on level-shifted input signal 240. Similarly, power regulator 411 may be an implementation of power regulator 233 of FIG. 2 and may be similar to power regulator 311 of FIG. 3. In some implementations, power regulator 411 may include transistors 434-437 and capacitor 441. Transistors 434-437 and capacitor 441 may be configured in a manner similar to that of transistors 334-337 and capacitor 341, respectively, of FIG. 3. Thus, transistors 434 and 436 may provide current IOUT4 to transistors 203 and 204 based at least in part on level-shifted input signal 241. Current source 420 includes transistors 438 and 439, which may be configured in a manner similar to that of transistors 338 and 339, respectively, of FIG.

[0039] 5 shows a simplified circuit diagram of another implementation of differential input buffer section 500 according to some implementations. In some implementations, the power conditioners 310, 311, 410, and 411 described above may be simplified to reduce the number of components at the expense of a small reduction in power supply or ground noise rejection performance. The differential input buffer section 500 may be used in place of the first differential input buffer section 300 of FIG. 3 and / or the second differential input buffer section 400 of FIG. 4. The differential input buffer section 500 may include transistors 201 and 202, resistors 210 and 211, level shifters 220 and 221, and current source 320 configured as described with respect to FIG. 3.

[0040] Differential input buffer section 500 may include a first power regulator 510 and a second power regulator 511. Power regulator 510 may include transistors 330 and 332 and may be configured in a manner similar to that of power regulator 310 of FIG. 3. Thus, a source of transistor 330 may be coupled to a supply voltage, a drain of transistor 330 may be coupled to a source of transistor 332, and a gate of transistor 330 may be coupled to a drain of transistor 332 and current source 320. Similar to power regulator 310, a gate of transistor 332 may be coupled to a level-shifted input signal 242. An output current IOUT5 may be provided (e.g., sourced or synchronized) by transistors 330 and 332. In contrast to power regulator 310 of FIG. 3, power regulator 510 includes only two transistors (transistors 330 and 332). Thus, the design of power regulator 510 is simplified, includes fewer components, and has lower bias voltage requirements compared to power regulator 310 of Figure 3. In some implementations, power regulator 510 may have increased susceptibility to power supply noise. However, advantages of power regulator 510 may include reduced area and simpler implementation.

[0041] Power regulator 511 includes transistors 334 and 336 and may be configured in a manner similar to that of power regulator 311. Thus, the source of transistor 334 may be coupled to ground, the drain of transistor 334 may be coupled to the source of transistor 336, and the gate of transistor 334 may be coupled to the drain of transistor 336 and to current source 320. The gate of transistor 336 may be coupled to level-shifted input signal 243. An output current IOUT6 may be provided by transistors 334 and 336. Current source 320 may function as described above with respect to FIG.

[0042] FIG. 6 illustrates a simplified circuit diagram of another implementation of a differential input buffer section 600 according to some implementations. In some cases, the noise associated with the power supply may be greater than the noise associated with the ground, and therefore, to simplify the implementation, the power conditioner configured to reduce the ground noise may be omitted. The differential input buffer section 600 is similar to the first differential input buffer section 300 of FIG. 3, with the power conditioner 311 omitted. Thus, the differential input buffer section 600 may include transistors 201 and 202, resistors 210 and 211, level shifters 220 and 221, power conditioner 310, and current source 320. The transistors 201, 202, 330-333, 338, and 339, resistors 210 and 211, level shifters 220 and 221, and capacitor 340 may be configured as described with respect to FIG. 3. Also, the source of transistor 202 and current source 320 may be coupled to ground. In some other implementations, power regulator 310 may be replaced with power regulator 510 of FIG. 5, further simplifying the implementation of differential input buffer section 600.

[0043] 7 shows an example flowchart illustrating example operations 700 for operating a differential input buffer according to some implementations. The operations 700 may be used to operate the differential signal buffer 200 of FIG. 2 or any other possible differential input buffer.

[0044] The operations 700 may begin with a differential input buffer receiving a differential input signal (702). With reference also to Figures 3 and 4, the differential input signal may include complementary input signals VIN_N and VIN_P. In some implementations, the differential input signal may be received by differential input buffer section 300 of Figure 3 and differential input buffer section 400 of Figure 4.

[0045] The operations 700 may proceed to generating (704) a first current for the differential input buffer based on the first level-shifted input signal. The differential input buffer sections 300 and 400 may include power regulators 310, 311, 410, and 411. The power regulator 310 may generate the first current for the differential input buffer section 300 based on the first level-shifted input signal 242. In some implementations, the first level-shifted input signal 242 may be received by a gate of a transistor in the power regulator 310. For example, the first level-shifted input signal 242 may be received by a gate of the transistor 332 to generate the first current.

[0046] The operations 700 may proceed to generating (706) a second current for the differential input buffer based on the second level-shifted input signal. In some implementations, the power regulator 410 may generate the second current for the differential input buffer section 400 based on the second level-shifted input signal 240. In some implementations, the second level-shifted input signal 240 may be received by a gate of a transistor in the power regulator 410. For example, the second level-shifted input signal 240 may be received by a gate of the transistor 432 to generate the second current.

[0047] The operations 700 may proceed to generating (708) a third current for the differential input buffer based on the third level-shifted input signal. This operation may be optional, as indicated by the dashed line. In some implementations, the power regulator 311 may generate a third current for the differential input buffer section 300 based on the third level-shifted input signal 243. In some implementations, the third level-shifted input signal 243 may be received by a gate of a transistor in the power regulator 311. For example, the third level-shifted input signal 243 may be received by a gate of the transistor 336 to generate the third current.

[0048] The operations 700 may proceed to generating (710) a fourth current for the differential input buffer based on the fourth level-shifted input signal. This operation may be optional, as indicated by the dashed line. In some implementations, the power regulator 411 may generate a fourth current for the differential input buffer section 400 based on the fourth level-shifted input signal 241. In some implementations, the fourth level-shifted input signal 241 may be received by a gate of a transistor in the power regulator 411. For example, the fourth level-shifted input signal 241 may be received by a gate of the transistor 436 to generate the fourth current.

[0049] The operations 700 may proceed to generating (712) a differential output signal based on the first current, the second current, and optionally the third current and the fourth current. In some implementations, the first current from power regulator 310 and the second current from power regulator 410 may be used to generate the differential output signal. In some other implementations, the third current from power regulator 311 and the fourth current from power regulator 411 may also be used to generate the differential output signal.

[0050] Those skilled in the art will appreciate that information and signals may be represented using any of a variety of different technologies and techniques. For example, the data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0051] Those skilled in the art will also appreciate that the various exemplary logic blocks, modules, circuits, and algorithm steps described in connection with the aspects disclosed herein may be implemented as electronic hardware, computer software, or a combination thereof. To clearly illustrate this interchangeability of hardware and software, various exemplary components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the particular application and design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

[0052] The methods, sequences, or algorithms described in connection with the aspects disclosed herein may be embodied directly in hardware, in software modules executed by a processor, or in a combination of the two. The software modules may reside in RAM latches, flash latches, ROM latches, EPROM latches, EEPROM latches, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. Alternatively, the storage medium may be integral to the processor.

[0053] In the foregoing specification, example implementations have been described with reference to specific example implementations thereof. It will be apparent, however, that various modifications and changes may be made thereto without departing from the broader scope of the disclosure as set forth in the appended claims.

Claims

1. A differential signal buffer (200), comprising: a first buffer circuit (260) configured to receive the first level-shifted differential signal (240), said first buffer circuit (260) comprising: a first NMOS transistor (202); a first PMOS transistor (201), the drain of the first NMOS transistor (202) being coupled to the drain of the first PMOS transistor (201), the first buffer circuit (260) further comprising: a first power conditioner (230) coupled to a source of the first PMOS transistor (201) and configured to receive a second level-shifted differential signal (242), the differential signal buffer (200) further comprising: a second buffer circuit (261) configured to receive the second level-shifted differential signal (242), the second buffer circuit (261) comprising: a second NMOS transistor (204); and a second PMOS transistor (203), the drain of the second NMOS transistor (204) being coupled to the drain of the second PMOS transistor (203), the second buffer circuit (261) further comprising: a second power conditioner (232) coupled to a source of the second PMOS transistor (203) and configured to receive the first level-shifted differential signal (240); the first buffer circuit (260) is configured to buffer the first level-shifted differential signal (240) based on the second level-shifted differential signal (242), and the second buffer circuit (261) is configured to buffer the second level-shifted differential signal (242) based on the first level-shifted differential signal (240); The first power regulator (230) is configured to provide a first current to the first NMOS transistor (202) and the first PMOS transistor (201) based on the second level-shifted differential signal (242).

2. 2. The differential signal buffer of claim 1, wherein the second power regulator is configured to provide a second current to the second NMOS transistor and the second PMOS transistor based on the first level-shifted differential signal.

3. The first power regulator (510) a third PMOS transistor (330); and a fourth PMOS transistor (332); 2. The differential signal buffer of claim 1, wherein a source of the third PMOS transistor is coupled to a power supply, a drain of the third PMOS transistor is coupled to a source of the fourth PMOS transistor, and a gate of the fourth PMOS transistor is configured to receive the second level-shifted differential signal.

4. 4. The differential signal buffer of claim 3, wherein the first current is provided by at least one of the third PMOS transistor or the fourth PMOS transistor.

5. The first power regulator (310) further comprises: A fifth PMOS transistor (331); a third NMOS transistor (333); 4. The differential signal buffer (300) of claim 3, wherein a source of the fifth PMOS transistor (331) is coupled to the power supply, a drain of the fifth PMOS transistor (331) is coupled to a drain of the third NMOS transistor (333), and a source of the third NMOS transistor (333) is coupled to a drain of the fourth PMOS transistor (332).

6. 6. The differential signal buffer of claim 5, further comprising: a capacitor coupled between the source and the drain of the third NMOS transistor and configured to provide a high frequency path between the source and the drain of the third NMOS transistor.

7. 2. The differential signal buffer of claim 1, wherein the first buffer circuit further comprises a third power regulator circuit configured to provide a third current to the first NMOS transistor and the first PMOS transistor based on a third level-shifted differential signal.

8. The third power regulator circuit (511) comprises: a fourth NMOS transistor (334); a fifth NMOS transistor (336); 8. The differential signal buffer (500) of claim 7, wherein a source of the fourth NMOS transistor (334) is coupled to ground, a drain of the fourth NMOS transistor (334) is coupled to a source of the fifth NMOS transistor (336), and a gate of the fifth NMOS transistor (336) is configured to receive the third level-shifted differential signal (243).

9. The third power regulator circuit (311) further comprises: a sixth NMOS transistor (335); a sixth PMOS transistor (337); 9. The differential signal buffer (300) of claim 8, wherein a source of the sixth NMOS transistor (335) is coupled to ground, a drain of the sixth NMOS transistor (335) is coupled to a drain of the sixth PMOS transistor (337), and a source of the sixth PMOS transistor (337) is coupled to a drain of a fifth NMOS transistor (336).

Images