Low-noise dynamic ring amplifier based on variable dead-zone voltage

Abstract

The invention relates to a low-noise dynamic ring amplifier based on variable dead-zone voltage. The amplifier comprises a ring amplifier unit and a noise reduction unit, the input end of the noise reduction unit is connected with a two-phase non-overlapping clock signal, and the noise reduction unit is used for responding to the two-phase non-overlapping clock signal and generating a plurality of bias voltages; wherein when the two-phase non-overlapping clock signal meets a first preset condition, a first bias voltage and a second bias voltage are correspondingly generated; when the two-phase non-overlapping clock signal meets a second preset condition, attenuating the first bias voltage to a first threshold value to generate a third bias voltage, and pulling up the second bias voltage to a second threshold value to generate a fourth bias voltage; and the ring amplifier unit dynamically adjusts the dead-zone voltage in the ring amplifier unit by using a plurality of bias voltages, so that the noise bandwidth of the ring amplifier unit is adjusted in real time. The device can meet the requirements of high bandwidth and low noise without increasing power consumption.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuit design, and in particular relates to a low-noise dynamic ring amplifier based on variable dead zone voltage. Background Art

[0002] As the process size continues to shrink, the power supply voltage decreases, and the intrinsic gain of transistors decreases, the design of analog circuits becomes increasingly difficult. For example, the margin amplifier used in pipeline analog-to-digital converters needs to meet the requirements of bandwidth, noise, linearity, power consumption, etc. For traditional transconductance operational amplifiers, their energy efficiency is low and the output swing is small. The ring amplifier is currently an amplifier suitable for low-voltage nanoscale processes. It consists of three stages, has a large gain, does not require frequency compensation, and has extremely high energy efficiency. In addition, the ring amplifier can provide an output swing that is almost rail-to-rail.

[0003] In some applications, amplifiers need to meet the requirements of high bandwidth and low noise at the same time. However, bandwidth and noise are two mutually exclusive parameters. The larger the bandwidth, the greater the noise. Under the premise of maintaining the same bandwidth, more power consumption is required to obtain lower noise. In other words, it is difficult for existing ring amplifiers to meet the requirements of high bandwidth and low noise without increasing power consumption. Summary of the invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a low-noise dynamic ring amplifier based on variable dead zone voltage. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0005] The present invention provides a low-noise dynamic ring amplifier based on variable dead zone voltage, comprising: a ring amplifier unit and a noise reduction unit; the noise reduction unit, whose input end is connected to a two-phase non-overlapping clock signal, is used to generate multiple bias voltages in response to the two-phase non-overlapping clock signal; wherein, when the two-phase non-overlapping clock signal meets a first preset condition, a first bias voltage and a second bias voltage are correspondingly generated; when the two-phase non-overlapping clock signal meets a second preset condition, the first bias voltage is attenuated to a first threshold value to generate a third bias voltage, and the second bias voltage is pulled up to a second threshold value to generate a fourth bias voltage; the voltage amplitude of the first bias voltage is greater than the voltage amplitude of the second bias voltage; the ring amplifier unit is used to dynamically adjust the dead zone voltage inside the ring amplifier unit by using the multiple bias voltages, thereby adjusting the noise bandwidth of the ring amplifier unit in real time.

[0006] In some embodiments, the two-phase non-overlapping clock signal includes: an amplified phase clock signal Φ A and reset phase clock signal Φ R .

[0007] In some embodiments, the first preset condition is: A is a low level signal, and the reset phase clock signal Φ R is a high level signal; the second preset condition is: the amplified phase clock signal Φ A is a high level signal, and the reset phase clock signal Φ R It is a low level signal.

[0008] In some embodiments, the noise reduction unit includes: a first noise reduction module and a second noise reduction module; wherein the first noise reduction module is connected to the amplified phase clock signal Φ A The second noise reduction module is connected to the reset phase clock signal Φ R ; The first noise reduction module is used to generate the first bias voltage and the third bias voltage, and the second noise reduction module is used to generate the second bias voltage and the fourth bias voltage.

[0009] In some embodiments, the first noise reduction module includes: a reset transistor M RP1 , charge and discharge transistor M N4 and capacitor C N1 ; Wherein, the reset transistor M RP1 The source is connected to the power supply VDD, and the gate and the charge and discharge transistor M N4 The gate of the amplifier is connected to the amplified phase clock signal Φ A The reset transistor M RP1 The drain of the charge and discharge transistor M N4 The drain and the capacitor C N1 The first end of the capacitor C N1 The first end of the charging and discharging transistor M is also used as the output end of the first noise reduction module and is connected to the first input end of the ring amplifier unit. N4 The source and the capacitor C N1 The second end is grounded.

[0010] In some embodiments, the second noise reduction module includes: a reset transistor M RN1 , charge and discharge transistor M P4 and capacitor C P1 ; Wherein, the charge and discharge transistor M P4 The source is connected to the power supply VDD, and the gate and the reset transistor M RN1 The gate of the reset phase clock signal Φ R ; The charge and discharge transistor M P4 The drain of the reset transistor M RN1 The drain and the capacitor C P1 The first end of the capacitor CP1 The first end of the capacitor C is also used as the output end of the second noise reduction module and is connected to the second input end of the ring amplifier unit. P1 The second terminal and the reset transistor M RN1 The source is grounded.

[0011] In some embodiments, the ring amplifier unit includes: a first-stage operational amplifier module, a second-stage operational amplifier module and a third-stage operational amplifier module connected in series in sequence; wherein the second-stage operational amplifier module is respectively connected to the first noise reduction module and the second noise reduction module.

[0012] In some embodiments, the ring amplifier unit includes: a first-stage operational amplifier module, a second-stage operational amplifier module and a third-stage operational amplifier module connected in series in sequence; wherein the second-stage operational amplifier module is respectively connected to the first noise reduction module and the second noise reduction module.

[0013] In some embodiments, the second stage operational amplifier module includes: MOS tube M P2 、MOS tube M N2 、CMOS tube M PB1 And CMOS tube M NB1 ; The MOS tube M P2 The source of the MOS tube M is connected to the power supply VDD. P2 The gate of the second stage op amp module is used as the third input terminal of the second stage op amp module, and is respectively connected to the MOS tube M N2 The gate of the first stage operational amplifier module is connected, and the drain is connected to the CMOS tube M PB1 The source and the CMOS tube M NB1 The drain connection of the MOS tube M P2 The drain of the MOS tube M also serves as the first output terminal of the second-stage operational amplifier module and is connected to the first input terminal of the third-stage operational amplifier module; N2 The drain of the CMOS tube M PB1 The drain and the CMOS tube M NB1 The source of the MOS tube M N2 The drain of the MOS tube M also serves as the second output terminal of the second stage operational amplifier module and is connected to the second input terminal of the third stage operational amplifier module. N2 The source of the CMOS tube M is grounded; PB1 The gate of the CMOS tube M is used as the second input terminal of the second stage operational amplifier module and connected to the output terminal of the second noise reduction module. NB1 The gate of the second-stage operational amplifier module is used as the first input terminal in the second-stage operational amplifier module and is connected to the output terminal of the first noise reduction module.

[0014] In some embodiments, the third-stage operational amplifier module includes: MOS tube M P3 And MOS tube M N3 ; The MOS tube M P3 The source is connected to the power supply VDD, the gate is connected to the first output terminal of the second-stage operational amplifier module, and the drain is connected to the MOS tube M N3 The drain of the MOS tube M is connected to serve as the output end of the ring amplifier unit; N3 The gate is connected to the second output terminal of the second-stage operational amplifier module, and the source is grounded.

[0015] Compared with the prior art, the present invention has the following beneficial effects:

[0016] In view of the problem that existing ring amplifiers are difficult to meet the requirements of high bandwidth and low noise without increasing power consumption, the present invention provides a low-noise dynamic ring amplifier based on variable dead zone voltage. The noise reduction unit in the ring amplifier is connected to a two-phase non-overlapping clock signal, and generates multiple bias voltages in response to the two-phase non-overlapping clock signal, and generates the multiple bias voltages to the ring amplifier unit to dynamically adjust the dead zone voltage inside the ring amplifier unit, thereby adjusting the size of the noise bandwidth of the ring amplifier unit in real time. Without changing the signal bandwidth and increasing additional power consumption, the noise of the ring amplifier is reduced, which can meet the requirements of high bandwidth and low noise without increasing power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a structural block diagram of a low-noise dynamic ring amplifier based on variable dead zone voltage provided by an embodiment of the present invention;

[0018] Figure 2 is a schematic diagram of changes in a two-phase non-overlapping clock signal provided by an embodiment of the present invention;

[0019] Figure 3 is a circuit connection diagram of a ring amplifier unit provided by an embodiment of the present invention;

[0020] Figure 4 Schematic diagram of circuit connection of the noise reduction unit provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0021] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0022] In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0023] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification.

[0024] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art may understand and implement other variations of the disclosed embodiments by viewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "one" or "an" does not exclude multiple situations. A single processor or other unit may implement several functions listed in the claims. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0025] Now, in conjunction with the accompanying drawings, a low-noise dynamic ring amplifier based on variable dead zone voltage provided by the present invention is described in detail.

[0026] Figure 1 is a structural block diagram of a low-noise dynamic ring amplifier based on a variable dead zone voltage provided by an embodiment of the present invention. Figure 1As shown, the amplifier includes: a ring amplifier unit and a noise reduction unit; the noise reduction unit, whose input end is connected to a two-phase non-overlapping clock signal, is used to generate multiple bias voltages in response to the two-phase non-overlapping clock signal; wherein, when the two-phase non-overlapping clock signal meets a first preset condition, a first bias voltage and a second bias voltage are correspondingly generated; when the two-phase non-overlapping clock signal meets a second preset condition, the first bias voltage is attenuated to a first threshold value to generate a third bias voltage, and the second bias voltage is pulled up to a second threshold value to generate a fourth bias voltage; the voltage amplitude of the first bias voltage is greater than the voltage amplitude of the second bias voltage; the ring amplifier unit is used to dynamically adjust the dead zone voltage inside the ring amplifier unit using multiple bias voltages, thereby adjusting the noise bandwidth of the ring amplifier unit in real time.

[0027] Here, the two-phase non-overlapping clock signal includes: the amplified phase clock signal Φ A and reset phase clock signal Φ R . Figure 2 Schematic diagram of the change of the two-phase non-overlapping clock signal provided by the embodiment of the present invention. Figure 2 As shown, the amplified phase clock signal Φ A When high, the reset phase clock signal Φ R is low level, the amplified phase clock signal Φ A When it is low, the reset phase clock signal Φ R In a possible implementation, the first preset condition is: the amplified phase clock signal Φ A is a low level signal, and the reset phase clock signal Φ R is a high level signal. And, the second preset condition is: the amplified phase clock signal Φ A is a high level signal, and the reset phase clock signal Φ R It is a low level signal.

[0028] Here, the circuit connection relationship of the low-noise dynamic ring amplifier based on variable dead-zone voltage provided by the embodiment of the present invention is described. Figure 3 FIG. 1 is a circuit connection diagram of a ring amplifier unit provided in an embodiment of the present invention. Figure 3 As shown, the ring amplifier unit includes: a first-stage operational amplifier module, a second-stage operational amplifier module and a third-stage operational amplifier module which are sequentially connected in series; wherein the second-stage operational amplifier module is respectively connected to the first noise reduction module and the second noise reduction module.

[0029] Here, the first-stage operational amplifier module includes: MOS tube M P1 And MOS tube M N1 ;MOS tube M P1 The gate and MOS tube M N1 The gate of the MOS tube M is connected to serve as the input end of the ring amplifier unit;P1 The source is connected to the power supply VDD, and the drain is connected to the MOS tube M N1 The drain of the second stage operational amplifier module is connected to the third input terminal, and the MOS tube M N1 The source is grounded.

[0030] And, the second stage operational amplifier module includes: MOS tube M P2 、MOS tube M N2 、CMOS tube M PB1 And CMOS tube M NB1 ;MOS tube M P2 The source of the MOS tube M is connected to the power supply VDD. P2 The gate of the second stage op amp module is used as the third input terminal, and is connected to the MOS tube M N2 The gate of the first stage operational amplifier module is connected, and the drain is connected to the CMOS tube M PB1 The source and CMOS tube M NB1 The drain connection of MOS tube M P2 The drain of the MOS tube M also serves as the first output terminal of the second-stage operational amplifier module and is connected to the first input terminal of the third-stage operational amplifier module; N2 The drain of CMOS tube M PB1 The drain and CMOS tube M NB1 The source connection of MOS tube M N2 The drain of the MOS tube M is also used as the second output terminal of the second stage operational amplifier module and connected to the second input terminal of the third stage operational amplifier module. N2 The source of the CMOS tube is grounded; PB1 The gate of the CMOS tube M is used as the second input terminal in the second stage operational amplifier module and connected to the output terminal of the second noise reduction module. NB1 The gate is used as the first input terminal in the second-stage operational amplifier module and is connected to the output terminal of the first noise reduction module.

[0031] And, the third-level operational amplifier module includes: MOS tube M P3 And MOS tube M N3 ;MOS tube M P3 The source is connected to the power supply VDD, the gate is connected to the first output terminal of the second-stage operational amplifier module, and the drain is connected to the MOS tube M N3 The drain of the MOS tube M is connected to serve as the output end of the ring amplifier unit; N3 The gate is connected to the second output terminal in the second-stage operational amplifier module, and the source is grounded.

[0032] Figure 4 Schematic diagram of the circuit connection of the noise reduction unit provided in the embodiment of the present invention. Figure 4As shown, the noise reduction unit includes: a first noise reduction module and a second noise reduction module; wherein the first noise reduction module is connected to the amplified phase clock signal Φ A , the second noise reduction module is connected to the reset phase clock signal Φ R The first noise reduction module is used to generate a first bias voltage and a third bias voltage, and the second noise reduction module is used to generate a second bias voltage and a fourth bias voltage. The first noise reduction module includes: a reset transistor M RP1 , charge and discharge transistor M N4 and capacitor C N1 ; Among them, the reset transistor M RP1 The source is connected to the power supply VDD, the gate and the charge and discharge transistor M N4 The gate of the amplifier is connected to the phase clock signal Φ A ; Reset transistor M RP1 The drain of the charge and discharge transistor M N4 The drain and capacitor C N1 The first end of the capacitor C N1 The first end of the first noise reduction module is also used as the output end of the first noise reduction module, and is connected to the first input end of the ring amplifier unit. N4 The source and capacitor C N1 The second end is grounded.

[0033] And, the second noise reduction module includes: a reset transistor M RN1 , charge and discharge transistor M P4 and capacitor C P1 ; Among them, the charge and discharge transistor M P4 The source of the transistor is connected to the power supply VDD, the gate and the reset transistor M RN1 The gate is connected to the reset phase clock signal Φ R ; Charge and discharge transistor M P4 The drain of the reset transistor M RN1 The drain and capacitor C P1 The first end of the capacitor C P1 The first end of the capacitor C is also used as the output end of the second noise reduction module and is connected to the second input end of the ring amplifier unit. P1 The second terminal and the reset transistor M RN1 The source is grounded.

[0034] Based on the above circuit connection, the implementation process of the technical solution provided by the embodiment of the present invention is now described.

[0035] For example, when the amplified phase clock signal Φ A is a low level signal, and the reset phase clock signal Φ R When the signal is high, the noise reduction unit is in a reset state. At this time, in the first noise reduction module, the reset transistor M RP1 To capacitor CN1 Quickly charge to the highest potential (VDD) so that the capacitor C N1 The voltage V at the first terminal BH Rapidly pull up to obtain the first bias voltage; in the second noise reduction module, reset transistor M RN1 For capacitor C P1 Gradually discharge the capacitor C P1 The voltage V at the first terminal BL It quickly decays to the lowest potential (GND) to obtain the second bias voltage.

[0036] And, when the amplified phase clock signal Φ A is a high level signal, and the reset phase clock signal Φ R When the signal is low level, the noise reduction unit performs noise reduction. In the first noise reduction module, the charge and discharge transistor M N4 With current I N For capacitor C N1 Gradually discharges, causing the capacitor C N1 The voltage V at the first terminal BH The voltage gradually decays and stops when the first threshold is reached, thereby obtaining a third bias voltage; and in the second noise reduction module, the charge-discharge transistor M P4 Gradually charge the capacitor C P1 The voltage V at the first terminal BL , and stops when reaching the second threshold, obtaining a fourth bias voltage. N1 The voltage V at the first terminal BH and capacitor C P1 The voltage V at the first terminal BL When changes occur, drive Figure 3 MOS tube M in P2 The voltage value at the drain is V BP Increase and MOS tube M N2 The voltage value at the drain is V BN Here, the dead zone voltage V DZ It can be expressed as: V BP -V BN ; Dead zone voltage V DZ Gradually increasing it can cause the noise bandwidth inside the ring amplifier unit to gradually decrease. Since bandwidth and noise are two mutually exclusive parameters, the larger the bandwidth, the greater the noise. Moreover, in the time period when the noise bandwidth gradually decreases, the signal bandwidth in the initial stage is large, and the signal bandwidth in the subsequent stage is small. The overall average signal bandwidth does not change, thus achieving noise reduction of the ring amplifier without increasing additional power consumption and changing the signal bandwidth.

[0037] In view of the problem that existing ring amplifiers are difficult to meet the requirements of high bandwidth and low noise without increasing power consumption, the present invention provides a low-noise dynamic ring amplifier based on variable dead zone voltage. The noise reduction unit in the ring amplifier is connected to a two-phase non-overlapping clock signal, and generates multiple bias voltages in response to the two-phase non-overlapping clock signal, and generates the multiple bias voltages to the ring amplifier unit to dynamically adjust the dead zone voltage inside the ring amplifier unit, thereby adjusting the size of the noise bandwidth of the ring amplifier unit in real time. Without changing the signal bandwidth and increasing additional power consumption, noise reduction of the input external electrical signal is achieved, which can meet the requirements of high bandwidth and low noise without increasing power consumption.

[0038] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A low noise dynamic ring amplifier based on variable dead zone voltage, characterized in that: include: Ring amplifier unit and noise reduction unit; The noise reduction unit, whose input end is connected to a two-phase non-overlapping clock signal, is used to generate a plurality of bias voltages in response to the two-phase non-overlapping clock signal; wherein, when the two-phase non-overlapping clock signal meets a first preset condition, a first bias voltage and a second bias voltage are correspondingly generated; when the two-phase non-overlapping clock signal meets a second preset condition, the first bias voltage is attenuated to a first threshold value to generate a third bias voltage, and the second bias voltage is pulled up to a second threshold value to generate a fourth bias voltage; the voltage amplitude of the first bias voltage is greater than the voltage amplitude of the second bias voltage; The ring amplifier unit is used to dynamically adjust the dead zone voltage inside the ring amplifier unit by using the multiple bias voltages, thereby adjusting the noise bandwidth of the ring amplifier unit in real time.

2. The low noise dynamic ring amplifier based on variable dead zone voltage according to claim 1, characterized in that: The two-phase non-overlapping clock signal includes: an amplified phase clock signal Φ A and reset phase clock signal Φ R .

3. The low noise dynamic ring amplifier based on variable dead zone voltage according to claim 2, characterized in that: The first preset condition is: the amplified phase clock signal Φ A is a low level signal, and the reset phase clock signal Φ R is a high level signal; the second preset condition is: the amplified phase clock signal Φ A is a high level signal, and the reset phase clock signal Φ R It is a low level signal.

4. The low noise dynamic ring amplifier based on variable dead zone voltage according to claim 2, characterized in that: The noise reduction unit includes: a first noise reduction module and a second noise reduction module; wherein the first noise reduction module is connected to the amplified phase clock signal Φ A The second noise reduction module is connected to the reset phase clock signal Φ R ; The first noise reduction module is used to generate the first bias voltage and the third bias voltage, and the second noise reduction module is used to generate the second bias voltage and the fourth bias voltage.

5. The low noise dynamic ring amplifier based on variable dead zone voltage according to claim 4, characterized in that: The first noise reduction module includes: a reset transistor M RP1 , charge and discharge transistor M N4 and capacitor C N1 ; Wherein, the reset transistor M RP1 The source is connected to the power supply VDD, and the gate and the charge and discharge transistor M N4 The gate of the amplifier is connected to the amplified phase clock signal Φ A The reset transistor M RP1 The drain of the charge and discharge transistor M N4 The drain and the capacitor C N1 The first end of the capacitor C N1 The first end of the charging and discharging transistor M is also used as the output end of the first noise reduction module and is connected to the first input end of the ring amplifier unit. N4 The source and the capacitor C N1 The second end is grounded.

6. The low noise dynamic ring amplifier based on variable dead zone voltage according to claim 4, characterized in that: The first noise reduction module and the second noise reduction module. The second noise reduction module includes: a reset transistor M RN1 , charge and discharge transistor M P4 and capacitor C P1 ; Wherein, the charge and discharge transistor M P4 The source is connected to the power supply VDD, and the gate and the reset transistor M RN1 The gate of the reset phase clock signal Φ R ; The charge and discharge transistor M P4 The drain of the reset transistor M RN1 The drain and the capacitor C P1 The first end of the capacitor C P1 The first end of the capacitor C is also used as the output end of the second noise reduction module and is connected to the second input end of the ring amplifier unit. P1 The second terminal and the reset transistor M RN1 The source is grounded.

7. The low noise dynamic ring amplifier based on variable dead zone voltage according to claim 4, characterized in that: The ring amplifier unit comprises: a first-stage operational amplifier module, a second-stage operational amplifier module and a third-stage operational amplifier module connected in series in sequence; wherein the second-stage operational amplifier module is connected to the first noise reduction module and the second noise reduction module respectively.

8. The low noise dynamic ring amplifier based on variable dead zone voltage according to claim 7, characterized in that: The first-stage operational amplifier module includes: MOS tube M P1 And MOS tube M N1 ; The MOS tube M P1 The gate and the MOS tube M N1 The gate of the MOS tube M is connected to serve as the input end of the ring amplifier unit; P1 The source is connected to the power supply VDD, and the drain is connected to the MOS tube M N1 The drain of the MOS tube M is connected to the third input terminal of the second stage operational amplifier module. N1 The source is grounded.

9. The low noise dynamic ring amplifier based on variable dead zone voltage according to claim 7, characterized in that: The second-stage operational amplifier module includes: MOS tube M P2 、MOS tube M N2 、CMOS tube M PB1 And CMOS tube M NB1 ; The MOS tube M P2 The source of the MOS tube M is connected to the power supply VDD. P2 The gate of the second stage op amp module is used as the third input terminal, and is connected to the MOS tube M N2 The gate of the first stage operational amplifier module is connected, and the drain is connected to the CMOS tube M PB1 The source and the CMOS tube M NB1 The drain connection of the MOS tube M P2 The drain of the second stage operational amplifier module also serves as the first output terminal of the second stage operational amplifier module, and is connected to the first input terminal of the third stage operational amplifier module; The MOS tube M N2 The drain of the CMOS tube M PB1 The drain and the CMOS tube M NB1 The source of the MOS tube M N2 The drain of the MOS tube M also serves as the second output terminal of the second stage operational amplifier module and is connected to the second input terminal of the third stage operational amplifier module. N2 The source is grounded; The CMOS tube M PB1 The gate of the CMOS tube M is used as the second input terminal of the second stage operational amplifier module and connected to the output terminal of the second noise reduction module. NB1 The gate of the second-stage operational amplifier module is used as the first input terminal in the second-stage operational amplifier module and is connected to the output terminal of the first noise reduction module.

10. The low noise dynamic ring amplifier based on variable dead zone voltage according to claim 7, characterized in that: The third-stage operational amplifier module includes: MOS tube M P3 And MOS tube M N3 ; The MOS tube M P3 The source is connected to the power supply VDD, the gate is connected to the first output terminal of the second-stage operational amplifier module, and the drain is connected to the MOS tube M N3 The drain of the ring amplifier unit is connected to serve as the output terminal of the ring amplifier unit; The MOS tube M N3 The gate is connected to the second output terminal of the second-stage operational amplifier module, and the source is grounded.

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