Semiconductor Cutoff Circuit

Abstract

To provide a semiconductor interruption circuit with an excellent light-weight property.SOLUTION: A semiconductor interruption circuit 1 comprises: a plurality of distribution paths kp1 to kp3 and kn1 to kn3 for transmitting a DC current distributed from common buses kp and kn connected with a DC power supply to a plurality of loads, respectively; a plurality of switch parts Sp1 to Sp3 and Sn1 to Sn3 provided on the plurality of distribution paths kp1 to kp3 and kn1 to kn3, respectively, each being configured by a semiconductor element; and energy absorption parts 10p and 10n that have capacitors Cap and Can, first diode bridges Dp1 and Dn1, and second diode bridges Dp21 to Dp23 and Dn21 to Dn23, respectively.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor shutoff circuit including a switch formed of a semiconductor element. [Background technology]

[0002] The DC grid of an electric aircraft is configured to quickly isolate the fault point and switch the connection so that the remaining healthy equipment can continue to operate even if some of the equipment fails. Therefore, DC circuit breakers that quickly isolate while limiting the fault current are considered to be important parts in electric aircraft. For example, Figure 86 of the following Non-Patent Document 1 shows the configuration of a redundant switching system. In this configuration, 72 DC circuit breakers are used.

[0003] In Figure 1 of Non-Patent Document 2 below, a multi-terminal power distribution configuration is proposed in which DC power is supplied to each load via multiple SSPCs (Solid State Power Controllers). When the load current exceeds a predetermined value, the SSPC shuts off the semiconductor element and leads the current to zero while processing the energy of the wiring inductor. In Figure 2 of Non-Patent Document 3 below, the configuration of an SSCB (Solid-state circuit breaker) using a SiC power semiconductor device is described. This SSCB is configured such that an avalanche diode for absorbing energy is connected in parallel to semiconductor elements connected in series in both directions. [Prior art documents] [Non-patent literature]

[0004] [Non-Patent Document 1] Michael Armstrong, “Stability, Transient ReSponse, Control, and Safety of a High-Power Electric Grid for Turboelectric Propulsion of Aircraft”, (US) NASA / CR-2013-217865, January 1, 2013, Figure 76. [Non-Patent Document 2] A. Barrado, et al. “Behavioural Modeling of Solid State Power Controllers (SSPC) for Distributed Power Systems”, (US) 10.1109 / APEC.2009.4802897, IEEE, 21 March, 2009, Figure 1. [Non-Patent Document 3] J.Hayes. et al. “Bidirectional, SiC module-based solid-state circuit breakers for 270 Vdc MEA / AEA systems”, 2016 IEEE 4th Workshop on Wide Bandgap Power Devices and Applications, (US) 10.1109 / WiPDA.2016.7799912, IEEE, 29 December, 2016, Figure 2. [Summary of the Invention] [Problems to be Solved by the Invention]

[0005] The inventor has found that when a multi-terminal power distribution system is configured with the above SSPC configuration, the following problems arise. First, the number of SSCBs increases due to the redundant configuration of the power distribution system. All SSCBs must be equipped with independent avalanche diodes and other energy absorbing parts. This increases the capacity of the device and increases its weight. Second, in the above SSCB configuration, the time it takes to absorb energy during interruption is determined by the magnitude of the avalanche diode voltage. Therefore, it is not possible to change the interruption speed depending on the situation. For example, when the load is light, it is not possible to adjust the interruption speed to place more importance on current limiting than interruption. Furthermore, since the technical concept of the above SSCB is to interrupt current, it is necessary to provide a current limiter externally. Or, it is necessary to connect a current limiting reactor externally. As a result, the weight increases.

[0006] SUMMARY OF THE PRESENT EMBODIMENTS Accordingly, an object of the present invention is to provide a semiconductor cutoff circuit that is lightweight. [Means for solving the problem]

[0007] A semiconductor cutoff circuit in an embodiment of the present invention includes a plurality of power distribution paths that transmit a DC current distributed from a common bus connected to a DC power source to a plurality of loads, a plurality of switch units formed of semiconductor elements and provided in each of the plurality of power distribution paths, a capacitor connected between the common bus and the power distribution path on the load side of each of the plurality of switch units, and an energy absorption unit having a first diode bridge provided between the common bus and the capacitor, and a plurality of second diode bridges provided between the capacitor and the power distribution path on the load side of each of the plurality of switch units. Effect of the Invention

[0008] According to the present invention, it is possible to provide a semiconductor cutoff circuit that is lightweight. [Brief description of the drawings]

[0009] [Figure 1]FIG. 2 is a diagram showing a configuration example of a semiconductor cutoff circuit according to an embodiment of the present invention. [Diagram 2] FIG. 4 is a diagram showing an example of a change in load current and voltage across a switch section during a fault. [Diagram 3] FIG. 4 is a diagram for explaining the relationship between the cutoff speed and the initial charging voltage. [Figure 4] A diagram showing a detailed configuration example of the switch section and the energy absorption circuit shown in FIG. 1. [Diagram 5] 4 is a diagram showing an example of a load current and a voltage across a switch unit that are controlled; [Figure 6] 13 is a diagram showing another example of the load current and the voltage across the switch unit to be controlled. FIG. [Figure 7] FIG. 13 is a diagram showing a modified example of the configuration of the switch unit. [Figure 8] FIG. 1 is a diagram showing an example of the configuration of a DC grid system according to an embodiment of the present invention. [Figure 9] FIG. 13 is a diagram showing a modified example of the configuration of the semiconductor cutoff circuit in the embodiment. [Figure 10] FIG. 13 is a diagram showing an example of the configuration of a reactor group when there are two power distribution paths (n=2). [Figure 11] 11 is a graph showing the results of a simulation of the load current at a fault location and the load current at a healthy location when a short-circuit fault occurs in the reactor group configuration shown in FIG. 10. [Figure 12] FIG. 13 is a diagram showing an example of the configuration of a reactor group when there are four power distribution paths (n=4). [Figure 13] FIG. 13 is a diagram showing an example of the configuration of a reactor group when there are eight power distribution paths (n=8). [Figure 14] 14 is a diagram showing a modified example of the configuration of the split reactor shown in FIG. 13. [Figure 15] 14 is a diagram showing another modified example of the configuration of the split reactor shown in FIG. 13. [Figure 16] 16 is a graph showing the results of a simulation of a load current in the split reactor configuration shown in FIG. 15. [Figure 17] FIG. 13 is a diagram showing another modified example of the configuration of the semiconductor cutoff circuit in the embodiment. [Figure 18]FIG. 13 is a diagram showing another modified example of the configuration of the semiconductor cutoff circuit according to the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] A semiconductor cutoff circuit in an embodiment of the present invention includes a plurality of power distribution paths that transmit a DC current distributed from a common bus connected to a DC power source to a plurality of loads, a plurality of switch units formed of semiconductor elements and provided in each of the plurality of power distribution paths, a capacitor connected between the common bus and the power distribution path on the load side of each of the plurality of switch units, and an energy absorption unit having a first diode bridge provided between the common bus and the capacitor, and a plurality of second diode bridges provided between the capacitor and the power distribution path on the load side of each of the plurality of switch units.

[0011] In the above configuration, the common bus side (upstream side) of the multiple switch units is connected to the capacitor via a common first diode bridge. The load side (downstream side) of the multiple switch units is connected to the capacitor via a separate second diode bridge. When a fault current is detected in one of the multiple power distribution paths, the fault current can be diverted to the capacitor through the first diode bridge by cutting off the switch unit of the power distribution path. The fault current flows to the load through the second diode bridge connected to the cut-off switch of the multiple second diode bridges while charging the capacitor. This charging causes energy to be absorbed in the capacitor, so that the fault current attenuates. This enables current limiting and cut-off. According to this configuration, even if an accident occurs in one load of the multiple power distribution paths, the energy is absorbed by the capacitor independently of the other power distribution paths. That is, the multiple switch units share one energy absorption circuit. This configuration is lighter than a configuration in which an energy absorption circuit is provided for each of the multiple switch units. In addition, the energy absorption circuit is composed of a capacitor. Therefore, the speed at which the fault current attenuates can be adjusted by adjusting the voltage of the capacitor. That is, the cut-off speed can be adjusted. Thus, according to the above configuration, a semiconductor cutoff circuit that is lightweight and allows the cutoff speed to be adjusted can be obtained.

[0012] The switch unit may be, for example, a bidirectional switch configured with a semiconductor switch element. For example, an IGBT (Insulated Gate Bipolar Transistor), an IGCT (Integrated Gate-commutated thyristor), or a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) may be used as the semiconductor switch element. For example, the sources of two semiconductor transistors connected together may be used as the switch unit.

[0013] The switch section may have a semiconductor switch element and a mechanical switch connected in parallel to the semiconductor switch element. This makes it possible to suppress conduction loss when the switch section is conductive. In this configuration, when the switch section is cut off, the mechanical switch may be cut off and then the semiconductor switch element may be cut off. That is, the mechanical switch may be cut off first, the semiconductor switch element may be brought into a conductive state, and the current may be diverted to the semiconductor switch, and then the semiconductor switch element may be cut off. This makes it possible to suppress arc generation in the mechanical switch.

[0014] The capacitor can be precharged to a predetermined voltage by, for example, a DC power supply to which the DC bus is connected or another DC power supply. For example, the capacitor may be configured to be precharged by a divided voltage of the DC power supply or a voltage obtained by converting the voltage of the DC power supply.

[0015] The common bus may include a positive-side bus connected to a bipolar DC power supply and having a positive DC voltage applied with respect to ground, and a negative-side bus to which a negative DC voltage is applied with respect to ground. The plurality of power distribution paths may include a plurality of positive power distribution paths distributed from the positive-side bus, and a plurality of negative power distribution paths distributed from the negative-side bus. The switch unit may include a plurality of positive-side switch units provided in each of the plurality of positive power distribution paths, and a plurality of negative-side switch units provided in each of the plurality of negative power distribution paths. The energy absorption unit may include a positive-side energy absorption unit connected between the positive-side bus and a power distribution path on a load side of the plurality of positive-side switch units, and a negative-side energy absorption unit connected between the negative-side bus and a power distribution path on a load side of the plurality of negative-side switch units. A voltage of a capacitor of the positive-side energy absorption unit may be formed by a first division of a voltage between the positive-side bus and the negative-side bus. The voltage of the capacitor of the negative energy absorption unit may be formed by a second division of the voltage between the positive bus and the negative bus.

[0016] According to the above configuration, in the bipolar configuration, multiple positive side power distribution paths share one positive side energy absorption circuit, and multiple negative side power distribution paths share one negative side energy absorption circuit. This allows the energy absorption section to be made smaller, making it possible to reduce weight. Furthermore, the voltage of the capacitor in the positive side energy absorption section is a divided voltage between the positive side voltage and the negative side voltage of the bipolar power supply. This widens the adjustment range of the voltage of the capacitor in the positive side energy absorption section. Similarly, the adjustment range of the voltage of the capacitor in the negative side energy absorption section is also widened. This widens the adjustable range of the interruption speed.

[0017] The semiconductor shutoff circuit may further include a shutoff control unit that shuts off the switch unit in response to a current flowing through the switch unit, thereby making it possible to shut off the current when the current in the switch unit exceeds a predetermined range due to, for example, a short circuit in the load.

[0018] The semiconductor cutoff circuit may further include a load current control unit that controls the current of the load by switching the switch unit between conductive and cutoff in response to the current flowing through the load. This allows, for example, the load current to be controlled to be within a predetermined range. For example, when the current is about to increase due to an accident, the current can be limited to prevent the current from exceeding the predetermined range.

[0019] The load current control unit may stop the control and cut off the switch unit when the voltage of the capacitor of the energy absorption unit becomes equal to or higher than a predetermined value during the control of the current of the load. By stopping and cutting off the control of the current due to the energy absorption of the capacitor when the capacitor becomes equal to or higher than the predetermined value, it is possible to prevent the capacitor from being overcharged.

[0020] The first divided voltage constituting the voltage of the capacitor of the positive side energy absorption unit may be variable. The second divided voltage constituting the voltage of the capacitor of the negative side energy absorption unit may be variable. This makes it possible to change the interruption speed of the positive side energy absorption unit and the negative side energy absorption unit. For example, the first divided voltage can be made variable by making a voltage dividing resistor connected in parallel to both ends of the capacitor of the positive side energy absorption unit variable. Similarly, the second divided voltage can be made variable by making a voltage dividing resistor connected in parallel to both ends of the capacitor of the negative side energy absorption unit variable.

[0021] A DC power distribution system including the above-mentioned semiconductor shutoff circuit is also included in the embodiments of the present invention. The DC power distribution system includes a DC power source, a common bus connected to the DC power source, and the semiconductor shutoff circuit connected to the common bus.

[0022] A DC grid system including the above-mentioned semiconductor interruption circuit is also included in an embodiment of the present invention. The DC grid system in this embodiment includes a first DC power source and a second DC power source, a first common bus connected to the first DC power source and a second common bus connected to the second DC power source, a first semiconductor interruption circuit connected to the first common bus and a second semiconductor interruption circuit connected to the second common bus, a plurality of first loads respectively connected to a plurality of power distribution paths of the first semiconductor interruption circuit and a plurality of second loads respectively connected to a plurality of power distribution paths of the second semiconductor interruption circuit, and a redundancy switch provided between the first common bus and the second common bus. The first semiconductor interruption circuit and the second semiconductor interruption circuit are the above-mentioned semiconductor interruption circuits.

[0023] A semiconductor cutoff circuit according to an embodiment of the present invention includes a plurality of power distribution paths for transmitting a DC current distributed from a common bus connected to a DC power source to a plurality of loads, a reactor group provided in each of the plurality of power distribution paths, a plurality of switch units each configured with a semiconductor element and provided in each of the plurality of power distribution paths, and an energy absorbing unit connected in parallel to the plurality of switch units and absorbing short-circuit energy when at least one of the plurality of switch units is cut off. The reactor provided in at least one of the plurality of power distribution paths shares a core with a reactor provided in the other power distribution paths.

[0024] In the above configuration, when at least one of the multiple switch units is cut off, the energy absorption unit absorbs the energy of the reactor of the cut-off power distribution path. This makes it possible to limit the current and cut off the power. The reactor groups provided in the multiple power distribution paths share a core with each other. This reduces the amount of core and makes the reactor lighter. As a result, a lightweight semiconductor cut-off circuit is obtained.

[0025] The energy absorption unit may include a capacitor or a voltage clamp element connected in parallel to the multiple switch units, a first diode bridge provided between the capacitor or voltage clamp element and the common bus, and a second diode bridge provided between the capacitor or voltage clamp element and a power distribution path on the load side of each of the multiple switch units.

[0026] With this configuration, even if an accident occurs in one of the loads of the multiple power distribution paths, the energy is absorbed by the capacitor or voltage clamp element independently of the other power distribution paths. That is, the multiple switch units share one energy absorption circuit. This configuration is lighter than a configuration in which an energy absorption circuit is provided for each of the multiple switch units.

[0027] The reactors provided in each of the plurality of power distribution paths may be divided in a series direction, and at least two of the plurality of split reactors in each of the plurality of power distribution paths may share a core with a split reactor in another power distribution path. The plurality of split reactors in each of the plurality of power distribution paths may have winding directions such that, when a short circuit occurs in the other power distribution path, the polarities of electromotive forces induced in at least two of the plurality of split reactors are different.

[0028] In this configuration, at least two split reactors in each distribution path share different cores with the split reactors of the other distribution paths. When a switch unit is cut off in one of the multiple distribution paths to cause a short circuit, an electromotive force is induced in the split reactor of the short-circuited distribution path and in the split reactors of the other distribution paths that share a core with the split reactor. The polarity of this electromotive force is determined by the winding direction of the split reactor. In the above configuration, when a short circuit occurs in any one of the multiple distribution paths, the winding direction of each split reactor is set so that at least two of the multiple split reactors that share a core with the multiple split reactors of the short-circuited distribution path have different polarities in all other distribution paths. Therefore, in each of the multiple distribution paths, at least two split reactors are induced with electromotive forces in opposite directions due to a short circuit. As a result, in other distribution paths where no short circuit occurs, voltage fluctuations due to a short circuit in the other distribution paths are suppressed. Therefore, fluctuations in load current and load voltage in the other distribution paths are also suppressed. In other words, it is possible to reduce the degree of influence of a short-circuited power distribution path on other power distribution paths, which is caused by reactor groups of a plurality of power distribution paths sharing a core.

[0029] The winding direction of a reactor is the direction in which the reactor, or inductor, winding is wound around the core. The winding direction can be either right-handed or left-handed when viewed from the axial direction of the core. If the winding direction is reversed, the polarity of the self-induced electromotive force of the reactor will be reversed (i.e., the phase will be reversed). For example, if current flows through a line in which two reactors with the same number of turns and cores but with opposite winding directions are connected in series, the electromotive forces induced in the two reactors will cancel each other out. In this case, the sum of the induced electromotive forces will essentially be zero.

[0030] In the semiconductor interrupter circuit, the number of the plurality of power distribution paths connected to the common bus may be n (n is an integer from 2 to 8). The number m of the split reactors in each of the plurality of power distribution paths is defined as follows: If n=2, then m=2, When n=3 or 4, m=4, When n=5 to 8, m=8 may be used. When n=2, the multiple split reactors in each of the multiple power distribution paths may be wound in a direction such that, when a short circuit occurs in another power distribution path, the electromotive forces generated in the m=2 split reactors cancel each other out. When n=3 or 4, the split reactors for the multiple power distribution paths may be configured with split reactors for three or four power distribution paths in a configuration in which four split reactors are connected to each of the four power distribution paths, and the winding direction is set so that the electromotive forces generated in the m=4 split reactors cancel each other out when a short circuit occurs in the other power distribution paths. When n=5 to 8, the split reactors for the multiple power distribution paths may be configured with split reactors for any number of power distribution paths from 5 to 8, in a configuration in which eight split reactors are connected to each of eight power distribution paths, and the winding direction is set so that electromotive forces generated in the m=8 split reactors cancel each other out when a short circuit occurs in the other power distribution paths.

[0031] With the above configuration, when a short circuit occurs due to the disconnection of the switch unit in one of the multiple distribution paths, the electromotive forces induced in the multiple split reactors in the other distribution paths cancel each other out, so that the degree of influence of a short-circuited distribution path on the other distribution paths caused by the reactor groups of the multiple distribution paths sharing a core can be further reduced.

[0032] In the above configuration, when n=2, the winding direction may be set so that the sum of electromotive forces generated in the m=2 split reactors when a short circuit occurs in another power distribution path becomes substantially zero. Here, the sum of electromotive forces being substantially zero also includes the case where an electromotive force is generated that is so small that it can be ignored as a function of the interrupter circuit.

[0033] The arrangement of the winding directions of the split reactors in multiple power distribution paths can be expressed as a matrix of the number of power distribution paths n × the number of split reactors in each power distribution path m, with the winding direction being 1 or -1. In this matrix, each row corresponds to each power distribution path, and each column corresponds to a split reactor that shares one core.

[0034] The matrix obtained by expanding the winding direction matrix (2×2 matrix) for n=2 to a 4×4 matrix in accordance with the definition of the Amadaar matrix indicates a configuration in which the winding direction is set so that, in the event of a short circuit occurring in one of the n=4 distribution paths, the electromotive forces generated in the m=4 split reactors cancel each other out. When n=3 or 4, of this 4×4 configuration, the winding direction arrangement of the split reactors in three or four distribution paths (i.e., a 3×4 or 4×4 configuration) can be adopted.

[0035] The matrix obtained by expanding the winding direction matrix (4×4 matrix) when n=4 to an 8×8 matrix according to the definition of the Amadaar matrix indicates a configuration in which the winding direction is set so that, in the event of a short circuit occurring in one of the n=8 distribution paths, the electromotive forces generated in the m=8 split reactors cancel each other out. When n=5 to 8, of these 8×8 configurations, it is possible to adopt the winding direction arrangement of the split reactors in any of the 5 to 8 distribution paths (i.e., any of the 5×8, 6×8, 7×8, or 8×8 configurations).

[0036] Among the m split reactors in each of at least the n power distribution paths, the split reactor located closest to the common bus may be shared with a split reactor in another power distribution path or may be omitted, thereby making it possible to further reduce the weight of the reactor group.

[0037] (Configuration example) FIG. 1 is a diagram showing an example of the configuration of a semiconductor cutoff circuit according to an embodiment of the present invention. The semiconductor cutoff circuit 1 shown in FIG. 1 is provided between a bipolar DC power supply and a plurality of loads. The DC power supply supplies a positive voltage +VDC with respect to ground and a negative voltage -VDC with respect to ground from independent wirings. The semiconductor cutoff circuit 1 is configured to limit and cut off current independently for each of a plurality of distribution paths branched from the positive wiring and the negative wiring of the DC power supply. For example, when an overcurrent, i.e., a fault current, occurs due to an accident such as a short circuit in a load connected to one of the plurality of distribution paths, the semiconductor cutoff circuit limits or cuts off the current only for the distribution path in which the fault current occurs.

[0038] In the example shown in FIG. 1, the semiconductor interrupter circuit 1 includes a plurality of positive-side power distribution paths kp1-kp3 (hereinafter simply referred to as power distribution paths kp1-kp3) connected to a positive-side common bus kp (hereinafter simply referred to as common bus kp), which is wiring for a positive-side voltage of a DC power source. A load is connected to each of the plurality of power distribution paths kp1-kp3. In each of the plurality of power distribution paths kp1-kp3, a positive-side switch unit Sp1-Sp3 (hereinafter simply referred to as switch unit Sp1-Sp3) is provided between the common bus kp and the load. The switch units Sp1-Sp3 are bidirectional switches formed of semiconductor switch elements. Each of the plurality of switch units Sp1-Sp3 is controlled to be on / off, i.e., conductive / interrupted, according to a current detected by a sensor bp1-bp3 (current sensor) provided in each of the power distribution paths kp1-kp3.

[0039] The semiconductor interrupter circuit 1 includes a plurality of negative-side power distribution paths kn1-kn3 (hereinafter simply referred to as power distribution paths kn1-kn3) connected to a negative-side common bus kn, which is a wiring for a negative-side voltage of a DC power supply. A load is connected to each of the plurality of power distribution paths kn1-kn3. In each of the plurality of power distribution paths kn1-kn3, negative-side switch units Sn1-Sn3 (hereinafter simply referred to as switch units Sn1-Sn3) are provided between the common bus kn and the load. The switch units Sn1-Sn3 are bidirectional switches formed of semiconductor switch elements. FIG. 9 shows that each of the plurality of switch units Sn1-Sp3 is controlled to be on / off, i.e., conductive / interrupted, according to a current detected by a sensor bn1-bn3 provided in each of the power distribution paths kn1-kn3.

[0040] A positive-side energy absorbing unit 10p (hereinafter, simply referred to as the energy absorbing unit 10p) is connected between the common bus kp and the power distribution paths kp1 to kp3 on the load side of the switch units Sp1 to Sp3. The energy absorbing unit 10p has one capacitor Cap as an energy absorbing circuit. The capacitor Cap is connected in parallel to the switch units Sp1 to Sp3. A first diode bridge Dp1 is provided between the common bus kp and the capacitor Cap. The first diode bridge Dp1 is composed of an arm including two diodes connected in series. The cathode of the arm of the first diode bridge Dp1 is connected to one electrode of the capacitor Cap, and the anode is connected to the other electrode of the capacitor Cap. A node between the two diodes constituting the arm of the first diode bridge Dp1 is connected to the common bus kp. Second diode bridges Dp21 to Dp23 are connected between the capacitor Cap and each of the multiple power distribution paths kp1 to kp3. The second diode bridge Dp21-Dp23 is configured with an arm including two diodes connected in series. The cathode of each arm of the second diode bridge Dp21-Dp23 is connected to one electrode of the capacitor Cap, and the anode is connected to the other electrode of the capacitor Cap. The node between the two diodes constituting each arm of the second diode bridge Dp21-Dp23 is connected to the power distribution paths kp1-kp3 on the load side of the switch units Sp1-Sp3, respectively. In the example shown in FIG. 1, the first diode bridge Dp1 and the second diode bridge Dp21-Dp23 are each configured with a half-bridge circuit.

[0041] The energy absorbing unit 10p forms a detour path for the switch units Sp1 to Sp3. The energy absorbing unit 10p leads the detour path from the common bus kp through a first diode bridge to an inlet of the energy absorbing circuit (i.e., one electrode of the capacitor Cap), and connects the outlet of the energy absorbing circuit (i.e., the other electrode of the capacitor Cap) to the downstream side of the switch units Sp1 to Sp3 of each of the power distribution paths kp1 to kp3 through each second diode bridge. With this configuration, even if an accident occurs in any load of the multiple power distribution paths kp1 to kp3, the energy can be independently absorbed by the capacitor Cap. The energy absorbing unit 10p is a common absorption circuit for the multiple power distribution paths kp1 to kp3.

[0042] In the example shown in Fig. 1, the capacitor Cap is configured to receive a divided voltage between the positive voltage +VDC and the negative voltage -VDC of the bipolar power supply. This divided voltage is determined by the resistance ratio of a first resistor Rp1, which is a voltage dividing resistor connected in parallel with the capacitor Cap, and a second resistor Rp2, which is a voltage dividing resistor connected between the first resistor Rp1 and the negative side common bus kn. With this configuration, the voltage Vcap0 of the capacitor Cap can be charged to a voltage equal to or higher than the voltage +VDC of the common bus kp.

[0043] A negative-side energy absorption unit 10n is connected between the negative-side common bus kn and the power distribution paths kn1-kn3 on the load side of the negative-side switch units Sn1-Sn3. The negative-side energy absorption unit 10n can be configured similarly to the positive-side energy absorption unit 10p. That is, the negative-side energy absorption unit 10n has a first diode bridge Dn1, a capacitor Can, and a second diode bridge Dn21-Dn23.

[0044] When the load current, i.e., the current detected by the sensors bp1 to bp3, exceeds a predetermined value in any one of the power distribution paths kp1 to kp3 among the multiple switch units Sp1 to Sp3, the switch unit of that power distribution path is cut off. The current of the power distribution path whose switch unit has been cut off flows to the energy absorption unit 10p. As a result, the energy of the inductor of the wiring in the power distribution path whose switch unit has been cut off is absorbed by the capacitor Cap, and the current of the power distribution path is attenuated and led to zero. In FIG. 1, the inductors (reactors) Lp1 to Lp3 of the wiring of the power distribution paths kp1 to kp3 are illustrated. That is, the energy absorption unit 10p absorbs the energy of the inductance of the power distribution path cut off by the switch unit when any one of the switch units Sp1 to Sp3 is turned off. The same is true for the negative side energy absorption unit 10n. In this way, the semiconductor cutoff circuit 1 is excellent in terms of light weight because the energy absorption unit can be shared among multiple power distribution paths. The negative side switch sections Sn1 to Sn3 and the energy absorbing section 10n have the same configurations and operate in the same manner.

[0045] For example, if an accident occurs in a load on the power distribution path kp1, the sensor bp1 detects the fault current and the switch unit Sp1 is turned off. This causes the fault current to be diverted to the energy absorption unit 10p. In the energy absorption unit 10p, the fault current enters from the common bus kp and is returned to the load via the second diode bridge Dp21 on the output side while further charging the capacitor Cap, which has been charged in advance to a predetermined voltage VCap0 (see arrow Y1 in FIG. 1). As a result, energy is charged in the capacitor Cap. The fault current starts to decay and becomes zero after a predetermined time. After the fault current becomes zero, for example, the contactor of the power distribution path kp1 in which the fault current was detected may be turned off, i.e., cut off. This causes the load in which the accident occurred to be separated from the power supply system.

[0046] Figure 2 is a diagram showing an example of the load current in a power distribution path when an accident occurs in a load, and the change in voltage across the switch unit of the power distribution path. As shown in Figure 2, when the switch unit is cut off, the energy absorption unit starts absorbing energy, and then the current decays to zero. When the switch unit is cut off, current flows through the energy absorption unit, and the voltage across the switch unit is mainly the voltage of the capacitor Cap. When the energy is absorbed in the energy absorption unit and the current becomes zero, the voltage across the switch unit becomes VDC, which is the voltage of the power supply.

[0047] As shown in FIG. 3, if the initial charging voltage Vcap0 of the capacitor Cap of the energy absorbing unit 10p is large, the energy absorption speed is fast. In this way, the time required to interrupt the fault current, i.e., the interruption speed, varies depending on the initial charging voltage Vcap0 of the capacitor Cap. In the example shown in FIG. 1, the initial charging voltage Vcap0 of the capacitor Cap is formed by dividing the voltage between the positive side voltage +VDC and the negative side voltage -VDC of the bipolar power supply. The initial charging voltage Vcap0 of the capacitor Cap can be made variable by making the first resistor Rp1 and the second resistor Rp2, which determine the voltage division, variable. In the example shown in FIG. 1, one end of the charging circuit of the capacitor Cap of the positive side energy absorbing unit 10p is connected to the negative side common bus kn (-VDC), and the other end is connected to the positive side common bus kp (+VDC). Therefore, the capacitor Cap can be initially charged with a voltage equal to or higher than the bus voltage.

[0048] In the example shown in Fig. 1, decreasing the ratio of the first resistance to the second resistance, i.e., the value of Rp1 / Rp2, slows down the energy absorption speed of the energy absorbing unit 10p. Increasing the value of Rp1 / Rp2 speeds up the energy absorption speed. Similarly, on the negative side, decreasing the value of Rn1 / Rn2 slows down the energy absorption speed of the energy absorbing unit 10n, and increasing the value of Rp1 / Rp2 speeds up the energy absorption speed.

[0049] Similarly, the capacitor Can of the negative energy absorption unit 10n is configured by dividing the voltage between the positive voltage +VDC and the negative voltage -VDC of the bipolar power supply. By making the first resistor Rn1 and the second resistor Rn2, which determine the voltage division, variable, the initial charging voltage Vcan0 of the capacitor Can can be made variable.

[0050] FIG. 4 is a diagram showing a detailed configuration example of the switch units Sp1 to Sp3 and the energy absorbing unit 10p shown in FIG. 1. In the example shown in FIG. 4, each of the switch units Sp1 to Sp3 has a semiconductor switch element. The semiconductor switch element has two semiconductor transistors connected in series. The sources of the two semiconductor transistors are connected to each other. A diode for preventing backflow is connected in parallel to each of the two semiconductor transistors. By controlling the gate voltages of the two semiconductor transistors, the on / off of the switch units Sp1 to Sp3 is controlled. The semiconductor transistors may be, for example, IGBT, IGCT, or MOS-FET. Furthermore, for example, Si or SiC may be used as the semiconductor of the semiconductor transistors.

[0051] The on / off of each of the switches Sp1 to Sp3 is controlled by the controllers Cp1 to Cp3. The controllers Cp1 to Cp3 control the on / off of the switches Sp1 to Sp3 according to the current detected by the sensors bp1 to bp3. The current detected by the sensors bp1 to bp3 is the load current, and is also the current flowing through the switches Sp1 to Sp3.

[0052] In the example of Fig. 4, each of the controllers Cp1 to Cp3 includes a cutoff control unit and a load current control unit. Each cutoff control unit cuts off each switch unit according to the current flowing through the switch unit. For example, when the current detected by each sensor exceeds a predetermined value, the cutoff control unit can switch the switch unit of the power distribution path to which the sensor is connected from on to off. This makes it possible to limit and / or cut off the fault current of each power distribution path.

[0053] Each load current control unit controls the current of each load by switching the conduction and interruption of each switch unit according to the current flowing through the load of each power distribution path. For example, the load current control unit repeats the switching operation of the switch unit according to the current of each load so that the current of each load becomes a target value of 0 or more. Here, an example configuration of the load current control unit of the switch unit Sp1 will be described, but the load current control units of the other switch units Sp2 and Sp3 can be configured in a similar manner. The load current control unit controls the load current to become a target value, for example, by turning the switch unit Sp1 on and off. In the control, the detection value of the sensor bp1 is compared with the target value, and the switch unit Sp1 is controlled to be on or off based on the comparison result.

[0054] FIG. 5 is a diagram showing an example of the load current and the voltage across the switch unit controlled by the load current control unit. In the example shown in FIG. 5, an upper limit Tu and a lower limit Td are set as target values ​​of the load current. When the load current reaches the upper limit Tu while the switch unit Sp1 is on, and the load current is equal to or greater than Tu, the load current control unit switches the switch unit Sp1 from on to off. When the load current reaches the lower limit Td while the switch unit Sp1 is off, and the load current is equal to or less than Td, the load current control unit switches the switch unit Sp1 from off to on. The load current control unit repeats this control, and the load current is maintained between the upper limit Tu and the lower limit Td. This makes it possible to limit, for example, a fault current. That is, the load current control unit is capable of current limiting control.

[0055] In this manner, the semiconductor interrupter circuit 1 of this embodiment is configured to be able to limit current by controlling the on / off of the switches Sp1 to Sp3. Therefore, for example, there is no need to further include a current limiter such as a reactor for limiting current. As a result, weight reduction is made easier.

[0056] FIG. 6 is a diagram showing another example of the load current controlled by the load current control unit and the voltage across the switch unit. During the period in which the switch unit Sp1 is controlled to be off by the load current control unit, the capacitor Cap is charged. Therefore, when the load current control unit repeatedly turns the switch unit Sp1 on and off, the voltage of the capacitor Cap gradually increases. Therefore, as shown in FIG. 6, when the voltage of the capacitor Cap becomes equal to or higher than a predetermined value (threshold value Th2 in the example of FIG. 6) during the control of the load current, the load current control unit may stop the control and cut off the switch unit Sp1. In this way, when the voltage Vcap of the capacitor Cap gradually increases and exceeds the predetermined value, it is determined that the load current control cannot be continued, and the load current control is stopped and cut off. The threshold value Th2 may be set to a value lower than the upper limit of charging the capacitor Cap.

[0057] The control of the switches Sp1 to Sp3 can be either cutoff control by a cutoff control unit or current control (e.g., current limiting) by a load current control unit. The controllers Cp1 to Cp3 may switch between cutoff control and current control (current limiting). For example, the control of the switches Sp1 to Sp3 can be switched between cutoff control and current control (e.g., current limiting) depending on the load situation.

[0058] For example, in a system operating condition where the load current tends to be large, it is preferable to quickly cut off the fault current. In such a condition, the control of the switch units Sp1 to Sp3 when the fault current occurs can be cut-off control. In this case, the switch units are cut off by the cut-off control unit when the fault current occurs. In contrast, in a system operating condition where the load current tends to be small, it may be preferable to continue operation by limiting the current rather than cutting off. In such a condition, the control of the switch units Sp1 to Sp3 when the fault current occurs can be current control (e.g., current limiting). In this case, when the fault current occurs, load current control (e.g., current limiting) is performed by controlling the switch units of the load current control unit.

[0059] The control of the switches Sp1 to Sp3 can be switched between cutoff and current control (current limiting) by the controllers Cp1 to Cp3 in response to a command from the system. That is, the operation of the switches Sp1 to Sp3 when a fault current occurs may be switched between cutoff and load current control (for example, current limiting) depending on the operating conditions of the loads in the system.

[0060] The semiconductor cutoff circuit 1 can be adjusted so that the initial charging voltage Vcap0 of the capacitor Cap is different between when the cutoff control unit cuts off the switch unit when a fault current occurs and when the load current control unit controls the load current when a fault current occurs. For example, the initial charging voltage Vcap0 may be adjusted so that it is smaller during load current control than during cutoff control. For example, under conditions where current limiting is desired, the rate at which energy is absorbed by the energy absorption unit 10p is slowed down by setting the value of Rp1 / Rp2 small in advance. This makes it easier to perform current limiting control.

[0061] The configuration and control of the switch units Sp1 to Sp3 shown in FIG. 4 can be similarly applied to the negative side switch units Sn1 to Sn3. The semiconductor cutoff circuit of this embodiment can also be applied to a DC power supply that is not bipolar. For example, in FIG. 4, the voltage for initially charging the capacitor Cap of the energy absorbing unit 10p is not limited to the voltage of a bipolar power supply, and the voltage of a DC power supply that is not bipolar may be used. In this case, the initial charging voltage Vcap0 of the capacitor Cap may be, for example, a divided voltage of the DC power supply of the common bus. Alternatively, a power supply for initially charging the capacitor Cap may be provided separately from the DC power supply.

[0062] Fig. 7 is a diagram showing a modified example of the switch section Sp1. In the example shown in Fig. 7, the switch section Sp1 has a configuration in which a semiconductor switch element Sp11 and a mechanical switch Sp12 are connected in parallel. The semiconductor switch element Sp11 is a two-way switch composed of semiconductor transistors with their sources connected together, similar to the configuration shown in Fig. 4. The mechanical switch Sp12 is a switch that physically switches between connection and non-connection (separation) of a line. Note that the switch sections Sp2, Sp3, and Sn1 to Sn3 other than the switch section Sp1 can also have the configuration shown in Fig. 7 as a modified example.

[0063] The mechanical switch Sp12 is switched on / off in accordance with, for example, a control signal from the controller Cp1. The semiconductor switch element Sp11 and the mechanical switch Sp12 are switched on / off in conjunction with each other. When the switch section Sp1 is in a conductive (on) state, both the semiconductor switch element Sp11 and the mechanical switch Sp12 are in a conductive (on) state, and when the switch section Sp1 is in a cut-off (off) state, both the semiconductor switch element Sp11 and the mechanical switch Sp12 are in a cut-off (off) state. Under normal circumstances, when the switch section Sp1 is conductive, the mechanical switch Sp12 is in an on (conductive) state, so that the conduction loss can be reduced compared to the case of only the semiconductor switch element Sp11.

[0064] When switching the switch unit Sp1 from on to off, the mechanical switch Sp12 can be turned off earlier than the semiconductor switch element Sp11. That is, the timing of switching off the semiconductor switch element Sp11 can be delayed from the timing of switching off the mechanical switch Sp12. In this case, the mechanical switch Sp12 can be turned off first to commutate the current to the semiconductor switch element Sp11, and then the semiconductor switch element Sp11 can be turned off. This makes it possible to suppress arcing in the mechanical switch.

[0065] In the above configuration, the operation of the switch units Sp1 to Sp3, Sn1 to Sn3 after they are cut off is not particularly limited. For example, after the load is restored from an accident, the cut-off switch unit can be switched from off to on. At this time, the load current control unit may control the load current by turning the switch unit on and off. This enables initial current limiting. For example, it is possible to suppress an overcurrent immediately after the switch unit is turned on.

[0066] (System configuration example) FIG. 8 is a diagram showing a configuration example of a DC grid system in this embodiment. The DC grid system shown in FIG. 8 has a first power supply unit P1 and a second power supply unit P2. The first power supply unit P1 and the second power supply unit P2 each independently supply DC power. The first power supply unit P1 is connected to a plurality of loads F1 via a first common bus ka1. The second power supply unit P2 is connected to a plurality of loads F2 via a second common bus ka2. That is, the DC grid system shown in FIG. 8 has a multi-terminal configuration. A first semiconductor cutoff circuit 1-1 is provided in a plurality of power distribution paths that supply DC power from the first power supply unit P1 to each of the plurality of loads F1. A second semiconductor cutoff circuit 1-2 is provided in a plurality of power distribution paths that supply DC power from the second power supply unit P2 to each of the plurality of loads F2. The configuration of each of the first semiconductor cutoff circuit 1-1 and the second semiconductor cutoff circuit 1-2 can be, for example, the configuration shown in FIG. 4.

[0067] A redundancy switch 3 is connected between the first common bus ka1 and the second common bus ka2. The redundancy switch 3 switches between conduction and cut-off between the first common bus ka1 and the second common bus ka2. When the redundancy switch 3 is conductive, the first power supply unit P1 is connected to both the multiple loads F1 and the multiple loads F2, and the second power supply unit P2 is connected to power to both the multiple loads F2 and the multiple loads F1. As a result, even if either the first power supply unit P1 or the second power supply unit P2 fails, the remaining one can supply power to both the multiple loads F1 and the multiple loads F2.

[0068] When an accident (e.g., a short circuit) occurs in one of the multiple loads F1, F2, the first semiconductor interrupter circuit 1-1 and the second semiconductor interrupter circuit 1-2 (hereinafter referred to as semiconductor interrupter circuits 1-1, 1-2) can interrupt or limit the fault current and maintain normal power supply to the remaining loads. Whether the semiconductor interrupter circuits 1-1, 1-2 interrupt the fault current or maintain the current while limiting the fault current may be controlled according to the operating status of the DC grid system.

[0069] The first power supply unit P1 and the second power supply unit P2 have a bipolar configuration, and supply a positive voltage +E and a negative voltage -E through separate paths. The first common bus ka1 and the second common bus ka2 each have a positive voltage line, a negative voltage line, and a ground line. Both a positive voltage and a negative voltage are supplied to each of the multiple loads F1 and F2. A positive voltage line, a negative voltage line, and a ground line are connected to each of the multiple loads F1 and F2. As described above, the semiconductor cutoff circuits 1-1 and 1-2 include an energy absorption unit 10p common to multiple positive power distribution paths and an energy absorption unit 10n supplied to multiple negative power distribution paths. In this way, by sharing the energy absorption unit with multiple wirings, it is possible to reduce weight.

[0070] In the example shown in Fig. 8, the first power supply unit P1 includes, as an example, a first engine e1, a first generator g1 that generates power using the driving force of the first engine e1, a first converter t1 that converts the power generated by the first generator g1 into DC, a first battery b1 that supplies DC power by charging and discharging the power converted by the first converter t1, and a first current limiter / circuit breaker r1 that is provided between the first battery b1 and the first common bus ka1 and limits or cuts off a fault current. Similarly, the second power supply unit P2 includes a second engine e2, a second generator g2, a second converter t2, a second battery b2, and a second current limiter / circuit breaker r2. Each of the multiple loads F1 and F2 includes, for example, an inverter that converts a DC voltage supplied via a power distribution path into AC, and a motor controlled by the inverter.

[0071] The DC grid system shown in FIG. 8 can be applied to an electric aircraft, as an example. In the DC grid system applied to an electric aircraft, even if an accident occurs in the load or power supply unit, the first and second current limiting / circuit breakers r1 and r2, the redundant switch 3, and the semiconductor circuit breaker circuits 1-1 and 1-2 can quickly isolate the accident point and / or switch the connection. This allows the aircraft to continue operation using the remaining healthy equipment. The semiconductor circuit breaker circuits 1-1 and 1-2 function as DC circuit breakers that quickly isolate the accident current while limiting it. A large number of semiconductor circuit breaker circuits 1-1 and 1-2 are provided for a redundant configuration. As described above, the multiple semiconductor circuit breaker circuits 1-1 and 1-2 are lightweight, and therefore contribute greatly to reducing the weight of the entire system.

[0072] As described above, the semiconductor cutoff circuits 1-1 and 1-2 can vary the initial charging voltages Vcap0 and Vcan0 of the capacitors Cap and Can in the energy absorption units 10p and 10n by resistor voltage division. This allows the speed of energy absorption of the fault current to be adjusted according to the state of the DC grid system. For example, when the load current is large, such as during takeoff, the initial charging voltages Vcap0 and Vcap0 can be set large. This allows the fault current to be quickly cut off in a situation where there is no room for the upper limit of the current. On the other hand, when the load current is small, such as during cruising, the initial charging voltages Vcap0 and Vcap0 are set small so that the current can be easily limited. This makes it easy to continue operation while limiting the fault current and not cutting off the current.

[0073] (Variations of configuration) FIG. 9 is a diagram showing a modified example of the configuration of the semiconductor interrupter circuit in this embodiment. The semiconductor interrupter circuit 1 shown in FIG. 9 is provided between a bipolar DC power supply and a plurality of loads, similarly to the example shown in FIG. 1. The semiconductor interrupter circuit 1 is configured to limit and interrupt current independently for each of a plurality of power distribution paths kp1-kp4, kn1-kn4 branched from the positive and negative wiring of the DC power supply. The positive side switch units Sp1-Sp3 (hereinafter simply referred to as switch units Sp1-Sp3), the negative side switch units Sn1-Sn3 (hereinafter simply referred to as switch units Sn1-Sn3), and the sensors bp1-bp4, bn1-bn4 can be configured similarly to FIG. 1. The configuration and operation of the switch units Sp1-Sp4, Sn1-Sn4 can be similar to the example shown in FIG. 1.

[0074] In the example of FIG. 9, positive side reactors Lp1 to Lp4 (hereinafter simply referred to as reactors Lp1 to Lp4) are provided on the power distribution paths kp1 to kp4, respectively. Negative side reactors Ln1 to Ln4 (hereinafter simply referred to as reactors Ln1 to Ln4) are provided on the power distribution paths kn1 to kn4, respectively. At least one of the reactors Lp1 to Lp4 shares a core with a positive side reactor provided on another positive side power distribution path. At least one of the reactors Ln1 to Ln4 shares a core with a negative side reactor provided on another negative side power distribution path. The detailed configurations of the reactors Lp1 to Lp4 and Ln1 to Ln4 will be described later.

[0075] A capacitor Cap, which is a common energy absorption circuit, is connected in parallel to each of the switch sections Sp1 to Sp4 of the power distribution paths kp1 to kp4. First diode bridges Dp11 to Dp14 are provided between the upstream side of each of the power distribution paths kp1 to kp4 and the capacitor Cap. Second diode bridges Dp21 to Dp24 are provided between the downstream side of each of the power distribution paths kp1 to kp4 and the capacitor Cap. Each of the first diode bridges Dp11 to Dp14 can be configured similarly to the first diode bridge Dp1 shown in FIG. 1.

[0076] The energy absorption unit 10p forms a bypass path for each of the switch units Sp1 to Sp4. The bypass path is a path passing through the first diode bridges Dp11 to Dp12, the capacitor Cap, and the second diode bridges Dp21 to Dp24. With this configuration, even if an accident occurs in any of the loads of the plurality of power distribution paths kp1 to kp4, the capacitor Cap can independently absorb energy.

[0077] Also, similar to the example of FIG. 1, the capacitor Cap is configured such that a divided voltage between the positive voltage +VDC and the negative voltage -VDC of the bipolar power supply is applied. To determine this divided voltage, as a voltage dividing resistor, a first resistor Rp1 is connected in parallel with the capacitor Cap, and a second resistor Rp2 connected between the first resistor Rp1 and the negative side common bus kn is connected.

[0078] The negative side energy absorption unit 10n can be configured in the same manner as the positive side energy absorption unit 10p. That is, the negative side energy absorption unit 10n includes first diode bridges Dn11 to Dn14, a capacitor Can, and second diode bridges Dn21 to Dn23.

[0079] (Configuration example of reactor group) Next, a configuration example of the reactor group will be described. In the example of FIG. 9, on each of the positive side and the negative side, the number of power distribution paths connected to the common bus is, as an example, four, but it is not limited to this, and any number of two or more may be used. Here, an example in the case where the number of power distribution paths is 2 to 8 will be described. Since the configuration of the reactor group of the power distribution paths can be the same on the positive side and the negative side, in the following description, the power distribution paths are denoted as power distribution paths k1, k2, k3 ··· kn without distinguishing between the positive side and the negative side.

[0080] FIG. 10 is a diagram showing a configuration example of a reactor group when there are two power distribution paths (n=2). In the example of FIG. 10, in each of the two power distribution paths k1 and k2, the reactor is divided into multiple parts in the series direction. That is, multiple split reactors are connected in series. In each of the power distribution paths k1 and k2, the multiple split reactors have the same excitation inductance. Each of the multiple split reactors has a separate core. Each split reactor shares a core with the split reactor of the other power distribution path. The core is a magnetic material. It is preferable that the material and size of the core, as well as the number of turns, are the same for the multiple split reactors in each power distribution path. In FIG. 10, the split reactor L11 of the power distribution path k1 and the split reactor L21 of the power distribution path k2 share the core J1, and the split reactor L12 of the power distribution path k1 and the split reactor L22 of the power distribution path k2 share the core J2. It is preferable that the four split reactors L11, L12, L21, and L22 have the same exciting inductance.

[0081] In the example of FIG. 10, the winding direction R11 of the split reactor L11 of the power distribution path k1 and the winding direction R12 of the split reactor L12 are the same. The winding direction R21 of the split reactor L21 of the power distribution path k2 and the winding direction R22 of the split reactor L22 are opposite. That is, the split reactors L21 and L22 are connected to be in opposite phases to each other. This allows the winding directions to be set so that when a short circuit occurs in one of the power distribution paths k1 and k2, the electromotive forces generated in the multiple split reactors of the other power distribution path cancel each other out. In FIG. 10, the winding directions are indicated by the positions of black circles. The reactor with the black circle on the right and the reactor with the black circle on the left have opposite winding directions to each other.

[0082] For example, in the configuration of Fig. 10, if a short circuit occurs on the load side of the power distribution path k1, the voltage E of the DC power supply is applied to both ends of the split reactors L11 and L12 of the power distribution path k1. At this time, an induced electromotive force is also generated in L21 and L22, which share a core with L11 and L12, respectively. In this case, V2 applied to both ends of L21 and L22 becomes V2 = 0 as shown in the following formula. V2=(E / 2)·(R11·R21)+(E / 2)·(R12·R22) =(E / 2)·{1·1+1·(-1)} =0 Here, the coupling coefficient M between the split reactors that share a core is 1, and the value of the winding direction R is 1 for left-handed winding and -1 for right-handed winding. Matrix R2 in Fig. 10 is a matrix representation of the arrangement of the winding directions R11, R12, R21, and R22 of the split reactors L11, L12, L21, and L22 shown in Fig. 10.

[0083] In the example of FIG. 10, when a short circuit occurs in the power distribution path k1, the electromotive forces induced in the split reactors L21 and L22 of the power distribution path k2 cancel each other out, and the sum is essentially zero. Also, when the power distribution path k2 is short-circuited, the electromotive forces induced in the split reactors L11 and L12 of the power distribution path k1 cancel each other out. In this way, when the number of power distribution paths n=2 and the number of split reactors m=2, L11 and L21 share the core J1, L12 and L22 share the core, and the winding directions of L11 and L12 are the same and the winding directions of L21 and L22 are reversed, so that even if a short circuit occurs in one of the power distribution paths, it does not affect the other power distribution paths. Also, by sharing the core, the amount of cores can be reduced.

[0084] Figure 11 is a graph showing the simulation results of the load current at the fault location and the load current at healthy locations when a short circuit fault occurs on the load side of the power distribution path k1 in the reactor group configuration shown in Figure 10. The results shown in Figure 11 show that the load current at the fault location is suppressed to within five times the current from the DC power source, confirming the current suppression effect of the current-limiting reactor. In addition, there is almost no fluctuation in the load current at healthy locations.

[0085] FIG. 12 is a diagram showing a configuration example of a reactor group when there are four power distribution paths (n=4). In the example of FIG. 12, in each of the four power distribution paths k1 to k4, the reactor is divided into a plurality of parts (m=4) in the series direction. That is, a plurality of split reactors (m=4) are connected in series. In each of the power distribution paths k1 to k4, the split reactors have the same excitation inductance. The split reactors of one power distribution path each have a separate core. Each split reactor shares a core with the split reactors of the other power distribution paths. In FIG. 12, the split reactors L11 to L41 of the power distribution paths k1 to k4 share the core J1, L12 to L42 share the core J2, L13 to L43 share the core J3, and L14 to L44 share the core J4. It is preferable that the exciting inductance of the 16 split reactors L11 to L44 is the same.

[0086] In the example of Fig. 12, the winding directions of the 4x4 split reactors are set so that the winding directions of the split reactors are as shown in the matrix R4 shown in the lower part of the figure. As a result, when a short circuit occurs in one of the power distribution paths k1 to k4, the winding directions can be set so that the electromotive forces generated in the four split reactors in each of the other power distribution paths cancel each other out. For example, when a short circuit occurs on the load side of the power distribution path k1 and a voltage E is applied to both ends of L11 to L14, the sum V4 of the voltages applied to L41, L42, L43, and L44 of the power distribution path k4 becomes V4=0 as shown in the following formula. V4=(E / 4)·(R11·R41)+(E / 4)·(R12·R42)+(E / 4)·(R13·R43)+(E / 4)·(R14·R44) =(E / 4)·{1·1+1·(-1)+1·(-1)+1·1} =0

[0087] The inventors noticed that matrix R2 (see FIG. 10) showing the arrangement of the winding directions when n=2, m=2 is a Hadamard matrix, and came up with the idea of ​​using the following property of the Hadamard matrix to expand the 2×2 matrix R2 to a 4×4 Hadamard matrix, and adopt the matrix R4, for the arrangement of the winding directions when n=4, m=4. By adopting this matrix R4, it is possible to set the winding directions so that, when a short circuit occurs in one of the four power distribution paths k1 to k4, the electromotive forces generated in the four split reactors in each of the other power distribution paths cancel each other out.

[0088] If the Hadamard matrix is ​​H, the following equation holds: H.H. t =kI In the above equation, k is the size of the square matrix, and I is the identity matrix. If H is a Hadamard matrix, then the following matrix is ​​also a Hadamard matrix:

[0089]

number

[0090] According to the definition of this Hadamard matrix, the 2×2 matrix R2 is expanded to a 4×4 Hadamard matrix, resulting in matrix R4 in FIG.

[0091] FIG. 12 is a configuration example of a split reactor when m=4. When m=3, the winding arrangement of the split reactors of three of the 4×4 distribution paths shown in FIG. 12 can be used. For example, the winding arrangement of the split reactors of the three distribution paths k1 to k3 in the range indicated by the dashed line B3 can be applied to the reactor group of the m=3 distribution paths. In this case, too, it can be configured so that when a short circuit occurs in one of the three distribution paths, the induced electromotive forces of the split reactors in each of the other distribution paths cancel each other. That is, when m=3, the arrangement of the split reactors of any three distribution paths can be the arrangement of the split reactors of the three distribution paths among the arrangements of the winding directions of the 4×4 split reactors of n=4 and m=4, in which the electromotive forces generated in the split reactors of each of the other distribution paths cancel each other when a short circuit occurs in one distribution path.

[0092] FIG. 13 is a diagram showing a configuration example of a reactor group when there are eight power distribution paths (n=8). In the example of FIG. 13, in each of the eight power distribution paths k1 to k8, the reactor is divided into multiple parts (m=8) in the series direction. In each of the power distribution paths k1 to k8, the multiple split reactors have the same excitation inductance. The multiple split reactors in one power distribution path each have a separate core. Each split reactor shares a core with the split reactors in the other power distribution paths. It is preferable that the 8×8=64 split reactors L11 to L88 have the same excitation inductance.

[0093] In the example of Fig. 13, the winding directions of the 8x8 split reactors are set so that the winding directions of the split reactors are as shown in the matrix R8 shown in the lower part of the figure. As a result, when a short circuit occurs in one of the power distribution paths k1 to k8, the winding directions can be set so that the electromotive forces generated in the eight split reactors in each of the other power distribution paths cancel each other out. According to the definition of the Hadamard matrix above, the 4x4 matrix R4 is expanded to an 8x8 Hadamard matrix, which is the matrix R8 in Fig. 13.

[0094] FIG. 13 shows an example of the configuration of the split reactor when m=8. When m=7, the winding arrangement of the split reactors of seven of the 8×8 power distribution paths shown in FIG. 13 can be adopted. For example, the winding arrangement of the split reactors of the seven power distribution paths k1 to k7 in the range indicated by the dashed line B7 can be applied to the reactor group of the m=7 power distribution paths. Similarly, when m=6, the winding arrangement of the split reactors of any six of the 8×8 configuration in FIG. 13 (for example, the configuration in the range of the dashed line B6) can be adopted as the winding direction arrangement of the split reactors, and when m=5, the winding arrangement of the split reactors of any five of the 8×8 configuration (for example, the configuration in the range of the dashed line B5) can be adopted as the winding direction arrangement of the split reactors. In these cases, too, when a short circuit occurs in one of the multiple power distribution paths, the split reactors in each of the other power distribution paths can be configured to cancel each other out.

[0095] In other words, when m=5, 6, or 7, the arrangement of the split reactors of any 5, 6, or 7 power distribution routes among the arrangements of 8 x 8 split reactors where n=8 and m=8 in the winding direction, in which the electromotive forces generated in the split reactors of the other power distribution routes cancel each other out when a short circuit occurs in one power distribution route, can be the arrangement of the split reactors of these power distribution routes.

[0096] Fig. 14 is a diagram showing a modified example of the configuration of the split reactor shown in Fig. 13. In the example of Fig. 14, the split reactor in the first row among the eight split reactors in each of the n=8 power distribution paths k1 to k8 is shared with the split reactors of the other power distribution paths. That is, the multiple power distribution paths 1k to 18 share the first row split reactor L11C. Specifically, the m-1 split reactors in each of the power distribution paths k1 to k8 are connected in series to one split reactor L11C that is connected to a common bus.

[0097] In the 8×8 configuration shown in FIG. 13, the magnetic flux coupling inductors of the split reactors in the first row (L11, L21, L31, L41, L51, L61, L71, L81) have a magnetomotive force in normal operation that is the number of power distribution paths n times the steady-state current I. On the other hand, the magnetic flux coupling inductors of the split reactors in the second and subsequent rows (second to eighth rows) have magnetomotive forces in normal operation that are cancelled out by each other and become substantially zero. Therefore, when a fault short circuit occurs, the magnetic flux of the fault short-circuit current is superimposed on the magnetic flux kI of the normal current in the magnetic flux coupling inductors of the split reactors in the first row. Therefore, it is preferable that the core J1 shared by the split reactors in the first row is large. In view of this situation, the inventor has come up with the idea of ​​making the split reactors in the first row of multiple power distribution paths 1k to 8k into a common single-winding as shown in FIG. 14. As shown in FIG. 13, the split reactors L11 to L81 in the first row have the same winding direction and number of turns, so the potentials at both ends of the split reactors L11 to L81 in the first row of the power distribution paths 1k to 8k are substantially the same. Therefore, these can be combined into one common single-winding split reactor. By making it a single winding, there is no need to consider the imbalance in the coupling coefficient of each winding, and it is possible to suppress an increase in the window area for magnetic flux leaking from the gap between the split reactors. As a result, it is possible to further reduce the size and weight of the reactor.

[0098] Even if the number of power distribution paths is other than n=8, the split reactors in the first row can be made common. For example, the split reactors L11 and L21 in the first row shown in Fig. 10 or the first example split reactors L11 to L41 shown in Fig. 12 may be made into a common single-winding to form one split reactor. Also, some of the split reactors in the first row may be made into a common single-winding.

[0099] FIG. 15 is a diagram showing another modified example of the configuration of the split reactor shown in FIG. 13. In the example of FIG. 15, the first row of split reactors among the eight split reactors in each of the n=8 power distribution paths k1 to k8 is omitted. This allows further weight reduction. In this case, if a short-circuit fault occurs in one of the power distribution paths k1 to k8, the electromotive forces induced in the seven split reactors in each of the other power distribution paths cancel each other out, but 1 / 7 of the induced electromotive force remains. A reactor group with a configuration in which the first row of split reactors is omitted can be applied to a system in which the voltage fluctuation of healthy parts due to this residual electromotive force is within an acceptable range.

[0100] Fig. 16 is a graph showing the results of a simulation of the load current in the split reactor configuration shown in Fig. 15. In the results shown in Fig. 16, a fluctuation of about 10% is observed in the current of healthy parts during the same period as the fluctuation of the load current of the faulty parts. This is considered to be due to the remaining induced electromotive force that would result from omitting the first row of split reactors. Although not particularly limited, for example, a reactor group with a configuration omitting the first row of split reactors can be applied to a system in which a fluctuation of 20% or less is allowed as the load current or load voltage of healthy parts when a fault short circuit occurs.

[0101] FIG. 16 shows an example in which the split reactor in the first row is omitted when m=8. The split reactor in the first row may also be omitted when m is other than 8, for example, when m=4. If the first row of m split reactors is omitted, an induced electromotive force of (1 / m) will remain. Therefore, if m is small, the first row may be omitted and a common single-winding split reactor with a reduced inductance value may be added to the first row. This makes it possible to reduce the remaining induced electromotive force.

[0102] The above describes examples of configurations of split reactors when m = 2 to 8. However, when m = 9 or more, a split reactor can be configured in the same manner as the above examples by adopting a winding direction arrangement represented by an expanded matrix of 8 × 8 matrix R8 in accordance with the definition of the Hadamard matrix.

[0103] FIG. 17 is a diagram showing another modified example of the configuration of the semiconductor cutoff circuit in this embodiment. The configuration shown in FIG. 17 is a configuration in which the capacitors of the energy absorbing units 10p and 10n in the configuration shown in FIG. 9 are replaced with voltage clamp elements Crp and Crn. In addition, in the configuration of FIG. 17, there is no dividing resistor for adjusting the voltage of the capacitor. In this way, a voltage clamp element may be used instead of a capacitor as the energy absorbing circuit in the energy absorbing units 10p and 10n. As an example, the voltage clamp element is composed of a varistor, a Zener diode, or a voltage clamp circuit using other semiconductors. Even in this case, weight reduction is possible by combining a reactor group sharing a core with the energy absorbing units 10p and 10n. In the example of FIG. 17, the configuration and operation of the switch units Sp1 to Sp4 and Sn1 to Sn4 can be the same as those in FIG. 1 or FIG. 9.

[0104] In the configuration examples of Fig. 9 and Fig. 17, the first diode bridges Dp11 to Dp14, Dn11 to Dn14 are provided for each power distribution path. As a modification of this, for example, as shown in Fig. 1, one first diode bridge may be shared by a plurality of power distribution paths. In this case, a reactor group may be connected between the switch unit and a connection point between the power distribution path and the first diode bridge. Furthermore, the position where the reactor group is connected is not limited to each power distribution path between the common bus and the switch unit as shown in Fig. 9 and Fig. 17. For example, as shown in Fig. 1, the reactor group may be connected between a contactor and a load.

[0105] Furthermore, the configuration of the energy absorbing units 10p, 10n is not limited to the above example. The energy absorbing units may have a configuration that does not use a diode bridge. Fig. 18 is a diagram showing a modified example of the energy absorbing unit. In the example shown in Fig. 18, energy absorbing circuits Vp11-Vp14, Vn11-Vn14 are connected in parallel to the switch units Sp1-Sp4, Sn1-Sn4 of the multiple power distribution paths, respectively. The energy absorbing circuits may be, for example, voltage clamp elements.

[0106] A semiconductor interrupter circuit including the reactor group exemplified in Fig. 9, Fig. 17 or Fig. 18 above can be used as the semiconductor interrupter circuit of the DC grid system shown in Fig. 8. The configuration of each of the first semiconductor interrupter circuit 1-1 and the second semiconductor interrupter circuit 1-2 in Fig. 8 can be, for example, the configuration shown in Fig. 9, Fig. 17 or Fig. 18.

[0107] The reactor group having the above configuration is also one of the embodiments of the present invention. For example, the reactor group having the above configuration of sharing a core can be applied to a circuit or system including a configuration in which a reactor is connected to each of a plurality of power distribution paths, in addition to a semiconductor cutoff circuit.

[0108] (Other variations) The present invention is not limited to the above embodiment. For example, in the example shown in Fig. 1, a contactor is provided between each of the switch sections Sp1 to Sp3, Sn1 to Sn3 and the load, but this contactor may be omitted. [Explanation of symbols]

[0109] 1: semiconductor cutoff circuit, ka1, ka2, kp, kn: common bus, Sp1 to Sp3: switch section, 10p, 10n: energy absorption section, Dp1: first diode bridge, Dp21 to Dp23: second diode bridge, Cap: capacitor

Claims

1. a plurality of power distribution paths for transmitting a DC current distributed from a common bus connected to a DC power source to a plurality of loads, respectively; A plurality of switch units each configured with a semiconductor element and provided in each of the plurality of power distribution paths; a capacitor connected between the common bus and a power distribution path on a load side of each of the plurality of switch units, and an energy absorption unit having a first diode bridge provided between the common bus and the capacitor, and a plurality of second diode bridges provided between the capacitor and a power distribution path on a load side of each of the plurality of switch units.

2. 2. The semiconductor shutoff circuit of claim 1, the common bus is connected to a bipolar DC power supply and includes a positive-side bus to which a positive DC voltage with respect to ground is applied, and a negative-side bus to which a negative DC voltage with respect to ground is applied, the plurality of power distribution paths include a plurality of positive side power distribution paths distributed from the positive side bus and a plurality of negative side power distribution paths distributed from the negative side bus, the switch unit includes a plurality of positive-side switch units provided in the plurality of positive-side power distribution paths, respectively, and a plurality of negative-side switch units provided in the plurality of negative-side power distribution paths, the energy absorption unit includes a positive-side energy absorption unit connected between the positive-side bus and a power distribution path on a load side of the plurality of positive-side switch units, and a negative-side energy absorption unit connected between the negative-side bus and a power distribution path on a load side of the plurality of negative-side switch units, a voltage of a capacitor of the positive side energy absorption unit is formed by a first division of a voltage between the positive side bus and the negative side bus; A semiconductor shutoff circuit, wherein the voltage of the capacitor of the negative side energy absorption unit is formed by a second division of the voltage between the positive side bus and the negative side bus.

3. 3. A semiconductor shutoff circuit according to claim 1, The semiconductor shutoff circuit further includes a shutoff control unit that shuts off the switch unit in response to a current flowing in the switch unit.

4. A semiconductor shutoff circuit according to any one of claims 1 to 3, The semiconductor shutoff circuit further includes a load current control unit that controls a current through the load by switching the switch unit between conductive and cut-off states in response to a current flowing through the load.

5. 5. The semiconductor shutoff circuit of claim 4, The load current control unit stops the control and shuts off the switch unit when the voltage of the capacitor of the energy absorption unit becomes equal to or higher than a predetermined value while controlling the current of the load.

6. 3. The semiconductor shutoff circuit of claim 2, the first divided voltage constituting the voltage of the capacitor of the positive-side energy absorption unit is variable, The second divided voltage constituting the voltage of the capacitor of the negative side energy absorption section is variable.

7. A DC grid system comprising the semiconductor interrupter circuit according to any one of claims 1 to 6, A first DC power source and a second DC power source; a first common bus connected to the first DC power source and a second common bus connected to the second DC power source; a first semiconductor shutoff circuit connected to the first common bus and a second semiconductor shutoff circuit connected to the second common bus; a plurality of first loads respectively connected to a plurality of power distribution paths of the first semiconductor interruption circuit, and a plurality of second loads respectively connected to a plurality of power distribution paths of the second semiconductor interruption circuit; a redundancy switch provided between the first common bus and the second common bus, The first semiconductor shutoff circuit and the second semiconductor shutoff circuit are the semiconductor shutoff circuits according to any one of claims 1 to 6. A DC grid system.

8. a plurality of power distribution paths for transmitting a DC current distributed from a common bus connected to a DC power source to a plurality of loads, respectively; A reactor group provided in each of the plurality of power distribution paths; A plurality of switch units each configured with a semiconductor element and provided in each of the plurality of power distribution paths; an energy absorbing unit that is connected in parallel to the plurality of switch units and absorbs short-circuit energy when at least one of the plurality of switch units is cut off; a reactor provided in at least one of the plurality of power distribution paths shares a core with a reactor provided in another power distribution path,

9. 9. The semiconductor shutoff circuit of claim 8, The reactors provided in each of the plurality of power distribution paths are divided in a series direction, and at least two of the plurality of split reactors in each of the power distribution paths share a core with a split reactor in another of the power distribution paths; a plurality of split reactors in each of the plurality of power distribution paths are wound in a direction such that, when a short circuit occurs in another power distribution path, the polarities of the electromotive forces induced in at least two of the plurality of split reactors are different.

10. 10. The semiconductor shutoff circuit of claim 9, the number of the plurality of power distribution paths connected to the common bus is n (n is an integer from 2 to 8); The number m of the split reactors in each of the plurality of power distribution paths is defined as: If n=2, then m=2, When n=3 or 4, m=4; When n=5 to 8, m=8; In the case of n=2, the plurality of split reactors in each of the plurality of power distribution paths are wound in a direction such that electromotive forces generated in the m=2 split reactors cancel each other out when a short circuit occurs in another power distribution path; In the case of n=3 or 4, four split reactors are connected to each of four power distribution paths, and the split reactors for the plurality of power distribution paths are configured with split reactors for three or four power distribution paths in a configuration in which the winding directions are set so that electromotive forces generated in the m=4 split reactors cancel each other out when a short circuit occurs in another power distribution path; When n = 5 to 8, eight split reactors are connected to each of eight power distribution paths, and the winding direction is set so that electromotive forces generated in the m = 8 split reactors cancel each other out when a short circuit occurs in the other power distribution paths. In this semiconductor interrupter circuit, the split reactors for the multiple power distribution paths are composed of split reactors for any number of power distribution paths from 5 to 8,

11. 11. The semiconductor shutoff circuit of claim 10, a split reactor among m split reactors in each of at least two of the n power distribution paths, the split reactor located closest to the common bus is shared with a split reactor of another power distribution path or is omitted.

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