Thin Film Transistor Circuit

Abstract

To improve current characteristics of an oxide semiconductor TFT and to suppress undesirable parasitic capacity from being generated.SOLUTION: A polysilicon layer includes a polysilicon part of a polysilicon thin film transistor. A first conductor layer includes a first gate electrode part of the polysilicon thin film transistor. A first insulator layer includes a first insulator part between the first gate electrode part and the polysilicon part. An oxide semiconductor layer includes an oxide semiconductor part of an oxide semiconductor thin film transistor. A second conductor layer includes a second gate electrode part of the oxide semiconductor thin film transistor. A second insulator layer includes a second insulator part between the second gate electrode part and oxide semiconductor part. The second insulator layer has a specific dielectric constant of 8 or larger. The entire region of the second insulator layer is covered with the second conductor layer.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present disclosure relates to thin film transistor circuits. [Background technology]

[0002] A technology that combines low-temperature polysilicon thin-film transistors (LTPS TFTs) and oxide semiconductor TFTs into one circuit has been put to practical use. For example, a pixel circuit that includes a low-temperature polysilicon TFT and an oxide semiconductor TFT has been proposed. By combining both a low-temperature polysilicon TFT with high mobility and an oxide semiconductor TFT with low leakage current into a circuit, it is possible to improve the circuit characteristics and reduce power consumption.

[0003] Since the mobility of oxide semiconductor TFTs is low, it has been proposed to use a high-k insulator as the gate insulator of an oxide semiconductor TFT in order to increase the on-state current or reduce the driving voltage of the oxide semiconductor TFT. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] US Patent Application Publication No. 2018 / 0308869 [Patent Document 2] US Patent Application Publication No. 2018 / 0033849 [Patent Document 3] US Patent Application Publication No. 2005 / 0045970 [Patent Document 4] US Patent Application Publication No. 2018 / 0061914 Summary of the Invention [Problem to be solved by the invention]

[0005] High-k films have a higher dielectric constant than typical gate insulating films such as silicon insulating films. This can increase the on-current of TFTs, but can also cause large parasitic capacitance. Therefore, technology is needed to improve the current characteristics of oxide semiconductor TFTs while suppressing the generation of undesirable parasitic capacitance. [Means for solving the problem]

[0006] A thin-film transistor circuit according to an embodiment of the present disclosure includes a polysilicon layer, a first conductor layer above the polysilicon layer, a first insulator layer between the first conductor layer and the polysilicon layer, an oxide semiconductor layer, a second conductor layer above the oxide semiconductor layer, and a second insulator layer between the second conductor layer and the oxide semiconductor layer. The polysilicon layer includes a polysilicon portion of a polysilicon thin-film transistor. The first conductor layer includes a first gate electrode portion of the polysilicon thin-film transistor. The first insulator layer includes a first insulator portion between the first gate electrode portion and the polysilicon portion. The oxide semiconductor layer includes an oxide semiconductor portion of an oxide semiconductor thin-film transistor. The second conductor layer includes a second gate electrode portion of the oxide semiconductor thin-film transistor. The second insulator layer includes a second insulator portion between the second gate electrode portion and the oxide semiconductor portion. The second insulator layer has a relative dielectric constant of 8 or more. The entire area of ​​the second insulator layer is covered by the second conductor layer.

[0007] A method for manufacturing a thin-film transistor circuit according to an embodiment of the present disclosure includes forming a polysilicon layer including a polysilicon portion of a polysilicon thin-film transistor, forming a first insulator layer above the polysilicon layer including an insulator portion of the polysilicon thin-film transistor, forming a first conductor layer above the first insulator layer including a gate electrode portion of the polysilicon thin-film transistor, forming an oxide semiconductor layer including an oxide semiconductor portion of an oxide semiconductor thin-film transistor, forming a second insulator layer above the oxide semiconductor layer including an insulator portion of the oxide semiconductor thin-film transistor, and forming a second conductor layer above the second insulator layer including a gate electrode portion of the oxide semiconductor thin-film transistor. The second insulator layer has a relative dielectric constant of 8 or more. The second conductor layer and the second insulator layer are etched simultaneously, or the second insulator layer is etched using the second conductor layer as a mask. Effect of the Invention

[0008] According to one aspect of the present disclosure, the characteristics of a circuit including a polysilicon thin film transistor and an oxide semiconductor thin film transistor can be improved. [Brief description of the drawings]

[0009] [Figure 1] 1 shows a schematic configuration example of an OLED display device. [Diagram 2] 2 shows a configuration example of a pixel circuit. [Diagram 3] 2 is a schematic diagram showing a cross-sectional structure of a portion of a TFT substrate. [Figure 4] 4A and 4B are schematic cross-sectional views of another part of the TFT substrate. [Diagram 5] 1 is a plan view of a portion of a TFT substrate. [Figure 6] An example of a CMOS circuit is shown below. [Figure 7] 7 shows a schematic diagram of an example of the cross-sectional structure of the CMOS circuit shown in FIG. [Figure 8A] The steps of an example method for manufacturing the structure shown in FIG. 3 are shown. [Figure 8B]The steps of an example method for manufacturing the structure shown in FIG. 3 are shown. [Figure 8C] The steps of an example method for manufacturing the structure shown in FIG. 3 are shown. [Figure 8D] The steps of an example method for manufacturing the structure shown in FIG. 3 are shown. [Figure 8E] The steps of an example method for manufacturing the structure shown in FIG. 3 are shown. [Figure 8F] The steps of an example method for manufacturing the structure shown in FIG. 3 are shown. [Figure 9] 13 is a schematic diagram showing a cross-sectional structure of a portion of a pixel circuit according to a second embodiment. [Figure 10] 5 is a schematic diagram showing a cross-sectional structure of a CMOS circuit according to a second embodiment. [Figure 11] 1 shows a cross-sectional view of a configuration example of an oxide semiconductor TFT according to a third embodiment. [Figure 12] 11 is a cross-sectional view of another example of the configuration of the oxide semiconductor TFT according to the third embodiment. [Figure 13A] The steps of an example of a method for manufacturing the oxide semiconductor TFT shown in FIG. 11 are shown below. [Figure 13B] The steps of an example of a method for manufacturing the oxide semiconductor TFT shown in FIG. 11 are shown below. [Figure 13C] The steps of an example of a method for manufacturing the oxide semiconductor TFT shown in FIG. 11 are shown below. [Figure 13D] The steps of an example of a method for manufacturing the oxide semiconductor TFT shown in FIG. 11 are shown below. [Figure 13E] The steps of an example of a method for manufacturing the oxide semiconductor TFT shown in FIG. 11 are shown below. [Figure 13F] The steps of an example of a method for manufacturing the oxide semiconductor TFT shown in FIG. 11 are shown below. [Figure 14] An example in which the oxide semiconductor TFT having the structure described with reference to FIG. 11 is applied to the pixel circuit shown in FIG. 4 will be described. [Figure 15] An example will be shown in which the oxide semiconductor TFT having the structure described with reference to FIG. 11 is applied to the CMOS circuit shown in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, an embodiment of the present disclosure will be described with reference to the accompanying drawings. It should be noted that this embodiment is merely an example for realizing the present disclosure and does not limit the technical scope of the present disclosure. The same reference symbols are used for common configurations in each drawing. For ease of explanation, the dimensions and shapes of the objects shown in the drawings may be exaggerated.

[0011] [overview] In the following, an OLED (Organic Light-Emitting Diode) display device will be described as an example of a device including a thin-film transistor circuit. The OLED display device of the present disclosure includes a low-temperature polysilicon thin-film transistor (LTPS TFT) and an oxide semiconductor TFT in a pixel circuit and / or a peripheral circuit. An example of the oxide semiconductor is IGZO (Indium Gallium Zinc Oxide).

[0012] Since the leakage current of the oxide semiconductor TFT is small, for example, the oxide semiconductor TFT is used as a switch transistor connected to a storage capacitor (capacitor element) for maintaining the gate potential of a drive transistor in a pixel circuit. A low-temperature polysilicon TFT with high mobility is used as a drive transistor. The configuration of the present disclosure can be applied to devices other than a display device.

[0013] In one embodiment of the present specification, the oxide semiconductor TFT has a top gate structure, and the gate insulator is made of a high-k insulator with a high dielectric constant. In the following description, the high-k insulator has a dielectric constant of 8 or more. By using an insulator with a high dielectric constant for the gate insulator, the on-current characteristics of the oxide semiconductor TFT can be improved and the element size and driving voltage can be reduced. The high-k insulator has a dielectric constant of, for example, 100 or less, and in another example, 50 or less.

[0014] In a thin film transistor circuit having a stacked structure, a gate electrode portion of the oxide semiconductor TFT is included in one conductor layer, a gate insulator portion of the oxide semiconductor TFT is included in one high-k insulator layer, and an oxide semiconductor portion of the oxide semiconductor TFT is included in one oxide semiconductor layer.

[0015] The gate electrode portion, the gate insulator portion, and the oxide semiconductor portion are each a part of the oxide semiconductor TFT, and are the entire material film or a part of the material film. A layer is formed by the same material and the same process, and may be one continuous film or a plurality of separated films. A film may have a single layer or a laminated structure.

[0016] In one embodiment of the present specification, the entire area of ​​the high-k insulator layer is covered by the conductor layer including the gate electrode portion when viewed in the stacking direction (in a plan view). This configuration makes it possible to suppress the generation of parasitic capacitance due to the high-k insulator. In one pixel circuit according to one embodiment of the present specification, the high-k insulator layer includes a gate insulator portion of an oxide semiconductor TFT. In another embodiment, the high-k insulator layer further includes an insulator portion of a storage capacitor for maintaining the gate potential of the driving TFT. This makes it possible to reduce the area of ​​the storage capacitor.

[0017] In one example pixel circuit, the only conductors and semiconductors that overlap with the insulator layer in the stacking direction below the insulator layer including the gate insulator are the oxide semiconductor portion of the oxide semiconductor TFT. In another example pixel circuit, the only conductors and semiconductors that overlap with the insulator layer in the stacking direction below the insulator layer including the gate insulator are the oxide semiconductor portion of the oxide semiconductor TFT and the lower electrode portion of the storage capacitor.

[0018] <Embodiment 1> [Display device configuration] 1 is a schematic diagram showing a configuration example of an OLED display device 1. The OLED display device 1 includes a TFT (Thin Film Transistor) substrate 10 on which OLED elements and pixel circuits are formed, a sealing substrate 20 for sealing the organic light-emitting elements, and a joint (glass frit seal) 30 for joining the TFT substrate 10 and the sealing substrate 20. Dry nitrogen, for example, is filled between the TFT substrate 10 and the sealing substrate 20, and the TFT substrate 10 and the sealing substrate 20 are sealed by the joint 30. The sealing substrate 20 and the joint 30 are one part of the sealing structure, and as another example, the sealing structure may have, for example, a thin film encapsulation (TFE) structure.

[0019] A scan driver 31, an emission driver 32, a protection circuit 33, a driver IC 34, and a demultiplexer 36 are arranged around the cathode electrode formation region 14 outside the display region 25 of the TFT substrate 10. The driver IC 34 is connected to an external device via an FPC (Flexible Printed Circuit) 35. The scan driver 31, the emission driver 32, and the protection circuit 33 are peripheral circuits formed on the TFT substrate 10.

[0020] The scan driver 31 drives the scan lines of the TFT substrate 10. The emission driver 32 drives the emission control lines to control the light emitting period of each pixel. The driver IC 34 is implemented using, for example, an anisotropic conductive film (ACF).

[0021] The protection circuit 33 prevents electrostatic damage to elements in the pixel circuits. The driver IC 34 provides power and timing signals (control signals) to the scan driver 31 and the emission driver 32. Furthermore, the driver IC 34 provides power and data signals to the demultiplexer 36.

[0022] The demultiplexer 36 sequentially outputs the output of one pin of the driver IC 34 to d data lines (d is an integer equal to or greater than 2). The demultiplexer 36 switches the output data line of the data signal from the driver IC 34 d times within a scanning period, thereby driving d times as many data lines as the number of output pins of the driver IC 34.

[0023] [Pixel circuit configuration] On the TFT substrate 10, a plurality of pixel circuits are formed, which control the current supplied to the anode electrodes of a plurality of sub-pixels (also simply called pixels). FIG. 2 shows an example of the configuration of the pixel circuits. Each pixel circuit includes a drive transistor T1, a selection transistor T2, an emission transistor T3, and a storage capacitor C1. The pixel circuit controls the emission of the OLED element E1. The transistors are TFTs. The transistors other than the drive transistor T1 are switch transistors.

[0024] The selection transistor T2 is a switch for selecting a subpixel. The selection transistor T2 is an n-channel oxide semiconductor TFT, and has a gate terminal connected to a scanning line 16. A source terminal is connected to a data line 15. A drain terminal is connected to the gate terminal of the driving transistor T1.

[0025] The driving transistor T1 is a transistor (driving TFT) for driving the OLED element E1. The driving transistor T1 is a p-channel low-temperature polysilicon TFT, and its gate terminal is connected to the drain terminal of the selection transistor T2. The source terminal of the driving transistor T1 is connected to the drain terminal of the emission transistor T3, and the drain terminal is connected to the OLED element E1. A storage capacitor C1 is formed between the gate terminal of the driving transistor T1 and the power line 18.

[0026] The emission transistor T3 is a switch that controls the supply and stop of the driving current to the OLED element E1. The emission transistor T3 is a p-channel polysilicon TFT, and the gate terminal is connected to the emission control line 17. The source terminal of the emission transistor T3 is connected to the power supply line 18. The drain terminal is connected to the source terminal of the driving transistor T1.

[0027] Next, the operation of the pixel circuit will be described. The scan driver 31 outputs a selection pulse to the scan line 16 to turn on the selection transistor T2. The data voltage supplied from the driver IC 34 via the data line 15 is stored in the storage capacitor C1. The storage capacitor C1 holds the stored voltage throughout one frame period. The hold voltage changes the conductance of the drive transistor T1 in an analog manner, and the drive transistor T1 supplies a forward bias current corresponding to the light emission gradation to the OLED element E1.

[0028] The emission transistor T3 is located on a supply path of the driving current. The emission driver 32 outputs a control signal to the emission control line 17 to control the on / off of the emission transistor T3. When the emission transistor T3 is in the on state, the driving current is supplied to the OLED element E1. When the emission transistor T3 is in the off state, the supply is stopped. By controlling the on / off of the emission transistor T3, the lighting period (duty ratio) within one frame period can be controlled. It should be noted that the pixel circuit in FIG. 2 is an example, and the pixel circuit may have another configuration.

[0029] [TFT substrate configuration] In the following, a configuration example of a TFT substrate including a low-temperature polysilicon TFT and an oxide semiconductor TFT will be described. The oxide semiconductor is, for example, IGZO. The configuration described in this specification can be applied to a circuit including a TFT of another type of oxide semiconductor.

[0030] 3 shows a schematic cross-sectional structure of a portion of the TFT substrate. A low-temperature polysilicon TFT 141, an oxide semiconductor TFT 142, a storage capacitor 143, and an OLED element 144 are formed on an insulating substrate 101. These correspond to the drive transistor T1, the selection transistor T2, the storage capacitor C1, and the OLED element E1 shown in FIG. 2, respectively.

[0031] The insulating substrate 101 is a flexible or inflexible substrate made of resin or glass. The low-temperature polysilicon TFT 141 includes a low-temperature polysilicon portion 102. The low-temperature polysilicon portion 102 is, for example, an island-shaped low-temperature polysilicon active film, and includes source / drain regions 104, 105 and a channel region 103 between the source / drain regions 104, 105 in the in-plane direction.

[0032] The source / drain regions 104, 105 are formed of low-temperature polysilicon whose resistance has been reduced by high-concentration impurity doping, and are connected to source / drain electrode portions 109, 110. The channel region 103 is formed of low-temperature polysilicon whose resistance has not been reduced (high-resistance low-temperature polysilicon).

[0033] The low-temperature polysilicon portion 102 is included in a low-temperature polysilicon layer. The low-temperature polysilicon layer includes low-temperature polysilicon portions of low-temperature polysilicon TFTs of a plurality of pixel circuits. The low-temperature polysilicon layer is formed (directly) on an insulating substrate 101. In the example of Fig. 3, the low-temperature polysilicon portion 102 contacts the insulating substrate 101, but there may be another insulating layer (e.g., a silicon nitride layer) between them.

[0034] The low-temperature polysilicon TFT 141 has a top gate structure. The low-temperature polysilicon TFT may include a bottom gate in addition to a top gate. This is similar to other embodiments. The low-temperature polysilicon TFT 141 further includes a gate electrode portion 107 and a gate insulator portion 106 that exists between the gate electrode portion 107 and the channel region 103 in the stacking direction. The gate insulator portion 106 (first insulator portion) is included in an insulator layer (first insulator layer) that includes the gate insulator portions of other low-temperature polysilicon TFTs. The channel region 103, the gate insulator portion 106, and the gate electrode portion 107 are stacked in this order from below (from the substrate side), and the gate insulator portion 106 is in contact with the channel region 103 and the gate electrode portion 107.

[0035] The gate electrode portion 107 (first gate electrode portion) is made of a conductor and is included in the conductor layer (first conductor layer). The gate electrode portion 107 is made of, for example, a metal. Any metal material may be used, and for example, Mo, W, Nb, Al, etc. are used. In the configuration example shown in FIG. 3, the metal film including the gate electrode portion 107 and the insulating film including the gate insulator portion 106 are island-shaped, and the entire area of ​​the insulating film is covered with the metal film. In this example, the gate insulator portion 106 is made of silicon oxide and is included in the silicon oxide layer. This can improve the operational stability of the low-temperature polysilicon TFT 141.

[0036] The interlayer insulating film 108 is formed so as to cover the low-temperature polysilicon portion 102, the gate insulator portion 106, and the gate electrode portion 107. The interlayer insulating film 108 is, for example, a silicon oxide film or a silicon nitride film. The source / drain electrode portions 109, 110 are formed on the interlayer insulating film 108 and are in contact with the source / drain regions 104, 105 via contact holes in the interlayer insulating film 108. The material of the source / drain electrode portions 109, 110 can be, for example, Al or Ti.

[0037] The storage capacitor 143 includes a lower electrode portion 111, an upper electrode portion 120 facing the lower electrode portion 111, and an insulator portion 118 between the lower electrode portion 111 and the upper electrode portion 120. The lower electrode portion 111 is continuous with the source / drain electrode portion 110 on the interlayer insulating film 108. The lower electrode portion 111 is included in the same conductor layer as the source / drain electrode portions 109, 110.

[0038] An interlayer insulating film 112 is laminated on the interlayer insulating film 108. The interlayer insulating film 112 is, for example, a silicon oxide film. The interlayer insulating film 112 is formed so as to cover the lower electrode portion 111, the source / drain electrode portions 109, 110, and the interlayer insulating film 108. An opening is formed in the interlayer insulating film 112 in a partial region between the lower electrode portion 111 and the upper electrode portion 120. An insulator portion 118 is formed in and around the opening.

[0039] The insulator portion 118 is made of a high-k insulating material, and is in contact with the lower electrode portion 111 in the opening, and its upper surface is in contact with the upper electrode portion 120. The entire insulator portion of the storage capacitor 143 is composed of the high-k insulator portion 118 and a part of the insulator portion of the interlayer insulating film 112. The high-k insulating material is, for example, a metal compound insulating material such as a metal oxide or a metal nitride. Specifically, TaOx, AlOx, HfOx, ZrOx, YOx, NbOx, etc. can be used. The presence of at least a part of the insulator portion 118 in the opening increases the average relative dielectric constant of the storage capacitor 143, thereby making it possible to further increase the capacitance.

[0040] The oxide semiconductor TFT 142 includes an oxide semiconductor section 113. The oxide semiconductor section 113 is, for example, an island-shaped oxide semiconductor active film, and includes source / drain regions 115, 116 and a channel region 114 between the source / drain regions 115, 116 in the in-plane direction.

[0041] The source / drain regions 115, 116 are formed of low-resistance IGZO, and are connected to source / drain electrode portions 122, 123. The channel region 114 is formed of IGZO that has not been low-resistance (high-resistance IGZO).

[0042] The oxide semiconductor portion 113 is included in an oxide semiconductor layer. The oxide semiconductor layer includes the oxide semiconductor portions of a plurality of oxide semiconductor TFTs. The oxide semiconductor layer is formed on an interlayer insulating film 112.

[0043] The oxide semiconductor TFT 142 has a top gate structure. The oxide semiconductor TFT may include a bottom gate in addition to a top gate. This is similar to other embodiments. The oxide semiconductor TFT 142 further includes a gate electrode portion 119 and a gate insulator portion 117 that is present between the gate electrode portion 119 and the channel region 114 in the stacking direction. The channel region 114, the gate insulator portion 117, and the gate electrode portion 119 are stacked in this order from below (from the substrate side), and the gate insulator portion 117 is in contact with the channel region 114 and the gate electrode portion 119.

[0044] The gate electrode portion 119 (second gate electrode portion) is made of a conductor and is included in the conductor layer (second conductor layer). The gate electrode portion 119 is made of, for example, a metal. Any metal material may be used, and examples of the metal that may be used include Mo, W, Nb, and Al.

[0045] The gate insulator 117 (second insulator) is included in a high-k insulator layer (second insulator layer) formed of a high-k insulating material. The high-k insulator layer includes an insulator 118 of a storage capacitor 143. The high-k includes oxide semiconductor TFTs of a plurality of pixel circuits and insulators of the storage capacitors. In the configuration example shown in FIG. 3, the metal film including the gate electrode portion 119 and the insulating film including the gate insulator 117 are island-shaped, and the entire area of ​​the insulating film is covered by the metal film. FIG. 3 shows one low-temperature polysilicon TFT and one oxide semiconductor TFT as an example, but the other low-temperature polysilicon TFTs and oxide semiconductor TFTs in the pixel circuit also have the same structure.

[0046] The interlayer insulating film 121 is formed so as to cover the oxide semiconductor portion 113, the gate insulator portion 117, and the gate electrode portion 119 of the oxide semiconductor TFT 142, as well as the insulator portion 118 and the upper electrode portion 120 of the storage capacitor 143. The interlayer insulating film 121 covers a part of the interlayer insulating film 112. The interlayer insulating film 121 is, for example, a silicon oxide film.

[0047] Source / drain electrode sections 122, 123 of the oxide semiconductor TFT 142 are formed on the interlayer insulating film 121. The source / drain electrode sections 122, 123 are connected to source / drain regions 115, 116 of the oxide semiconductor TFT 142 via contact holes formed in the interlayer insulating film 121.

[0048] Furthermore, the connection portion 129 continuous with the source / drain electrode portion 123 is connected to the upper electrode portion 120 of the storage capacitor 143 through a contact hole formed in the interlayer insulating film 121, and is connected to the gate electrode portion 107 of the low-temperature polysilicon TFT 141 through contact holes formed in the interlayer insulating films 121, 112, and 108. The connection portion 129 interconnects the source / drain electrode portion 123, the upper electrode portion 120, and the gate electrode portion 107. The source / drain electrode portions 122, 123, and the connection portion 129 are included in the conductor layer. The material of the conductor layer is arbitrary, and for example, Al or Ti can be used.

[0049] An insulating planarization film 124 is laminated so as to cover the exposed portions of the conductor layer and the interlayer insulating film 121. The planarization film 124 can be made of, for example, an organic material. An anode electrode portion 125 is formed on the planarization film 124. The anode electrode portion 125 is connected to the source / drain electrode portion 109 of the low-temperature polysilicon TFT 141 via contact holes in the planarization film 124 and the interlayer insulating films 121 and 112.

[0050] The anode electrode section 125 includes three layers: a transparent film such as ITO or IZO, a reflective film of a metal such as Ag, Mg, Al, or Pt, or an alloy containing these metals, and the transparent film. Note that the three-layer structure of the anode electrode section 125 is just an example, and it may be a two-layer structure.

[0051] An insulating pixel definition layer 126 is formed on the anode electrode section 125 to separate the OLED elements 144. The pixel definition layer 126 can be made of, for example, an organic material. An organic light-emitting film 127 is formed on the anode electrode section 125. The organic light-emitting film 127 is composed of, from the bottom up, a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer. The layered structure of the organic light-emitting film 127 is determined by design.

[0052] Furthermore, a cathode electrode unit 128 is formed on the organic light-emitting film 127. The cathode electrode unit 128 of one OLED element 144 is a part of a continuous conductor film. The cathode electrode unit 128 transmits a part of visible light from the organic light-emitting film 127. The laminated film of the anode electrode unit 125, the organic light-emitting film 127, and the cathode electrode unit 128 formed in the opening of the pixel definition layer 126 constitutes the OLED element 144.

[0053] Fig. 4 shows a schematic cross-sectional structure of another part of the TFT substrate. Fig. 4 does not show the OLED elements 144 shown in Fig. 3, but shows the scanning lines 130 that transmit selection signals for selecting sub-pixels to which data signals are applied. The scanning lines 130 are formed on the planarization film 124, and are connected to the gate electrode portions 119 of the oxide semiconductor TFTs 142 through contact holes formed in the planarization film 124 and the interlayer insulating film 121.

[0054] In Fig. 4, layers including conductive components are indicated by symbols. In the example described below, the conductor layer is a metal layer. Specifically, the gate electrode portion 107 of the low-temperature polysilicon TFT 141 is included in the metal layer M1. The lower electrode portion 111 of the storage capacitor 143 and the source / drain electrode portions 109, 110 of the low-temperature polysilicon TFT 141 are included in the metal layer M2.

[0055] The gate electrode portion 119 of the oxide semiconductor TFT 142 and the upper electrode portion 120 of the storage capacitor 143 are included in a metal layer M3. The source / drain electrode portions 122, 123 and the connection portion 129 of the oxide semiconductor TFT 142 are included in a metal layer M4. The scanning line 130 is included in a metal layer M5. As described above, the gate insulator portion of the oxide semiconductor TFT 142 and the insulator portion of the storage capacitor 143 are included in the same high-k insulator layer.

[0056] 5 shows a plan view of a portion of the TFT substrate. A metal film 151 included in the lowermost metal layer M1 includes a gate electrode portion 107 of a low-temperature polysilicon TFT 141. The gate electrode portion 107 is, for example, a portion of the metal film 151 that overlaps with the low-temperature polysilicon portion 102 in a plan view (stacking direction).

[0057] The metal layer M2 above the metal layer M1 includes metal films 152 and 153. The metal film 152 includes a source / drain electrode portion 109 of the low-temperature polysilicon TFT 141. The metal film 153 includes a source / drain electrode portion 110 of the low-temperature polysilicon TFT 141 and a lower electrode portion 111 of the storage capacitor 143. The lower electrode portion 111 is, for example, a region that overlaps with the upper electrode portion 120 of the storage capacitor 143 in a plan view.

[0058] The metal layer M3 above the metal layer M2 includes a metal film 154 and an upper electrode portion 120 of the storage capacitor 143 which is a metal film. The metal film 154 includes a gate electrode portion 119 of the oxide semiconductor TFT 152 and a connection portion that connects the gate electrode portion 119 to the scanning line 130. The gate electrode portion 119 is, for example, a portion of the metal film 154 that overlaps with the oxide semiconductor portion 113 in a planar view (stacking direction). The upper electrode portion 120 is composed of one metal film. The upper electrode portion 120 is smaller than the metal film 153, and the outer periphery of the upper electrode portion 120 is inside the outer periphery of the metal film 153 in a planar view, and the entire area is within the area of ​​the metal film 153.

[0059] A high-k insulator film including a gate insulator portion 117 is disposed directly below the metal film 154. The entire area of ​​this insulator film is covered by the metal film 154. In one example, the outer periphery of this insulator film coincides with the outer periphery of the metal film 154. Furthermore, an insulator portion 118 of the storage capacitor 143, which is a high-k insulator film, is disposed directly below the upper electrode portion 120 of the storage capacitor 143. The entire area of ​​the insulator portion 118 (insulator film) is covered by the upper electrode portion 120. In one example, the outer periphery of this insulator portion 118 coincides with the outer periphery of the upper electrode portion 120.

[0060] As described above, the gate insulator 117 and the insulator 118 are included in the same high-k insulator layer. Similarly, the entire area of ​​the insulator film including the gate insulator of the other oxide semiconductor TFTs in the pixel circuit is covered with a metal film including the gate electrode portion. The gate insulator of all the oxide semiconductor TFTs in the pixel circuit are included in the same high-k insulator layer. The entire area of ​​the high-k insulator layer including these insulator portions is covered with the metal layer M3. This configuration makes it possible to suppress an increase in parasitic capacitance due to the high-k insulator.

[0061] The metal layer M4 above the metal layer M3 includes a metal film 155. The metal film 155 is a part of the source / drain electrode portion of the oxide semiconductor TFT 142. 123 It also includes a connection portion 129 that interconnects the source / drain electrode portion 123 , the upper electrode portion 120 and the gate electrode portion 107 of the low-temperature polysilicon TFT 141 .

[0062] Metal layer M5 above metal layer M4 includes scanning line 130. Since scanning line 130 connected to gate electrode portion 119 of oxide semiconductor TFT 142 is formed in a metal layer different from that of gate electrode portion 119, no high-k insulator is formed directly below scanning line 130, and parasitic capacitance can be suppressed.

[0063] In one example of a pixel circuit, the only conductor below the high-k insulator layer that overlaps with the high-k insulator layer in a planar view is the lower electrode portion 111 of the storage capacitor 143. Also, the only semiconductors that overlap with the high-k insulator layer are the oxide semiconductor portions of all the oxide semiconductor TFTs in the pixel circuit. This configuration can effectively suppress the occurrence of parasitic capacitance due to the high-k insulator. Note that the entire insulator portion of the storage capacitor 143 may be formed of an insulator other than the high-k insulator, such as silicon oxide or silicon nitride.

[0064] Next, the CMOS circuit configuration included in the driver circuits 31 and 32 on the TFT substrate will be described. Fig. 6 shows an example of the CMOS circuit. The CMOS circuit includes a p-channel low-temperature polysilicon TFT 201 and an n-channel oxide semiconductor TFT 202. The source / drain of the low-temperature polysilicon TFT 201 is connected to the source / drain of the n-channel oxide semiconductor TFT 202. The gates of the low-temperature polysilicon TFT 201 and the oxide semiconductor TFT 202 are connected, and the same signal is input to them.

[0065] 7 is a schematic diagram showing an example of the cross-sectional structure of the CMOS circuit shown in FIG. 6. The differences from the cross-sectional structure shown in FIG. 3 will be mainly described. In the example shown in FIG. 7, the retention capacitance of the example shown in FIG. 143 In addition, the source / drain electrode section 210 of the low-temperature polysilicon TFT 201 and the source / drain electrode section 223 of the oxide semiconductor TFT 202 are connected, and further, the gate electrode section 207 and the gate electrode section 219 are connected.

[0066] In one example, the low-temperature polysilicon TFT 201 in FIG. 7 has a similar structure to the low-temperature polysilicon TFT 141 shown in FIG. 3, although their sizes may differ. The low-temperature polysilicon TFT 201 includes a low-temperature polysilicon portion 208, a gate insulator portion 206, and a gate electrode portion 207. The low-temperature polysilicon portion 208 includes a channel region 203 and source / drain regions 204, 205. The source / drain electrode portions 209, 210 are connected to the source / drain regions 204, 205 through contact holes in the interlayer insulating film 108.

[0067] The low-temperature polysilicon portion 208, the gate insulator portion 206, the gate electrode portion 207, and the source / drain electrode portions 209 and 210 correspond to the low-temperature polysilicon portion 102, the gate insulator portion 106, the gate electrode portion 107, and the source / drain electrode portions 109 and 110 shown in Fig. 3, respectively. Corresponding components are included in the same layer.

[0068] In one example, the oxide semiconductor TFT 202 in FIG. 7 has a similar configuration to the oxide semiconductor TFT 142 shown in FIG. 3. Their sizes may be different. The oxide semiconductor TFT 202 includes an oxide semiconductor portion 213, a gate insulator portion 217, and a gate electrode portion 219. The oxide semiconductor portion 213 includes a channel region 214 and source / drain regions 215, 216. The oxide semiconductor portion 213, the gate insulator portion 217, and the gate electrode portion 219 correspond to the oxide semiconductor portion 113, the gate insulator portion 117, and the gate electrode portion 119 shown in FIG. 3, respectively. Corresponding components are included in the same layer.

[0069] The connection portion 229 is continuous with the source / drain electrode portion 223 of the oxide semiconductor TFT 202, and is connected to the source / drain electrode portion 210 of the low-temperature polysilicon TFT 201 through a contact hole penetrating the interlayer insulating films 112 and 121. The connection portion 230 is connected to the gate electrode portion 219 of the oxide semiconductor TFT 202 through a contact hole penetrating the interlayer insulating film 121 and the planarizing film 124. The connection portion 230 is further connected to the gate electrode portion 207 of the low-temperature polysilicon TFT 201 through a contact hole penetrating the interlayer insulating films 108, 112, 121 and the planarizing film 124. The connection portion 230 is included in the metal layer M5.

[0070] 3, the gate insulator 217 of the oxide semiconductor TFT 202 is included in the high-k insulator layer. In the driver circuits 31 and 32, the entire area of ​​the insulator film including the gate insulator of the oxide semiconductor TFT is covered with a metal film including the gate electrode of the oxide semiconductor TFT.

[0071] The gate insulators of all the oxide semiconductor TFTs in the driver circuits 31 and 32 are included in the same high-k insulator layer. The entire high-k insulator layer, including these insulators, is covered by a metal layer including the gate electrode portion 219 of the oxide semiconductor TFT 202. This configuration of the insulator layer can suppress an increase in parasitic capacitance due to the high-k insulator. In one example, the periphery of each high-k insulator layer coincides with the periphery of the metal film that overlaps it.

[0072] In one example, in the driver circuits 31 and 32, the conductors and semiconductors that overlap the high-k insulator layer in a plan view below the high-k insulator layer are only the oxide semiconductor parts of one or more oxide semiconductor TFTs in the driver circuits, or only the oxide semiconductor parts of one or more oxide semiconductor TFTs and the lower electrodes of one or more capacitors. With this configuration, it is possible to effectively suppress the generation of parasitic capacitance due to the high-k insulator.

[0073] [Manufacturing method] Referring to FIGS. 8A to 8F, a manufacturing method of the structure shown in FIG. 3 will be described. As shown in FIG. 8A, the manufacturing starts with forming a low-temperature polysilicon TFT 141. First, a low-temperature polysilicon portion 102 is formed on an insulating substrate 101. Specifically, for example, amorphous silicon is deposited by a CVD method and crystallized by excimer laser annealing to form a low-temperature polysilicon film. By patterning using photolithography, an island-shaped low-temperature polysilicon portion 102 is formed.

[0074] Next, in the manufacturing, an insulator layer (for example, a SiOx film) including a gate insulator portion 106 is formed by, for example, a CVD method or the like. Further, a metal layer M1 (see FIG. 4) is formed by a sputtering method or the like, and patterning (etching) of the metal layer M1 and the insulator layer is performed simultaneously (in the same process using the same mask) by photolithography to form a gate electrode portion 107 and an insulator portion 106. Thereby, an insulator remains only directly under the metal layer M1. Another example is that after etching the metal layer including the gate electrode portion 107, the lower insulator layer may be etched using this metal layer M1 as a mask.

[0075] Furthermore, impurities are implanted into the low-temperature polysilicon portion 102 using the gate electrode portion 107 as a mask to form low-resistance regions 104 and 105. The high-resistance region covered by the gate electrode portion 107 is the channel region 103.

[0076] Next, in the manufacturing, an interlayer insulating film 108 is formed by a CVD method or the like, and a contact hole is formed in the stacked insulating film by anisotropic etching. Further, a metal layer M2 (see FIG. 4) is formed by a sputtering method or the like, and patterning is performed by photolithography to form source / drain electrode portions 109 and 110 and a lower electrode portion 111 of a holding capacitor 143 (see FIG. 4).

[0077] 8B, the manufacturing process involves forming an interlayer insulating film 112 by a CVD method or the like on the interlayer insulating film 108 and the source / drain electrode portions 109 and 110. Next, an oxide semiconductor layer is formed by a sputtering method or the like, and patterned by photolithography. As a result, an island-shaped oxide semiconductor portion 113 of the oxide semiconductor TFT 142 (see FIG. 4) is formed.

[0078] Next, referring to FIG. 8C, in the manufacturing process, a part of the interlayer insulating film 112 is removed by etching to expose a part of the lower electrode portion 111 of the storage capacitor 143 (see FIG. 4) from the opening of the interlayer insulating film 112.

[0079] Next, referring to Fig. 8D, in the manufacturing process, a high-k insulating film is formed by a sputtering method or the like. Furthermore, a metal layer M3 (see Fig. 4) is formed by a sputtering method or the like. The metal layer M3 and the high-k insulating film are patterned (etched) by photolithography simultaneously (in the same process using the same mask) to form a gate electrode portion 119 of the oxide semiconductor TFT 142, an upper electrode portion 120 of the storage capacitor 143, a gate insulator portion 117, and an insulator portion 118 of the storage capacitor 143.

[0080] As a result, the high-k insulator is left only directly below the metal layer M3, and the entire high-k insulating layer is covered with the metal layer M3. In another example, the metal layer M3 is patterned to form the gate electrode portion 119 and the upper electrode portion 120, and the high-k insulating film is patterned using the metal layer (metal pattern) M3 as a mask. The insulator portion 118 of the storage capacitor 143 is also formed in the opening of the interlayer insulating film 112. This increases the average relative dielectric constant of the storage capacitor 143, and increases the capacitance of the storage capacitor 143.

[0081] 8E, the manufacturing process involves using the gate electrode portion 119 as a mask to reduce the resistance of both end regions 115, 116 of the oxide semiconductor portion 113. The reduction in resistance is achieved, for example, by exposing the region of the oxide semiconductor portion 113 exposed from the gate electrode portion 119 to He plasma. The region 114 covered by the gate electrode portion 119 is a high-resistance channel region. The reduction in resistance may be achieved when the next interlayer insulating film 121 is formed.

[0082] 8F, the manufacturing process involves forming an interlayer insulating film 121 by a CVD method or the like, and performing anisotropic etching by photolithography to form contact holes. Furthermore, a metal layer M4 (see FIG. 4) is formed by a sputtering method or the like, and patterning is performed by photolithography. As a result, source / drain electrode parts 122, 123 and a connection part 129 of the oxide semiconductor TFT 142 are formed.

[0083] Although not shown in the figure, the manufacturing process then includes forming a planarization film 124 and a metal layer M5, and then forming an anode electrode portion 125. Furthermore, after forming a pixel definition layer 126, an organic light-emitting material is formed on the anode electrode portion 125. The organic light-emitting film is formed by evaporating the organic light-emitting material at positions corresponding to the pixels using a metal mask. Furthermore, a metal material for the cathode electrode portion 128 is attached.

[0084] <Embodiment 2> Hereinafter, a description will be given of an example of a circuit including an oxide semiconductor TFT having a structure different from that of embodiment 1. Fig. 9 shows a schematic cross-sectional structure of a portion of a pixel circuit. Below, differences from the configuration shown in Fig. 3 will be mainly described.

[0085] The entire gate insulator of the oxide semiconductor TFT 142 is composed of multiple stacked insulator parts. Specifically, it is composed of a high-k insulator part 136 and an interface insulator part 135. The interface insulator part 135 forms an interface with each of the high-k insulator part 136 and the oxide semiconductor part 113.

[0086] In one example, the interface insulator 135 is included in a silicon insulator layer that includes the interface insulator of another oxide semiconductor TFT. For example, the silicon insulator layer is formed of, for example, silicon oxide (SiOx). Another example is silicon nitride. By inserting a silicon insulator between the high-k insulator and the oxide semiconductor, the characteristics of the oxide semiconductor TFT 142 can be stabilized.

[0087] The dielectric constant of silicon oxide is smaller than that of the high-k insulating material. In one example, the interfacial insulator 135 is thinner than the high-k insulator 136. This avoids the dielectric constant of the entire gate insulator from being too small.

[0088] In another example, the interface insulator section 135 is made of a high-k insulating material containing carbon elements, and the high-k insulator section 136 is made of a high-k insulating material that is substantially free of carbon elements (carbon-free). The interface insulator section 135 is included in a high-k insulator layer containing carbon elements, including an interface insulator section of another oxide semiconductor TFT. The high-k insulator section 136 is included in a high-k insulator layer that is substantially free of carbon elements, including a high-k insulator section of another oxide semiconductor TFT. By inserting a high-k insulator containing carbon elements between the high-k insulator that is substantially free of carbon elements and the oxide semiconductor, the characteristics of the oxide semiconductor TFT 142 can be stabilized.

[0089] In one example, the interface insulator portion 135 made of a high-k insulating material containing carbon elements is thinner than the high-k insulator portion 136 that is substantially free of carbon elements. The high-k insulator that is substantially free of carbon elements can be deposited by a general sputtering method. On the other hand, the high-k insulator that contains carbon elements is deposited by, for example, atomic layer deposition (ALD), which is a CVD method using an organic metal as a precursor. Contains carbon The deposition of high-k insulators is Carbon Free This requires more time than forming a high-k insulator film, so the above-mentioned film thickness relationship can reduce the process time.

[0090] Here, the carbon concentration in the high-k insulator containing carbon is 1×10 18 (cm -3 ) and the carbon concentration in the carbon-free high-k insulator is 1×10 18 (cm -3 ) the characteristics of the oxide semiconductor TFT 142 can be further stabilized.

[0091] 9, the entire insulator portion of the storage capacitor 143 is composed of the interface insulator portion 137, the high-k insulator portion 138, and a part of the interlayer insulating film 112. The interface insulator portion 137 is included in the same layer as the interface insulator portion 135. The high-k insulator portion 138 is included in the same layer as the high-k insulator portion 136.

[0092] The metal layer M3, the insulator layer including the interface insulator portions 135 and 137, and the insulator layer including the high-k insulator portions 136 and 138 have the same planar shape. These stacks can be formed by etching the two insulator layers simultaneously with the metal layer M3 (in the same process using the same mask), or by etching using the metal layer M3 as a mask. Note that the interface insulator portion 137 may be omitted.

[0093] Fig. 10 shows a schematic cross-sectional structure of a CMOS circuit. Differences from the configuration example shown in Fig. 7 will be mainly described. The entire gate insulator of the oxide semiconductor TFT 202 is composed of a high-k insulator 236 and an interface insulator 235. The high-k insulator 236 may be included in the same layer as the high-k insulators 136 and 138. The interface insulator 235 may be included in the same layer as the interface insulators 135 and 137.

[0094] The interface insulator 235 is a high-k insulator. 236 and an oxide semiconductor portion 213The interface insulator portion 235 is formed of, for example, silicon oxide (SiOx). By inserting silicon oxide between the high-k insulator and the oxide semiconductor, the characteristics of the oxide semiconductor TFT 202 can be stabilized.

[0095] In one example, the interfacial insulator portion 235 is thinner than the high-k insulator portion 236. This avoids a decrease in the dielectric constant of the entire gate insulator portion.

[0096] In another example, the interface insulator portion 235 is Contains carbon element The high-k insulator portion 236 is made of a high-k insulating material. Carbon Free This is made of high-k insulating material. This allows the oxide semiconductor TFT 202 In one example, the characteristics of Contains carbon element The interface insulator portion 235 made of a high-k insulating material is Carbon Free It is thinner than the high-k insulator portion 236. This film thickness relationship allows the process time to be shortened.

[0097] <Embodiment 3> Other configuration examples of the oxide semiconductor TFT will be described below. The oxide semiconductor TFT described below includes a compound layer of a high-k insulating material and an oxide semiconductor as an interface layer between the source / drain region of the oxide semiconductor section and the source / drain electrode section. The interface layer forms an interface with each of the source / drain region and the source / drain electrode section. The interface layer can obtain good contact characteristics between the source / drain region and the source / drain electrode section. An oxide semiconductor TFT having a top gate structure will be described below as an example, but the interface layer can also be applied to a bottom gate structure.

[0098] 11 shows a cross-sectional view of an example of the configuration of an oxide semiconductor TFT. The oxide semiconductor TFT is formed on an insulating substrate 301. An example of an oxide semiconductor material is IGZO. The oxide semiconductor TFT includes an oxide semiconductor section 311. The oxide semiconductor section 311 is, for example, an island-shaped oxide semiconductor active film, and includes source / drain regions 315, 316 and a channel region 314 between the source / drain regions 315, 316 in the in-plane direction.

[0099] The source / drain regions 315 and 316 are formed of a low-resistance oxide semiconductor. The channel region 314 is formed of an oxide semiconductor that is not low-resistance. A mixed interface portion 317 is formed on the channel region 314, which is formed of a mixture of an oxide semiconductor and a high-k insulating material. In addition to the high dielectric constant mentioned in the first embodiment, a ferroelectric material having remanent polarization (PZT, etc.) can be used as the high-k insulating material. The mixed interface portion 317 forms an interface with each of the gate insulator portion 321 and the channel region 314, which are formed of a high-k insulating material.

[0100] Compound interfaces 318, 319 made of a compound of an oxide semiconductor and a high-k insulating material are formed on the source / drain regions 315, 316. The source / drain regions 315, 316 are connected to source / drain electrode portions 322, 323 via the compound interfaces 318, 319. The compound interfaces 318, 319 form interfaces with the source / drain electrode portions 322, 323 and the source / drain regions 315, 316, respectively.

[0101] For example, when InGaZnOX is used as the oxide semiconductor and AlOY is used as the high-k insulating material, the mixed interface 317 can be expressed as (IGZOX+AlOY). The compound interfaces 318, 319 can be expressed as (IGZOX-1AlOY+1), for example. In this way, oxygen deficiency in the oxide semiconductor increases at the compound interfaces 318, 319. This makes the resistance of the compound interfaces 318, 319 lower than that of the source / drain regions 315, 316, and better contact characteristics and on-current characteristics can be obtained.

[0102] As described above, the compound interfaces 318, 319 may be made of elements of an oxide semiconductor and a high-k insulating material, for example, In-Ga-Zn-Al-O, or may contain elements of a process gas in a manufacturing process. For example, as described below, when exposed to a plasma containing fluorine, the compound interfaces 318, 319 may be made of In-Ga-Zn-Al-FO. As described above, elements contained in high-k insulating materials include Ta, Hf, and the like, in addition to Al.

[0103] The gate electrode portion 320 is laminated on the gate insulator portion 321. The gate electrode portion 320 is formed of a conductor, and for example, a metal such as Mo, W, Nb, or Al is used. As in the configurations of the other embodiments described above, the entire area of ​​the insulator layer including the gate insulator portion 321 is covered with the metal layer including the gate electrode portion 320.

[0104] An interlayer insulating film 324 is formed to cover the above-mentioned components of the oxide semiconductor section. The interlayer insulating film 324 is, for example, a silicon oxide film. Source / drain electrode sections 322, 323 of the oxide semiconductor TFT are formed on the interlayer insulating film 324. The source / drain electrode sections 322, 323 are connected to source / drain regions 315, 316 via contact holes formed in the interlayer insulating film 324 and compound interface sections 318, 319.

[0105] Fig. 12 shows a cross-sectional view of another example of the configuration of an oxide semiconductor TFT. The differences from the example of the configuration shown in Fig. 11 will be mainly described. In the oxide semiconductor TFT shown in Fig. 12, the high-k insulator part existing between the gate electrode part 320 and the oxide semiconductor part 311 is included in the high-k insulator film 325 that extends to the outside of the gate electrode part 320. The high-k insulator film 325 covers the oxide semiconductor part 311. Unlike the configurations of the first and second embodiments, the compound interface parts 318 and 319 can also be applied to a circuit in which the high-k insulator extends outward from the region directly under the gate electrode part.

[0106] Regarding this compound interface, for example, before forming the high-k insulator film 325, the surface of the oxide semiconductor portion 311 is exposed to plasma containing fluorine, and the resistance of the compound interface is further reduced by the kinetic energy and thermal energy of particles (plasma particles and radical particles) during the subsequent formation of the high-k insulator film 325. Here, in the configuration shown in Figures 11 and 12, the gate insulator portion 321 can also have a layered configuration made of, from the bottom, a high-k insulating material and a low-k insulating material with a relative dielectric constant of less than 8.

[0107] Next, an example of a method for manufacturing the oxide semiconductor TFT shown in Fig. 11 will be described with reference to Fig. 13A to Fig. 13F. With reference to Fig. 13A, in the manufacturing process, an oxide semiconductor layer is formed on an insulating substrate 301 by a sputtering method or the like, and patterned by photolithography. As a result, an island-shaped oxide semiconductor film 351 is formed.

[0108] 13B, in the manufacturing process, a high-k insulator film 352 is formed by sputtering or the like. As a result, a mixed portion 354 of a high-k insulating material and an oxide semiconductor is formed in the oxide semiconductor film 351. The layer below this is an oxide semiconductor portion 311 made only of an oxide semiconductor. In addition, in the manufacturing process, a metal film 353 is formed by sputtering or the like.

[0109] 13C, in patterning by photolithography, the metal film 353 and the high-k insulator film 352 are etched simultaneously (in the same process using the same mask) to form the gate electrode portion 320 and the gate insulator portion 321. In another example, after etching the metal film 353, etching may be performed using the gate electrode portion 320 as a mask to form the gate insulator portion 321.

[0110] Next, referring to FIG. 13D, the manufacturing process uses the gate electrode portion 320 as a mask to expose the mixed portion 354 and the exposed regions of the oxide semiconductor portion 311 to fluorine plasma. This forms compound interface portions 318, 319 and source / drain regions 315, 316. The compound interface portions 318, 319 may contain fluorine elements in addition to the elements of the oxide semiconductor and the high-k insulating material. The region between the compound interface portions 318, 319 is the mixed interface portion 317, and the region between the source / drain regions 315, 316 is the high-resistance channel region 314. Such fluorine plasma processing can be achieved, for example, by performing etching as shown in FIG. 13C and then exposing to plasma of a gas such as CF4.

[0111] Next, referring to Fig. 13E, the manufacturing process involves forming an interlayer insulating film 324 by a CVD method or the like. Next, referring to Fig. 13F, the manufacturing process involves performing anisotropic etching by photolithography to form contact holes in the interlayer insulating film 324. Furthermore, a metal film is formed by a sputtering method or the like, and patterned by photolithography. As a result, source / drain electrode portions 322 and 323 of the oxide semiconductor TFT are formed.

[0112] 14 and 15 show examples in which the oxide semiconductor TFT having the structure described with reference to FIG. 11 is applied to the pixel circuit shown in FIG. 4 and the CMOS circuit shown in FIG. 7. In the pixel circuit of FIG. 14, the oxide semiconductor TFT 142 includes compound interface portions 401 and 402. In the CMOS circuit of FIG. 15, the oxide semiconductor TFT 202 includes compound interface portions 405 and 406. Each of the circuits can achieve the effects described in the first and third embodiments. In this way, the oxide semiconductor TFT of this embodiment can be applied to various types of circuits.

[0113] The compound interface portion described in the third embodiment and the interface insulator portion described in the second embodiment can be applied to one oxide semiconductor TFT, thereby realizing the operational stability and good on-current characteristics of the oxide semiconductor TFT.

[0114] Although the embodiments of the present disclosure have been described above, the present disclosure is not limited to the above embodiments. A person skilled in the art can easily change, add, or convert each element of the above embodiments within the scope of the present disclosure. It is possible to replace a part of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add the configuration of another embodiment to the configuration of one embodiment. [Explanation of symbols]

[0115] 1 OLED display device, 10 TFT substrate, 31 scan driver, 32 emission driver, 101 insulating substrate, 102 low-temperature polysilicon portion, 106 gate insulator portion, 107 gate electrode portion, 111 lower electrode portion, 113 oxide semiconductor portion, 113 gate electrode portion, 114 channel region, 115, 116 source / drain region, 117 high-k gate insulator portion, 118 high-k insulator portion, 119 gate electrode portion, 120 upper electrode portion, 122, 123 source / drain electrode portion, 134 OLED element, 135, 137 interface insulator portion, 136, 138 high-k insulator portion, 141, 201 low-temperature polysilicon TFT, 142, 152, 202 oxide semiconductor TFT, 143 storage capacitor, 144 OLED element, 151-155 metal film, 213 Oxide semiconductor portion, 214 Channel region, 215, 216 Drain region, 217 Gate insulator portion, 219 Gate electrode portion, 223 Source / drain electrode portion, 235 Interface insulator portion, 236 High-k insulator portion, 311 Oxide semiconductor portion, 314 Channel region, 315, 316 Source / drain region, 317 Mixed interface portion, 318 Oxide semiconductor portion, 318, 319 Compound interface portion, 320 Gate electrode portion, 321 Gate insulator portion, 322, 323 Drain electrode, 325, 352 High-k insulator film, 351 Oxide semiconductor film, 354 Mixed portion, 401, 405 Compound interface portion, 422 Storage capacitance, M1-M5 Metal layer

Claims

1. 1. A thin film transistor circuit, comprising: A polysilicon layer; a first conductor layer above the polysilicon layer; a first insulator layer between the first conductor layer and the polysilicon layer; an oxide semiconductor layer; a second conductor layer above the oxide semiconductor layer; a second insulator layer between the second conductor layer and the oxide semiconductor layer; Including, the polysilicon layer includes a polysilicon portion of a polysilicon thin film transistor; the first conductor layer includes a first gate electrode portion of the polysilicon thin film transistor; the first insulator layer includes a first insulator portion between the first gate electrode portion and the polysilicon portion, the oxide semiconductor layer includes an oxide semiconductor portion of an oxide semiconductor thin film transistor, the second conductor layer includes a second gate electrode portion of the oxide semiconductor thin film transistor, the second insulator layer includes a second insulator portion between the second gate electrode portion and the oxide semiconductor portion, The second insulator layer has a relative dielectric constant of 8 or more, The entire area of ​​the second insulating layer in a plan view is covered with the second conductor layer, the first insulating layer has a dielectric constant lower than the dielectric constant of the second insulating layer; the second conductor layer includes an upper electrode portion of a capacitance element, an upper electrode portion of the capacitance element is connected to the first gate electrode portion; the second insulator layer includes an insulator portion of the capacitive element; Thin film transistor circuit.

2. The thin film transistor circuit of claim 1, the oxide semiconductor portion includes a channel region and source / drain regions sandwiching the channel region; One of the source / drain regions and the first gate electrode portion are connected. Thin film transistor circuit.

3. The thin film transistor circuit of claim 1, the oxide semiconductor portion includes a channel region and source / drain regions sandwiching the channel region; the polysilicon portion includes a channel region and source / drain regions sandwiching the channel region; one of the source / drain regions of the oxide semiconductor portion and one of the source / drain regions of the polysilicon portion are connected to each other. Thin film transistor circuit.

4. The thin film transistor circuit of claim 1, a silicon insulator portion forming an interface with each of the oxide semiconductor portion and the second insulator portion, Thin film transistor circuit.

5. A thin film transistor circuit comprising: A polysilicon layer; a first conductor layer above the polysilicon layer; a first insulator layer between the first conductor layer and the polysilicon layer; an oxide semiconductor layer; a second conductor layer above the oxide semiconductor layer; a second insulator layer between the second conductor layer and the oxide semiconductor layer; Including, the polysilicon layer includes a polysilicon portion of a polysilicon thin film transistor; the first conductor layer includes a first gate electrode portion of the polysilicon thin film transistor; the first insulator layer includes a first insulator portion between the first gate electrode portion and the polysilicon portion, the oxide semiconductor layer includes an oxide semiconductor portion of an oxide semiconductor thin film transistor, the second conductor layer includes a second gate electrode portion of the oxide semiconductor thin film transistor, the second insulator layer includes a second insulator portion between the second gate electrode portion and the oxide semiconductor portion, The second insulator layer has a relative dielectric constant of 8 or more, The entire area of ​​the second insulating layer in a plan view is covered with the second conductor layer, an interface insulator portion forming an interface with each of the oxide semiconductor portion and the second insulator portion, The interface insulator has a relative dielectric constant of 8 or more, the carbon concentration of the interface insulator portion is 1×10 18 cm −3 or more, and the carbon concentration of the second insulator portion is less than 1×10 18 cm −3 ; Thin film transistor circuit.

6. The thin film transistor circuit of claim 1, the oxide semiconductor portion includes a channel region and source / drain regions sandwiching the channel region; a compound interface portion containing a constituent element of the oxide semiconductor portion and a constituent element of the second insulator layer and having a lower resistance than the channel region is formed on the source / drain region; Thin film transistor circuit.

7. A method for manufacturing a thin film transistor circuit, comprising the steps of: forming a polysilicon layer including a polysilicon portion of a polysilicon thin film transistor; forming a first insulating layer including an insulating portion of the polysilicon thin film transistor above the polysilicon layer; forming a first conductor layer including a first gate electrode portion of the polysilicon thin film transistor above the first insulator layer; forming an oxide semiconductor layer including an oxide semiconductor portion of an oxide semiconductor thin film transistor; forming a second insulator layer including an insulator portion of the oxide semiconductor thin film transistor above the oxide semiconductor layer; forming a second conductor layer including a second gate electrode portion of the oxide semiconductor thin film transistor above the second insulator layer; The second insulator layer has a relative dielectric constant of 8 or more, The second conductor layer and the second insulator layer are etched simultaneously, or the second insulator layer is etched using the second conductor layer as a mask. the first insulating layer has a dielectric constant lower than the dielectric constant of the second insulating layer; the second conductor layer includes an upper electrode portion of a capacitance element, an upper electrode portion of the capacitance element is connected to the first gate electrode portion; the second insulator layer includes an insulator portion of the capacitive element; A method for manufacturing thin film transistor circuits.

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