Semiconductor device and power conversion device

Abstract

To provide a semiconductor device which makes the current flow in the bidirection and can accurately detect the current.SOLUTION: There is provided a semiconductor device in which a transistor and a diode are formed on a common semiconductor substrate and which comprises a first electrode, a second electrode, a third electrode for current sense and a fourth electrode for current sense. The semiconductor substrate comprises: a transistor region in which the transistor is formed; a diode region in which the diode is formed; and an isolation region provided between the transistor region and the diode region. The first electrode is provided on a first principal surface of the transistor region and on a first principal surface of the diode region. The second electrode is provided on a second principal surface of the transistor region and on a second principal surface of the diode region. The third electrode is provided so as to be apart from the first electrode on the first principal surface of the transistor region. The fourth electrode is provided so as to be apart from the first electrode on the first principal surface of the diode region of the semiconductor substrate.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device and a power conversion device. [Background technology]

[0002] Patent Document 1 discloses a reverse-conducting insulated gate bipolar transistor (RC-IGBT), which is a semiconductor device capable of passing a current in both directions. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2009-99690 A Summary of the Invention [Problem to be solved by the invention]

[0004] In conventional RC-IGBTs, the forward current-forward voltage characteristics of an FWD (Free Wheeling Diode) element change depending on whether or not a gate signal is present, whereas the forward current-forward voltage characteristics of an FWD sense element do not change significantly depending on whether or not a gate signal is present, making it difficult to detect the current accurately.

[0005] The present disclosure has been made to solve the above-mentioned problems, and has an object to provide a semiconductor device that allows current to flow in both directions and is capable of detecting the current with high accuracy. [Means for solving the problem]

[0006] In one aspect, the semiconductor device of the present disclosure is a semiconductor device in which a transistor and a diode are formed on a common semiconductor substrate, the semiconductor substrate including a first electrode, a second electrode, a third electrode for current sensing, a fourth electrode for current sensing, and a first gate electrode, the semiconductor substrate including a first main surface and a second main surface as one main surface and the other main surface, a transistor region in which a transistor is formed, a diode region in which a diode is formed, and a gate electrode provided between the transistor region and the diode region. Minutes and a separation region, the transistor region includes a first semiconductor layer of a first conductivity type, an eighth semiconductor layer of the first conductivity type provided on the second main surface side of the first semiconductor layer and having a higher impurity concentration of the first conductivity type than the first semiconductor layer, a second semiconductor layer of a second conductivity type provided on the second main surface side of the eighth semiconductor layer, a third semiconductor layer of the second conductivity type provided on the first main surface side of the first semiconductor layer, and a fourth semiconductor layer of the first conductivity type selectively provided on the first main surface side of the third semiconductor layer, and the diode region includes the first semiconductor layer, an eighth semiconductor layer provided on the second main surface side of the first semiconductor layer, and a fifth semiconductor layer of a first conductivity type provided on the second main surface side of the conductor layer and having a higher concentration of the first conductivity type impurity than the first semiconductor layer, and a sixth semiconductor layer of a second conductivity type provided on the first main surface side of the first semiconductor layer, wherein the first electrode is provided on the first main surface of the transistor region and on the first main surface of the diode region, the second electrode is provided on the second main surface of the transistor region and on the second main surface of the diode region, the third electrode is provided on the first main surface of the transistor region of the semiconductor substrate and is spaced apart from the first electrode, and the fourth electrode is provided on the third main surface of the diode region of the semiconductor substrate. 2 On the main surface 2the sixth semiconductor layer is provided spaced apart from the electrode, in the transistor region, the third semiconductor layer and the fourth semiconductor layer are electrically connected to the first electrode at the first main surface, in the transistor region, the third semiconductor layer and the fourth semiconductor layer are electrically connected to the third electrode at the first main surface, in the transistor region, the second semiconductor layer is electrically connected to the second electrode at the second main surface, in the transistor region, the first gate electrode faces the first semiconductor layer, the third semiconductor layer and the fourth semiconductor layer via a first insulating film, in the diode region, the sixth semiconductor layer is electrically connected to the first electrode at the first main surface, in the diode region, The fifth semiconductor layer has a second major surface. The fifth semiconductor layer is electrically connected to the fourth electrode, and in the diode region, the fifth semiconductor layer is electrically connected to the second electrode at the second major surface. Effect of the Invention

[0007] The present disclosure provides a semiconductor device that allows current to flow in both directions and can detect the current with high accuracy. [Brief description of the drawings]

[0008] [Figure 1] 1 is a plan view showing a schematic configuration of a semiconductor device according to a first embodiment. [Diagram 2] 1 is a cross-sectional view of a semiconductor device according to a first embodiment. [Diagram 3] FIG. 2 is a diagram illustrating a feedback circuit according to the first embodiment. [Figure 4] FIG. 2 is a diagram illustrating a feedback circuit according to the first embodiment. [Diagram 5] FIG. 11 is a cross-sectional view of a semiconductor device according to a second embodiment. [Figure 6] FIG. 11 is a plan view showing a schematic configuration of a semiconductor device according to a third embodiment. [Figure 7] FIG. 11 is a cross-sectional view of a semiconductor device according to a third embodiment. [Figure 8] 13 is a diagram showing operation modes of the semiconductor device according to the third embodiment. FIG. [Figure 9]It is a plan view showing a schematic configuration of a modified example of the semiconductor device according to Embodiment 3. [Figure 10] It is a cross-sectional view of a modified example of the semiconductor device according to Embodiment 3. [Figure 11] It is a schematic plan view of the first main surface of the semiconductor substrate of the semiconductor device according to Embodiment 3. [Figure 12] It is a schematic plan view of the first main surface of the semiconductor substrate of the semiconductor device according to Embodiment 3. [Figure 13] It is a cross-sectional view showing the vicinity of the first main surface of the semiconductor substrate of the semiconductor device according to Embodiment 3. [Figure 14] It is a block diagram showing the configuration of a power conversion system to which the power conversion device according to Embodiment 4 is applied. [Figure 15] It is a cross-sectional view of the semiconductor device according to Embodiment 1.

Embodiments for Carrying Out the Invention

[0009] In the following description, n-type and p-type indicate the conductivity type of the semiconductor. In the present disclosure, the first conductivity type is described as n-type and the second conductivity type as p-type, but the first conductivity type may be p-type and the second conductivity type may be n-type. n - type indicates that the impurity concentration is lower than that of the n-type, and n + type indicates that the impurity concentration is higher than that of the n-type. Similarly, p - type indicates that the impurity concentration is lower than that of the p-type, and p + type indicates that the impurity concentration is higher than that of the p-type.

[0010] <A. Embodiment 1> <A-1. Configuration> FIG. 1 is a plan view showing a schematic configuration of the semiconductor device 1a according to Embodiment 1.

[0011] FIG. 2 is a cross-sectional view taken along the line I-I of FIG. 1.

[0012] The semiconductor device 1a is a semiconductor device that functions as an RC-IGBT.

[0013] The semiconductor device 1a is used, for example, as a power switching element in an inverter module for controlling a motor.

[0014] The semiconductor device 1 a includes a semiconductor substrate 100 , an electrode 19 , an electrode 20 , an electrode 22 , an electrode 23 , and an insulating film 21 .

[0015] The electrodes 19, 20, 22, and 23 are formed using, for example, an aluminum-based material.

[0016] As shown in FIG. 1, the semiconductor substrate 100 has an IGBT region 41 in which an IGBT is formed, a diode region 42 in which a diode is formed, an isolation region 40 provided between the IGBT region 41 and the diode region 42, a pad region 3, and a termination region 2.

[0017] 2, the semiconductor body 100 has a first main surface 100a and a second main surface 100b as one main surface and the other main surface. The thickness of the semiconductor body 100, that is, the distance between the first main surface 100a and the second main surface 100b, is, for example, about 120 μm.

[0018] The IGBT region 41 and the diode region 42 are separated by an isolation region 40 .

[0019] The IGBT region 41 has an IGBT main region 31 and an IGBT sense region 51 .

[0020] The diode region 42 includes a diode main region 32 and a diode sense region 52 .

[0021] In the pad region 3, a gate pad 3a is provided on the first main surface 100a of the semiconductor substrate 100. The gate pad 3a is formed of, for example, an aluminum-based material. The gate pad 3a is electrically separated from the electrodes 19 and 22. Further, the gate pad 3a is electrically connected to a gate electrode 12, which will be described later. By inputting a drive signal from the outside to the gate pad, the IGBT provided in the IGBT region 41 can be controlled.

[0022] The termination region 2 is a region provided at the outer peripheral portion of the semiconductor substrate 100. The termination region 2 is provided so as to surround the regions of the IGBT region 41, the diode region 42, the isolation region 40, and the pad region 3 combined. In the termination region 2, a termination structure for suppressing electric field concentration is provided in the surface layer portion on the first main surface 100a side of the semiconductor substrate 100.

[0023] The semiconductor device 1a is manufactured using, for example, an n-type single-crystal bulk silicon substrate with an impurity concentration of about 1×10 14 cm -3 The single-crystal bulk silicon substrate is manufactured using, for example, the FZ (floating zone) method. The single-crystal bulk silicon substrate corresponds to the semiconductor substrate 100. ― The single-crystal bulk silicon substrate is manufactured using, for example, the FZ (floating zone) method. The single-crystal bulk silicon substrate corresponds to the semiconductor substrate 100.

[0024] <A-1-1. Structure of IGBT Region> The IGBT region 41 has an IGBT main region 31 and an IGBT sense region 51. The IGBT main region 31 and the IGBT sense region 51 are adjacent to each other. The IGBT sense region 51 is surrounded by the IGBT main region 31 in a plan view, for example.

[0025] The IGBT main region 31 and the IGBT sense region 51 share the electrode 20. On the other hand, the electrode 19 provided on the first main surface 100a of the IGBT main region 31 and the electrode 22 provided on the first main surface 100a of the IGBT sense region 51 are provided apart from each other.

[0026] The IGBT sense region 51 has a smaller area in a plan view than the IGBT main region 31. The area of ​​the IGBT sense region 51 in a plan view is, for example, 1 / 3000 to 1 / 300, for example, about 1 / 1000, of the area of ​​the IGBT main region 31.

[0027] The IGBT main region 31 and the IGBT sense region 51 have the same structure except for their different sizes in a plan view. Hereinafter, the structures of the IGBT main region 31 and the IGBT sense region 51 will be collectively described as the structure of the IGBT region 41.

[0028] In the IGBT region 41, the semiconductor substrate 100 has n - a n-type drift layer 10, an n-type buffer layer 16, + A p-type collector layer 14, a p-type base layer 11, and an n + The semiconductor device further comprises a type emitter layer 13 .

[0029] The base layer 11 is provided on the drift layer 10 on the first main surface 100a side.

[0030] The emitter layer 13 is selectively provided on the first major surface 100a side of the base layer 11.

[0031] The semiconductor substrate 100 is provided with a trench 17 that extends from the first major surface 100a through the emitter layer 13 and the base layer 11 to the drift layer 10. A gate electrode 12 is provided within the trench 17 via a gate insulating film 18 provided on the bottom and side surfaces of the trench 17. The gate electrode 12 has an impurity concentration of, for example, 1×10 20 cm -3 The trench 17 is formed by using polysilicon having a thickness of about 100 .mu.m. The trench 17 is provided to extend in one direction within the surface, for example.

[0032] The gate electrode 12 faces the emitter layer 13, the base layer 11, and the drift layer 10 with a gate insulating film 18 interposed therebetween.

[0033] In the IGBT region 41, the base layer 11 includes a base layer 11a and a base layer 11b.

[0034] The base layer 11a is a mesa-shaped portion in which the emitter layer 13 is selectively formed on the surface layer on the first principal surface 100a side, among the multiple mesa shapes formed by dividing the base layer 11 by the trenches 17. The base layer 11b is a mesa-shaped portion in which the emitter layer 13 is not formed on the surface layer on the first principal surface 100a side, among the multiple mesa shapes formed by dividing the base layer 11 by the trenches 17. The base layer 11a and the base layer 11b are alternately arranged, for example, in a direction intersecting with the extension direction of the trenches 17.

[0035] In this embodiment, the thickness of the emitter layer 13 is, for example, about 0.5 μm, and the impurity concentration of the emitter layer 13 is, for example, 3×10 19 cm -3 That's about it.

[0036] In the IGBT main region 31, the electrode 19 is provided on the first main surface 100a.

[0037] In the IGBT sense region 51, the electrode 22 is provided on the first main surface 100a.

[0038] In the IGBT main region 31 and the IGBT sense region 51, the electrode 20 is provided on the second main surface 100b.

[0039] The emitter layer 13 and the base layer 11a are electrically connected to an electrode 19 on the first main surface 100a. The electrode 19 functions as an emitter electrode of the IGBT element formed in the IGBT region 41.

[0040] A region of the base layer 11 a facing the gate electrode 12 functions as a channel region of the IGBT element formed in the IGBT region 41 .

[0041] Most of the surface on the first major surface 100a side of the base layer 11b is covered by the insulating film 21. Only a part of the surface on the first major surface 100a side of the base layer 11b that is not covered by the insulating film 21 is connected to the electrode 19. The area of the portion where the base layer 11b and the electrode 19 are connected is small, and the electrical resistance of the path passing through the portion where the base layer 11b and the electrode 19 are connected is large. The illustration of the region where the base layer 11b and the electrode 19 are electrically connected is omitted.

[0042] The buffer layer 16 is provided on the second major surface 100b side of the drift layer 10.

[0043] The buffer layer 16 is for suppressing the spread of the depletion layer that spreads from the pn junction at the boundary between the drift layer 10 and the base layer 11.

[0044] The collector layer 14 is provided on the second major surface 100b side of the buffer layer 16. The thickness of the collector layer 14 is, for example, about 0.5 μm, and the impurity concentration of the collector layer 14 is, for example, 1×10 18 cm -3 or so.

[0045] In the IGBT main region 31, the base layer 11a and the emitter layer 13 are electrically connected to the electrode 19 on the first major surface 100a.

[0046] In the IGBT sense region 51, the base layer 11a and the emitter layer 13 are electrically connected to the electrode 22 on the first major surface 100a.

[0047] In the IGBT main region 31 and the IGBT sense region 51, the collector layer 14 is electrically connected to the electrode 20 on the second major surface 100b.

[0048] <A-1-2. Diode Region> The diode region 42 has a diode main region 32 and a diode sense region 52. The diode main region 32 and the diode sense region 52 are adjacent to each other. The diode sense region 52 is, for example, surrounded by the diode main region 32 in a plan view.

[0049] The diode main region 32 and the diode sense region 52 share an electrode 20. On the other hand, the electrode 19 provided on the first major surface 100a of the diode main region 32 and the electrode 23 provided on the first major surface 100a of the diode sense region 52 are provided apart from each other.

[0050] The diode sense region 52 has a smaller area in plan view than the diode main region 32. The area of ​​the diode sense region 52 in plan view is, for example, 1 / 3000 to 1 / 300, for example, about 1 / 1000, of the area of ​​the diode main region 32.

[0051] The diode main region 32 and the diode sense region 52 have the same structure except for their different sizes in a plan view. Hereinafter, the structures of the diode main region 32 and the diode sense region 52 will be collectively described as the structure of the diode region 42.

[0052] The semiconductor substrate 100 has n - a n-type drift layer 10, an n-type buffer layer 16, + The semiconductor device further comprises a p-type cathode layer 15 and a p-type base layer 11 .

[0053] The base layer 11 has an anode layer 11c in the diode region 42. The anode layer 11c has a structure similar to that of the base layer 11b in the IGBT region 41.

[0054] The drift layer 10 in the diode region 42 is connected to and integrated with the drift layer 10 in the IGBT region 41 and the drift layer 10 in the isolation region 40 .

[0055] In the diode region 42, the buffer layer 16 is provided on the second major surface 100b side of the drift layer 10.

[0056] In the diode region 42, the cathode layer 15 is provided on the second major surface 100b side of the buffer layer 16. The thickness of the cathode layer 15 is, for example, about 0.5 μm, and the impurity concentration of the cathode layer 15 is, for example, 1×10 18 cm -3 The buffer layer 16 and the cathode layer 15 may be integral as shown in FIG. + The semiconductor layer may be an integral semiconductor layer of the type. The integral semiconductor layer may be formed, for example, by a single ion implantation process. The impurity concentration of the integral semiconductor layer may be, for example, 1×10 18 cm -3 That's about it.

[0057] In the diode main region 32, the electrode 19 is provided on the first major surface 100a.

[0058] The electrode 19 is common to the IGBT main region 31 and the diode main region 32 .

[0059] In the diode sense region 52, the electrode 23 is provided on the first major surface 100a.

[0060] The electrode 20 is provided on the second main surface 100b in the diode main region 32 and the diode sense region 52. The electrode 20 is common to the diode region 42 and the IGBT region 41.

[0061] In the diode main region 32, the anode layer 11c is electrically connected to the electrode 19 on the first major surface 100a. The electrode 19 functions as the anode electrode of the diode formed in the diode region .

[0062] In the diode sense region 52, the anode layer 11c is electrically connected to the electrode 23 on the first major surface 100a.

[0063] In the diode main region 32 and the diode sense region 52, the cathode layer 15 is electrically connected to the electrode 20 on the second main surface 100b.

[0064] <A-1-3. Separation Region> The semiconductor substrate 100 has a separation region 40 provided between the IGBT region 41 and the diode region 42. The IGBT region 41 and the diode region 42 are separated by the separation region 40.

[0065] Since the IGBT region 41 and the diode region 42 are separated from each other by the separation region 40, the electrical resistance between the IGBT region 41 and the diode region 42 increases. Thereby, the mutual functional interference due to the IGBT and the diode being integrally formed is suppressed.

[0066] The width of the separation region 40 is, for example, 3 times or more the thickness of the semiconductor substrate 100. The width of the separation region 40 is, for example, about 5 times the thickness of the semiconductor substrate 100. In the present embodiment, the thickness of the semiconductor substrate 100 is, for example, about 120 μm, and the width of the separation region 40 is, for example, about 600 μm.

[0067] Due to the separation region 40, the IGBT region 41 and the diode region 42 are, for example, separated by 3 times or more the thickness of the semiconductor substrate 100. Due to the separation region 40, the IGBT region 41 and the diode region 42 are, for example, separated by about 5 times the thickness of the semiconductor substrate 100. Due to the separation region 40, the IGBT region 41 and the diode region 42 are, for example, separated by about 600 μm.

[0068] In the separation region 40, the semiconductor substrate 100 includes an n - -type drift layer 10, an n-type buffer layer 16, a p + -type collector layer 14, a p-type base layer 11b, and an n + -type cathode layer 15.

[0069] In the separation region 40, the base layer 11b is provided on the first main surface 100a side of the drift layer 10. The base layer 11b in the separation region 40 has a structure similar to that of the base layer 11b in the IGBT region 41. An insulating film 21 is provided between the base layer 11b and the electrode 19 in the separation region 40, and, for example, the base layer 11b and the electrode 19 are not in contact with each other in the separation region 40.

[0070] In the separation region 40, the buffer layer 16 is provided on the second major surface 100b side of the drift layer 10.

[0071] In the isolation region 40, the collector layer 14 is selectively provided on the second major surface 100b side of the buffer layer 16.

[0072] In the separation region 40, the cathode layer 15 is selectively provided on the second major surface 100b side of the buffer layer 16.

[0073] The collector layer 14 provided in the IGBT region 41 is provided so as to protrude into the separation region 40. The cathode layer 15 provided in the diode region 42 is provided so as to protrude into the separation region 40. That is, in a plan view, the boundary between the collector layer 14 and the cathode layer 15 is at least partially included in the separation region 40. The cathode layer 15 is provided, for example, in a region that includes the entire diode region 42 in a plan view. The boundary between the collector layer 14 and the cathode layer 15 is, for example, completely included in the separation region 40.

[0074] If the boundary between the collector layer 14 and the cathode layer 15 extends into the diode region 42, the size of the cathode layer 15 will be reduced and the forward voltage of the diode formed in the diode region 42 will increase. If the boundary between the collector layer 14 and the cathode layer 15 extends into the IGBT region 41, the suppression of functional interference between the IGBT formed in the IGBT region 41 and the diode formed in the diode region 42 will be insufficient.

[0075] By locating the boundary between the collector layer 14 and the cathode layer 15 in the separation region 40, the distance from the cathode layer 15 to the IGBT main region 31 is secured, the electrical resistance from the cathode layer 15 to the IGBT main region 31 is increased, and functional interference between the IGBT region 41 and the diode region 42 can be suppressed.

[0076] In the case where the separation region 40 is not provided, when a current flows in the forward direction of the diode in the diode region 42, that is, in the direction from the electrode 19 to the electrode 20, an on-voltage is applied to the gate electrode 12 to turn on the channel of the IGBT region 41, and in a region of the diode region 42 that is close to the IGBT region 41 and is not separated from the IGBT region 41 by a sufficiently large resistance, the anode layer 11c and the drift layer 10 tend to have the same potential. That is, the on-voltage applied to the gate electrode 12 makes it difficult for a part of the diode region 42 to operate in the forward direction. As a result, there is a problem that the forward voltage Vf of the diode region 42 increases, and thus the forward loss of the diode region 42 increases. In addition, since a part of the diode region 42 becomes difficult to operate in the forward direction, the ratio of the current in the diode main region 32 to the current in the diode sense region 52 varies depending on whether the gate potential applied to the gate electrode 12 is on or off. That is, there is a problem that the current flowing in the diode main region 32 cannot be detected accurately by the diode sense region 52. In the semiconductor device 1a of the present embodiment, the isolation region 40 is provided, so that these problems can be suppressed, and the current flowing through the diode main region 32 can be detected by the diode sense region 52 with high accuracy.

[0077] Since the isolation region 40 is provided, the path for current to flow from the electrode 19 in the IGBT region 41 to the electrode 20 in the diode region 42, that is, the path from the electrode 19 through the base layer 11a, the drift layer 10, the buffer layer 16, and the cathode layer 15 to the electrode 20 becomes a high resistance, and this path does not become an effective current path. By turning the gate signal applied to the gate electrode 12 on and off, the resistance of this path changes, thereby affecting the operation of the diode main region 32. However, since this path is originally a high resistance, the influence of the on and off of the gate signal applied to the gate electrode 12 on the operation of the diode main region 32 is suppressed. Further, in the IGBT main region 31, only the collector layer 14 is connected to the electrode 20, and due to the pn junction between the drift layer 10 and the collector layer 14, almost no current flows in the direction from the electrode 19 to the electrode 20 in the IGBT main region 31. Therefore, the influence of the on and off of the gate signal applied to the gate electrode 12 and the operation of the IGBT main region 31 on the operation of the diode main region 32 is suppressed.

[0078] Thus, in this embodiment, since the isolation region 40 is provided, the influence of the on and off of the gate signal applied to the gate electrode 12 on the forward current - forward voltage characteristics of the diode main region 32 is suppressed, and thereby, the diode sense region 52 can accurately detect the current of the diode main region 32. By making the width of the isolation region 40 sufficiently large, these effects can be obtained more reliably.

[0079] <A-2. Operation> For example, after the electrode 20 is soldered to a metal film on an insulating substrate (not shown) outside the semiconductor device 1a, the semiconductor device 1a is incorporated into a case. The case is, for example, a case to which an emitter terminal 96, an emitter sense terminal 91, a collector terminal 95, a gate terminal 90, an IGBT sense terminal 92, and a diode sense terminal 93 are attached.

[0080] Thereafter, the electrode 19 and the emitter terminal 96, the electrode 19 and the emitter sense terminal 91, the metal film to which the electrode 20 is soldered and the collector terminal 95, the gate pad 3a and the gate terminal 90, the electrode 22 and the IGBT sense terminal 92, and the electrode 23 and the diode sense terminal 93 are electrically connected by bonding with aluminum wire, etc. In Fig. 2, these electrical connections are shown diagrammatically.

[0081] In the semiconductor device 1a, the sense electrode 22 and the sense electrode 23 are both located on the first main surface 100a side. Therefore, in the wire bonding process for connecting the electrode 19 and the emitter sense terminal 91, the electrode 22 and the IGBT sense terminal 92 and the electrode 23 and the diode sense terminal 93 can be bonded at the same time, which prevents an increase in the number of assembly processes.

[0082] Thereafter, the semiconductor device 1a and the aluminum wires are covered with a resin such as silicon gel, and a lid is attached to the case, thereby packaging the semiconductor device 1a.

[0083] The operation of the feedback circuit 150 using the semiconductor device 1a packaged in this manner will be described below.

[0084] As shown in Fig. 3, the feedback circuit 150 includes the semiconductor device 1a, an AND circuit 110, a sense resistor 111, a feedback unit 112, and a gate resistor 113. In Fig. 3, the semiconductor device 1a is shown in a schematic equivalent circuit having an IGBT and a diode. A load, a power supply, and the like (not shown) are connected between the emitter terminal 96 and the collector terminal 95.

[0085] A PWM (pulse width modulation) gate signal, which is a drive signal for driving the semiconductor device 1a, and the output of the feedback unit 112 are input to the AND circuit 110. The PWM gate signal is generated by a PWM signal generating circuit or the like outside the feedback circuit 150, and is input to an input terminal of the AND circuit 110.

[0086] The AND circuit 110 is a logic circuit that outputs a high-level signal when, and only when, all input signals are at a high level.

[0087] When the signal input from the feedback section 112 to the AND circuit 110 is a high-level signal, the PWM gate signal is permitted to pass through the AND circuit 110, and the AND circuit 110 outputs the input PWM gate signal.

[0088] When the signal input from the feedback unit 112 to the AND circuit 110 is a low-level signal, the PWM gate signal is prevented from passing through the AND circuit 110. In other words, when the signal input from the feedback unit 112 to the AND circuit 110 is a low-level signal, the AND circuit 110 outputs a low-level signal regardless of whether the PWM gate signal is high or low.

[0089] The AND circuit 110 is electrically connected to the gate pad 3a of the semiconductor device 1a via a gate resistor 113 and a gate terminal 90. The gate voltage applied to the gate electrode 12 is controlled by a PWM gate signal supplied from the AND circuit 110 to the semiconductor device 1a via the gate resistor 113 and the gate terminal 90.

[0090] When the PWM gate signal is a high-level signal and the high-level PWM gate signal is permitted to pass through the AND circuit 110 , an on-voltage is applied to the gate electrode 12 .

[0091] When the PWM gate signal is a low-level signal, the output of the AND circuit 110 is a low-level signal, and an off voltage is applied to the gate electrode 12 .

[0092] When the PWM gate signal is stopped from passing through the AND circuit 110, the output of the AND circuit 110 is a low level signal and an off voltage is applied to the gate electrode 12.

[0093] One end of the sense resistor 111 is connected to the electrode 22 via the IGBT sense terminal 92, and is also connected to the electrode 23 via the diode sense terminal 93. The other end of the sense resistor 111 is connected to the electrode 19 via the emitter sense terminal 91. As a result, a current having a magnitude corresponding to the main current flowing through the IGBT main region 31 and a current having a magnitude corresponding to the main current flowing through the diode main region 32 flow through the sense resistor 111.

[0094] The potential difference Vs across the sense resistor 111 is fed back to the feedback section 112. In Fig. 3, as an example, the sense resistor 111 is used for both detecting the current flowing through the IGBT main region 31 and the current flowing through the diode main region 32, but different resistors may be used for detecting the current flowing through the IGBT main region 31 and the current flowing through the diode main region 32. If the sense resistor 111 is used for both detecting the current flowing through the IGBT main region 31 and the current flowing through the diode main region 32, the manufacturing cost of the feedback circuit 150 can be reduced.

[0095] The feedback section 112 is configured by combining circuits such as operational amplifiers.

[0096] The feedback unit 112 determines whether or not a current is flowing in the diode main region 32 and whether or not an excessive current is flowing in the IGBT main region 31, and based on the determination result, allows or stops the passage of the PWM gate signal input to the AND circuit 110.

[0097] The feedback unit 112 has a diode current detection threshold Vth1 used to determine whether or not a current flows in the diode main region 32, and an overcurrent detection threshold Vth2 used to determine whether or not an overcurrent flows in the IGBT main region 31. In this embodiment, Vth1 and Vth2 are voltage values.

[0098] When a current flows in the IGBT main region 31 in the direction from the second main surface 100b to the first main surface 100a, almost no current flows in the diode main region 32. When a current flows in the IGBT main region 31 in the direction from the second main surface 100b to the first main surface 100a, a current also flows in the IGBT sense region 51 in the direction from the second main surface 100b to the first main surface 100a, and a current also flows in the sense resistor 111 in the direction from the IGBT sense terminal 92 through the sense resistor 111 to the emitter sense terminal 91. As a result, the potential difference Vs across the sense resistor 111 becomes a positive value. The sign of the potential difference Vs across the sense resistor 111 is defined to be positive when the potential on the side connected to the IGBT sense terminal 92 and the diode sense terminal 93 is higher than the potential on the side connected to the emitter sense terminal 91. When an excessive current flows in the IGBT main region 31, the potential difference Vs across the sense resistor 111 becomes larger as a positive value. Therefore, the overcurrent detection threshold Vth2 is set to a positive value. When the potential difference Vs across the sense resistor 111 is larger than the overcurrent detection threshold Vth2, the feedback unit 112 determines that an overcurrent flows in the IGBT main region 31, and when the potential difference Vs across the sense resistor 111 is smaller than the overcurrent detection threshold Vth2, the feedback unit 112 determines that an overcurrent does not flow in the IGBT main region 31.

[0099] When a current flows from the first main surface 100a to the second main surface 100b in the diode main region 32, almost no current flows in the IGBT main region 31. When a current flows from the first main surface 100a to the second main surface 100b in the diode main region 32, a current also flows in the diode sense region 52 in the direction from the first main surface 100a to the second main surface 100b, and a current also flows in the sense resistor 111 in the direction from the emitter sense terminal 91 through the sense resistor 111 to the diode sense terminal 93. In this case, the potential difference Vs across the sense resistor 111 becomes a negative value. Therefore, the diode current detection threshold Vth1 is set to a negative value. The feedback section 112 determines that a current is flowing in the diode main region 32 when the potential difference Vs across the sense resistor 111 is smaller than the diode current detection threshold Vth1, and determines that a current is not flowing in the diode main region 32 when the potential difference Vs across the sense resistor 111 is larger than the diode current detection threshold Vth1.

[0100] When the potential difference Vs across the sense resistor 111 is greater than the diode current detection threshold Vth1 and less than the overcurrent detection threshold Vth2, the feedback unit 112 outputs a high-level signal to the AND circuit 110 so as to permit passage of the PWM gate signal input to the AND circuit 110. On the other hand, when the potential difference Vs across the sense resistor 111 is less than the diode current detection threshold Vth1 or greater than the overcurrent detection threshold Vth2, the feedback unit 112 outputs a low-level signal to the AND circuit 110 so as not to permit passage of the PWM gate signal input to the AND circuit 110.

[0101] When a current flows normally from the second main surface 100b to the first main surface 100a in the IGBT main region 31, that is, when a current that is not an overcurrent flows, the potential difference Vs across the sense resistor 111 is greater than the diode current detection threshold Vth1 and is smaller than the overcurrent detection threshold Vth2. Therefore, a high-level signal is output from the feedback unit 112 and input to the AND circuit 110. This allows the PWM gate signal to pass through the AND circuit 110, and a current continues to flow in the IGBT main region 31 from the second main surface 100b to the first main surface 100a.

[0102] When an overcurrent flows in the IGBT main region 31 in the direction from the second main surface 100b to the first main surface 100a, the potential difference Vs across the sense resistor 111 becomes greater than the overcurrent detection threshold Vth2. Therefore, a low-level signal is output from the feedback unit 112 and input to the AND circuit 110. As a result, the PWM gate signal is stopped from passing through the AND circuit 110, and an off-voltage is applied to the gate electrode 12. This makes it possible to prevent the semiconductor device 1a from being destroyed by an overcurrent flowing through the IGBT main region 31.

[0103] When a current flows in the diode main region 32 from the first main surface 100a to the second main surface 100b, the potential difference Vs across the sense resistor 111 becomes negative. When the potential difference Vs becomes smaller than the diode current detection threshold Vth1, a low-level signal is output from the feedback unit 112 and input to the AND circuit 110. As a result, the PWM gate signal is stopped from passing through the AND circuit 110, and an off-voltage is applied to the gate electrode 12. This can further suppress the problem that the forward voltage Vf of the diode main region 32 increases due to the application of an on-voltage to the gate electrode 12, thereby increasing the forward loss of the diode main region 32.

[0104] The feedback circuit 150 may be as shown in FIG.

[0105] 3, the feedback circuit 150 shown in Fig. 4 further includes a control circuit 203 and a drive circuit 202. The feedback unit 112 has an overcurrent detection threshold Vth3 used to determine whether an overcurrent flows in the diode main region 32, instead of the diode current detection threshold Vth1. When the potential difference Vs across the sense resistor 111 is smaller than the overcurrent detection threshold Vth3, it is determined that an overcurrent flows in the diode main region 32, and notifies the control circuit 203 to that effect. The control circuit 203 operates, for example, a protection circuit (not shown) to protect the semiconductor device 1a from an overcurrent.

[0106] <A-3.まとめ> As described above, the semiconductor device 1a is a semiconductor device in which an IGBT and a diode are formed on a common semiconductor substrate 100. The semiconductor device 1a includes the electrode 19, the electrode 20, the electrode 22 for current sensing, the electrode 23 for current sensing, and the gate electrode 12.

[0107] The semiconductor substrate 100 has an IGBT region 41 in which an IGBT is formed, a diode region 42 in which a diode is formed, and an isolation region 40 provided between the IGBT region 41 and the diode region 42.

[0108] The electrode 19 is provided on the first main surface 100a of the IGBT region 41 and the first main surface 100a of the diode region 42. The electrode 20 is provided on the second main surface 100b of the IGBT region 41 and the second main surface 100b of the diode region 42.

[0109] The electrode 22 is provided on the first main surface 100 a of the IGBT sense region 51 in the IGBT region 41 of the semiconductor substrate 100 , separated from the electrode 19 .

[0110] The electrode 23 is provided on the first main surface 100 a of the diode sense region 52 in the diode region 42 of the semiconductor substrate 100 , and is spaced apart from the electrode 19 .

[0111] In the IGBT main region 31 of the IGBT region 41, the base layer 11a and the emitter layer 13 are electrically connected to the electrode 19 on the first main surface 100a.

[0112] In the IGBT sense region 51 of the IGBT region 41, the base layer 11a and the emitter layer 13 are electrically connected to the electrode 22 on the first main surface 100a.

[0113] In the IGBT region 41, the collector layer 14 is electrically connected to the electrode 20 on the second main surface 100b.

[0114] In the IGBT region 41, the gate electrode 12 faces the drift layer 10, the base layer 11a, and the emitter layer 13 with the gate insulating film 18 interposed therebetween.

[0115] In the diode main region 32 of the diode region 42, the anode layer 11c is electrically connected to the electrode 19 on the first major surface 100a.

[0116] In the diode sense region 52 of the diode region 42, the anode layer 11c is electrically connected to the electrode 23 on the first major surface 100a.

[0117] In the diode region 42, the cathode layer 15 is electrically connected to the electrode 20 on the second major surface 100b.

[0118] In the semiconductor device 1a, the IGBT region 41 and the diode region 42 are separated by a separation region 40. Even when a PWM gate signal is input to the gate electrode 12 through the gate terminal 90, the influence on the forward current-forward voltage characteristics of the diode region 42 is small. Even when an on-voltage is applied to the gate electrode 12 when the diode sense region 52 operates in the forward direction of the diode, due to the presence of the separation region 40, the tendency for the anode layer 11c and the drift layer 10 to become at the same potential is suppressed, and it is suppressed that the diode sense region 52 becomes difficult to operate in the forward direction due to the potential of the gate electrode 12. The same applies to the diode main region 32. That is, the ratio of the current flowing through the diode sense region 52 to the current flowing through the diode main region 32 is hardly affected by the gate signal input to the gate electrode 12. Therefore, the current flowing through the diode main region 32 can be accurately detected by the diode sense region 52. For example, it becomes possible to accurately detect an overcurrent flowing through the diode main region 32 and accurately control overcurrent breakdown. That is, the current-carrying capacity of the diode main region 32 can be utilized to the maximum extent.

[0119] Also, in a direction perpendicular to the thickness direction of the semiconductor substrate 100, the IGBT region 41 and the diode region 42 are formed with a sufficient gap by the separation region 40. Therefore, at least a part of the carriers accumulated in the drift layer 10 along with the operation of the IGBT region 41, that is, the holes injected from the collector layer 14 into the drift layer 10, can be suppressed from flowing across the separation region 40 into the anode layer 11c of the diode region 42 and causing fluctuations in the forward current-forward voltage characteristics of the diode region 42. That is, the current detected using the diode sense region 52, that is, the current accurately corresponds to the current flowing through the diode main region 32.

[0120] <A-4. Others> Even if the ratio of the size of the IGBT sense region 51 to the size of the IGBT main region 31 and the ratio of the size of the diode sense region 52 to the size of the diode main region 32 are made the same, the current value detected by the IGBT sense region 51 during IGBT operation and the current value detected by the diode sense region 52 during diode operation are not necessarily approximately the same. This is because the on-current-on-voltage characteristics of the IGBT region 41 are significantly affected by the channel resistance, whereas the forward current-forward voltage characteristics of the diode region 42 are hardly affected by the channel resistance.

[0121] By matching the sense ratio of the IGBT and the sense ratio of the diode, the current value detected by the IGBT sense region 51 during IGBT operation becomes approximately equal to the current value detected by the diode sense region 52 during diode operation.

[0122] For example, the larger of the sense ratios of the IGBT and the diode is 1.2 times or less than the smaller one. The sense ratio of the IGBT is the current I flowing through the electrode 19 when an on-voltage is applied to the gate electrode 12 and the same negative voltage is applied to the electrodes 19 and 22 with respect to the electrode 20. 1 and the current I flowing through electrode 22 2 Comparison with I 1 / I 2 The sense ratio of the diode is the current I flowing through electrode 19 when the same positive voltage is applied to electrode 19 and electrode 23 with electrode 20 as the reference. 3 and the current I flowing through electrode 23 4 Comparison with I 3 / I 4 It is.

[0123] If the current value detected by the IGBT sense region 51 and the current value detected by the diode sense region 52 are approximately the same, instead of using separate sense resistors dedicated to the IGBT and the diode, a common resistor such as the sense resistor 111 in the feedback circuit 150 can be used, thereby reducing the number of sense resistors.

[0124] By changing the size of the electrode 23 in the diode sense region 52 and changing the magnitude of the contact resistance between the electrode 23 and the semiconductor substrate 100, the forward current-forward voltage characteristics of the diode sense region 52 can be changed, and the ratio of the current flowing through the diode main region 32 to the current flowing through the diode sense region 52 can be changed. The same applies to the IGBT region 41. Also, by changing the sense ratio, the current detection sensitivity can be changed without changing the sense resistor 111.

[0125] <B. Embodiment 2> FIG. 1 is a plan view showing a schematic configuration of the semiconductor device 1b according to Embodiment 2.

[0126] FIG. 5 is a cross-sectional view showing the configuration of the semiconductor device 1b according to the present embodiment, and is a cross-sectional view taken along line I-I in FIG. 1.

[0127] Compared with the semiconductor device 1a of Embodiment 1, the semiconductor device 1b does not have the electrode 23 that was provided spaced apart from the electrode 19 on the first main surface 100a in Embodiment 1, and the electrode 19 is provided on the first main surface 100a also in the diode sense region 52. Also, on the second main surface 100b of the diode sense region 52, the electrode 24 is provided separately from the electrode 20. The semiconductor device 1b is the same as the semiconductor device 1a of Embodiment 1 in other respects.

[0128] In other words, in the semiconductor device 1a of Embodiment 1, the sense current was taken out from the first main surface 100a side in the diode sense region 52, whereas in the present embodiment, the sense current is taken out from the second main surface 100b side in the diode sense region 52.

[0129] Since the sense current is taken out from the second main surface 100b side in the diode sense region 52, there is an advantage that the wiring of the electrode 24 can be performed when soldering the semiconductor device 1b to the metal film on the insulating substrate outside the semiconductor device 1b.

[0130] For example, the larger of the sense ratios of the IGBT and the diode is 1.2 times or less than the smaller one. The sense ratio of the IGBT is the current I flowing through the electrode 19 when an on-voltage is applied to the gate electrode 12 and the same negative voltage is applied to the electrodes 19 and 22 with respect to the electrode 20. 5 and the current I flowing through electrode 22 6 Comparison with I 5 / I 6 The sense ratio of the diode is the current I flowing through the electrode 20 when the same negative voltage is applied to the electrodes 20 and 24 with respect to the electrode 19 as a reference. 7 and the current I flowing through electrode 24 8 Comparison with I 7 / I 8 It is.

[0131] During the operation of the semiconductor device 1b, a large potential difference occurs between the electrode 22 on the first main surface 100a side of the IGBT sense region 51 and the electrode 24 on the second main surface 100b side of the diode sense region 52. Therefore, in the first embodiment, the IGBT sense terminal 92 and the diode sense terminal 93 are directly connected to the sense resistor 111, but when the semiconductor device 1b is used in a feedback circuit, the diode sense terminal 94 connected to the electrode 24 cannot be directly connected to the sense resistor 111. In order to prevent a large potential difference from being directly transmitted to the sense resistor 111 and then transmitted to the feedback unit 112 or the electrode 19 through the sense resistor 111, which would lead to the breakdown of the feedback unit 112 or the semiconductor device 1b, the diode sense terminal 94 must be connected to the sense resistor 111 via a potential difference suppression device such as a level shift circuit.

[0132] In this embodiment as well, by implementing such a feature in the feedback circuit and performing the same control as in the first embodiment, it is possible to suppress, for example, the destruction of the semiconductor device 1b caused by an overcurrent flowing through the diode region 42. In this embodiment as well, the isolation region 40 is provided, so that the current flowing through the diode main region 32 can be accurately detected by the diode sense region 52, and the destruction of the semiconductor device 1b caused by an overcurrent can be accurately controlled.

[0133] <C. Embodiment 3> <C-1. Configuration> FIG. 6 is a plan view showing a schematic configuration of the semiconductor device 1c according to Embodiment 3.

[0134] FIG. 7 is a cross-sectional view taken along line II-II in FIG. 6.

[0135] The semiconductor device 1c includes a semiconductor substrate 100, electrodes 19, 20, 22, an insulating film 21, and an insulating film 29.

[0136] As shown in FIG. 6, the semiconductor substrate 100 has an IGBT region 41b in which an IGBT is formed, a pad region 3, and a termination region 2.

[0137] In the pad region 3, a gate pad 3a is provided on the first main surface 100a of the semiconductor substrate 100. In the pad region 3, a gate pad 3b is provided on the second main surface 100b of the semiconductor substrate 100. The gate pad 3a and the gate pad 3b are formed using, for example, an aluminum-based material. The gate pad 3a is electrically separated from the electrodes 19 and 22. The gate pad 3a is electrically connected to the gate electrode 12, and a drive signal can be input to the gate electrode 12 from the outside via the gate pad 3a. The gate pad 3b is electrically separated from the electrode 20. The gate pad 3b is electrically connected to a gate electrode 27 described later, and a drive signal can be input to the gate electrode 27 from the outside via the gate pad 3b.

[0138] The termination region 2 is the same as that described in Embodiment 1.

[0139] As shown in FIG. 7, the semiconductor substrate 100 has a first main surface 100a and a second main surface 100b as one main surface and the other main surface.

[0140] The semiconductor device 1c of this embodiment is a double-sided gate IGBT having a MOS gate not only on the first main surface 100a side but also on the second main surface 100b side. By controlling the gate, the semiconductor device 1c can function as an IGBT element and a free wheel diode element.

[0141] The IGBT region 41b has an IGBT main region 31b and an IGBT sense region 51b.

[0142] In the IGBT main region 31b and the IGBT sense region 51b, an electrode 20 is provided on the second main surface 100b. The IGBT main region 31b and the IGBT sense region 51b share the electrode 20. On the other hand, the electrode 19 provided on the first main surface 100a of the IGBT main region 31b and the electrode 22 provided on the first main surface 100a of the IGBT sense region 51b are provided at a distance from each other.

[0143] The IGBT sense region 51b has a smaller area in plan view than the IGBT main region 31b. The area of ​​the IGBT sense region 51b in plan view is, for example, 1 / 3000 to 1 / 300, for example, about 1 / 1000, of the area of ​​the IGBT main region 31b in plan view.

[0144] The IGBT main region 31b and the IGBT sense region 51b have the same structure except for their different sizes in a plan view. Hereinafter, the IGBT main region 31b and the IGBT sense region 51b will be collectively described as the structure of the IGBT region 41b.

[0145] The semiconductor device 1c has an impurity concentration of, for example, 1×10 14 cm -3 degree of n ― The semiconductor substrate 100 is manufactured using a single crystal bulk silicon substrate of the same type. The single crystal bulk silicon substrate is manufactured using, for example, a floating zone (FZ) method. The single crystal bulk silicon substrate corresponds to the semiconductor substrate 100.

[0146] In the IGBT region 41b, the semiconductor substrate 100 has - a n-type drift layer 10, an n-type buffer layer 16, + a p-type collector layer 14, a p-type base layer 11, + 13, and the n-type emitter layer + A collector layer 25 of the mold is provided.

[0147] The base layer 11 is provided on the drift layer 10 on the first main surface 100a side.

[0148] The emitter layer 13 is selectively provided on the first major surface 100a side of the base layer 11.

[0149] The semiconductor substrate 100 is provided with a trench 17 that extends from the first major surface 100a through the emitter layer 13 and the base layer 11 to the drift layer 10. A gate electrode 12 is provided within the trench 17 via a gate insulating film 18 provided on the bottom and side surfaces of the trench 17. The gate electrode 12 has an impurity concentration of, for example, 1×10 20 cm -3 The trench 17 is formed by using polysilicon having a thickness of about 100 .mu.m. The trench 17 is provided to extend in one direction within the surface, for example.

[0150] The gate electrode 12 faces the emitter layer 13, the base layer 11, and the drift layer 10 with a gate insulating film 18 interposed therebetween.

[0151] In the IGBT region 41b, the base layer 11 includes a base layer 11a and a base layer 11b.

[0152] The base layer 11a is a mesa-shaped portion in which the emitter layer 13 is selectively formed on the surface layer on the first principal surface 100a side, among the multiple mesa shapes formed by dividing the base layer 11 by the trenches 17. The base layer 11b is a mesa-shaped portion in which the emitter layer 13 is not formed on the surface layer on the first principal surface 100a side, among the multiple mesa shapes formed by dividing the base layer 11 by the trenches 17. The base layer 11a and the base layer 11b are alternately arranged, for example, in a direction intersecting with the extension direction of the trenches 17.

[0153] In this embodiment, the thickness of the emitter layer 13 is, for example, about 0.5 μm, and the impurity concentration of the emitter layer 13 is, for example, 3×10 19 cm -3 That's about it.

[0154] In the IGBT main region 31b, the emitter layer 13 and the base layer 11a are electrically connected to an electrode 19 on the first main surface 100a. The electrode 19 functions as an emitter electrode of the IGBT element formed in the IGBT region 41b.

[0155] In the IGBT sense region 51b, the emitter layer 13 and the base layer 11a are electrically connected to the electrode 22 on the first main surface 100a.

[0156] A region of the base layer 11a facing the gate electrode 12 functions as a channel region of the IGBT element formed in the IGBT region 41b.

[0157] Most of the surface of the base layer 11b on the first principal surface 100a side is covered with the insulating film 21. Only a portion of the surface of the base layer 11b on the first principal surface 100a side that is not covered with the insulating film 21 is connected to the electrode 19. The area of ​​the portion where the base layer 11b and the electrode 19 are connected is small, and the electrical resistance of the path passing through the portion where the base layer 11b and the electrode 19 are connected is high. The region where the base layer 11b and the electrode 19 are electrically connected is omitted from the illustration.

[0158] The buffer layer 16 is provided on the drift layer 10 on the second major surface 100b side.

[0159] The buffer layer 16 is intended to suppress the spread of a depletion layer extending from the pn junction at the boundary between the drift layer 10 and the base layer 11 .

[0160] The collector layer 14 is provided on the second major surface 100b side of the buffer layer 16. The thickness of the collector layer 14 is, for example, about 0.5 μm, and the impurity concentration of the collector layer 14 is, for example, 1×10 18 cm -3 That's about it.

[0161] The collector layer 25 is selectively provided on the second major surface 100b side of the collector layer 14.

[0162] The semiconductor substrate 100 is provided with a trench 26 that extends from the second main surface 100b through the collector layer 25 and the collector layer 14 to the drift layer 10. A gate electrode 27 is provided in the trench 26 via a gate insulating film 28 provided on the bottom and side surfaces of the trench 26. The gate electrode 27 has an impurity concentration of, for example, 1×10 20 cm -3 The trench 26 is formed using polysilicon of about 1000 nm thick. The trench 26 is provided to extend in one direction in the plane, for example. The extending direction of the trench 17 and the extending direction of the trench 26 are, for example, the same, but they do not have to be the same.

[0163] The gate electrode 27 faces the collector layer 25, the collector layer 14, the buffer layer 16, and the drift layer 10 with a gate insulating film 28 interposed therebetween.

[0164] In the IGBT region 41b, the collector layer 14 includes a collector layer 14a and a collector layer 14b.

[0165] The collector layer 14a is a mesa-shaped portion in the surface layer on the second main surface 100b side among the plurality of mesa shapes formed by partitioning the collector layer 14 by the trench 26, where the collector layer 25 is selectively formed. The collector layer 14b is a mesa-shaped portion among the plurality of mesa shapes formed by partitioning the collector layer 14 by the trench 26, where the collector layer 25 is not formed in the surface layer on the second main surface 100b side. The collector layer 14a and the collector layer 14b are alternately arranged, for example, in a direction intersecting the extending direction of the trench 26.

[0166] The collector layer 14a and the collector layer 25 are electrically connected to the electrode 20 on the second main surface 100b.

[0167] The region of the collector layer 14a facing the gate electrode 27 functions as the channel region of the IGBT element formed in the IGBT region 41b. Thereby, a current path is formed from the electrode 19 through the base layer 11a, the drift layer 10, the buffer layer 16, the channel region of the collector layer 14a, and the collector layer 25 to the electrode 20, and conduction in the direction corresponding to the conduction of the diode of the semiconductor device 1a which is an RC-IGBT can be achieved.

[0168] Most of the surface on the second main surface 100b side of the collector layer 14b is covered by the insulating film 29. Only a part of the surface on the second main surface 100b side of the collector layer 14b that is not covered by the insulating film 29 is connected to the electrode 20. The area of the portion where the collector layer 14b and the electrode 20 are connected is small, and the electrical resistance of the path passing through the portion where the collector layer 14b and the electrode 20 are connected is large. The illustration of the region where the collector layer 14b and the electrode 20 are electrically connected is omitted.

[0169] <C-2. Operation> The operation mode by gate control of the semiconductor device 1c which is a double-sided gate IGBT is shown in FIG. 8.

[0170] The semiconductor device 1c has operation modes 1 to 8. The operation modes are classified according to the positive or negative collector voltage, the first gate voltage applied to the gate electrode 12, and the second gate voltage applied to the gate electrode 27. The collector voltage represents the potential of the electrode 20 when the electrode 19 is grounded and the potential of the electrode 19 is zero.

[0171] In FIG. 8, a gate voltage "applied" indicates that an on-voltage is applied, and a gate voltage "not applied" indicates that an on-voltage is not applied.

[0172] 8, the "Aspect" column indicates whether or not a current flows when the semiconductor device 1c is operating normally, and if so, in which direction the current flows. In the "Aspect" column of FIG. 8 and the following description of this embodiment, a forward current indicates a current flowing in the direction from electrode 20 to electrode 19, and a reverse current indicates a current flowing in the direction from electrode 19 to electrode 20.

[0173] In operation modes 2 and 3, semiconductor device 1c passes current in a direction corresponding to the current passing through semiconductor device 1a, which is an RC-IGBT, as an IGBT. In operation modes 7 and 8, semiconductor device 1c passes current in a direction corresponding to the current passing through semiconductor device 1a, which is an RC-IGBT, as a diode. In operation modes 7 and 8, semiconductor device 1c can function similarly to a free wheel diode element.

[0174] The current-voltage characteristics of the forward current vary depending on the drive signal input to the gate electrode 27. That is, the current-voltage characteristics differ between the operation modes 2 and 3.

[0175] The current-voltage characteristics of the reverse current vary depending on the drive signal input to the gate electrode 12. That is, the current-voltage characteristics vary between the operation modes 7 and 8.

[0176] The current-voltage characteristics of the forward current fluctuate due to the drive signal input to the gate electrode 27. However, since the current-voltage characteristics fluctuate correspondingly in the IGBT main region 31b and the IGBT sense region 51b, fluctuations in the ratio between the current flowing through the IGBT main region 31b and the current flowing through the IGBT sense region 51b can be suppressed. Therefore, the IGBT sense region 51b can accurately detect the forward current flowing through the IGBT main region 31b. Similarly, the IGBT sense region 51b can accurately detect the reverse current flowing through the IGBT main region 31b.

[0177] Similar to the case of the feedback circuit 150 described in Embodiment 1, the feedback circuit can prevent thermal breakdown of the semiconductor device 1c. For this purpose, for example, the electrode 22 is connected to one end of the sense resistor of the feedback circuit, the electrode 19 is connected to the other end of the sense resistor of the feedback circuit, the potential difference Vs between both ends of the sense resistor is detected, and the potential difference Vs between both ends of the sense resistor is compared with an overcurrent detection threshold Vth2 for determining whether the forward current is an overcurrent and an overcurrent detection threshold Vth3 for determining whether the reverse current is an overcurrent, and fed back to the gate signal.

[0178] In operation mode 2 or operation mode 3, the potential difference Vs between both ends of the sense resistor becomes a positive value. That is, the potential of the side connected to the electrode 19 becomes lower among both ends of the sense resistor. In operation mode 7 or operation mode 8, the potential difference Vs between both ends of the sense resistor becomes a negative value. That is, the potential of the side connected to the electrode 19 becomes higher among both ends of the sense resistor.

[0179] <C-3. Modification Example> In the present embodiment, a configuration in which the IGBT sense region 51b is used to detect both the forward current and the reverse current has been described. However, as shown in FIGS. 9 and 10, even in a semiconductor device 1d including the IGBT sense region 51b and the IGBT sense region 52b, thermal breakdown can be prevented with the same accuracy. FIG. 10 is a cross-sectional view taken along line III-III of FIG. 9.

[0180] Compared with the semiconductor device 1c, the semiconductor device 1d further includes an IGBT sense region 52b in the IGBT region 41b. In the IGBT sense region 52b, the electrode 24 is provided spaced apart from the electrode 20 on the second main surface 100b, which is different. The semiconductor device 1d is the same as the semiconductor device 1c in other respects.

[0181] The structure of the semiconductor substrate 100 in the IGBT sense region 52b is the same as the structure of the semiconductor substrate 100 in the IGBT main region 31b and the IGBT sense region 51b.

[0182] In the semiconductor device 1d, a forward current can be detected by the IGBT sense region 51b, and a reverse current can be detected by the IGBT sense region 52b. Also in the semiconductor device 1d, similar to the case of the semiconductor device 1c, the forward and reverse currents can be accurately detected while suppressing the influence of the drive signal input to the gate electrode 12 or the gate electrode 27.

[0183] <C-4. Others> Since the termination region 2 is provided on the outer periphery in the surface layer portion on the first main surface 100a side of the semiconductor substrate 100, the effective operation region on the first main surface 100a side has a smaller area than the effective operation region on the second main surface 100b side. Therefore, in the semiconductor device 1c, even if both the forward current and the reverse current are detected by the IGBT sense region 51b, the sense ratios are different for the forward current and the reverse current. Also, in the semiconductor device 1d, even if the ratio of the size of the IGBT sense region 51b to the size of the IGBT main region 31b is the same as the ratio of the size of the IGBT sense region 52b to the size of the IGBT main region 31b, the sense ratios are different for the forward current and the reverse current.

[0184] In the semiconductor devices 1c and 1d, the current-voltage characteristics of the forward current are affected by the channel resistance of the channel formed in the base layer 11, whereas the current-voltage characteristics of the reverse current are affected by the channel resistance of the channel formed in the collector layer 14. The difference between the magnitude of the channel resistance of the channel formed in the base layer 11 and the magnitude of the channel resistance of the channel formed in the collector layer 14 also causes a difference between the forward current sense ratio and the reverse current sense ratio.

[0185] The channel resistance is affected by the impurity concentration of the semiconductor layer in which the channel is formed, the channel length, the channel width, and the like. Among these, the channel width is less affected by the manufacturing process and can be easily optimized. FIG. 11 is a schematic plan view of the first main surface 100a of the IGBT main region 31b. FIG. 13 is a cross-sectional view taken along the line IV-IV in FIG. 11, showing the gate width GW of the emitter layer 13. The gate width of the emitter layer 13 represents the width at which each region of the emitter layer 13 contacts the trench 17 on the first main surface 100a. This width is the width in the extension direction of the trench 17. In FIG. 13, only the vicinity of the first main surface 100a is shown.

[0186] As shown in FIG. 10 or FIG. 11, in the mesa shape formed by partitioning the base layer 11 by trenches 17, the emitter layer 13 may not be connected between one trench 17 and the other trench 17, or as shown in FIG. 12, the emitter layer 13 may be connected between one trench 17 and the other trench 17.

[0187] Changing the gate width of the emitter layer 13 in the IGBT sense region 51b or the gate width of the emitter layer 13 in the IGBT main region 31b changes the channel resistance in the IGBT sense region 51b or the channel resistance in the IGBT main region 31b, and changes the ratio of the forward current flowing through the IGBT main region 31b to the forward current flowing through the IGBT sense region 51b. Thereby, the sense ratio of the forward current of the semiconductor device 1c can be changed without changing the size of the IGBT sense region 51b and the circuit outside the semiconductor device 1c. Also, in this case, the change in the ratio of the reverse current flowing through the IGBT main region 31b to the reverse current flowing through the IGBT sense region 51b is smaller than the change in the ratio of the forward current flowing through the IGBT main region 31b to the forward current flowing through the IGBT sense region 51b. Therefore, by changing the gate width of the emitter layer 13 in the IGBT sense region 51b or the gate width of the emitter layer 13 in the IGBT main region 31b, it is possible to adjust the sense ratio to be the same for both the forward current and the reverse current.

[0188] Similarly, in the semiconductor device 1c, by changing the gate width of the collector layer 25 in the IGBT sense region 51b or the gate width of the collector layer 25 in the IGBT main region 31b, it is also possible to adjust the sense ratio to be the same for both the forward current and the reverse current. The gate width of the collector layer 25 represents the width at which each region of the collector layer 25 is in contact with the trench 26 on the second main surface 100b. The said width is the width in the extending direction of the trench 26.

[0189] In the semiconductor device 1c, for example, the larger of the forward current sense ratio and the reverse current sense ratio is 1.2 times or less than the smaller one. Therefore, for example, the ratio W1 / W2 of the sum W1 of the gate widths of the emitter layer 13 in the region overlapping in plan view with the region where the electrode 19 is provided on the first main surface 100a to the sum W2 of the gate widths of the emitter layer 13 in the region overlapping in plan view with the region where the electrode 22 is provided on the first main surface 100a, and the ratio W3 / W4 of the sum W3 of the gate widths of the collector layer 25 in the region overlapping in plan view with the region where the electrode 19 is provided on the first main surface 100a to the sum W4 of the gate widths of the collector layer 25 in the region overlapping in plan view with the region where the electrode 22 is provided on the first main surface 100a are different.

[0190] In the semiconductor device 1c, the sense ratio of the forward current is the ratio of the current I flowing through the electrode 19 when an on-voltage is applied to the gate electrode 12 and the same negative voltage is applied to the electrodes 19 and 22 with respect to the electrode 20. 9 and the current I flowing through electrode 22 10 Comparison with I 9 / I 10 In the semiconductor device 1c, the sense ratio of the reverse current is the ratio of the current I flowing through the electrode 19 when an on-voltage is applied to the gate electrode 27 and the same positive voltage is applied to the electrodes 19 and 22 with respect to the electrode 20. 11 and the current I flowing through electrode 22 12 Comparison with I 11 / I 12 It is.

[0191] Similarly, in the case of semiconductor device 1d, the gate width of emitter layer 13 in IGBT sense region 51b, the gate width of emitter layer 13 in IGBT main region 31b, the gate width of collector layer 25 in IGBT sense region 52b, or the gate width of collector layer 25 in IGBT main region 31b can be changed to adjust the sense ratio to be the same for forward current and reverse current.

[0192] In the semiconductor device 1d, for example, the larger one of the sense ratio of the forward current and the sense ratio of the reverse current is 1.2 times or less of the smaller one. For this purpose, for example, the sum W5 of the gate widths of the emitter layer 13 in the region overlapping with the region where the electrode 19 is provided on the first main surface 100a in a plan view, and the sum W6 of the gate widths of the emitter layer 13 in the region overlapping with the region where the electrode 22 is provided on the first main surface 100a in a plan view, the ratio W5 / W6 thereof, the sum W7 of the gate widths of the collector layer 25 in the region overlapping with the region where the electrode 20 is provided on the second main surface 100b in a plan view, and the sum W8 of the gate widths of the collector layer 25 in the region overlapping with the region where the electrode 24 is provided on the second main surface 100b in a plan view, the ratio W7 / W8 thereof, are different.

[0193] In the semiconductor device 1d, the sense ratio of the forward current is the current I flowing through the electrode 19 when an on-voltage is applied to the gate electrode 12 and negative voltages of the same magnitude are applied to the electrode 19 and the electrode 22 with respect to the electrode 20. 13 and the current I flowing through the electrode 22 14 and the ratio I 13 / I 14 is. Further, in the semiconductor device 1d, the sense ratio of the reverse current is the current I flowing through the electrode 20 when an on-voltage is applied to the gate electrode 27 and negative voltages of the same magnitude are applied to the electrode 20 and the electrode 24 with respect to the electrode 19. 15 and the current I flowing through the electrode 24 16 and the ratio I 15 / I 16 is.

[0194] In the semiconductor device 1d, in order that the larger one of the sense ratio of the forward current and the sense ratio of the reverse current is 1.2 times or less of the smaller one, the area of the electrode 22 in a plan view and the area of the electrode 24 in a plan view may be made different.

[0195] <D. Embodiment 4> In this embodiment, the semiconductor device according to any one of the above-mentioned embodiments 1 to 3 is applied to a power conversion device. Although the application of the semiconductor device according to any one of the embodiments 1 to 3 is not limited to a specific power conversion device, a case where the semiconductor device according to any one of the embodiments 1 to 3 is applied to a three-phase inverter will be described below as embodiment 4.

[0196] FIG. 14 is a block diagram showing a configuration of a power conversion system to which the power conversion device according to this embodiment is applied.

[0197] The power conversion system shown in Fig. 14 is composed of a power source 160, a power conversion device 200, and a load 300. The power source 160 is a DC power source and supplies DC power to the power conversion device 200. The power source 160 can be composed of various things, for example, a DC system, a solar cell, or a storage battery, or it may be composed of a rectifier circuit or an AC / DC converter connected to an AC system. The power source 160 may also be composed of a DC / DC converter that converts DC power output from a DC system into a predetermined power.

[0198] The power conversion device 200 is a three-phase inverter connected between the power source 160 and the load 300, converts DC power supplied from the power source 160 into AC power, and supplies the AC power to the load 300. As shown in Fig. 14, the power conversion device 200 includes a main conversion circuit 201 that converts DC power into AC power and outputs the AC power, a drive circuit 202 that outputs drive signals that drive each switching element of the main conversion circuit 201, and a control circuit 203 that outputs a control signal for controlling the drive circuit 202 to the drive circuit 202. Although a configuration in which the output of the drive circuit 202 is input to the semiconductor device 1a via the AND circuit 110 is shown in Fig. 4, the drive circuit 202 may include the AND circuit 110 and a feedback unit 112.

[0199] The load 300 is a three-phase motor driven by AC power supplied from the power conversion device 200. The load 300 is not limited to a specific application, but is a motor mounted on various electric devices, and is used as, for example, a motor for a hybrid vehicle, an electric vehicle, a railroad car, an elevator, or an air conditioner.

[0200] The power conversion device 200 will be described in detail below. The main conversion circuit 201 includes a switching element (not shown), and converts DC power supplied from the power source 160 into AC power by switching the switching element, and supplies the AC power to the load 300. In this embodiment, the switching element included in the main conversion circuit 201 is an RC-IGBT element or a double-sided gate IGBT element. There are various specific circuit configurations of the main conversion circuit 201, but the main conversion circuit 201 according to this embodiment is a two-level three-phase full bridge circuit, and can be configured with six switching elements, that is, six RC-IGBT elements or six double-sided gate IGBT elements. The semiconductor device according to any one of the above-mentioned embodiments 1 to 3 is applied to each switching element of the main conversion circuit 201. Two switching elements of the six switching elements are connected in series to configure upper and lower arms, and each upper and lower arm configures each phase (U phase, V phase, W phase) of the full bridge circuit. The output terminals of each upper and lower arm, that is, the three output terminals of the main conversion circuit 201, are connected to the load 300.

[0201] The drive circuit 202 generates drive signals for driving the switching elements of the main conversion circuit 201 and supplies them to the control electrodes of the switching elements of the main conversion circuit 201. Specifically, in accordance with a control signal from a control circuit 203 described later, the drive circuit 202 outputs to the control electrodes of each switching element a drive signal for turning the switching element on and a drive signal for turning the switching element off. When maintaining a switching element in the on state, the drive signal is a voltage signal (on signal) equal to or higher than the threshold voltage of the switching element, and when maintaining a switching element in the off state, the drive signal is a voltage signal (off signal) equal to or lower than the threshold voltage of the switching element.

[0202] The control circuit 203 controls the switching elements of the main conversion circuit 201 so that a desired power is supplied to the load 300. Specifically, the control circuit 203 calculates the time (on time) for each switching element of the main conversion circuit 201 to be in the on state based on the power to be supplied to the load 300. For example, the main conversion circuit 201 can be controlled by PWM control that modulates the on time of the switching elements according to the voltage to be output. Then, the control circuit 203 outputs a control command (control signal) to the drive circuit 202 so that an on signal is output to the switching element that should be in the on state at each point in time, and an off signal is output to the switching element that should be in the off state. The drive circuit 202 outputs an on signal or an off signal as a drive signal to the control electrode of each switching element according to this control signal.

[0203] In the power conversion device according to the present embodiment, the semiconductor device according to any one of the first to third embodiments is applied as a switching element of the main conversion circuit 201, so that the return current can be detected with high accuracy. This makes it possible to prevent the power conversion device from being destroyed due to an overcurrent flowing through the switching element, for example.

[0204] When the power conversion device 200 includes a semiconductor device 1a as a switching element, the drive circuit 202 or the control circuit 203, or both, protect the semiconductor device 1a from overcurrent, for example, based on at least one of the current flowing through electrode 22 and the current flowing through electrode 23.

[0205] When the power conversion device 200 includes the semiconductor device 1b as a switching element, the drive circuit 202 or the control circuit 203, or both, protect the semiconductor device 1b from overcurrent, for example, based on at least one of the current flowing through the electrode 22 and the current flowing through the electrode 24.

[0206] When the power conversion device 200 includes the semiconductor device 1c as a switching element, the drive circuit 202 and / or the control circuit 203 protect the semiconductor device 1c from an overcurrent based on the current flowing through the electrode 22, for example.

[0207] When the power conversion device 200 includes the semiconductor device 1d as a switching element, the drive circuit 202 or the control circuit 203, or both, protect the semiconductor device 1d from overcurrent, for example, based on at least one of the current flowing through the electrode 22 and the current flowing through the electrode 24.

[0208] When the power conversion device 200 includes the semiconductor device 1a, the semiconductor device 1b, or the semiconductor device 1d as a switching element, for example, the power conversion device 200 includes a resistor, and the resistor is arranged so that the current flowing through the electrode 22 and the current flowing through the electrode 23 or the current flowing through the electrode 24 flow through the resistor, like the sense resistor 111 in the feedback circuit 150 shown in FIG. 4. The drive circuit 202 or the control circuit 203, or both of them, protect the semiconductor device 1a, the semiconductor device 1b, or the semiconductor device 1d based on the potential difference across the resistor. By detecting the bidirectional current flowing through the semiconductor device 1a, the semiconductor device 1b, or the semiconductor device 1d using one resistor, the configuration is simplified and the manufacturing cost can be suppressed.

[0209] In the present embodiment, an example in which the semiconductor device according to any one of the first to third embodiments is applied to a two-level three-phase inverter has been described, but the application of the semiconductor device according to any one of the first to third embodiments is not limited to this, and the semiconductor device can be applied to various power conversion devices. In the present embodiment, the two-level power conversion device is described, but the semiconductor device can be a three-level or multilevel power conversion device, and when power is supplied to a single-phase load, the semiconductor device according to any one of the first to third embodiments can be applied to a single-phase inverter. Furthermore, when power is supplied to a DC load or the like, the semiconductor device according to any one of the first to third embodiments can be applied to a DC / DC converter or an AC / DC converter.

[0210] Furthermore, a power conversion device to which the semiconductor device according to any one of the first to third embodiments is applied is not limited to the case where the load described above is an electric motor, but can also be used, for example, as a power supply device for an electric discharge machine, a laser processing machine, an induction heating cooker, or a non-contact power supply system, and can also be used as a power conditioner for a solar power generation system or a power storage system, etc.

[0211] It should be noted that the embodiments can be freely combined, and each embodiment can be modified or omitted as appropriate. [Explanation of symbols]

[0212] 1a, 1b, 1c, 1d semiconductor device, 2 termination region, 3 pad region, 3a, 3b gate pad, 10 drift layer, 11, 11a, 11b base layer, 11c anode layer, 12, 27 gate electrode, 13 emitter layer, 14, 14a, 14b, 25 collector layer, 15 cathode layer, 16 buffer layer, 17, 26 trench, 18, 28 gate insulating film, 19 electrode, 20, 22, 23, 24 electrode, 21, 29 insulating film, 31, 31b IGBT main region, 32 diode main region, 40 isolation region, 41, 41b IGBT region, 42 diode region, 51, 51b, 52b IGBT sense region, 52 diode sense region, 90 gate terminal, 91 emitter sense terminal, 92 IGBT sense terminal, 93 Diode sense terminal, 94 diode sense terminal, 95 collector terminal, 96 emitter terminal, 100 semiconductor substrate, 100a first main surface, 100b second main surface, 110 AND circuit, 111 sense resistor, 112 feedback section, 113 gate resistor, 150 feedback circuit, 160 power supply, 200 power conversion device, 201 main conversion circuit, 202 drive circuit, 203 control circuit, 300 load.

Claims

1. A semiconductor device in which a transistor and a diode are formed on a common semiconductor substrate, A first electrode; A second electrode; A third electrode for current sensing; A fourth electrode for current sensing; A first gate electrode; Equipped with The semiconductor substrate is a first main surface and a second main surface as one main surface and the other main surface; a transistor region in which the transistor is formed; a diode region in which the diode is formed; an isolation region provided between the transistor region and the diode region; having The transistor region is A first semiconductor layer of a first conductivity type; an eighth semiconductor layer of a first conductivity type provided on the second main surface side of the first semiconductor layer and having a higher first conductivity type impurity concentration than the first semiconductor layer; a second semiconductor layer of a second conductivity type provided on the second major surface side of the eighth semiconductor layer; a third semiconductor layer of a second conductivity type provided on the first major surface side of the first semiconductor layer; a fourth semiconductor layer of a first conductivity type selectively provided on the first major surface side of the third semiconductor layer; Equipped with The diode region is The first semiconductor layer; the eighth semiconductor layer provided on the second major surface side of the first semiconductor layer; a fifth semiconductor layer of a first conductivity type provided on the second major surface side of the eighth semiconductor layer and having a higher first conductivity type impurity concentration than the first semiconductor layer; a sixth semiconductor layer of a second conductivity type provided on the first major surface side of the first semiconductor layer; Equipped with the first electrode is provided on the first main surface of the transistor region and on the first main surface of the diode region; the second electrode is provided on the second main surface of the transistor region and on the second main surface of the diode region; the third electrode is provided on the first main surface of the transistor region of the semiconductor substrate and spaced apart from the first electrode; the fourth electrode is provided on the second main surface of the diode region of the semiconductor substrate and spaced apart from the second electrode, In the transistor region, the third semiconductor layer and the fourth semiconductor layer are electrically connected to the first electrode on the first major surface, In the transistor region, the third semiconductor layer and the fourth semiconductor layer are electrically connected to the third electrode on the first major surface, In the transistor region, the second semiconductor layer is electrically connected to the second electrode at the second major surface, in the transistor region, the first gate electrode faces the first semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer via a first insulating film; In the diode region, the sixth semiconductor layer is electrically connected to the first electrode at the first major surface, In the diode region, the fifth semiconductor layer is electrically connected to the fourth electrode at the second major surface, In the diode region, the fifth semiconductor layer is electrically connected to the second electrode at the second major surface. Semiconductor device.

2. 2. The semiconductor device according to claim 1, When an on-voltage is applied to the first gate electrode, and when a voltage of the same magnitude is applied to the first electrode and the third electrode with respect to the second electrode, the voltage is positive when the first conductivity type is p-type, and negative when the first conductivity type is n-type, the current I flowing through the first electrode is ５ and the current I flowing through the third electrode ６ Comparison with I ５ / I ６ and, A current I flowing through the second electrode when a voltage of the same magnitude is applied to the second electrode and the fourth electrode with respect to the first electrode as a reference, the voltage being positive when the first conductivity type is p-type and negative when the first conductivity type is n-type. ７ and the current I flowing through the fourth electrode ８ Comparison with I ７ / I ８ and, The larger of these is not more than 1.2 times the smaller of these. Semiconductor device.

3. 3. The semiconductor device according to claim 1, In a plan view, a boundary between the second semiconductor layer and the fifth semiconductor layer is at least partially included in the separation region. Semiconductor device.

4. 4. The semiconductor device according to claim 1, the fifth semiconductor layer and the eighth semiconductor layer are integral with each other; Semiconductor device.

5. A semiconductor device having a transistor formed on a semiconductor substrate, A first electrode; A second electrode; A third electrode for current sensing; A first gate electrode; A second gate electrode; Equipped with the semiconductor substrate has a first main surface and a second main surface as one main surface and the other main surface, The semiconductor substrate is A first semiconductor layer of a first conductivity type; an eighth semiconductor layer of a first conductivity type provided on the second main surface side of the first semiconductor layer and having a higher first conductivity type impurity concentration than the first semiconductor layer; a second semiconductor layer of a second conductivity type provided on the second major surface side of the eighth semiconductor layer; a seventh semiconductor layer of a first conductivity type selectively provided on the second major surface side of the second semiconductor layer; a third semiconductor layer of a second conductivity type provided on the first major surface side of the first semiconductor layer; a fourth semiconductor layer of a first conductivity type selectively provided on the first major surface side of the third semiconductor layer; Equipped with the first electrode is provided on the first main surface of the semiconductor substrate, the second electrode is provided on the second main surface of the semiconductor substrate, the third electrode is provided on the first main surface of the semiconductor substrate and spaced apart from the first electrode; the third semiconductor layer and the fourth semiconductor layer are electrically connected to the first electrode at the first major surface, the third semiconductor layer and the fourth semiconductor layer are electrically connected to the third electrode on the first major surface, the second semiconductor layer and the seventh semiconductor layer are electrically connected to the second electrode on the second major surface, the first gate electrode faces the first semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer via a first insulating film; the second gate electrode faces the first semiconductor layer, the second semiconductor layer, the seventh semiconductor layer, and the eighth semiconductor layer via a second insulating film; Semiconductor device.

6. 6. The semiconductor device according to claim 5, When an on-voltage is applied to the first gate electrode, and when a voltage of the same magnitude is applied to the first electrode and the third electrode with respect to the second electrode, the voltage is positive when the first conductivity type is p-type, and negative when the first conductivity type is n-type, the current I flowing through the first electrode is ９ and the current I flowing through the third electrode １０ Comparison with I ９ / I １０ and, When an on-voltage is applied to the second gate electrode, and when a voltage of the same magnitude is applied to the first electrode and the third electrode with respect to the second electrode, the voltage is negative when the first conductivity type is p-type, and positive when the first conductivity type is n-type, the current I flowing through the first electrode is １１ and the current I flowing through the third electrode １２ Comparison with I １１ / I １２ and, The larger of these is not more than 1.2 times the smaller of these. Semiconductor device.

7. 7. The semiconductor device according to claim 6, the first gate electrode is provided in a first trench extending in a first direction in the first main surface of the semiconductor substrate, with the first insulating film interposed therebetween; the second gate electrode is provided in a second trench extending in a second direction in the second main surface of the semiconductor substrate via the second insulating film; the fourth semiconductor layer is provided so as to be in contact with the first trench at the first major surface, the seventh semiconductor layer is provided so as to be in contact with the second trench at the second major surface, a ratio W1 / W2 of a sum W1 of widths in the first direction in which the fourth semiconductor layer is in contact with the first trenches on the first main surface in a region overlapping in a plan view with a region in which the first electrode is provided on the first main surface, and a sum W2 of widths in the first direction in which the fourth semiconductor layer is in contact with the first trenches on the first main surface in a region overlapping in a plan view with a region in which the third electrode is provided on the first main surface; a ratio W3 / W4 of a sum W3 of widths in the second direction in which the seventh semiconductor layer is in contact with the second trenches on the second main surface in a region overlapping in a plan view with a region in which the first electrode is provided on the first main surface, and a sum W4 of widths in the second direction in which the seventh semiconductor layer is in contact with the second trenches on the second main surface in a region overlapping in a plan view with a region in which the third electrode is provided on the first main surface; is different, Semiconductor device.

8. A semiconductor device having a transistor formed on a semiconductor substrate, A first electrode; A second electrode; A third electrode for current sensing; A fourth electrode for current sensing; A first gate electrode; A second gate electrode; Equipped with the semiconductor substrate has a first main surface and a second main surface as one main surface and the other main surface, The semiconductor substrate is A first semiconductor layer of a first conductivity type; an eighth semiconductor layer of a first conductivity type provided on the second main surface side of the first semiconductor layer and having a higher first conductivity type impurity concentration than the first semiconductor layer; a second semiconductor layer of a second conductivity type provided on the second major surface side of the eighth semiconductor layer; a seventh semiconductor layer of a first conductivity type selectively provided on the second major surface side of the second semiconductor layer; a third semiconductor layer of a second conductivity type provided on the first major surface side of the first semiconductor layer; a fourth semiconductor layer of a first conductivity type selectively provided on the first major surface side of the third semiconductor layer; Equipped with the first electrode is provided on the first main surface of the semiconductor substrate, the second electrode is provided on the second main surface of the semiconductor substrate, the third electrode is provided on the first main surface of the semiconductor substrate and spaced apart from the first electrode; the fourth electrode is provided on the second main surface of the semiconductor substrate and spaced apart from the second electrode, the third semiconductor layer and the fourth semiconductor layer are electrically connected to the first electrode at the first major surface, the third semiconductor layer and the fourth semiconductor layer are electrically connected to the third electrode on the first major surface, the second semiconductor layer and the seventh semiconductor layer are electrically connected to the second electrode on the second major surface, the second semiconductor layer and the seventh semiconductor layer are electrically connected to the fourth electrode on the second major surface, the first gate electrode faces the first semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer via a first insulating film; the second gate electrode faces the first semiconductor layer, the second semiconductor layer, the seventh semiconductor layer, and the eighth semiconductor layer via a second insulating film; Semiconductor device.

9. 9. The semiconductor device according to claim 8, When an on-voltage is applied to the first gate electrode, and when a voltage of the same magnitude is applied to the first electrode and the third electrode with respect to the second electrode, the voltage is positive when the first conductivity type is p-type, and negative when the first conductivity type is n-type, the current I flowing through the first electrode is １３ and the current I flowing through the third electrode １４ Comparison with I １３ / I １４ and, When an on-voltage is applied to the second gate electrode, and when a voltage of the same magnitude is applied to the second electrode and the fourth electrode with respect to the first electrode, the voltage is positive when the first conductivity type is p-type, and negative when the first conductivity type is n-type, the current I flowing through the second electrode is １５ and the current I flowing through the fourth electrode １６ Comparison with I １５ / I １６ and, The larger of these is not more than 1.2 times the smaller of these. Semiconductor device.

10. 10. The semiconductor device according to claim 9, the first gate electrode is provided in a first trench extending in a first direction, which is one in-plane direction, on the first main surface of the semiconductor substrate, with the first insulating film interposed therebetween; the second gate electrode is provided in a second trench extending in a second direction, which is one in-plane direction, on the second main surface of the semiconductor substrate, with the second insulating film interposed therebetween; the fourth semiconductor layer is provided so as to be in contact with the first trench at the first major surface, the seventh semiconductor layer is provided so as to be in contact with the second trench at the second major surface, a ratio W5 / W6 of a sum W5 of widths in the first direction in which the fourth semiconductor layer is in contact with the first trenches on the first main surface in a region overlapping in a plan view with a region in which the first electrode is provided on the first main surface, and a sum W6 of widths in the first direction in which the fourth semiconductor layer is in contact with the first trenches on the first main surface in a region overlapping in a plan view with a region in which the third electrode is provided on the first main surface; a ratio W7 / W8 of a sum W7 of widths in the second direction in which the seventh semiconductor layer is in contact with the second trenches on the second main surface in a region overlapping in a plan view with a region in which the second electrode is provided on the second main surface, and a sum W8 of widths in the second direction in which the seventh semiconductor layer is in contact with the second trenches on the second main surface in a region overlapping in a plan view with a region in which the fourth electrode is provided on the second main surface; is different, Semiconductor device.

11. 10. The semiconductor device according to claim 9, an area of ​​the third electrode in a plan view and an area of ​​the fourth electrode in a plan view are different from each other; Semiconductor device.

12. A main conversion circuit having the semiconductor device according to any one of claims 1 to 11; a drive circuit that outputs a drive signal for driving the semiconductor device to the semiconductor device; a control circuit that outputs a control signal to the drive circuit to control the drive circuit; Equipped with The main conversion circuit converts the input power and outputs it. Power conversion equipment.

13. The power conversion device according to claim 12, The semiconductor device is a semiconductor device according to claim 1 or 8, the drive circuit or the control circuit, or both, protect the semiconductor device from an overcurrent based on at least one of a current flowing through the third electrode and a current flowing through the fourth electrode. Power conversion equipment.

14. The power conversion device according to claim 12 or 13, The semiconductor device is a semiconductor device according to claim 1 or 8, With resistance, the resistor is arranged such that a current passing through the third electrode flows through the resistor; the resistor is arranged such that a current passing through the fourth electrode flows through the resistor; the drive circuit or the control circuit, or both, protect the semiconductor device from an overcurrent based on a potential difference across the resistor. Power conversion equipment.

15. The power conversion device according to claim 12, The semiconductor device is a semiconductor device according to claim 5, the drive circuit or the control circuit, or both, protect the semiconductor device from an overcurrent based on a current flowing through the third electrode. Power conversion equipment.

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