Power Conversion Equipment

Abstract

The converter cell (10) included in the power conversion device includes a cell control unit (15), a first switching circuit (21), and a second switching circuit (22). The first switching circuit (21) includes a first semiconductor element (31), a second semiconductor element (32), and a first energy storage element (EP). The second switching circuit (22) includes a third semiconductor element (33), a fourth semiconductor element (34), and a second energy storage element (EN). The converter cell (10) includes first to fourth gate control units (91 to 94). When one of the first to fourth gate control units (91 to 94) detects a short-circuit current flowing through a semiconductor element to be driven, the gate control unit controls the semiconductor element to an OFF state and transmits abnormality detection information. When the cell control unit (15) receives the abnormality detection information, the cell control unit (15) transmits a control signal to the first to fourth gate control units (91 to 94) for controlling the semiconductor element to be driven to an OFF state.

Description

[Technical field]

[0001] The present disclosure relates to a power conversion device. [Background technology]

[0002] In recent years, modular multilevel converters (MMCs) have become known as high-voltage, large-capacity power conversion devices that are applied to high-voltage systems such as power grids. MMCs are composed of arms in which converter cells are cascaded. The converter cells include multiple semiconductor switches and capacitors, and output either the voltage across the capacitor or zero voltage by turning the semiconductor switches on and off. In addition, power conversion devices are known that, when an abnormality occurs in a converter cell, enable continued operation by shorting the converter cell using a bypass element.

[0003] For example, the power conversion device disclosed in Japanese Patent Publication No. 5889498 (Patent Document 1) is configured such that, when an abnormality is detected in a converter cell, a semiconductor element selected from among a plurality of semiconductor elements is turned on so as to continuously form a current path that does not include a bypass element for a period until a closed circuit of the bypass element is established. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent No. 5889498 Summary of the Invention [Problem to be solved by the invention]

[0005] In Patent Document 1, a method is considered for preventing damage to the bypass element by suppressing an overcurrent that flows through the bypass element when the bypass element closes when an abnormality occurs in the converter cell. The converter cell according to Patent Document 1 is configured with a half-bridge circuit or a full-bridge circuit.

[0006] On the other hand, in a converter cell having a configuration in which two half-bridge circuits are connected in series, the voltage applied to the entire converter cell can be divided by the two half-bridge circuits, so that the voltage applied to each half-bridge circuit can be reduced. In a converter cell having such a configuration, a short circuit may occur in an abnormality. Therefore, even when such a short circuit occurs, it is necessary to protect the semiconductor element included in the converter cell. However, Patent Document 1 does not teach or suggest a solution for realizing such protection.

[0007] An object of one aspect of the present disclosure is to provide a power conversion device capable of protecting semiconductor elements included in a converter cell when an abnormality occurs in the converter cell composed of two half-bridge circuits connected in series. [Means for solving the problem]

[0008] According to an embodiment, a power conversion device including a plurality of converter cells connected in series is provided. Each of the plurality of converter cells includes a cell control unit, a first switching circuit and a second switching circuit connected in series, and a first input / output terminal and a second input / output terminal. The first switching circuit includes a first semiconductor element, a second semiconductor element, and a first energy storage element connected in parallel to a series body including the first semiconductor element and the second semiconductor element. The first input / output terminal is connected to a connection point between a negative terminal of the first semiconductor element and a positive terminal of the second semiconductor element. The second switching circuit includes a third semiconductor element, a fourth semiconductor element, and a second energy storage element connected in parallel to a series body including the third semiconductor element and the fourth semiconductor element. The second input / output terminal is connected to a connection point between a negative terminal of the third semiconductor element and a positive terminal of the fourth semiconductor element. Each of the plurality of converter cells further includes a first gate control unit that drives the first semiconductor element, a second gate control unit that drives the second semiconductor element, a third gate control unit that drives the third semiconductor element, and a fourth gate control unit that drives the fourth semiconductor element. When one of the first to fourth gate control units detects a short-circuit current flowing through a semiconductor element that is the driving target of the one of the first to fourth gate control units, the gate control unit controls the driving target semiconductor element to an OFF state and transmits abnormality detection information to the cell control unit. When the cell control unit receives the abnormality detection information, the cell control unit transmits a control signal to each of the first to fourth gate control units for controlling the driving target semiconductor element of the gate control unit to an OFF state. Effect of the Invention

[0009] According to the present disclosure, when an abnormality occurs in a converter cell formed of two half-bridge circuits connected in series, it is possible to protect a semiconductor element included in the converter cell. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a schematic configuration diagram of a power conversion device. [Diagram 2] FIG. 2 is a diagram illustrating a configuration example of a converter cell. [Diagram 3] FIG. 2 is a diagram showing an example of a path of a short-circuit current. [Figure 4] FIG. 11 is a diagram showing another example of a path of a short-circuit current. [Diagram 5] FIG. 1 is a diagram showing an example of a path of a short-circuit current that may occur when a bypass element is closed; [Figure 6] 11 is a diagram showing another example of a path of a short-circuit current that may occur when a bypass element is closed; FIG. [Figure 7] FIG. 1 is a diagram for explaining an example of a method for detecting a short-circuit current. [Figure 8] FIG. 11 is a diagram for explaining another example of a method for detecting a short-circuit current. [Figure 9] FIG. 11 is a diagram for explaining still another example of a method for detecting a short-circuit current. [Figure 10] 10 is a flowchart illustrating an example of a processing procedure of a gate control unit. [Figure 11] 13 is a flowchart showing another example of the processing procedure of the gate control unit. [Figure 12] 13 is a flowchart illustrating an example of a processing procedure of a cell control unit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, the present embodiment will be described with reference to the drawings. In the following description, the same components are denoted by the same reference numerals. Their names and functions are also the same. Therefore, detailed description thereof will not be repeated.

[0012] <Configuration of power conversion device> FIG. 1 is a schematic diagram of a power converter. Referring to FIG. 1, the power converter 100 includes a power converter 110 including a plurality of converter cells 10 connected in series with each other, and a control device 120 for controlling the power converter 110. The "converter cell" is also called a "sub-module" or a "unit converter". The power converter 110 is configured by a modular multilevel converter. Typically, the power converter 110 performs power conversion between a DC circuit 130 and an AC circuit 150.

[0013] The power converter 110 includes a plurality of leg circuits 40u, 40v, 40w (hereinafter collectively referred to as "leg circuits 40") connected in parallel with each other between a positive DC terminal (i.e., a high potential side DC terminal) Np and a negative DC terminal (i.e., a low potential side DC terminal) Nn.

[0014] The leg circuit 40 is provided for each of the multiple phases constituting the AC. The leg circuit 40 is connected between the DC circuit 130 and the AC circuit 150, and performs power conversion between the two circuits. FIG. 1 shows a case where the AC circuit 150 is a three-phase AC system, and three leg circuits 40u, 40v, and 40w are provided corresponding to the U phase, V phase, and W phase, respectively. AC terminals Nu, Nv, and Nw provided in the leg circuits 40u, 40v, and 40w, respectively, are connected to the AC circuit 150 via a transformer 140. The AC circuit 150 is, for example, an AC power system including an AC power source or the like.

[0015] A positive DC terminal Np and a negative DC terminal Nn commonly connected to each leg circuit 40 are connected to a DC circuit 130. The DC circuit 130 is, for example, a DC terminal of a DC power system including a DC transmission network or other power conversion device.

[0016] The leg circuit 40u includes a positive arm from the positive DC terminal Np to the AC terminal Nu, and a negative arm from the negative DC terminal Nn to the AC terminal Nu. The AC terminal Nu, which is a connection point between the positive arm and the negative arm, is connected to the transformer 140. The leg circuits 40v and 40w have a similar configuration.

[0017] The positive arm includes a plurality of cascaded converter cells 10 and a reactor 14P. The plurality of converter cells 10 and the reactor 14P are connected in series to each other. The negative arm includes a plurality of cascaded converter cells 10 and a reactor 14N. The plurality of converter cells 10 and the reactor 14N are connected in series to each other.

[0018] The reactor 14P may be inserted at any position in the positive arm, and the reactor 14N may be inserted at any position in the negative arm. There may be a plurality of reactors 14P and 14N. The reactor 14P and the reactor 14N may be magnetically coupled to form one reactor. Only the reactor 14P or only the reactor 14N may be provided. Note that instead of providing a reactor, a configuration may be used in which a parasitic inductance such as a wiring inductance serves as a substitute for the reactor.

[0019] The control device 120 controls the power converter 110 based on detection signals detected by various electric quantity detectors (not shown) (for example, an AC voltage detector, an AC current detector, a DC voltage detector, an arm current detector, etc.). The control device 120 may be configured by a dedicated circuit, or may be configured in whole or in part by a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a microprocessor, etc.

[0020] <Converter cell configuration> Fig. 2 is a diagram showing a configuration example of a converter cell. Referring to Fig. 2, the converter cell 10 includes a cell control unit 15, gate control units 91 to 94, a switching circuit 21 and a switching circuit 22 connected in series, a bypass element 25, a high-potential side input / output terminal Po, and a low-potential side input / output terminal No.

[0021] The switching circuits 21 and 22 are configured as half-bridge circuits. Specifically, the switching circuit 21 includes a semiconductor element 31, a semiconductor element 32, and a capacitor EP as an energy storage element.

[0022] The semiconductor element 31 includes a switching element 31s and a diode 31d. The diode 31d is connected in anti-parallel to the switching element 31s (i.e., in parallel and in a reverse bias direction). The semiconductor element 32 includes a switching element 32s and a diode 32d. The diode 32d is connected in anti-parallel to the switching element 32s. The switching element 31s may be configured to include the diode 31d.

[0023] The switching circuit 22 includes a semiconductor element 33, a semiconductor element 34, and a capacitor EN as an energy storage element. The semiconductor element 33 includes a switching element 33s and a diode 33d. The diode 33d is connected in anti-parallel to the switching element 33s. The semiconductor element 34 includes a switching element 34s and a diode 34d. The diode 34d is connected in anti-parallel to the switching element 34s.

[0024] The switching elements 31s, 32s, 33s, and 34s are configured by switching elements such as IGBTs (Insulated Gate Bipolar Transistors), GCTs (Gate Commutated Turn-off thyristors), and MOSFETs (Metal Oxide Semiconductor Field-Effect Transistors).

[0025] Capacitor EP is connected in parallel to a series circuit including semiconductor element 31 and semiconductor element 32, and holds a DC voltage. An input / output terminal Po is connected to the connection point between the negative terminal of semiconductor element 31 and the positive terminal of semiconductor element 32. The positive terminal of capacitor EP is connected to the positive terminal of semiconductor element 31, and the negative terminal of capacitor EP is connected to the negative terminal of semiconductor element 32.

[0026] Capacitor EN is connected in parallel to a series circuit including semiconductor element 33 and semiconductor element 34. I / O terminal No is connected to the connection point between the negative terminal of semiconductor element 33 and the positive terminal of semiconductor element 34. The positive terminal of capacitor EN is connected to the positive terminal of semiconductor element 33, and the negative terminal of capacitor EN is connected to the negative terminal of semiconductor element 34.

[0027] The bypass element 25 is connected between the input / output terminal Po and the input / output terminal No. The converter cell 10 is bypassed by closing (i.e., turning on) the bypass element 25. For example, when an element (e.g., semiconductor elements 31 to 34, etc.) of the converter cell 10 fails, the bypass element 25 is used to bypass the converter cell 10. As a result, even if any one of the multiple converter cells 10 fails, the other converter cells 10 can be used to continue operating the power converter 110.

[0028] Gate control units 91 to 94 are provided corresponding to semiconductor elements 31 to 34, respectively. Therefore, the targets to be driven by gate control units 91 to 94 are semiconductor elements 31 to 34, respectively.

[0029] The gate control unit 91 includes a gate drive circuit for driving the semiconductor element 31, and a detection circuit for detecting an abnormal current (i.e., an overcurrent) flowing through the semiconductor element 31. The gate control unit 91 is connected to the semiconductor element 31 via control lines 91a and 91b. Specifically, the gate control unit 91 drives and controls the semiconductor element 31 via the control line 91a, and receives a detection signal of a current flowing through the semiconductor element 31 via the control line 91b.

[0030] Similarly, the gate control unit 92 drives and controls the semiconductor element 32 via a control line 92a, and receives a detection signal of a current flowing through the semiconductor element 32 via a control line 92b. The gate control unit 93 drives and controls the semiconductor element 33 via a control line 93a, and receives a detection signal of a current flowing through the semiconductor element 33 via a control line 93b. The gate control unit 94 drives and controls the semiconductor element 34 via a control line 94a, and receives a detection signal of a current flowing through the semiconductor element 34 via a control line 94b.

[0031] The cell control unit 15 controls the operation of the gate control units 91-94. During normal operation (for example, power conversion operation when no abnormality occurs in the semiconductor elements 31-34 included in the switching circuits 21, 22), the cell control unit 15 transmits a signal to the gate control units 91-94 to control the switching elements 31s-34s to an ON or OFF state. The gate control units 91-94 output a voltage pulse to turn the switching elements 31s-34s to an ON or OFF state in accordance with the signal. By controlling the switching elements 31s-34s to an ON or OFF state, zero voltage or a positive voltage is output between the input / output terminals Po and No. The operation of the cell control unit 15 and the gate control units 91-94 when an abnormality occurs in the semiconductor elements 31-34 will be described later.

[0032] The cell control unit 15 and the gate control units 91 to 94 are realized by processing circuits. For example, the processing circuits are configured by FPGAs, ASICs, or a combination of these.

[0033] 2, the two switching circuits 21 and 22 are connected in series, which reduces the voltage applied to each of the switching circuits 21 and 22. Therefore, such a configuration of the converter cell 10 is particularly useful when the voltage applied to the converter cell 10 becomes high due to the miniaturization and high density of the MMC.

[0034] <Operation when switching circuit is abnormal> When the cell control unit 15 detects an abnormality in any of the converter cells 10 (e.g., a failure in a semiconductor element, an abnormality in a control power supply used in a gate drive circuit of the semiconductor element, an abnormal current flowing through a semiconductor element, etc.), it transmits information indicating the abnormality of the converter cell 10 to the control device 120, which is higher than the cell control unit 15. The control device 120 determines whether the abnormality of the converter cell 10 is valid. When the control device 120 determines that the converter cell 10 is abnormal (i.e., the abnormality of the converter cell 10 is valid), it transmits an instruction to the cell control unit 15 to close the bypass element 25 of the converter cell 10. The cell control unit 15 closes the bypass element 25 in accordance with the instruction. This causes the converter cell 10 to be bypassed.

[0035] If the number of converter cells 10 is designed to be redundant so that an operation equivalent to a steady-state operation is performed, even if any of the converter cells 10 becomes abnormal, the power converter 110 can continue to perform the power conversion operation by bypassing the abnormal converter cell 10. However, the following problems may occur.

[0036] Fig. 3 is a diagram showing an example of a path of a short-circuit current. With reference to Fig. 3, it is assumed that a failure or control abnormality occurs in semiconductor element 31 constituting the upper arm of switching circuit 21, causing semiconductor element 31 to enter a short-circuit state. If semiconductor element 32 is turned on while semiconductor element 31 is in a short-circuit state, semiconductor elements 31 and 32 enter a short-circuit state, the energy charge stored in capacitor EP is discharged, and a short-circuit current (i.e., an overcurrent) flows through path R1 of capacitor EP, semiconductor element 31, and semiconductor element 32.

[0037] In addition, when a failure or control abnormality occurs in the semiconductor element 32 constituting the lower arm of the switching circuit 21 causing the semiconductor element 32 to enter a short-circuit state and the semiconductor element 31 is turned on, a short-circuit current also flows through the path R1.

[0038] Fig. 4 is a diagram showing another example of the path of the short-circuit current. With reference to Fig. 4, it is assumed that a failure or control abnormality occurs in semiconductor element 33 constituting the upper arm of switching circuit 22, causing semiconductor element 33 to enter a short-circuit state. If semiconductor element 34 is turned on while semiconductor element 33 is in a short-circuit state, semiconductor elements 33 and 34 enter a short-circuit state, the energy charge stored in capacitor EN is discharged, and a short-circuit current (i.e., an overcurrent) flows through path R2 of capacitor EN, semiconductor element 33, and semiconductor element 34.

[0039] In addition, when a failure or control abnormality occurs in the semiconductor element 34 constituting the lower arm of the switching circuit 22, causing the semiconductor element 34 to enter a short-circuit state and the semiconductor element 33 to turn on, a short-circuit current also flows through the path R2. Hereinafter, the short circuit shown in the paths R1 and R2 is also referred to as a "local short circuit."

[0040] If the short-circuit current cannot be immediately shut off, the power modules, connection bus bars, peripheral electronic components, etc., which form the semiconductor elements 31-34, may fly apart, or radiation noise and conduction noise may occur when these explode. In this case, the cell control unit 15, the gate control units 91-94, and the bypass element 25 may fail or malfunction. As a result, if the converter cell 10 cannot be normally bypassed, the power converter 110 may not be able to continuously perform power conversion operations. Therefore, when a short-circuit current occurs, it is necessary to immediately detect the short-circuit current and shut off the semiconductor elements 31-34 (i.e., control them to the off state). The state in which the semiconductor elements 31-34 are controlled (fixed) to the off state is also called a gate block state.

[0041] Hereinafter, a control procedure for controlling the semiconductor elements 31 to 34 (specifically, the switching elements 31s to 34s) to be in the OFF state when a local short circuit occurs will be described. As an example, a case where an abnormality occurs in the semiconductor element 31 will be described.

[0042] Assume that the gate control unit 91 detects an abnormality related to a short circuit failure of the semiconductor element 31 (hereinafter, also referred to as a "short circuit related abnormality"). One example of a short circuit related abnormality is an abnormality in which the resistance value between the collector and emitter (between the drain and source in the case of a MOSFET) drops due to deterioration or an accidental failure of the semiconductor element 31, making it impossible to hold the capacitor EP voltage. Another example is an operational abnormality in the gate drive circuit included in the gate control unit 91. This is an abnormality in which an ON signal is input to the semiconductor element 31 at a timing when an OFF signal should be input to the semiconductor element 31, causing the semiconductor element 31 to unintentionally turn ON. When such an abnormality occurs, the resistance value between the collector and emitter (between the drain and source in the case of a MOSFET) of the semiconductor element 31 drops unintentionally.

[0043] When a short-circuit related abnormality occurs in semiconductor element 31 and semiconductor element 32, which is in a healthy state, is turned on by gate control unit 92, as shown in FIG. 3, the energy charged in capacitor EP is discharged, causing a short-circuit current to flow through path R1, resulting in a local short circuit.

[0044] At this time, the voltage of capacitor EP is divided by semiconductor element 31 and semiconductor element 32. That is, when a divided high voltage is applied to semiconductor element 31 (or semiconductor element 32), a short-circuit current flows, causing energy to concentrate in semiconductor element 31 (or semiconductor element 32), which may result in destruction of at least one of semiconductor element 31 and semiconductor element 32. Hereinafter, this destruction mode is also referred to as "local short-circuit destruction."

[0045] In order to prevent such local short-circuit destruction, the gate control unit 91 receives information for detecting short-circuit current (e.g., a current detection signal) from the control line 91b, and if it determines that the semiconductor element 31 is abnormal (i.e., a short-circuit current is flowing through the semiconductor element 31), it immediately controls the semiconductor element 31 (specifically, the switching element 31s) to the off state by its own judgment, regardless of the signal received from the cell control unit 15.

[0046] Furthermore, when gate control unit 91 detects an abnormality in semiconductor element 31, it transmits abnormality detection information to cell control unit 15 along with the above control to turn semiconductor element 31 off. When cell control unit 15 receives the abnormality detection information, it transmits an OFF control signal to gate control units 91-94 for controlling semiconductor elements 31-34 to the OFF state. When gate control units 91-94 receive the OFF control signal from cell control unit 15, they control semiconductor elements 31-34 to the OFF state.

[0047] Here, the reason why the cell control unit 15 transmits an OFF control signal to the gate control units 91 to 94 when it receives abnormality detection information indicating an abnormality in the semiconductor element 31 from the gate control unit 91 will be described.

[0048] First, the gate control unit 91 is configured to control the semiconductor element 31 to the off state at its own discretion if an abnormality is detected in the semiconductor element 31, but in preparation for any unforeseen circumstances, the cell control unit 15 sends an off control signal to the gate control unit 91.

[0049] Furthermore, if the gate control unit 91 has a malfunction, there is a possibility that the gate control unit 91 cannot control the semiconductor element 31 to the OFF state even if it detects an abnormality. Therefore, assuming that the gate control unit 91 has a malfunction, the cell control unit 15 transmits an OFF control signal to the gate control unit 92. The gate control unit 92 controls the semiconductor element 32 (specifically, the switching element 32s) to the OFF state in accordance with the received OFF control signal.

[0050] Furthermore, if a local short circuit occurs in the switching circuit 21, the switching circuit 22 may malfunction due to the influence of the local short circuit, causing a local short circuit in the path R2. As a result, if the bypass element 25 does not operate normally and the converter cell 10 cannot be bypassed, the power converter 110 will not be able to continuously perform the power conversion operation. Therefore, the cell control unit 15 transmits an OFF control signal to the gate control units 93 and 94. The gate control units 93 and 94 control the semiconductor elements 33 and 34 (specifically, the switching elements 33s and 34s) of the switching circuit 22 to the OFF state in accordance with the received OFF control signal.

[0051] When a local short circuit occurs in the switching circuit 21, a short circuit current flows through the semiconductor element 31 and the semiconductor element 32. In this case, the gate control unit 91 performs an abnormality determination for the current flowing through the semiconductor element 31 using the current detection signal received via the control line 91b, and the gate control unit 92 performs an abnormality determination for the current flowing through the semiconductor element 32 using the current detection signal received via the control line 91b.

[0052] Here, the same current flows through semiconductor element 31 and semiconductor element 32, but strictly speaking there is a difference between the current detection signal received by gate control unit 91 and the current detection signal received by gate control unit 92. Therefore, a time difference occurs between timing T1 at which gate control unit 91 determines that semiconductor element 31 is abnormal and timing T2 at which gate control unit 92 determines that semiconductor element 32 is abnormal.

[0053] For example, if timing T1 is earlier than timing T2, gate control unit 91 determines that semiconductor element 31 is abnormal first, controls semiconductor element 31 to the OFF state, and transmits abnormality detection information to cell control unit 15. Then, while an OFF control signal is being transmitted from cell control unit 15 to gate control unit 92, gate control unit 92 determines that semiconductor element 32 is abnormal. In this case, gate control unit 92 controls semiconductor element 32 to the OFF state at the earlier of the timing of receiving the OFF control signal from cell control unit 15 or the timing of its own determination.

[0054] Although the above describes a representative case where gate control unit 91 detects an abnormality in semiconductor element 31, similar control is also executed when gate control unit 92 detects an abnormality in semiconductor element 32. For example, when gate control unit 92 detects a short-circuit current flowing through semiconductor element 32, it controls semiconductor element 32 to the OFF state at its own discretion and transmits abnormality detection information to cell control unit 15. When cell control unit 15 receives the abnormality detection information, it transmits an OFF control signal to gate control units 91-94.

[0055] Similar control is also executed when gate control units 93, 94 detect abnormalities in semiconductor elements 33, 34, respectively. For example, when gate control unit 93 detects a short-circuit current flowing through semiconductor element 33, it controls semiconductor element 33 to the OFF state at its own discretion and transmits abnormality detection information to cell control unit 15. When gate control unit 94 detects a short-circuit current flowing through semiconductor element 34, it controls semiconductor element 34 to the OFF state at its own discretion and transmits abnormality detection information to cell control unit 15. When cell control unit 15 receives abnormality detection information, it transmits an OFF control signal to gate control units 91-94.

[0056] Furthermore, each of the gate control units 91-94 controls the semiconductor element to be driven to the OFF state at the earlier of the timing of receiving the OFF control signal and the timing of its own judgment. Specifically, when each of the gate control units 91-94 detects a short-circuit current flowing through the semiconductor element to be driven before receiving the OFF control signal (i.e., before the timing of receiving the OFF control signal), it controls the semiconductor element to be driven to the OFF state at its own judgment. On the other hand, when each of the gate control units 91-94 receives an OFF control signal before detecting a short-circuit current flowing through the semiconductor element to be driven (i.e., before the timing of its own detection of the short-circuit current), it controls the semiconductor element to be driven to the OFF state based on the reception of the OFF control signal.

[0057] For this reason, when one of gate control units 91-94 (for convenience, also referred to as "gate control unit X") detects a short-circuit current flowing through a semiconductor element that is the driving target of gate control unit X among semiconductor elements 31-34, it controls the driving target semiconductor element to the OFF state and transmits abnormality detection information to cell control unit 15. When cell control unit 15 receives the abnormality detection information, it transmits a control signal to each of gate control units 91-94 for controlling the driving target semiconductor element of that gate control unit to the OFF state.

[0058] Furthermore, when each of the gate control units 91 to 94 receives an OFF control signal, if the semiconductor element to be driven by the gate control unit is not controlled to the OFF state, the gate control unit controls the semiconductor element to be driven to the OFF state.

[0059] By the above control procedure, the short-circuit current flowing through paths R1 and R2 can be cut off as quickly as possible.

[0060] <Operation when bypass element is turned on incorrectly> In the above, a configuration has been described in which, when a short-circuit related abnormality occurs in the semiconductor elements 31-34, the semiconductor elements 31-34 are controlled to the off state based on the self-judgment of the gate control units 91-94 or the off control signal from the cell control unit 15. Here, a configuration will be described in which the semiconductor elements 31-34 are prevented from being damaged when the bypass element 25 is erroneously turned on (i.e., closed) while the semiconductor elements 31-34 are in a normal state.

[0061] Fig. 5 is a diagram showing an example of a path of a short-circuit current that may occur when the bypass element is closed. Referring to Fig. 5, if the semiconductor element 31 is controlled to be in the on state when the bypass element 25 malfunctions (i.e., is closed) due to the influence of noise or the like, the energy charged in the capacitor EP is discharged, and a short-circuit current (i.e., an overcurrent) flows through the path R3 passing through the capacitor EP, the semiconductor element 31, the bypass element 25, and the semiconductor element 33.

[0062] Fig. 6 is a diagram showing another example of a path of a short-circuit current that may occur when the bypass element is closed. Referring to Fig. 6, if the semiconductor element 34 is controlled to be in the on state when the bypass element 25 malfunctions due to the influence of noise or the like, the energy charged in the capacitor EN is discharged, and a short-circuit current flows through the path R4 passing through the capacitor EN, the semiconductor element 32, the bypass element 25, and the semiconductor element 34.

[0063] The bypass element 25 has a large inductance component. Therefore, the inductance components of paths R3 and R4 are large compared to the inductance components of paths R1 and R2 of the local short circuit described above. Therefore, the short circuit current is limited by the inductance component of the bypass element 25, and the current rise rate per unit time is low for the local short circuit. Hereinafter, a short circuit such as that shown by paths R3 and R4 is also referred to as a "bypass element short circuit."

[0064] When a bypass element short circuit occurs, a current of several tens of kA to several hundreds of kA flows through the bypass element 25, and the bypass element 25 may be mechanically damaged due to melting or the like. In this case, there is a possibility that the converter cell 10 may not be able to be bypassed normally.

[0065] When a bypass element short circuit occurs along the path R3 shown in Fig. 5, an overcurrent flows while the voltage of the capacitor EP is applied to the semiconductor element 31, which may cause energy destruction of the semiconductor element 31. In this case, the power module, connection bus bar, peripheral electronic components, etc. that form the semiconductor element 31 may fly apart, possibly causing damage to the cell control unit 15, the gate control units 91 to 94, and the bypass element 25. In addition, the semiconductor element 32 may also malfunction and turn on, causing a local short circuit along the path R1 shown in Fig. 3. Furthermore, the switching circuit 22 may also malfunction, causing a local short circuit along the path R2 shown in Fig. 4.

[0066] If the malfunctioning bypass element 25 cannot maintain a closed state due to these effects, the power converter 110 will not be able to continuously perform power conversion operations. In addition, since the converter cell 10 is in a healthy state to begin with, if the bypass element short circuit can be prevented, the converter cell 10 can be restored to a normal state by repairing the bypass element 25.

[0067] Hereinafter, a control procedure for controlling the semiconductor elements 31 to to be in the OFF state when a bypass element short circuit occurs will be described. As an example, a case where the gate control unit 91 detects a short circuit current will be described.

[0068] When the gate control unit 91 receives a current detection signal from the control line 91b and determines that the semiconductor element 31 is abnormal (i.e., a short-circuit current is flowing through the semiconductor element 31), it controls the semiconductor element 31 to the off state at its own discretion, regardless of the signal it receives from the cell control unit 15.

[0069] Furthermore, the gate control unit 91 controls the semiconductor element 31 to the OFF state and transmits abnormality detection information indicating an abnormality in the semiconductor element 31 to the cell control unit 15. When the cell control unit 15 receives the abnormality detection information, it transmits an OFF control signal to the gate control units 91-94 for controlling the semiconductor elements 31-34 to the OFF state. When the gate control units 91-94 receive the OFF control signal from the cell control unit 15, they control the semiconductor elements 31-34 to the OFF state.

[0070] Here, the reason why the cell control unit 15 transmits an OFF control signal to the gate control units 91 to 94 when it receives abnormality detection information from the gate control unit 91 will be described.

[0071] 5, even if the semiconductor element 33 (specifically, the switching element 33s) is turned off, the short-circuit current flows due to the diode 33d. Therefore, the cell control unit 15 transmits an OFF control signal to the gate control unit 91. The gate control unit 91 controls the semiconductor element 31 to the OFF state according to the received OFF control signal.

[0072] However, if the short-circuit current of path R3 is not successfully interrupted by controlling semiconductor element 31 to be off, semiconductor element 31 will fail. If semiconductor element 32 is controlled to be in the on state while semiconductor element 31 is in a failed state, a local short circuit of path R1 shown in Fig. 3 will occur. In order to prevent this local short circuit, semiconductor element 32 must also be controlled to be in the off state, so cell control unit 15 transmits an off control signal to gate control unit 92.

[0073] Furthermore, if a bypass element short circuit occurs along path R3 due to the semiconductor element 31 being turned on when the bypass element 25 is closed, then when the semiconductor element 34 is turned on by normal control, a bypass element short circuit occurs along path R4 shown in FIG. 6. If a short-circuit current flows along path R4, the short-circuit current cannot be interrupted even if the semiconductor element 32 (specifically, the switching element 32s) is turned off, and therefore the semiconductor element 34 must be turned off. Therefore, the cell control unit 15 transmits an off control signal to the gate control unit 94. The gate control unit 94 controls the semiconductor element 34 to the off state according to the received off control signal.

[0074] However, if the short-circuit current of path R4 is not successfully interrupted by controlling the semiconductor element 34 to be off, the semiconductor element 34 will fail. If the semiconductor element 33 is turned on in a state in which the semiconductor element 34 has failed, a local short circuit of path R2 shown in Fig. 4 will occur. In order to prevent this local short circuit, the semiconductor element 33 must also be controlled to be in the off state, so the cell control unit 15 sends an off control signal to the gate control unit 93.

[0075] Furthermore, if a bypass element short circuit occurs along path R3, a short-circuit current flows through the semiconductor element 31 and the semiconductor element 33. In this case, the gate control unit 91 performs an abnormality determination for the current flowing through the semiconductor element 31 using the current detection signal received via control line 91b, and the gate control unit 93 performs an abnormality determination for the current flowing through the semiconductor element 33 using the current detection signal received via control line 93b.

[0076] Although the same current flows through semiconductor element 31 and semiconductor element 33, strictly speaking, there is a difference between the current detection signal received by gate control unit 91 and the current detection signal received by gate control unit 93. Therefore, a time difference occurs between timing T3 at which gate control unit 91 determines that semiconductor element 31 is abnormal and timing T4 at which gate control unit 93 determines that semiconductor element 33 is abnormal.

[0077] For example, if timing T3 is earlier than timing T4, gate control unit 91 first controls semiconductor element 31 to be turned off and transmits abnormality detection information to cell control unit 15. Then, while an OFF control signal is being transmitted from cell control unit 15 to gate control unit 93, gate control unit 93 determines that semiconductor element 33 is abnormal. In this case, gate control unit 93 controls semiconductor element 33 to the OFF state at the earlier of the timing of receiving the OFF control signal from cell control unit 15 and the timing of its own determination.

[0078] Although the above describes a typical case where gate control unit 91 detects a short-circuit current flowing through semiconductor element 31, similar control is also executed when gate control unit 92 detects a short-circuit current flowing through semiconductor element 32. For example, when gate control unit 92 detects a short-circuit current flowing through semiconductor element 32, it controls semiconductor element 32 to the OFF state at its own discretion and transmits abnormality detection information to cell control unit 15. When cell control unit 15 receives the abnormality detection information, it transmits an OFF control signal to gate control units 91-94.

[0079] Similar control is also executed when gate control units 93, 94 detect short-circuit currents flowing through semiconductor elements 33, 34, respectively. For example, when gate control unit 93 detects a short-circuit current flowing through semiconductor element 33, it controls semiconductor element 33 to the OFF state at its own discretion and transmits abnormality detection information to cell control unit 15. When gate control unit 94 detects a short-circuit current flowing through semiconductor element 34, it controls semiconductor element 34 to the OFF state at its own discretion and transmits abnormality detection information to cell control unit 15. When cell control unit 15 receives abnormality detection information, it transmits OFF control signals to gate control units 91-94.

[0080] By the above control procedure, the short-circuit current flowing through paths R3 and R4 can be cut off as quickly as possible.

[0081] In this way, the short-circuit current path when the bypass element is short-circuited is different from the short-circuit current path when a local short circuit occurs, but it is understood that the operation of each gate control unit 91-94 when it detects a short-circuit current flowing through the semiconductor element to be driven when the bypass element is short-circuited is similar to the corresponding operation of each gate control unit 91-94 when a local short circuit occurs.

[0082] <Short circuit current detection method> Fig. 7 is a diagram for explaining an example of a method for detecting a short-circuit current. With reference to Fig. 7, current sensors 51-63 are provided in converter cell 10. Current sensor 51 is provided between capacitor EP and semiconductor element 31, and current sensor 52 is provided between semiconductor element 31 and the connection point of semiconductor elements 31, 32. Current sensor 53 is provided between semiconductor element 32 and the connection point of semiconductor elements 31, 32, and current sensor 54 is provided between semiconductor element 32 and the connection point of semiconductor elements 32, 33.

[0083] Current sensor 55 is provided between the connection point of semiconductor elements 32, 33 and semiconductor element 33, and current sensor 56 is provided between semiconductor element 33 and the connection point of semiconductor elements 33, 34. Current sensor 57 is provided between the connection point of semiconductor elements 33, 34 and semiconductor element 34, and current sensor 58 is provided between capacitor EN and semiconductor element 34.

[0084] Current sensor 59 is provided between the connection point of capacitors EP and EN and the connection point of semiconductor elements 32, 33. Current sensor 60 is provided between the connection point of semiconductor elements 31, 32 and input / output terminal Po. Current sensor 61 is provided between input / output terminal Po and bypass element 25, and current sensor 62 is provided between input / output terminal No and bypass element 25. Current sensor 63 is provided between the connection point of semiconductor elements 33, 34 and input / output terminal No.

[0085] The gate control units 91 to 94 receive current detection signals from at least one of the current sensors 51 to 63 via the control lines 91b to 94b, respectively. The gate control units 91 to 94 detect the short-circuit current flowing through the semiconductor elements 31 to 34 based on at least one current detection signal.

[0086] For example, the gate control unit 91 detects the short-circuit current flowing through the semiconductor element 31 based on the current detection signal of the current sensor 51 or the current sensor 52. For example, when the current indicated by the current detection signal of the current sensor 51 is equal to or greater than the threshold value, the gate control unit 91 determines that a short-circuit current is flowing through the semiconductor element 31. The gate control unit 92 detects the short-circuit current flowing through the semiconductor element 32 based on the current detection signal of the current sensor 53 or the current sensor 54. The gate control unit 93 detects the short-circuit current flowing through the semiconductor element 33 based on the current detection signal of the current sensor 55 or the current sensor 56. The gate control unit 94 detects the short-circuit current flowing through the semiconductor element 34 based on the current detection signal of the current sensor 57 or the current sensor 58. Note that each of the gate control units 91 to 94 may detect the current flowing through the semiconductor element to be driven using the current detection signals of other current sensors.

[0087] Note that the converter cell 10 may have a configuration including the current sensors necessary for each of the gate control units 91 to 94 to detect the short-circuit current flowing through the semiconductor element to be driven. Therefore, the converter cell 10 does not necessarily have a configuration including all of the current sensors 51 to 63 as shown in FIG. 7.

[0088] FIG. 8 is a diagram for explaining another example of the short-circuit current detection method. Referring to FIG. 8, the converter cell 10 includes, for a target semiconductor element 81 (for example, the semiconductor element 31), a gate drive circuit 80 (for example, the gate drive circuit included in the gate control unit 91), a detection unit 82 that detects a short-circuit current (for example, the detection circuit of the gate control unit 91), and a cutoff unit 83 that performs a cutoff operation when a short-circuit current is detected.

[0089] When an on signal is input to semiconductor element 81, detection unit 82 determines whether the collector potential is equal to or higher than a specified potential. When a short-circuit current is flowing, the voltage of capacitor EP is applied to both ends of semiconductor element 81, causing the voltage in the on state to rise. On the other hand, when no short-circuit current is flowing, the voltage drop of semiconductor element 81 is several volts. Detection unit 82 determines whether or not a short-circuit current is flowing by comparing the detected collector potential using a comparator.

[0090] The cutoff unit 83 receives a signal from the detection unit 82 and performs a cutoff operation on the semiconductor element 81. The cutoff unit 83 may employ a "soft cutoff" that cuts off through a resistance larger than that during cutoff in normal operation.

[0091] 9 is a diagram for explaining yet another example of a method for detecting a short-circuit current. Referring to FIG. 9, the gate control unit detects a short-circuit current by utilizing parasitic inductances 71 to 76 of wiring of the converter cell 10.

[0092] Assume that a local short circuit occurs and a short circuit current shown in a path R1 (see FIG. 3) flows. In this case, a voltage is generated in a parasitic inductance 71 on the emitter side of the semiconductor element 31 and a parasitic inductance 72 on the emitter side of the semiconductor element 32 due to a self-induced electromotive force generated in the path R1 based on a time change in the short circuit current. Typically, the gate control unit 91 detects the short circuit current flowing in the semiconductor element 31 based on the voltage of the parasitic inductance 71 on the emitter side of the semiconductor element 31 to be driven. Specifically, the gate control unit 91 determines that the short circuit current has occurred when the voltage of the parasitic inductance 71 is equal to or higher than a threshold value. Similarly, the gate control unit 92 determines that a short circuit current is flowing in the semiconductor element 32 when the voltage of the parasitic inductance 72 is equal to or higher than a threshold value.

[0093] The cell control unit 15 may receive a detection result from the gate control units 91 and 92 that a short-circuit current has occurred in the semiconductor elements 31 and 32, and may determine that a short-circuit current indicated by the path R1 has occurred based on the detection result.

[0094] Assume that a local short circuit occurs and a short circuit current shown in path R2 (see FIG. 4) flows. In this case, a self-induced electromotive force is generated in path R2 based on the time change of the short circuit current, and a voltage is generated in parasitic inductance 73 on the emitter side of semiconductor element 33 and in parasitic inductance 74 on the emitter side of semiconductor element 34. Typically, gate control unit 93 determines that a short circuit current flows in semiconductor element 33 when the voltage of parasitic inductance 73 is equal to or higher than a threshold value. Furthermore, gate control unit 94 determines that a short circuit current flows in semiconductor element 34 when the voltage of parasitic inductance 74 is equal to or higher than a threshold value.

[0095] The cell control unit 15 may receive a detection result from the gate control units 93 and 94 that a short-circuit current has occurred in the semiconductor elements 33 and 34, and may determine that a short-circuit current indicated by the path R2 has occurred based on the detection result.

[0096] To detect a local short circuit along path R1, it is sufficient to detect the voltage of at least one of the parasitic inductances 71 and 72. To detect a local short circuit along path R2, it is sufficient to detect the voltage of at least one of the parasitic inductances 73 and 74.

[0097] Assume that a bypass element short circuit occurs and a short-circuit current shown in the path R3 (see FIG. 5) flows. In this case, a voltage is generated in the parasitic inductance 71, the parasitic inductance 75, or the combined inductance of the parasitic inductances 71 and 75 due to a self-induced electromotive force generated in the path R3 based on the time change of the short-circuit current. Also, a voltage is generated in the parasitic inductance 76, the parasitic inductance 73, or the combined inductance of the parasitic inductances 76 and 73. For example, the gate control unit 91 determines that a short-circuit current is flowing in the semiconductor element 31 when the voltage of the combined inductance of the parasitic inductances 71 and 75 is equal to or higher than a threshold value. For example, the gate control unit 93 determines that a short-circuit current is flowing in the semiconductor element 33 when the voltage of the combined inductance of the parasitic inductances 76 and 73 is equal to or higher than a threshold value.

[0098] The cell control unit 15 may receive a detection result from the gate control units 91 and 93 that a short-circuit current has occurred in the semiconductor elements 31 and 33, and may determine that a short-circuit current has occurred along the path R3 based on the detection result.

[0099] Assume that a bypass element short circuit occurs and a short-circuit current shown in the path R4 (see FIG. 6) flows. In this case, a voltage is generated in the parasitic inductance 72, the parasitic inductance 75, or the combined inductance of the parasitic inductances 72 and 75 due to a self-induced electromotive force generated in the path R4 based on the time change of the short-circuit current. Also, a voltage is generated in the parasitic inductance 76, the parasitic inductance 74, or the combined inductance of the parasitic inductances 76 and 74. For example, the gate control unit 92 determines that a short-circuit current is flowing in the semiconductor element 32 when the voltage of the combined inductance of the parasitic inductances 72 and 75 is equal to or higher than a threshold value. For example, the gate control unit 94 determines that a short-circuit current is flowing in the semiconductor element 34 when the voltage of the combined inductance of the parasitic inductances 76 and 74 is equal to or higher than a threshold value.

[0100] The cell control unit 15 may receive a detection result from the gate control units 92 and 94 that a short-circuit current has occurred in the semiconductor elements 32 and 34, and may determine that a short-circuit current indicated by the path R4 has occurred based on the detection result.

[0101] When detecting the short-circuit current flowing through the bypass element 25 using the detection method using the collector potential described in Fig. 8, the rise of the collector potential is slow, so that it may be difficult to detect the short-circuit current itself, or the detection may take time. In this respect, the detection method in Fig. 9 is more useful than the detection method in Fig. 8.

[0102] <Flowchart> As described above, the gate controllers 91-94 execute the same process when detecting a short circuit current, regardless of whether the short circuit is a local short circuit or a bypass element short circuit. Here, the process procedure of any one of the gate controllers 91-94 and the process procedure of the cell controller 15 will be described.

[0103] Fig. 10 is a flowchart showing an example of a processing procedure of the gate control unit. Referring to Fig. 10, the gate control unit (for example, the gate control unit 91) judges whether or not a short-circuit current flowing through a semiconductor element to be driven (for example, the semiconductor element 31 to be driven by the gate control unit 91) is detected based on a current detection signal received via a corresponding control line (step S10). If a short-circuit current is not detected (NO in step S10), the gate control unit executes step S10 again. On the other hand, if a short-circuit current is detected (YES in step S10), the gate control unit judges whether or not the semiconductor element to be driven (hereinafter also simply referred to as the "target semiconductor element") is already controlled to the off state based on an off control signal received from the cell control unit 15 (step S12).

[0104] If the target semiconductor element is controlled to the OFF state (YES in step S12), the gate control unit ends the process. If the target semiconductor element is not controlled to the OFF state (NO in step S12), the gate control unit controls the target semiconductor element to the OFF state by its own judgment (step S14). Then, the gate control unit transmits abnormality detection information to the cell control unit 15 (step S16).

[0105] Fig. 11 is a flowchart showing another example of the processing procedure of the gate control unit. Referring to Fig. 11, the gate control unit judges whether or not an OFF control signal has been received from the cell control unit 15 (step S30). If an OFF control signal has not been received (NO in step S30), the gate control unit executes step S30 again. On the other hand, if an OFF control signal has been received (YES in step S30), the gate control unit judges by itself whether or not the target semiconductor element has already been controlled to the OFF state (step S32).

[0106] If the target semiconductor element is controlled to the OFF state (YES in step S32), the gate control unit ends the process. If the target semiconductor element is not controlled to the OFF state (NO in step S32), the gate control unit controls the target semiconductor element to the OFF state based on the OFF control signal (step S34).

[0107] Each of the gate control units 91-94 executes in parallel the processes according to the flowcharts shown in Fig. 10 and Fig. 11. As a result, each of the gate control units 91-94 controls the target semiconductor element to be turned off at the earlier of the timing of detecting the short-circuit current flowing through the target semiconductor element and the timing of receiving the off control signal.

[0108] Fig. 12 is a flowchart showing an example of a processing procedure of the cell control unit. Referring to Fig. 12, the cell control unit 15 determines whether or not it has received abnormality detection information from any of the gate control units 91-94 (step S50). If it has not received abnormality detection information (NO in step S50), the cell control unit 15 executes the processing of step S50 again. If it has received abnormality detection information (YES in step S50), the cell control unit 15 transmits an OFF control signal to each of the gate control units 91-94 (step S52).

[0109] <Advantages> According to this embodiment, when a short-circuit-related abnormality occurs in any of the semiconductor elements 31 to 34, the short-circuit current due to the local short circuit along the paths R1 and R2 can be cut off as early as possible. Therefore, the normal semiconductor elements included in the converter cell 10 can be protected. Also, when the semiconductor elements 31 to 34 are in a normal state but the bypass element 25 is erroneously turned on, the short-circuit current due to the bypass element short circuit along the paths R3 and R4 can be cut off as early as possible. Therefore, the semiconductor elements included in the converter cell 10 can be protected. Therefore, in both cases when an abnormality occurs in the semiconductor element and when the bypass element is erroneously turned on, the bypass element 25 operates normally and the converter cell 10 can be normally bypassed. Therefore, the operation of the power conversion device 100 can be continued.

[0110] Other embodiments. (1) In the above-described embodiment, the gate control units 91 to 94 are configured to detect the short-circuit current flowing through the semiconductor elements 31 to 34 to be driven, respectively. However, in consideration of the paths R1 and R2 of the short-circuit current in the event of a local short circuit and the paths R3 and R4 of the short-circuit current in the event of a bypass element short circuit, it is not necessary for all of the gate control units 91 to 94 to detect the short-circuit current.

[0111] 3 and 5, both the path R1 and the path R3 include the semiconductor element 31. Therefore, when a local short circuit occurs in the path R1 or a bypass element short circuit occurs in the path R3, the semiconductor element 31 is controlled to an off state, so that the short circuit currents flowing in the paths R1 and R3 can be cut off.

[0112] For example, assume that a short-circuit current flows through path R1 or path R3. In this case, the gate control unit 91 detects the short-circuit current flowing through the semiconductor element 31 and controls the semiconductor element 31 to the OFF state by its own judgment. As a result, the short-circuit current flowing through path R1 or path R3 is cut off. Furthermore, the gate control unit 91 transmits abnormality detection information to the cell control unit 15. Based on receiving the abnormality detection information, the cell control unit 15 transmits an OFF control signal to the gate control units 91-94. As a result, the semiconductor elements 31-34 to be driven by each of the gate control units 91-94 are controlled to the OFF state, and as a result, the short-circuit current flowing through all of the paths R1-R4 is cut off.

[0113] 4 and 6, both of the paths R2 and R4 include the semiconductor element 34. Therefore, when a local short circuit occurs in the path R2 or a bypass element short circuit occurs in the path R4, the semiconductor element 34 is controlled to an off state, so that the short circuit currents flowing in the paths R2 and R4 can be cut off.

[0114] For example, assume that a short-circuit current flows through path R2 or path R4. In this case, the gate control unit 94 detects the short-circuit current flowing through the semiconductor element 34 and controls the semiconductor element 34 to the OFF state by its own judgment. As a result, the short-circuit current flowing through path R2 or path R4 is cut off. Furthermore, the gate control unit 94 transmits abnormality detection information to the cell control unit 15. Based on receiving the abnormality detection information, the cell control unit 15 transmits an OFF control signal to the gate control units 91-94. As a result, the semiconductor elements 31-34 to be driven by each of the gate control units 91-94 are controlled to the OFF state, and as a result, the short-circuit current flowing through all of the paths R1-R4 is cut off.

[0115] For this reason, the gate control unit 91 and the gate control unit 94 may be selected as gate control units having a detection circuit for detecting a short-circuit current. In this case, the gate control units 91 and 94 each have a function of controlling the semiconductor elements 31 and 34 to the OFF state by their own judgment, but the gate control units 92 and 93 do not have this function. Therefore, the gate control units 92 and 93 control the semiconductor elements 32 and 33 to the OFF state, respectively, based on an OFF control signal received from the cell control unit 15.

[0116] (2) The restart of the converter cell 10 after the semiconductor elements 31-34 are controlled to the off state according to the above-mentioned embodiment will be described. When a local short circuit or bypass element short circuit occurs and the semiconductor elements 31-34 are controlled to the off state (for example, gate blocked), the charges of the capacitors EP and EN continue to be held. However, strictly speaking, when the voltage Vep of the capacitor EP and the voltage Ven of the capacitor EN are applied to the semiconductor elements 31-34, a leakage current occurs in the semiconductor elements 31-34, and the capacitors EP and EN are naturally discharged. However, the discharge time depends on the level of the leakage current, and in the case of semiconductor elements with a low leakage current, the charges of the capacitors EP and EN may be held for several minutes to several hours.

[0117] When the on / off control of the semiconductor elements 31-34 is resumed while the capacitors EP and EN are charged, that is, while a voltage is being applied to the semiconductor elements 31-34 (for example, when the semiconductor elements 31-34 in the gate blocked state are put into the deblocked state (that is, the state in which the semiconductor elements 31-34 can be turned on and off)), a local short circuit or bypass element short circuit may occur again. In this case, the gate control units 91-94 can control each of the semiconductor elements 31-34 to the off state by detecting the short-circuit current. However, if the short-circuit current flows repeatedly through the switching circuits 21, 22, the semiconductor elements 31-34 and the bypass element 25 may wear out.

[0118] Therefore, when the voltages Vep and Ven become low, it is preferable to restart the converter cell 10 (i.e., to resume the on / off control of the semiconductor elements 31 to 34). The capacitor voltage at which restart is permitted is determined by the operator. Here, the capacitor voltage at which restart can be initiated is assumed to be "Vth."

[0119] The cell control unit 15 constantly monitors the voltages Vep and Ven, and maintains the semiconductor elements 31-34 in the off state until both the voltages Vep and Ven become less than the capacitor voltage Vth. When both the voltages Vep and Ven become less than the capacitor voltage Vth, the cell control unit 15 resumes the on / off control of the semiconductor elements 31-34 that have been maintained in the off state (i.e., the semiconductor elements 31-34 in the gate blocked state are put into the deblocked state). Specifically, the cell control unit 15 transmits a deblock command to each of the gate control units 91-94. When the gate control units 91-94 receive the deblock command, they each resume the on / off control of the semiconductor elements 31-34.

[0120] As a result, when the converter cell 10 is restarted with the capacitors EP and EN in a low voltage state and the semiconductor elements 31 to 34 are on / off controlled, even if a local short circuit or bypass element short circuit occurs again, the degree of wear can be reduced. Specifically, the short circuit current can be reduced, and the energy of the semiconductor elements when a short circuit occurs can be reduced.

[0121] (3) In the above-described embodiment, when an abnormality is detected in the semiconductor element of the converter cell 10, the cell control unit 15 closes the bypass element 25 in accordance with an instruction to close the bypass element 25 received from the control device 120. However, the present invention is not limited to this configuration.

[0122] For example, when the cell control unit 15 receives abnormality detection information from any of the gate control units 91-94, the cell control unit 15 may execute control to close the bypass element 25. In this case, the cell control unit 15 transmits an OFF control signal to each of the gate control units 91-94 during a period before the bypass element 25 is closed in response to the control. This controls the semiconductor elements 31-34 to be in the OFF state before the bypass element 25 is closed. Therefore, at the time when the bypass element 25 is actually closed, a short-circuit current that may flow through the path R3 or the path R4 is suppressed, and damage to the bypass element 25 can be prevented.

[0123] (4) The configurations exemplified as the above-mentioned embodiments are examples of the configurations of the present disclosure, and may be combined with other known technologies, or may be modified, such as by omitting some parts, without departing from the scope of the present disclosure. In addition, the above-mentioned embodiments may be implemented by appropriately adopting the processes and configurations described in other embodiments.

[0124] The embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. The scope of the present disclosure is defined by the claims, not the above description, and is intended to include all modifications within the meaning and scope of the claims. [Explanation of symbols]

[0125] 10 converter cell, 14N, 14P reactor, 15 cell control unit, 21, 22 switching circuit, 25 bypass element, 31-34, 81 semiconductor element, 31d-34d diode, 31s-34s switching element, 40u-40w leg circuit, 51-63 current sensor, 71-76 parasitic inductance, 80 gate drive circuit, 82 detection unit, 83 cutoff unit, 91-94 gate control unit, 100 power conversion device, 110 power converter, 120 control device, 130 DC circuit, 140 transformer, 150 AC circuit, EN, EP capacitor, Nn negative DC terminal, No, Po input / output terminal, Np positive DC terminal, Nu, Nv, Nw AC terminal, R1-R4 path.

Claims

1. A power conversion device including a plurality of converter cells connected in series, Each of the plurality of transducer cells comprises: A cell control unit; a first switching circuit and a second switching circuit connected in series; a first input / output terminal and a second input / output terminal; the first switching circuit includes a first semiconductor device, a second semiconductor device, and a first energy storage element connected in parallel to a series circuit including the first semiconductor device and the second semiconductor device; the first input / output terminal is connected to a connection point between a negative terminal of the first semiconductor element and a positive terminal of the second semiconductor element; the second switching circuit includes a third semiconductor device, a fourth semiconductor device, and a second energy storage element connected in parallel to a series circuit including the third semiconductor device and the fourth semiconductor device; the second input / output terminal is connected to a connection point between a negative terminal of the third semiconductor element and a positive terminal of the fourth semiconductor element; Each of the plurality of converter cells further includes a first gate control unit that drives the first semiconductor element, a second gate control unit that drives the second semiconductor element, a third gate control unit that drives the third semiconductor element, and a fourth gate control unit that drives the fourth semiconductor element; When one of the first to fourth gate control units detects a short circuit current flowing through a semiconductor element to be driven by the one of the first to fourth gate control units, the one of the first to fourth semiconductor elements controls the semiconductor element to be driven to an off state and transmits abnormality detection information to the cell control unit; When the cell control unit receives the abnormality detection information, the cell control unit transmits a control signal to each of the first to fourth gate control units to control a semiconductor element to be driven by the gate control unit to an off state; a power conversion device, wherein each of the remaining gate control units other than the first gate control unit among the first to fourth gate control units controls the semiconductor element to be driven to an off state at an earlier timing of a first timing at which a short-circuit current flowing through the semiconductor element to be driven by the gate control unit is detected and a second timing at which the control signal is received.

2. A power conversion device comprising a plurality of converter cells connected in series, Each of the plurality of transducer cells comprises: A cell control unit; a first switching circuit and a second switching circuit connected in series; a first input / output terminal and a second input / output terminal; the first switching circuit includes a first semiconductor device, a second semiconductor device, and a first energy storage element connected in parallel to a series circuit including the first semiconductor device and the second semiconductor device; the first input / output terminal is connected to a connection point between a negative terminal of the first semiconductor element and a positive terminal of the second semiconductor element; the second switching circuit includes a third semiconductor device, a fourth semiconductor device, and a second energy storage element connected in parallel to a series circuit including the third semiconductor device and the fourth semiconductor device; the second input / output terminal is connected to a connection point between a negative terminal of the third semiconductor element and a positive terminal of the fourth semiconductor element; Each of the plurality of converter cells further includes a first gate control unit that drives the first semiconductor element, a second gate control unit that drives the second semiconductor element, a third gate control unit that drives the third semiconductor element, and a fourth gate control unit that drives the fourth semiconductor element; When one of the first to fourth gate control units detects a short circuit current flowing through a semiconductor element to be driven by the one of the first to fourth gate control units, the one of the first to fourth semiconductor elements controls the semiconductor element to be driven to an off state and transmits abnormality detection information to the cell control unit; When the cell control unit receives the abnormality detection information, the cell control unit transmits a control signal to each of the first to fourth gate control units to control a semiconductor element to be driven by the gate control unit to an off state; A power conversion device, wherein after receiving the abnormality detection information, the cell control unit maintains the first to fourth semiconductor elements in an off state until both the first voltage of the first energy storage element and the second voltage of the second energy storage element become less than a threshold value.

3. When the first to fourth gate control units receive the control signal, if the semiconductor element to be driven by the gate control unit is not controlled to the off state, the semiconductor element to be driven by the gate control unit is controlled to the off state. The power conversion device according to claim 2.

4. The power conversion device according to any one of claims 1 to 3, wherein the first gate control unit is the first gate control unit or the fourth gate control unit.

5. The power conversion device according to claim 4, wherein the first gate control unit detects a short-circuit current flowing through a semiconductor element to be driven, based on a voltage of a parasitic inductance on an emitter side of the semiconductor element to be driven, among the first to fourth semiconductor elements.

6. Each of the plurality of converter cells further includes a bypass element connected between the first input / output terminal and the second input / output terminal; When the cell control unit receives the abnormality detection information, executing a control for closing the bypass element; The power conversion device according to any one of claims 1 to 3, wherein the control signal is transmitted to each of the first to fourth gate control units during a period before the bypass element is closed in response to the control.

Images