Semiconductor device

Abstract

To provide a semiconductor device that can maintain phase characteristics even when wires connecting circuit boards in a semiconductor package are shortened.SOLUTION: A semiconductor device has a substrate, a first circuit board on the substrate, a second circuit board on the substrate, a first wire connecting the first circuit board and the second circuit board, and a first ferrite located on the substrate and directly under the first wire.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] Embodiments relate to semiconductor devices.

Background Art

[0002] A variable tuning filter is known in which a ferrite ball storage hole is formed in a portion far from the central portion of a bonding wire conductor formed on the surface of a semiconductor substrate, and a magnetostatic mode ferrite single crystal ball is stored in the ferrite ball storage hole.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Summary of the Invention

Problems to be Solved by the Invention

[0004] A semiconductor device has a plurality of circuit boards in the device, and each circuit board is connected by a wire. In recent years, it has been desired to mount many devices on a circuit board in order to realize various functions. For this reason, it has become necessary to increase the size of the circuit boards in the semiconductor device. On the other hand, when the size of the circuit board is increased, since there is a limit in size within the semiconductor device, the distance between the circuit boards becomes narrow, and as a result, the length of the wire connecting the circuit boards also becomes short. When the wire becomes short, the phase characteristics cannot be maintained, and there is a possibility that the performance of the semiconductor device deteriorates.

[0005] An embodiment aims to provide a semiconductor device capable of maintaining phase characteristics even when wires connecting circuit boards within the semiconductor device are shortened.

Means for Solving the Problem

[0006] A semiconductor device according to an embodiment includes a substrate, a first circuit board provided on the substrate, at a distance from the first circuit board a second circuit board provided on the substrate, provided across the distance a first wire connecting the first circuit board and the second circuit board, fixed on the substrate between the first circuit board and the second circuit board, and arranged with a gap between the first circuit board and the second circuit board respectively, and a rod-shaped located directly below the first wire and a first ferrite.

Brief Description of the Drawings

[0007]

Figure 1

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Mode for Carrying Out the Invention

[0008] Hereinafter, embodiments will be described with reference to the drawings. Note that the disclosure is merely an example, and the invention is not limited by the contents described in the following embodiments. Modifications that can be easily conceived by those skilled in the art are naturally included in the scope of the disclosure. For the sake of clarity, in the drawings, the sizes, shapes, etc. of each part may be changed and schematically represented with respect to the actual embodiment. In a plurality of drawings, the same reference numerals may be assigned to corresponding elements, and detailed descriptions may be omitted.

[0009] (First Embodiment) FIG. 1 is a plan view showing an example of a schematic configuration of a semiconductor package which is a semiconductor device, and FIG. 2 is a cross-sectional view taken along line A-A of FIG. 1.

[0010] As shown in FIG. 1, the semiconductor package 1 is configured with a rectangular wall 11 provided so as to surround a rectangular heat sink (substrate) 10. On the heat sink 10, a rectangular first circuit board 12 and a rectangular second circuit board 13 are provided at a predetermined distance apart. In the present embodiment, the case where the first circuit board 12 and the second circuit board 13 have the same size will be described. The first circuit board 12 is connected by a lead electrode portion (first electrode portion) 15 provided through a part of the wall 11 (the upper side in FIG. 1) and a wire group W3. Further, the second circuit board 13 is connected by a lead electrode portion (second electrode portion) 16 provided through a part of the wall 11 (the bottom side in FIG. 1) at a position facing the wall 11 and a wire group W4. The first circuit board 12 and the second circuit board 13 are, for example, matching circuits containing alumina (aluminum oxide: Al2O3) as a material and having a predetermined dielectric constant.

[0011] A field effect transistor 14 is disposed between the first circuit board 12 and the second circuit board 13. The field effect transistor 14 is rectangular and is disposed so as to be parallel between the first circuit board and the second circuit board. The field effect transistor 14 and the first circuit board 12 are connected by a wire group (first wire group) W1, and the field effect transistor 14 and the second circuit board 13 are connected by a wire group (second wire group) W2. Further, the wire groups W1, W2 are connected to the field effect transistor 14 and the first circuit board 12 or the second circuit board 13 so as to form a semi-circle above the heat sink 10. In FIG. 1, each of the wire groups W1, W2 is shown as being connected by four (two sets of two), but the number of wires in the wire groups W1, W2 is not limited to this, and can be arbitrarily determined, and it may have at least one wire.

[0012] On the surfaces of the first circuit board 12, the second circuit board 13, and the field effect transistor 14, microstrip lines (not shown) are provided. In the semiconductor package 1 in which such microstrip lines are formed, the current input from the lead electrode portion 15 passes through the wire group W3, the microstrip line of the first circuit board 12, the wire group W1, the electrode of the field effect transistor 14, the wire group W2, the microstrip line of the second circuit board 13, the wire group W2, and the lead electrode portion 16.

[0013] In the present embodiment, between the first circuit board 12 and the field effect transistor 14, a ferrite (first ferrite) F1 is disposed on the heat sink 10 and directly below the wire group W1. Also, between the second circuit board 13 and the field effect transistor 14, a ferrite (second ferrite) F2 is disposed on the heat sink 10 and directly below the wire group W2. The ferrites F1 and F2 are rod-shaped members (rectangular parallelepiped shape) having a rectangular cross section. In the present embodiment, the case where the lengths of the ferrites F1 and F2 are substantially the same as the longitudinal lengths of the first circuit board 12, the second circuit board 13, and the field effect transistor 14 will be described.

[0014] One surface of the ferrites F1 and F2 (the surface with a short cross-sectional length as shown in FIG. 2) is adhered to the heat sink 10 with, for example, solder, whereby the ferrites F1 and F2 are fixed to the semiconductor package 1. Here, the ferrites F1 and F2 are magnetic materials (electronic materials) obtained by mixing and sintering cobalt, nickel, manganese, etc. with iron oxide as the main component, and are manufactured by baking the powder raw material at a high temperature of 1,000 to 1,400 °C. There are many types depending on the components and mixing ratios of the materials, and since the powder is pressed and solidified, it is possible to easily produce the rectangular parallelepiped-shaped ferrites F1 and F2.

[0015] As described above, the semiconductor package 1 of this embodiment arranges the ferrites F1 and F2. Therefore, when an electric current is passed through the semiconductor package 1, it is assumed that it will be affected by the magnetic forces generated from the ferrites F1 and F2. Hereinafter, a case where no ferrite is arranged in the semiconductor package (hereinafter referred to as Case 1), a case where the wire is extended without arranging a ferrite in the semiconductor package (hereinafter referred to as Case 2), and a case where a ferrite is arranged in the semiconductor package (hereinafter referred to as Case 3) will be described. The results of the simulation for these three cases will be described.

[0016] First, Case 1 will be described. FIGS. 3 to 5 are diagrams for explaining the simulation conditions of Case 1. FIG. 3 is a diagram showing a cross section of the simulation conditions, FIG. 4 is a plan view of the simulation conditions, and FIG. 5 is a perspective view of the simulation conditions. In the simulation of this embodiment, a simulation is performed to examine the influence of arranging a ferrite using the case of connecting two circuit boards with a wire (one transmission line).

[0017] As shown in FIG. 3, the width of the microstrip lines L1 and L2 and the wire W11 respectively wired on the two dielectric substrates D1 and D2 is 8.9 mm, the height from the microstrip lines L1 and L2 is 3.5 mm, and the height of the dielectric substrates D1 and D2 is 0.1875 mm. Further, metal plates H1 and H2 are respectively provided below the dielectric substrates D1 and D2, and the simulation is performed under the condition that a 50Ω resistor is applied to the reference surfaces R1 and R2 on the side surfaces of the dielectric substrates D1 and D2. The air layer above the microstrip lines L1 and L2 is set as a radiation boundary. Also, as shown in FIG. 4, the vertical width of the two dielectric substrates D1 and D2 is 6.0 mm, and the microstrip lines L1 and L2 are to be connected by the wires W11 and W12.

[0018] Next, Case 2 will be described. FIGS. 6 to 8 are diagrams for explaining the simulation conditions of Case 2. The simulation conditions of Case 2 are the same as those of Case 1 except that the length (electrical length) of the wire is different. FIG. 6 shows a case where simulation is performed using wire groups W11a and W12a (not shown) having an electrical length 0.2 mm longer than the wire group W11 of Case 1, and FIG. 7 shows a case where simulation is performed using wire groups W11b and W12b (not shown) having an electrical length 1.0 mm longer than the wire group W11 of Case 1. As shown in FIGS. 6 and 7, the wire groups W11a and W11b, W11b and W12b are extended in length in a shape extending vertically from the bases of the microstrip lines L1 and L2. In this way, Case 2 explains the case where the electrical length of the wire is increased from Case 1. If the electrical length of the wire can be increased, the physical length of the wire can be shortened.

[0019] FIG. 8 is a diagram showing an example of the phase characteristic shift that occurs according to the length of the wire. In FIG. 8, the horizontal axis represents the length of the wire (mm), and the vertical axis represents the phase. Point P1 is the case of the condition of FIG. 3 (Case 1) because the wire length is 0, point P2 is the case of the condition of FIG. 6 (Case 2) because the wire length is 0.2 mm, and point P3 is the case of the condition of FIG. 7 (Case 2) because the wire length is 1.0 mm. FIG. 8 shows that the phase is delayed as the wire length increases. For example, at point P3 where the wire length is extended by 1.0 mm from the state of FIG. 3, it is shown that the phase is delayed by about 4 deg.

[0020] Next, Case 3 will be described. FIGS. 9 to 11 are diagrams for explaining the simulation conditions of Case 3. The simulation of Case 3 is the same as that of Case 1 except that a ferrite F1 is disposed directly below the wires W11 and W12. In this simulation, the ferrite F1 is a rectangular parallelepiped of 0.05 × 1.0 × 0.4 (mm). Also, the material constant (relative permeability) of the ferrite F1 uses 640 of the Ni-Zn system.

[0021] Next, the simulation results will be described. FIGS. 12 to 14 are diagrams showing the results of comparing the simulation results for Case 1, Case 2 (wire length 1.0 mm), and Case 3. FIG. 12 is a diagram showing an example of the simulation result of the S11 characteristic, FIG. 13 is a diagram showing an example of the simulation result of the S21 characteristic, and FIG. 14 is a diagram showing an example of the simulation result of the phase characteristic. Here, the S11 characteristic is a characteristic indicating, for example, the amount of power input to Port 1 (microstrip line L1) that returns to Port 1, and the S21 characteristic is a characteristic indicating, for example, the amount of power input to Port 1 that is reflected to Port 2 (microstrip line L2).

[0022] It can be seen that the S11 characteristic shown in FIG. 12 and the S21 characteristic shown in FIG. 13 generally give equal characteristics. Also, it can be seen that in the phase characteristic shown in FIG. 14, the phase is delayed in Case 3 compared to Case 1. From this simulation result, it can be understood that by arranging the ferrite F1, without changing the S11 characteristic and the S21 characteristic, a phase delay similar to that when the electrical length is increased can be obtained.

[0023] Therefore, from the above simulation results, in the semiconductor package 1, by arranging the ferrite F1 on the heat sink 10 and directly below the wire group W1, the phase of the current from the first circuit board 12 to the field effect transistor 14 can be adjusted, and an effect similar to that when the electrical length is increased can be obtained. Also, by arranging the ferrite F2 on the heat sink 10 and directly below the wire group W2, the phase of the current from the field effect transistor 14 to the second circuit board 14 can be adjusted, and an effect similar to that when the electrical length is increased can be obtained. Since an effect similar to increasing the electrical length can be obtained in this way, without affecting the phase characteristic, the semiconductor package 1 can shorten the length of each wire of the wire groups W1 and W2.

[0024] In addition, since the semiconductor package 1 can shorten the length of each wire in the wire groups W1 and W2 as described above, the sizes of the first circuit board 12, the second circuit board 13, and the field effect transistor 14 can be increased within the semiconductor package 1. Therefore, it becomes possible to increase the functions mounted on the first circuit board 12, the second circuit board 13, and the field effect transistor 14.

[0025] (Second Embodiment) FIG. 15 is a diagram showing an example of the configuration of the semiconductor package 100 according to the second embodiment, and FIG. 16 is a cross-sectional view taken along line B-B of FIG. 15. Compared with the semiconductor package 1 of the first embodiment, the configuration of the field effect transistor is more detailed. Note that the same components as those of the semiconductor package 1 described above are denoted by the same reference numerals, and detailed descriptions thereof are omitted. In addition, the illustration of the microstrip line is omitted.

[0026] As shown in FIGS. 15 and 16, an electrode 12a is provided on the first circuit board 12, and an electrode 13a is provided on the second circuit board 13. In addition, the field effect transistor 14 is provided with a plurality of electrodes 14a on the first circuit board 12 side and an electrode 14b on the second circuit board 13 side. The plurality of electrodes 14a are arranged at equal intervals in the longitudinal direction of the field effect transistor 14 as an example. The electrode 14b has a rectangular shape and is arranged parallel to the longitudinal direction of the field effect transistor 14.

[0027] The electrode 12a is configured to spread fan-shaped from the lead electrode portion 15 side so as to correspond to the widths of the plurality of electrodes 14a of the field effect transistor 14. The wire group (first wire group) W5 connects each of the plurality of electrodes 14a and the electrode 12a. The electrode 13a is configured to spread fan-shaped from the lead electrode portion 16 side so as to correspond to the width of the electrode 14b of the field effect transistor 14. The wire group (second wire group) W6 connects the electrode 14b and the electrode 13a with a plurality of wires.

[0028] Furthermore, the ferrite F1 is disposed between the first circuit board 12 and the field effect transistor 14 on the heat sink 10 and directly below the wire group W5. Also, the ferrite F1 has a rectangular parallelepiped shape, and both end portions in the longitudinal direction of the ferrite F1 are configured to exceed the width in the arrangement direction of the wire group W5. Similarly, the ferrite F2 is disposed between the second circuit board 13 and the field effect transistor 14 on the heat sink 10 and directly below the wire group W6. Also, the ferrite F2 has a rectangular parallelepiped shape, similar to the ferrite F1, and both end portions in the longitudinal direction of the ferrite F2 are configured to exceed the width in the arrangement direction of the wire group W5.

[0029] Even in the semiconductor package 100 configured as described above, the same effects as those of the first embodiment can be achieved. More specifically, in the semiconductor package 100, by disposing the ferrite F1 on the heat sink 10 and directly below the wire group W5, the phase of the current from the first circuit board 12 to the field effect transistor 14 can be adjusted, and the same effect as lengthening the electrical length can be obtained. Also, by disposing the ferrite F2 on the heat sink 10 and directly below the wire group W6, the phase of the current from the field effect transistor 14 to the second circuit board 14 can be adjusted, and the same effect as lengthening the electrical length can be obtained. Since the same effect as lengthening the electrical length can be obtained in this way, without affecting the phase characteristics, the semiconductor package 100 can shorten the length of each wire of the wire groups W5 and W6.

[0030] Also, since the semiconductor package 100 can shorten the length of each wire of the wire groups W5 and W6 as described above, the sizes of the first circuit board 12, the second substrate circuit 13, and the field effect transistor 14 can be increased within the semiconductor package 100. For this reason, it is possible to increase the functions mounted on the first circuit board 12, the second circuit board 13, and the field effect transistor 14, which is the same as in the first embodiment.

[0031] Furthermore, in the above-described first and second embodiments, ferrite F1 (or ferrite F2) is disposed directly below the wire groups W1, W5 (or wire groups W2, W6) that connect the first circuit board 12 (or the second circuit board 13) and the field-effect transistor 14. However, even when the first circuit board 12 (or the second circuit board 13) and the field-effect transistor 14 are not connected, the same effect can be achieved by disposing ferrite directly below the circuit board and the wire that connects the circuit boards. In addition, the above technology can be applied to any semiconductor package 100 that has at least two circuit boards and the two circuit boards are connected by wires.

[0032] Furthermore, in each of the above embodiments, the description has been given assuming that the cross-sectional shapes of the ferrites F1 and F2 are rectangular, but the present invention is not limited to this. For example, the cross-sectional shapes of the two ferrites may be circular, and the ferrites F1 and F2 having such cross-sectional shapes may be disposed on the heat sink 10 and directly below the wire groups W1, W5 (or wire groups W2, W6) within the semiconductor packages 1 and 100.

[0033] Furthermore, the technology of the above embodiments can be applied not only when increasing the sizes of the first circuit board 12, the second circuit board 13, and the field-effect transistor 14 within the semiconductor packages 1 and 100, but also when reducing the distance between the circuit boards. In other words, according to the technology of the present embodiment, the degree of freedom in design within the semiconductor packages 1 and 100 can be improved. Also, if the circuit board is made into an integrated circuit and the number of stages of the integrated circuit is increased within the semiconductor package, the semiconductor packages 1 and 100 can, for example, achieve broadbanding in the S band.

[0034] Furthermore, although the semiconductor packages 1 and 100 of the above-described embodiments have the first circuit board 12, the second circuit board 13, and the field effect transistor 14, and have the wire groups W1, W2 or the wire groups W5, W6 connecting them, and have the ferrites F1, F2, the present invention is not limited thereto. The semiconductor package may have four or more circuit boards, and ferrites may be arranged on the heat sink and directly below the wire groups connecting the respective circuit boards.

[0035] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and its equivalent scope.

Description of Reference Numerals

[0036] 1, 100... semiconductor package, 10... heat sink, 11... wall, 12... first circuit board, 13... second circuit board, 14... field effect transistor, 15, 16... lead electrode portions, D1, D2... dielectric circuits, F1, F2... ferrites, L1, L2... microstrip lines, H1, H2... metal plates, W1, W2, W3, W4, W5, W6... wire groups

Claims

1. A substrate, a first circuit board provided on the substrate, a second circuit board provided on the substrate with a gap from the first circuit board, a first wire provided across the gap to connect the first circuit board and the second circuit board, a rod-shaped first ferrite fixed on the substrate between the first circuit board and the second circuit board, disposed with a gap from the first circuit board and the second circuit board respectively, and located directly below the first wire, A semiconductor device comprising the above.

2. The first wire is a wire group provided across the gap to connect the first circuit board and the second circuit board at a plurality of locations, The first ferrite has a rectangular parallelepiped shape, Both ends in the longitudinal direction of the first ferrite are configured to extend beyond the wires at both ends in the arrangement direction of the wire group, The semiconductor device according to Claim 1.

3. The first circuit board is a matching circuit for adjusting the phase of the voltage, The second circuit board is a field effect transistor, The semiconductor device according to Claim 1.

4. A third circuit board provided on the substrate with a gap from the second circuit board, a second wire provided across the gap between the second circuit board and the third circuit board to connect the third circuit board and the second circuit board, a rod-shaped second ferrite fixed on the substrate between the second circuit board and the third circuit board, disposed with a gap from the second circuit board and the third circuit board respectively, and located directly below the second wire, The semiconductor device according to Claim 1, further comprising the above.

5. A rectangular wall erected to surround the substrate, a first electrode portion penetrating one side of the wall, a second electrode portion penetrating the wall on the opposite side of the one side of the wall, The first circuit board is connected to the first electrode portion, The third circuit board is connected to the second electrode portion, The semiconductor device according to Claim 4.

6. The height of the first ferrite is higher than the thickness of at least one of the first circuit board and the second circuit board. The semiconductor device according to Claim 1.

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