Analog Switch Circuit

Abstract

To provide a low cost analog switch circuit that uses a transistor having a normal gate breakdown voltage and that can be used at a voltage higher than the gate breakdown voltage.SOLUTION: An analog switch circuit according to an embodiment includes: a CMOS analog switch having a gate operation breakdown voltage being VGT; and first and second gate drive circuits to which an enable signal and a control signal are respectively input. In a case of VGT<VSH≤(2×VGT), if the enable signal is 0, the second gate drive circuit outputs a signal of voltage (VSH / 2) to a gate terminal of a PMOS when the control signal is 0, and the first gate drive circuit outputs the signal of voltage (VSH / 2) to the gate terminal of an NMOS when the control signal is 1.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] Embodiments of the present invention relate to an analog switch circuit in which an N-type MOSFET and a P-type MOSFET are arranged in parallel.

Background Art

[0002] When an N-type MOSFET (hereinafter referred to as NMOS) is used as an analog switch, the high voltage side of the input signal may be distorted in the output signal. Further, when a P-type MOSFET (hereinafter referred to as PMOS) is used as an analog switch, the low voltage side of the input signal may be distorted in the output signal. Therefore, a CMOS analog switch in which NMOS and PMOS are arranged in parallel to reduce distortion of the output signal has been conventionally used.

[0003] The gate terminals of NMOS and PMOS are insulated from the source terminal side and the drain terminal side by an oxide film. However, for example, if a voltage higher than the gate breakdown voltage is applied between the gate terminal and the source terminal, the insulating oxide film may be broken. Therefore, the analog switch is used at a voltage equal to or lower than the gate breakdown voltage.

[0004] When using at a voltage higher than the general gate breakdown voltage, a transistor with a high gate breakdown voltage is used. However, a transistor with a high gate breakdown voltage is costly.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] Therefore, an object of the embodiment is to provide a low-cost analog switch circuit using a transistor with a normal gate breakdown voltage that can be used at a voltage higher than the gate breakdown voltage.

Means for Solving the Problem

[0007] The analog switch circuit of the embodiment connects the source terminals of an N-type MOSFET and a P-type MOSFET with a gate operating breakdown voltage of VGT and connects the drain terminals to each other, arranges the N-type MOSFET and the P-type MOSFET in parallel, and sets a voltage higher than VGT and equal to or lower than (2×VGT) as VSH. Then, an analog switch in which the potential of the drain terminal is (VSH / 2), a first gate drive circuit to which an enable signal and a control signal are input and which is connected to the gate terminal of the N-type MOSFET of the analog switch, and an enable signal and the control signal are input and which is connected to the gate terminal of the P-type MOSFET of the analog switch, and a second gate drive circuit. When the logical value of the enable signal is 0, a voltage of 0 or a voltage of VSH is applied to the source terminal of the analog switch according to whether the logical value of the control signal is 0 or 1. When the logical value of the control signal is 0, the first gate drive circuit outputs a signal of voltage 0 to the gate terminal of the N-type MOSFET, and the second gate drive circuit outputs a signal of voltage (VSH / 2) to the gate terminal of the P-type MOSFET. When the logical value of the control signal is 1, the first gate drive circuit outputs a signal of voltage (VSH / 2) to the gate terminal of the N-type MOSFET, and the second gate drive circuit outputs a signal of voltage VSH to the gate terminal of the P-type MOSFET.

Brief Description of the Drawings

[0008]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

DETAILED DESCRIPTION OF THE INVENTION

[0009] Before specifically describing the embodiments, the configuration of the analog switch and the operation of the comparative example will be described. FIG. 1 is a diagram showing the configuration of a general analog switch.

[0010] The analog switch 10 is a CMOS (Complementary MOS) analog switch in which an N-type MOSFET (N-type Metal-Oxide-Semiconductor Field-Effect Transistor) (hereinafter, NMOS) 10n and a P-type MOSFET (P-type Metal-Oxide-Semiconductor Field-Effect Transistor) (hereinafter, PMOS) 10p are connected in parallel.

[0011] The source terminal (S) of NMOS10n and the source terminal (S) of PMOS10p are connected at the input terminal 10a of the analog switch 10. The drain terminal (D) of NMOS10n and the drain terminal (D) of PMOS10p are connected at the output terminal 10b of the analog switch 10.

[0012] An analog input signal IN is input to the input terminal 10a. An analog output signal OUT is output from the output terminal 10b.

[0013] A gate drive signal GN is input to the gate terminal (G) of NMOS10n, and a gate drive signal GP is input to the gate terminal (G) of PMOS10p. Let the gate operating breakdown voltage of NMOS10n and PMOS10p be VGT (the unit of voltage and potential is, for example, volt, and hereinafter, the explicit indication of the unit is omitted).

[0014] The back gate terminal (B) of NMOS10n is connected to ground, and the back gate terminal (B) of PMOS10p is connected to a positive power supply. Here, it is assumed that the voltage VSH is higher than VGT and is a voltage of (2×VGT) or less [VGT < VSH ≦ (2×VGT)]. At this time, NMOS10n and PMOS10p have a back gate operating breakdown voltage of VSH or more.

[0015] The output terminal 10b is connected to the power supply 20. The power supply 20 maintains the potential of the output terminal 10b at (VSH / 2). Therefore, the potentials of the drain terminal (D) of NMOS10n and the drain terminal (D) of PMOS10p are both (VSH / 2).

[0016] FIG. 2 is a diagram for explaining the operation of the analog switch 10 according to the comparative example.

[0017] The voltage V_IN of the input signal IN before the analog switch 10 turns on (conducts) is 0 or VSH.

[0018] When a gate drive signal GN with a voltage V_GN = VSH is input to the gate terminal (G) of NMOS10n and a gate drive signal GP with a voltage V_GP = 0 is input to the gate terminal (G) of PMOS10p, the analog switch 10 turns on.

[0019] When the analog switch 10 turns on, the input terminal 10a and the output terminal 10b become conductive. Then, regardless of whether the voltage V_IN of the input signal IN before the analog switch 10 turns on (conducts) is 0 or VSH, the potential of the input terminal 10a, that is, the potentials of the source terminals (S) of NMOS10n and PMOS10p, become (VSH / 2).

[0020] At this time, the gate-source voltage of NMOS10n is (VSH / 2), and the gate-source voltage of PMOS10p is (-VSH / 2) (see the switch-on column in Fig. 2). Since (VGT / 2) < (VSH / 2) ≤ VGT, when the analog switch 10 is on, the absolute values of the gate-source voltages of NMOS10n and PMOS10p both satisfy the condition of being below the gate breakdown voltage VGT.

[0021] On the other hand, when a gate drive signal GN with a voltage V_GN = 0 is input to the gate terminal (G) of NMOS10n and a gate drive signal GP with a voltage V_GP = VSH is input to the gate terminal (G) of PMOS10p, the analog switch 10 turns off.

[0022] At this time, if the voltage V_IN of the input signal IN is VSH, the gate-source voltage of NMOS10n is (-VSH), and the gate-source voltage of PMOS10p is 0. Also, if the voltage V_IN of the input signal IN is 0, the gate-source voltage of NMOS10n is 0, and the gate-source voltage of PMOS10p is VSH (see the switch-off column in Fig. 2). Therefore, when the analog switch 10 is off, the absolute value of either one of the gate-source voltages of NMOS10n and PMOS10p becomes higher than the gate breakdown voltage VGT.

[0023] In the embodiment where the analog switch 10 is off and the gate-source voltage of NMOS 10n and PMOS 10p is set to be equal to or lower than the gate breakdown voltage VGT regardless of whether the voltage V_IN of the input signal IN is 0 or VSH, the configuration will be described below with reference to the drawings. (First Embodiment) (Configuration)

[0024] FIG. 3 is a diagram showing an example of a circuit configuration to which the analog switch circuit 1 according to the first embodiment is applied.

[0025] The analog signal output circuit 30 receives the control signal CNT, generates an analog input signal IN according to the control signal CNT, and outputs the generated input signal IN to the analog switch 10. The control signal CNT takes a logical value of "0" or "1". When CNT = 0, the analog signal output circuit 30 outputs an input signal IN with a voltage V_IN = 0, and when CNT = 1, it outputs an input signal IN with a voltage V_IN = VSH.

[0026] FIG. 4 is a diagram showing the configuration of the analog switch circuit 1 according to the first embodiment.

[0027] The analog switch circuit 1 includes an analog switch 10, an NMOS gate drive circuit 11 (first gate drive circuit), and a PMOS gate drive circuit 12 (second gate drive circuit).

[0028] The NMOS gate drive circuit 11 is connected to the gate terminal (G) of NMOS 10n of the analog switch 10. The NMOS gate drive circuit 11 receives the enable signal EN and the control signal CNT. The NMOS gate drive circuit 11 generates a gate drive signal GN with a voltage V_GN according to the enable signal EN and the control signal CNT, and outputs it to the gate terminal (G) of NMOS 10n.

[0029] The PMOS gate drive circuit 12 is connected to the gate terminal (G) of the PMOS 10p of the analog switch 10. An enable signal EN and a control signal CNT are input to the PMOS gate drive circuit 12. The PMOS gate drive circuit 12 generates a gate drive signal GP of a voltage V_GP according to the enable signal EN and the control signal CNT, and outputs it to the gate terminal (G) of the PMOS 10p.

[0030] The enable signal EN takes a logical value of "0" or "1". When the enable signal EN takes a logical value of "0", the analog switch 10 turns off, and when the enable signal EN takes a logical value of "1", the analog switch 10 turns off.

[0031] When the logical value of the enable signal EN is 0, the voltage V_IN of the input signal IN output from the analog signal output circuit 30 is applied to the source terminal (S) of the analog switch 10. The voltage V_IN applied to the source terminal (S) is 0 when the logical value of the control signal CNT is 0, and is VSH when the logical value of the control signal CNT is 1. (Operation)

[0032] Referring to FIGS. 5 to 8, the operation of the analog switch circuit 1 will be described. FIG. 5 is a timing chart showing a first operation example of the analog switch circuit 1 according to the first embodiment. FIG. 6 is a timing chart showing a second operation example of the analog switch circuit 1 according to the first embodiment. FIG. 7 is a diagram for explaining the operations of the NMOS gate drive circuit 11 and the PMOS gate drive circuit 12 of the analog switch circuit 1 according to the first embodiment. FIG. 8 is a diagram showing an example of the gate-source voltage of the analog switch circuit 1 according to the first embodiment.

[0033] In the first operation example shown in FIG. 5, the logical value of the control signal CNT changes from "0" to "1" at time t1.

[0034] When the logical value of the control signal CNT is "0" and the switch 10 is off, the analog signal output circuit 30 outputs an input signal IN with a voltage V_IN = 0.

[0035] When the control signal CNT = 0 and the enable signal EN = 0 (in the OFF1 case), as shown in the CNT = 0 column of Fig. 7, the NMOS gate drive circuit 11 outputs a gate drive signal GN with a voltage V_GN = 0 (normal operation), and the PMOS gate drive circuit 12 outputs a gate drive signal GP with a voltage V_GP = (VSH / 2). Here, the voltage V_GP = (VSH / 2) of the gate drive signal GP output by the PMOS gate drive circuit 12 is a voltage (VSH / 2) lower than the normal voltage VSH.

[0036] At this time, since the voltage V_IN = 0, the voltage between the gate and source of NMOS10n is 0, and the voltage between the gate and source of PMOS10p is (VSH / 2) (refer to the column of V_IN = 0 and switch off in Fig. 8).

[0037] At time t1, the control signal CNT changes from 0 to 1 and the enable signal EN changes from 0 to 1. When the enable signal EN = 1, regardless of the logical value of the control signal CNT, the NMOS gate drive circuit 11 outputs a gate drive signal GN with a voltage V_GN = VSH (normal operation), and the PMOS gate drive circuit 12 outputs a gate drive signal GP with a voltage V_GP = 0 (normal operation). As a result, the analog switch 10 turns on and the input terminal 10a and the output terminal 10b are electrically connected, and the potential of the input terminal 10a becomes (VSH / 2) (refer to V_IN in the timing chart of Fig. 5).

[0038] The voltage between the gate and source of NMOS10n and the voltage between the gate and source of PMOS10p when the analog switch 10 is on are the same as those in the switch-on column shown in the comparative example of Fig. 2, as shown in the switch-on column of Fig. 8. That is, the voltage between the gate and source of NMOS10n is (VSH / 2), and the voltage between the gate and source of PMOS10p is (-VSH / 2).

[0039] With the control signal CNT maintained at 1, at time t2 after time t1, the enable signal EN changes from 1 to 0.

[0040] When the logical value of the control signal CNT is "1" and the switch 10 is off, the analog signal output circuit 30 outputs an input signal IN with voltage V_IN = VSH.

[0041] When the control signal CNT = 1 and the enable signal EN = 0 (in the case of OFF2), as shown in the CNT = 1 column of FIG. 7, the NMOS gate drive circuit 11 outputs a gate drive signal GN with voltage V_GN = (VSH / 2), and the PMOS gate drive circuit 12 outputs a gate drive signal GP with voltage V_GP = VSH (normal operation). Here, the voltage V_GN = (VSH / 2) of the gate drive signal GN output by the NMOS gate drive circuit 11 is a voltage (VSH / 2) higher than the normal voltage 0.

[0042] At this time, since the voltage V_IN = VSH, the gate-source voltage of NMOS10n is (-VSH / 2), and the gate-source voltage of PMOS10p is 0 (refer to the column of V_IN = VSH and switch off in FIG. 8).

[0043] Therefore, as shown in FIG. 8, when the analog switch 10 is on, when the analog switch 10 is OFF1, and when the analog switch 10 is OFF2, the absolute values of the gate-source voltage of NMOS10n and the gate-source voltage of PMOS10p are maintained below the gate breakdown voltage VGT.

[0044] In the second operation example shown in FIG. 6, the logical value of the control signal CNT changes from "1" to "0" at time t3. Also, the logical value of the enable signal EN changes from "0" to "1" at time t3 and changes from "1" to "0" at time t4 after time t3.

[0045] In the second operation example, the NMOS gate drive circuit 11 and the PMOS gate drive circuit 12 perform the OFF2 operation when CNT = 1 and EN = 0, perform the ON operation regardless of the logical value of CNT when EN = 0, and perform the OFF1 operation when CNT = 0 and EN = 0, in the same manner as in the first operation example shown in FIG. 5.

[0046] FIG. 9 is a flowchart showing the operation of the analog switch circuit 1 according to the first embodiment.

[0047] When the process starts, the analog switch circuit 1 branches the process according to whether the enable signal EN = 0 (step S1).

[0048] Here, when the enable signal EN = 1, the NMOS gate drive circuit 11 and the PMOS gate drive circuit 12 of the analog switch circuit 1 perform the normal operation of turning on the analog switch circuit 1 (step S2).

[0049] Also, in step S1, when the enable signal EN = 0, the analog switch circuit 1 branches the process according to whether the control signal CNT = 0 (step S3).

[0050] Here, when the control signal CNT = 0, the NMOS gate drive circuit 11 of the analog switch circuit 1 performs the normal operation to set V_GN = 0, and the PMOS gate drive circuit 12 reduces the voltage by (VSH / 2) from the normal voltage VSH to set V_GP = (VSH / 2) (step S4).

[0051] On the other hand, in step S3, when the control signal CNT = 1, the NMOS gate drive circuit 11 of the analog switch circuit 1 increases the voltage by (VSH / 2) from the normal voltage 0 to set V_GN = (VSH / 2), and the PMOS gate drive circuit 12 performs the normal operation to set V_GP = VSH (step S5).

[0052] When the processes of steps S2, S4, or S5 are performed, the analog switch circuit 1 ends the process of FIG. 9.

[0053] FIG. 10 is a diagram showing a ΔΣ modulator 40 as an example of a circuit to which the analog switch circuit 1 according to the first embodiment is applied.

[0054] The ΔΣ modulator 40 is an analog-to-digital converter that inputs an analog signal AIN, processes the analog signal AIN to generate a digital signal DOUT, and outputs the digital signal DOUT. The ΔΣ modulator 40 includes a differentiator 41, an integrator 42, a comparator 43, and a digital-to-analog converter (DAC) 44.

[0055] The analog signal AIN is input to the differentiator 41 and subtracted from the analog signal from the DAC 44. The differentiator 41 outputs the subtracted analog signal to the integrator 42. The integrator 42 integrates the input analog signal and outputs an analog signal VOUT. The comparator 43 compares the voltage of the analog signal VOUT with a predetermined voltage, quantizes the analog signal VOUT based on the comparison result, and generates a 1-bit digital signal DOUT. The digital signal DOUT generated by the comparator 43 is output to the outside of the ΔΣ modulator 40 and also output to the DAC 44. The DAC 44 converts the digital signal DOUT input from the comparator 43 into an analog signal and outputs it to the differentiator 41.

[0056] FIG. 11 is a diagram showing a circuit configuration example of the differentiator 41 and the integrator 42 in the ΔΣ modulator 40 according to the first embodiment. FIG. 11 shows a circuit configuration example of the portion surrounded by a dotted line in FIG. 10.

[0057] The differentiator 41 and the integrator 42 include, for example, a switched-capacitor (SC) circuit 45, an operational amplifier 46, a capacitor 47, and the analog switch circuit 1.

[0058] The SC circuit 45 includes a capacitor 45a, a switch 45b, a switch 45c, a switch 45d, and a switch 45e. The switch 45b, the capacitor 45a, and the switch 45e are connected in series in this order. The switch 45c is connected between the switch 45b and the capacitor 45a, and the switch 45d is connected between the capacitor 45a and the switch 45e. Further, an analog signal AIN is input to the switch 45b. The switch 45c is connected to the DAC 44, the switch 45d is connected to the power supply 20A (see FIG. 12), and the switch 45e is connected to the inverting input terminal 46a of the operational amplifier 46.

[0059] The non-inverting input terminal 46b of the operational amplifier 46 is connected to the power supply 20A (see FIG. 12) having a voltage (VSH / 2). Therefore, the voltage of the inverting input terminal 46a, which is virtually short-circuited to the non-inverting input terminal 46b, is (VSH / 2).

[0060] The capacitor 47 is connected in the feedback path of the operational amplifier 46, that is, between the output terminal 46c and the inverting input terminal 46a. The analog switch circuit 1 is connected across the capacitor 47. Thus, the integrator 42 is configured as an SC integrator and is an inverting analog integrator that inverts and integrates the signal input from the inverting input terminal 46a.

[0061] The SC circuit 45 performs a crawl-type operation. When the switch 45b and the switch 45d are on and the switch 45c and the switch 45e are off, the analog signal AIN is connected to the capacitor 45a.

[0062] Also, when the switch 45b and the switch 45d are off and the switch 45c and the switch 45e are on, the DAC 44 is connected to the capacitor 45a. At this time, since the inverted integration signal from the integrator 42 is input to the capacitor 45a via the comparator 43 and the DAC 44, the operation of the differentiator 41 is performed by connecting the DAC 44 to the capacitor 45a.

[0063] When the analog switch circuit 1 connected to both ends of the capacitor 47 is turned off, the capacitor 47 can be charged, and when it is turned on, the capacitor 47 is discharged.

[0064] The analog signal VOUT output from the output terminal 46c of the operational amplifier 46 is a pulse wave that changes between voltage 0 and voltage VSH, and is input to the comparator 43.

[0065] The comparator 43 compares the voltage of the analog signal VOUT with a predetermined voltage, for example, (VSH / 2), and outputs a logical value "1" when it is (VSH / 2) or more, and outputs a logical value "0" when it is less than (VSH / 2). Therefore, depending on whether the logical value of the digital signal DOUT is 1 or 0, it is possible to determine whether the voltage of the analog signal VOUT is VSH or 0.

[0066] The digital signal DOUT output from the comparator 43 is output to the outside of the ΔΣ modulator 40 and to the DAC 44 as described above, and is further output as a control signal CNT to the analog switch circuit 1 (see FIG. 12).

[0067] FIG. 12 is a diagram showing a configuration example in which the analog switch circuit 1 is applied to the ΔΣ modulator 40 according to the first embodiment.

[0068] The DAC 44, the SC circuit 45, the operational amplifier 46, and the capacitor 47 correspond to the analog signal output circuit 30 in FIG. 3.

[0069] The output terminal 10b of the analog switch 10 is connected to the inverting input terminal 46a that is virtually short-circuited with the non-inverting input terminal 46b. Therefore, the potential of the output terminal 10b is maintained at (VSH / 2) as described above.

[0070] The input terminal 10a of the analog switch 10 is connected to the output terminal 46c of the operational amplifier 46. Therefore, an analog signal VOUT that changes between voltage 0 and voltage VSH is input to the input terminal 10a as an input signal IN.

[0071] The analog switch circuit 1 operates as described above in response to the enable signal EN and the control signal CNT. That is, when the analog switch 10 is off, the voltage of the analog signal VOUT input from the operational amplifier 46 to the input terminal 10a of the analog switch 10 is determined based on the digital signal DOUT (i.e., the control signal CNT) fed back to the DAC44 side, and the NMOS gate drive circuit 11 and the PMOS gate drive circuit 12 control the voltages of the gate drive signal GN and the gate drive signal GP. Thereby, even when the switch is off, the absolute value of the gate-source voltage of the analog switch circuit 1 can be maintained below the gate breakdown voltage VGT. Also, as described above, the absolute value of the gate-source voltage of the analog switch circuit 1 is maintained below the gate breakdown voltage VGT when the switch is on.

[0072] According to the first embodiment, the voltages of the gate drive signals GN and GP when the switch is off are controlled according to the control signal CNT. For this reason, even if gate drive signals GN and GP having a voltage higher than the gate breakdown voltage VGT are output to the gate terminal (G) of the analog switch 10 when the switch is on, regardless of whether the analog switch 10 is on or off, the absolute value of the gate-source voltage does not exceed the gate breakdown voltage VGT.

[0073] Thereby, the transistor constituting the analog switch 10 is not destroyed, and the reliability does not decrease. And since the analog switch circuit 1 can be configured using transistors with a normal gate breakdown voltage, the analog switch circuit 1 can be made low-cost.

[0074] Although some embodiments of the present invention have been described, these embodiments are shown by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are included in the invention described in the claims and its equivalent scope.

Description of Symbols

[0075] 1…Analog switch circuit, 10…Analog switch, 10a…Input terminal, 10b…Output terminal, 10n…NMOS, 10p…PMOS, 11…NMOS gate drive circuit, 12…PMOS gate drive circuit, 20, 20A…Power supply, 30…Analog signal output circuit, 40…ΔΣ modulator, 41…Differentiator, 42…Integrator, 43…Comparator, 44…DAC, 45…SC circuit, 45a…Capacitor, 45b, 45c, 45d, 45e…Switch, 46…Operational amplifier, 46a…Inverting input terminal, 46b…Non-inverting input terminal, 46c…Output terminal, 47…Capacitor, AIN, VOUT…Analog signal, CNT…Control signal, DOUT…Digital signal, EN…Enable signal, GN, GP…Gate drive signal, IN…Input signal, OUT…Output signal, VGT…Gate breakdown voltage

Claims

1. an analog switch having source terminals connected to each other and drain terminals connected to each other of an N-type MOSFET and a P-type MOSFET, each having a gate operating withstand voltage of VGT, arranged in parallel with the P-type MOSFET, the drain terminal having a potential of (VSH / 2) where VSH is a voltage higher than VGT but not higher than (2×VGT); a first gate drive circuit to which an enable signal and a control signal are input and which is connected to a gate terminal of the N-type MOSFET of the analog switch; a second gate drive circuit to which the enable signal and the control signal are input and which is connected to a gate terminal of the P-type MOSFET of the analog switch; Equipped with When the logic value of the enable signal is 0, a voltage of 0 or a voltage VSH is applied to the source terminal of the analog switch depending on whether the logical value of the control signal is 0 or 1; when the logical value of the control signal is 0, the first gate drive circuit outputs a signal of voltage 0 to the gate terminal of the N-type MOSFET, and the second gate drive circuit outputs a signal of voltage (VSH / 2) to the gate terminal of the P-type MOSFET; When the logical value of the control signal is 1, the first gate drive circuit outputs a signal of a voltage (VSH / 2) to the gate terminal of the N-type MOSFET, and the second gate drive circuit outputs a signal of a voltage VSH to the gate terminal of the P-type MOSFET. Analog switch circuit.

2. When the logic value of the enable signal is 1, Regardless of the logical value of the control signal, the first gate drive circuit outputs a signal of voltage VSH to the gate terminal of the N-type MOSFET, and the second gate drive circuit outputs a signal of voltage 0 to the gate terminal of the P-type MOSFET; The source terminal of the analog switch is electrically connected to the drain terminal, and has a potential of (VSH / 2).

2. The analog switch circuit according to claim 1.

3. an analog signal output circuit that receives the control signal and outputs a signal of a voltage of 0 or a voltage VSH to the source terminal of the analog switch depending on whether the logical value of the control signal is 0 or 1; 2. The analog switch circuit according to claim 1.

4. the N-type MOSFET and the P-type MOSFET of the analog switch have a back-gate operation withstand voltage of a voltage VSH or higher; 2. The analog switch circuit according to claim 1.

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